Index: firmware/.cproject =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/.cproject (.../.cproject) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/.cproject (.../.cproject) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -36,6 +36,11 @@ @@ -45,8 +50,10 @@ Index: firmware/.settings/org.eclipse.core.resources.prefs =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/.settings/org.eclipse.core.resources.prefs (.../org.eclipse.core.resources.prefs) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/.settings/org.eclipse.core.resources.prefs (.../org.eclipse.core.resources.prefs) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -1,4 +1,12 @@ eclipse.preferences.version=1 +encoding//Debug/App/Modes/subdir_rules.mk=UTF-8 +encoding//Debug/App/Modes/subdir_vars.mk=UTF-8 +encoding//Debug/App/Services/FlashAPI/subdir_rules.mk=UTF-8 +encoding//Debug/App/Services/FlashAPI/subdir_vars.mk=UTF-8 +encoding//Debug/App/Services/subdir_rules.mk=UTF-8 +encoding//Debug/App/Services/subdir_vars.mk=UTF-8 +encoding//Debug/App/Tasks/subdir_rules.mk=UTF-8 +encoding//Debug/App/Tasks/subdir_vars.mk=UTF-8 encoding//Debug/makefile=UTF-8 encoding//Debug/objects.mk=UTF-8 encoding//Debug/source/subdir_rules.mk=UTF-8 Index: firmware/App/BLCommon.h =================================================================== diff -u --- firmware/App/BLCommon.h (revision 0) +++ firmware/App/BLCommon.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,35 @@ +/* + * BLCommon.h + * + * Created on: Aug 1, 2024 + * Author: fw + */ + +#ifndef __BLCOMMON_H__ +#define __BLCOMMON_H__ + +#include "hal_stdtypes.h" + +// ********** version ********** + +#define BL_VERSION_MAJOR 0 +#define BL_VERSION_MINOR 0 +#define BL_VERSION_MICRO 0 +#define BL_VERIOSN_BUILD 0 + + +// **** Types **** + +typedef float F32; ///< 32-bit floating point type +typedef double F64; ///< 64-bit floating point type +typedef long long S64; ///< 64-bit signed integer type +typedef unsigned int U32; ///< 32-bit unsigned integer type +typedef int S32; ///< 32-bit signed integer type +typedef unsigned short U16; ///< 16-bit unsigned integer type +typedef short S16; ///< 16-bit signed integer type +typedef unsigned char U08; ///< 8-bit unsigned integer type +typedef unsigned int BOOL; ///< 32-bit boolean type +typedef unsigned char BYTE; ///< 8-bit byte type + + +#endif Index: firmware/App/Modes/ModeInitPOST.c =================================================================== diff -u --- firmware/App/Modes/ModeInitPOST.c (revision 0) +++ firmware/App/Modes/ModeInitPOST.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,8 @@ +/* + * ModeInitPOST.c + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#include "ModeInitPOST.h" Index: firmware/App/Modes/ModeInitPOST.h =================================================================== diff -u --- firmware/App/Modes/ModeInitPOST.h (revision 0) +++ firmware/App/Modes/ModeInitPOST.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,13 @@ +/* + * ModeInitPOST.h + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#ifndef __MODEINITPOST_H__ +#define __MODEINITPOST_H__ + + + +#endif Index: firmware/App/Modes/ModeStandby.c =================================================================== diff -u --- firmware/App/Modes/ModeStandby.c (revision 0) +++ firmware/App/Modes/ModeStandby.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,8 @@ +/* + * ModeStandby.c + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#include "ModeStandby.h" Index: firmware/App/Modes/ModeStandby.h =================================================================== diff -u --- firmware/App/Modes/ModeStandby.h (revision 0) +++ firmware/App/Modes/ModeStandby.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,13 @@ +/* + * ModeStandby.h + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#ifndef __MODESTANDBY_H__ +#define __MODESTANDBY_H__ + + + +#endif Index: firmware/App/Modes/ModeUpdate.c =================================================================== diff -u --- firmware/App/Modes/ModeUpdate.c (revision 0) +++ firmware/App/Modes/ModeUpdate.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,8 @@ +/* + * ModeUpdate.c + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#include "ModeUpdate.h" Index: firmware/App/Modes/ModeUpdate.h =================================================================== diff -u --- firmware/App/Modes/ModeUpdate.h (revision 0) +++ firmware/App/Modes/ModeUpdate.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,13 @@ +/* + * ModeUpdate.h + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#ifndef _MODEUPDATE_H__ +#define _MODEUPDATE_H__ + + + +#endif Index: firmware/App/Services/FlashAPI/CGT.CCS.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/CGT.CCS.h (revision 0) +++ firmware/App/Services/FlashAPI/CGT.CCS.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,54 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: CGT.CCS.h + * + * Description: TI CCS compiler specific info used by the F021 API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef CGT_CCS_H_ +#define CGT_CCS_H_ + +#if defined(__big_endian__) /* is big endian compile */ +#if !defined(_BIG_ENDIAN) + #define _BIG_ENDIAN /* FAPI generic define for big endian */ +#endif +#elif defined(__little_endian__) /* is little endian compile */ +#if !defined(_LITTLE_ENDIAN) + #define _LITTLE_ENDIAN /* FAPI generic define for little endian */ +#endif +#endif + +/* Defines the method to indicate packed enums */ +#if defined(__TI_GNU_ATTRIBUTE_SUPPORT__) && (__TI_GNU_ATTRIBUTE_SUPPORT__==1) +/* --gcc option enabled so we can specify this */ +#define ATTRIBUTE_PACKED __attribute__((packed)) +#else +/* --gcc option not enabled so we cannot specify this */ +#define ATTRIBUTE_PACKED +#endif + + +#endif /* CGT_CCS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: CGT.CCS.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/CGT.gcc.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/CGT.gcc.h (revision 0) +++ firmware/App/Services/FlashAPI/CGT.gcc.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,48 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: CGT.gcc.h + * + * Description: gcc compiler specific info used by the F021 API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef CGT_GCC_H_ +#define CGT_GCC_H_ + +#if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) /* is big endian compile */ +#if !defined(_BIG_ENDIAN) + #define _BIG_ENDIAN /* FAPI generic define for big endian */ +#endif +#endif +#if (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) /* is little endian compile */ +#if !defined(_LITTLE_ENDIAN) + #define _LITTLE_ENDIAN /* FAPI generic define for little endian */ +#endif +#endif + +/* Defines the method to indicate packed enums */ +#define ATTRIBUTE_PACKED __attribute__((packed)) + +#endif /* CGT_GCC_H_ */ + +/********************************************************************************************************************** + * END OF FILE: CGT.GCC.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/Compatibility.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/Compatibility.h (revision 0) +++ firmware/App/Services/FlashAPI/Compatibility.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,54 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Compatibility.h + * + * Description: A set of macro defines to provide backwards compatibility to v1.x API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef COMPATIBILITY_H_ +#define COMPATIBILITY_H_ + +/*LDRA_NOANALYSIS*/ +/* This header file is intended for backwards compatibility only and is not meant to be MISRA-C compliant */ + +/* Define to provide backwards compatibility with Fapi_initializeFlashApi() */ +#define Fapi_initializeAPI(mControlRegister,mFrequency) (Fapi_initializeFlashBanks((mFrequency))) + +/* Define to provide backwards compatibility with Fapi_getFsmStatus() */ +#define Fapi_getFsmStatus() (FAPI_GET_FSM_STATUS) + +/* Define to provide backwards compatibility with Fapi_issueFsmSuspendCommand() */ +#define Fapi_issueFsmSuspendCommand() (FAPI_SUSPEND_FSM) + +/* Define to provide backwards compatibility with Fapi_writeEwaitValue() */ +#define Fapi_writeEwaitValue(mEwait) (FAPI_WRITE_EWAIT((mEwait))) + +/* Define to provide backwards compatibility with Fapi_checkFsmForReady() */ +#define Fapi_checkFsmForReady() (FAPI_CHECK_FSM_READY_BUSY) + + +#endif +/*LDRA_ANALYSIS*/ + +/********************************************************************************************************************** + * END OF FILE: Compatibility.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/Constants.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/Constants.h (revision 0) +++ firmware/App/Services/FlashAPI/Constants.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,67 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Constants.h + * + * Description: A set of Constant Values used by the Flash Memory Controller. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef CONSTANTS_H_ +#define CONSTANTS_H_ + +/* Specifies the bit mask for determining all address bits exclusive of the offest + imposed by the memory map register */ +#define F021_PROGRAM_ADDRESS_MASK 0x07FFFFFFU + +/* Specifies the Offset to the TI OTP */ +#define F021_PROGRAM_TIOTP_OFFSET 0xF0080000U + +/* FMC memory map defines */ +#define F021_FLASH_MAP_BEGIN 0x00000000U +#define F021_FLASH_MAP_END 0x00FFFFFFU +#define F021_OTP_MAP_BEGIN 0xF0000000U +#define F021_OTP_MAP_END 0xF000FFFFU +#define F021_OTPECC_MAP_BEGIN 0xF0040000U +#define F021_OTPECC_MAP_END 0xF0041FFFU +#define F021_EEPROMECC_MAP_BEGIN 0xF0100000U +#define F021_EEPROMECC_MAP_END 0xF01FFFFFU +#define F021_EEPROM_MAP_BEGIN 0xF0200000U +#define F021_EEPROM_MAP_END 0xF03FFFFFU +#define F021_FLASHECC_MAP_BEGIN 0xF0400000U +#define F021_FLASHECC_MAP_END 0xF04FFFFFU + +#define F021_CPU0_REGISTER_ADDRESS 0xFFF87000U + +/* Specific TI OTP Offsets */ +#define F021_TIOTP_PER_BANK_SIZE 0x2000U +#define F021_TIOTP_SETTINGS_BASE 0x150U +#define F021_TIOTP_BANK_SECTOR_OFFSET 0x158U + +/* Define to map the direct access to the TI OTP memory */ +#define F021_TIOTP_BASE_ADDRESS ((Fapi_TiOtpBytesType *)(F021_PROGRAM_TIOTP_OFFSET + F021_TIOTP_SETTINGS_BASE)) + +#define F021_MINIMUM_HCLK_FREQUENCY 10U + +#endif /* CONSTANTS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Constants.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/F021.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/F021.h (revision 0) +++ firmware/App/Services/FlashAPI/F021.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,52 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: F021.h + * + * Description: Main include file for F021 devices. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef F021_H_ +#define F021_H_ + +#if !defined(F021) + #define F021 +#endif + +#if !defined(_FMC) + #define _FMC +#endif + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +#include "../FlashAPI/Types.h" +#include "../FlashAPI/Helpers.h" +#include "../FlashAPI/Constants.h" +#include "../FlashAPI/Registers.h" +#include "../FlashAPI/FapiFunctions.h" +#include "../FlashAPI/Compatibility.h" + +#endif /*F021_H_*/ + +/********************************************************************************************************************** + * END OF FILE: F021.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/FapiFunctions.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/FapiFunctions.h (revision 0) +++ firmware/App/Services/FlashAPI/FapiFunctions.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,185 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: FapiFunctions.h + * + * Description: All the FAPI function extern definitions. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef FAPI_FUNCTIONS_H_ +#define FAPI_FUNCTIONS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flash C API functions*/ + +/* Flash State Machine commands */ +extern Fapi_StatusType Fapi_enableMainBankSectors(uint16_t u16SectorsEnables); + +extern Fapi_StatusType Fapi_enableEepromBankSectors( + uint32_t u32SectorsEnables_31_0, + uint32_t u32SectorsEnables_63_32 + ); + +extern Fapi_StatusType Fapi_enableFsmDoneEvent(void); + +extern Fapi_StatusType Fapi_disableFsmDoneEvent(void); + +extern Fapi_StatusType Fapi_initializeFlashBanks(uint32_t u32HclkFrequency); + +extern Fapi_StatusType Fapi_setActiveFlashBank(Fapi_FlashBankType oNewFlashBank); + +extern Fapi_StatusType Fapi_enableBanksForOtpWrite(uint8_t u8Banks); + +extern Fapi_StatusType Fapi_disableBanksForOtpWrite(void); + +/* Functions only available on devices with L2FMC Flash controllers */ +#if defined(_L2FMC) + +extern Fapi_StatusType Fapi_enableAutoEccCalculation(void); +extern Fapi_StatusType Fapi_disableAutoEccCalculation(void); + +#endif /* defined(_L2FMC) */ + +extern void Fapi_flushPipeline(void); + +extern uint32_t* Fapi_remapEccAddress(uint32_t u32EccAddress); + +extern uint32_t Fapi_remapMainAddress(uint32_t u32MainAddress); + +extern boolean_t Fapi_isAddressEcc(uint32_t u32Address); + +extern boolean_t Fapi_isAddressEEPROM(uint32_t u32Address); + +/* Async Commands */ +extern Fapi_StatusType Fapi_issueAsyncCommandWithAddress( + Fapi_FlashStateCommandsType oCommand, + uint32_t* pu32StartAddress + ); + +extern Fapi_StatusType Fapi_issueAsyncCommand(Fapi_FlashStateCommandsType oCommand); + +/* Info Commands */ +extern Fapi_LibraryInfoType Fapi_getLibraryInfo(void); +extern Fapi_DeviceInfoType Fapi_getDeviceInfo(void); +extern Fapi_StatusType Fapi_getBankSectors( + Fapi_FlashBankType oBank, + Fapi_FlashBankSectorsType* poFlashBankSectors + ); +extern uint32_t Fapi_getNumberOfBankSectors( uint32_t u32Bank); +/* Read commands */ +extern Fapi_StatusType Fapi_doBlankCheck( + uint32_t* pu32StartAddress, + uint32_t u32Length, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern Fapi_StatusType Fapi_doMarginRead( + uint32_t* pu32StartAddress, + uint32_t* pu32ReadBuffer, + uint32_t u32Length, + Fapi_FlashReadMarginModeType oReadMode + ); + +extern Fapi_StatusType Fapi_doVerify( + uint32_t* pu32StartAddress, + uint32_t u32Length, + uint32_t* pu32CheckValueBuffer, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern uint32_t Fapi_calculatePsa( + uint32_t* pu32StartAddress, + uint32_t u32Length, + uint32_t u32PsaSeed, + Fapi_FlashReadMarginModeType oReadMode + ); + +extern Fapi_StatusType Fapi_doPsaVerify( + uint32_t* pu32StartAddress, + uint32_t u32Length, + uint32_t u32PsaValue, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern Fapi_StatusType Fapi_doBlankCheckByByte( + uint8_t* pu8StartAddress, + uint32_t u32Length, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern Fapi_StatusType Fapi_doMarginReadByByte( + uint8_t* pu8StartAddress, + uint8_t* pu8ReadBuffer, + uint32_t u32Length, + Fapi_FlashReadMarginModeType oReadMode + ); + +extern Fapi_StatusType Fapi_doVerifyByByte( + uint8_t* pu8StartAddress, + uint32_t u32Length, + uint8_t* pu8CheckValueBuffer, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +/* Programming Commands */ +extern Fapi_StatusType Fapi_issueProgrammingCommand( + uint32_t* pu32StartAddress, + uint8_t* pu8DataBuffer, + uint8_t u8DataBufferSizeInBytes, + uint8_t* pu8EccBuffer, + uint8_t u8EccBufferSizeInBytes, + Fapi_FlashProgrammingCommandsType oMode + ); + +extern Fapi_StatusType Fapi_issueProgrammingCommandForEccAddresses( + uint32_t* pu32StartAddress, + uint8_t* pu8EccBuffer, + uint8_t u8EccBufferSizeInBytes + ); + +/* Utility Commands */ +extern Fapi_StatusType Fapi_waitDelay(volatile uint32_t u32WaitDelay); + +extern uint32_t Fapi_calculateFletcherChecksum( + uint32_t u32Address, + uint32_t u32Length + ); + +extern uint8_t Fapi_calculateEcc( + uint32_t u32Address, + uint64_t u64Data + ); + +/* User Defined Functions */ +extern Fapi_StatusType Fapi_serviceWatchdogTimer(void); + +#ifdef __cplusplus +} +#endif + +#endif /*FAPI_FUNCTIONS_H_*/ + +/********************************************************************************************************************** + * END OF FILE: FapiFunctions.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/Fapi_UserDefinedFunctions.c =================================================================== diff -u --- firmware/App/Services/FlashAPI/Fapi_UserDefinedFunctions.c (revision 0) +++ firmware/App/Services/FlashAPI/Fapi_UserDefinedFunctions.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,78 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.00.00 Build(000776) - Alpha + * Build Date: 2012-12-25 + * + * + * Description: Contains all user defined callback functions used by the F021 Flash API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* +* Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* +* Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the +* distribution. +* +* Neither the name of Texas Instruments Incorporated nor the names of +* its contributors may be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* +*/ + + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +#include + +/********************************************************************************************************************** + * Fapi_serviceWatchdogTimer + *********************************************************************************************************************/ +/*! Callback function to service watchdog timer. Used by the Blank, Read, and Verify fuctions. + * + * \param [in] none + * \param [out] none + * \return Fapi_StatusType + * \retval Fapi_Status_Success + * \note TI FEE API. + *********************************************************************************************************************/ +Fapi_StatusType Fapi_serviceWatchdogTimer(void) +{ + /* User to add their own watchdog servicing code here */ + + return(Fapi_Status_Success); +} + +/********************************************************************************************************************** + * END OF FILE: Fapi_UserDefinedFunctions.c + *********************************************************************************************************************/ + Index: firmware/App/Services/FlashAPI/Helpers.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/Helpers.h (revision 0) +++ firmware/App/Services/FlashAPI/Helpers.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,83 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Helpers.h + * + * Description: These helper Macros are to facilitate common operations. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef HELPERS_H_ +#define HELPERS_H_ + +/* Quick Register referencing macro */ +#define REGISTER(mRegister) (* (volatile uint32_t* )(mRegister)) + +/* Macro allowing a write to a locked FSM register */ +#define FAPI_WRITE_LOCKED_FSM_REGISTER(mRegister,mValue) \ + do { \ + FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x5U; \ + (mRegister) = (mValue); \ + FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x2U; \ + } while(0) + + + +/* These are helper functions to handle generic Big Endian/Little Endian code bases */ +#if defined(_LITTLE_ENDIAN) + #define EI16(idx) ((idx) ^ 1) + #define EI8(idx) ((idx) ^ 3) +#else + #define EI16(idx) (idx) + #define EI8(idx) (idx) +#endif + +/* These are helper functions to handle generic Big Endian/Little Endian code bases */ +#if defined(_L2FMC) && defined(_BIG_ENDIAN) +#define L2EI16(idx) ((idx) ^ 1) +#define L2EI8(idx) ((idx) ^ 3) +#else +#define L2EI16 EI16 +#define L2EI8 EI8 +#endif + +/* Macro that reads the FMSTAT register and indicates if the FSM is Ready or Busy */ +#define FAPI_CHECK_FSM_READY_BUSY \ + (FLASH_CONTROL_REGISTER->FmStat.FMSTAT_BITS.BUSY ? Fapi_Status_FsmBusy : Fapi_Status_FsmReady) + +/* Macro that clears the FSM_DONE event */ +#define FAPI_CLEAR_FSM_DONE_EVENT (FLASH_CONTROL_REGISTER->FedAcStatus.FEDACSTATUS_BITS.FSM_DONE = 1U) + +/* Macro that returns the value in the FMStat Register */ +#define FAPI_GET_FSM_STATUS (FLASH_CONTROL_REGISTER->FmStat.u32Register) + +/* Macro that issues a Suspend command to the FSM */ +#define FAPI_SUSPEND_FSM \ + FAPI_WRITE_LOCKED_FSM_REGISTER(FLASH_CONTROL_REGISTER->FsmExecute.FSM_EXECUTE_BITS.SUSPEND_NOW, 0x5U) + +/* Macro to set the EWAIT value */ +#define FAPI_WRITE_EWAIT(_mEwait) \ + FAPI_WRITE_LOCKED_FSM_REGISTER(FLASH_CONTROL_REGISTER->EepromConfig.EEPROM_CONFIG_BITS.EWAIT,(_mEwait)) + +#endif /* HELPERS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Helpers.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/Registers.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/Registers.h (revision 0) +++ firmware/App/Services/FlashAPI/Registers.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,92 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Registers.h + * + * Description: A complete mapping of the F021 Flash Registers facilitating named access to the F021 Flash Registers. + * This file will select the appropriate definitions based on selected compile Endianness. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef REGISTERS_H_ +#define REGISTERS_H_ + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +/*LDRA_NOANALYSIS*/ +/*LDRA_INSPECTED 42 S MR: 3.5 "Necessary for FMC register definitions" */ +/*LDRA_INSPECTED 74 S MR: 18.4 "Necessary for FMC register definitions" */ +#if defined(_LITTLE_ENDIAN) + #include "../FlashAPI/Registers_FMC_LE.h" +#else + #include "Registers_FMC_BE.h" +#endif +/*LDRA_ANALYSIS*/ + +/* Certain non released devices did not contain this information in the FMC */ +#if defined(_BIG_ENDIAN) && defined(__TI_TMS470_V7M3__) + #define WIDTH_MAIN_BANK 0x10U; + #define WIDTH_MAIN_ECC 0x2U; + #define WIDTH_EEPROM_BANK 0x10U; + #define WIDTH_EEPROM_ECC 0x2U; +#else + /* Macro to get the width of the Data on Main Banks */ + #define WIDTH_MAIN_BANK ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.MAIN_BANK_WIDTH \ + & (uint32_t)0x1C0U) >> 3U)) + /* Macro to get the width of the ECC on Main Banks */ + #define WIDTH_MAIN_ECC ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.MAIN_BANK_WIDTH \ + & (uint32_t)0x038U) >> 3U)) + /* Macro to get the width of the Data on EEPROM Bank */ + #define WIDTH_EEPROM_BANK ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.EE_BANK_WIDTH \ + & (uint32_t)0x0C0U) >> 3U)) + /* Macro to get the width of the ECC on EEPROM Bank */ + #define WIDTH_EEPROM_ECC ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.EE_BANK_WIDTH \ + & (uint32_t)0x018U) >> 3U)) +#endif + +/* Typedef pointer to Fapi_FmcRegistersType */ +typedef Fapi_FmcRegistersType* pFapi_FmcRegistersType; + +/* Typedef byte pointer to FWPWRITEx Registers */ +typedef volatile uint8_t FwpWriteByteAccessorType; +/* Typedef dword pointer to FWPWRITEx Registers */ +typedef volatile uint32_t FwpWriteDWordAccessorType; + +/* Offset from FMC base address to the start of the FWPWRITEx registers */ +#define FWP_WRITE_OFFSET 0x120U +/* Macro that creates a byte accessor pointer to the FWPWRITEx registers */ +#define FWPWRITE_BYTE_ACCESSOR_ADDRESS ((FwpWriteByteAccessorType*)(F021_CPU0_REGISTER_ADDRESS + 0x120U)) +/* Macro that creates a byte accessor pointer to the FWPWRITE_ECC register */ +#define FWPWRITE_ECC_BYTE_ACCESSOR_ADDRESS ((FwpWriteByteAccessorType*)(F021_CPU0_REGISTER_ADDRESS + 0x140U)) +/* Macro that creates a dword accessor pointer to the FWPWRITEx registers */ +#define FWPWRITE_DWORD_ACCESSOR_ADDRESS ((FwpWriteDWordAccessorType*)(F021_CPU0_REGISTER_ADDRESS + 0x120U)) + +/* Macro that creates an object pointer to the start of the FMC registers */ +#define FLASH_CONTROL_REGISTER ((pFapi_FmcRegistersType)(F021_CPU0_REGISTER_ADDRESS)) + +/* Macro that defines the base address for the FMC registers structure */ +#define F021_CPU0_BASE_ADDRESS ((Fapi_FmcRegistersType*)F021_CPU0_REGISTER_ADDRESS) + +#endif /* REGISTERS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Registers.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/Registers_FMC_LE.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/Registers_FMC_LE.h (revision 0) +++ firmware/App/Services/FlashAPI/Registers_FMC_LE.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,1592 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Registers_FMC_LE.h + * + * Description: A complete mapping of the F021 Flash Registers facilitating named access to the F021 Flash Registers. + * This file is for Little Endian devices. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef REGISTERS_LE_H_ +#define REGISTERS_LE_H_ + +/* Flash Configuration Registers */ + +/*! + Structure describing the Flash Wrapper registers allowing register and bit + level accesses. +*/ +#if defined(_L2FMC) +typedef volatile struct FMC_REGISTERS +{ + /*! + Defines whole and bit level accesses to the Read Control Register - 0x00 + */ + + union FRDCNTL + { + uint32_t u32Register; /* Read Control Register, bits 31:0 */ + struct + { + uint32_t PFUENA :1;/*!< Read Mode, bit 0 */ + uint32_t PFUENB :1;/*!< Address Setup Wait State Enable, bit 4 */ + uint32_t _FRDCNTL_Reserved_07_02 :6;/*!< Reserved, bits 7:5 */ + uint32_t RWAIT :4;/*!< Random Read Wait State, bits 11:8 */ + uint32_t _FRDCNTL_Reserved_31_12 :20;/*!< Reserved, bits 31:12 */ + } FRDCNTRL_BITS; + } FrdCntl; + + uint32_t _Reserved_04; /* Reserved Address Locations 0x04 */ + + /*! + Defines whole and bit level accesses to the Error Correction Control Register1 - 0x08 + */ + union FEDACCTRL1 + { + uint32_t u32Register; /* Error Correction Control Register1, bits 31:0 */ + struct + { + uint32_t _FEDACCTRL1_Reserved_03_00 :4;/* !< Reserved bit 03:00 */ + uint32_t EZCV :1;/*!< Zero Condition Valid, bit 4 */ + uint32_t EOCV :1;/*!< One Condition Valid, bit 5 */ + uint32_t _FEDACCTRL1_Reserved_31_06 :26;/*!< Reserved, bits 31:06 */ + + } FEDACCTRL1_BITS; + } FedAcCtrl1; + + + uint32_t _Reserved_0C; /* Reserved Address Locations 0x0C */ + + uint32_t _Reserved_10; /* Reserved Address Locations 0x10 */ + + /*! + Defines whole and bit level accesses to the Port A Error and Status Register - 0x14 + */ + union FEDAC_PASTATUS + { + uint32_t u32Register; /* Port A Error and Status Register, bits 31:0 */ + struct + { + uint32_t _FEDACPASTATUS_Reserved_09_00 :10; /* !< Reserved bits 09:00 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t _FEDACPASTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ + uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ + uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ + uint32_t _FEDACPASTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ + } FEDAC_PASTATUS_BITS; + } FedacPAStatus; + + /*! + Defines whole and bit level accesses to the Port B Error and Status Register - 0x18 + */ + union FEDAC_PBSTATUS + { + uint32_t u32Register; /* Port B Error and Status Register, bits 31:0 */ + struct + { + uint32_t _FEDACPBSTATUS_Reserved_09_00 :10; /*!< Reserved bits 09:00 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t _FEDACPBSTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ + uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ + uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ + uint32_t _FEDACPBSTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ + } FEDAC_PBSTATUS_BITS; + } FedacPBStatus; + + /*! + Defines whole and bit level accesses to the Global Error and Status Register - 0x1C + */ + union FEDAC_GBLSTATUS + { + uint32_t u32Register; /* Global Error and Status Register ,bits 31:0 */ + struct + { + uint32_t _FEDACGLBSTATUS_Reserved_12_00 :13; /*!< Reserved bits 12:00 */ + uint32_t IMPLICIT_UNC_ERR :1;/*!< UnCorrectable error during implicit two reads from OTP, bit 13 */ + uint32_t IMPLICIT_COR_ERR :1;/*!< Correctable error during implicit two reads from OTP, bit 14 */ + uint32_t RCR_ERR :1;/*!< L2FMC_Config_out port correction, bit 15 */ + uint32_t _FEDACGLBSTATUS_Reserved_23_16 :8; /*!< Reserved bits 23:16 */ + uint32_t FSM_DONE :1;/*!< FSM done event, bit 24 */ + uint32_t RVF_EVT :1;/*!< FSM Command Read_Verify failed error event, bit 25 */ + uint32_t _FEDACGLBSTATUS_Reserved_31_26 :6 ;/*!< Reserved bits 31:26 */ + } FEDAC_GLBSTATUS_BITS; + } FedacGblStatus; + + uint32_t _Reserved_20; /* Reserved Address Locations 0x20 */ + + /*! + Defines whole and bit level accesses to the Error Detection Sector Disable Register - 0x24 + */ + union FEDACSDIS + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID0 :6;/*!< Sector ID0 , bits 05:00 */ + uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ + uint32_t SectorID0_inverse :6;/*!< Sector ID0 Inverse, bits 13:08 */ + uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ + uint32_t SectorID1 :6;/*!< Sector ID1 , bits 21:16 */ + uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ + uint32_t SectorID1_inverse :6;/*!< Sector ID1 Inverse, bits 29:24 */ + uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ + } FEDACSDIS_BITS; + } FedAcsDis; + + /*! + Defines whole and bit level accesses to the Primary Address Tag Register - 0x28 + */ + union FPRIM_ADD_TAG + { + uint32_t u32Register; /* Primary Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :5;/*!< This field always returns 0000, bits 4:0 */ + uint32_t PRIM_ADD_TAG :27;/*!< Primary Address Tag Register, bits 31:5 */ + } FPRIM_ADD_TAG_BITS; + } FprimAddTag; + + /*! + Defines whole and bit level accesses to the Redundant Address Tag Register - 0x2C + */ + union FDUP_ADD_TAG + { + uint32_t u32Register; /* Duplicate Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :5;/*!< This field always returns 0000, bits 4:0 */ + uint32_t DUP_ADD_TAG :27;/*!< Duplicate Address Tag Register, bits 31:5 */ + } FDUP_ADD_TAG_BITS; + } FdupAddTag; + + /*! + Defines whole and bit level accesses to the Bank Sector Enable Register - 0x30 + */ + union FBPROT + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t PROTL1DIS :1; /*!< Level 1 Protection Disabled, bit 0 */ + uint32_t _FBPROT_Reserved_31_01 :31;/*!< Reserved, bits 31:1 */ + } FBPROT_BITS; + } Fbprot; + + /*! + Defines whole and bit level accesses to the Bank Protection Register - 0x34 + */ + union FBSE + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t BSE :16;/*!< Bank Sector Enable, bits 15:0 */ + uint32_t _FBSE_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FBSE_BITS; + } Fbse; + + /*! + Defines whole and bit level accesses to the Bank Busy Register - 0x38 + */ + union FBBUSY + { + uint32_t u32Register; /* Bank Busy Register, bits 31:0 */ + struct + { + uint32_t BUSY :8; /*!< Bank Busy, bits 7:0 */ + uint32_t _FBBUSY_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FBPROT_BITS; + } Fbbusy; + + /*! + Defines whole and bit level accesses to the Bank Access Control Register - 0x3C + */ + union FBAC + { + uint32_t u32Register; /* Bank Access Control Register, bits 31:0 */ + struct + { + uint32_t VREADS :8;/*!< VREAD Setup, bits 7:0 */ + uint32_t _FBAC_Reserved_15_08 :8;/*!< Reserved, bits 15:8 */ + uint32_t OTPPROTDIS :8;/*!< OTP Sector Protection Disable, bits 23:16 */ + uint32_t _FBAC_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBAC_BITS; + } Fbac; + + /*! + Defines whole and bit level accesses to the Bank Power mode Register - 0x40 + */ + union FBFALLBACK + { + uint32_t u32Register; /* Bank Fallback Power Register, bits 31:0 */ + struct + { + uint32_t BANKPWR0 :2;/*!< Bank 0 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR1 :2;/*!< Bank 1 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR2 :2;/*!< Bank 2 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR3 :2;/*!< Bank 3 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR4 :2;/*!< Bank 4 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR5 :2;/*!< Bank 5 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR6 :2;/*!< Bank 6 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR7 :2;/*!< Bank 7 Fallback Power Mode, bits 15:14 */ + uint32_t _FBAC_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FBFALLBACK_BITS; + } Fbfallback; + + /*! + Defines whole and bit level accesses to the Bank/Pump Ready Register - 0x44 + */ + union FBPRDY + { + uint32_t u32Register; /* Bank/Pump Ready Register, bits 31:0 */ + struct + { + uint32_t BANKRDY :8;/*!< Bank Ready, bits 7:0 */ + uint32_t _FBPRDY_Reserved_14_08 :7;/*!< Reserved, bits 14:8 */ + uint32_t PUMPRDY :1;/*!< Pump Ready, bit 15 */ + uint32_t BANKBUSY :8;/*!< Bank Busy with FSM, SW_INTF, CPU or PMT, bits 23:16 */ + uint32_t _FBPRDY_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBPRDY_BITS; + } Fbprdy; + + /*! + Defines whole and bit level accesses to the Pump Access Control Register 1 - 0x48 + */ + union FPAC1 + { + uint32_t u32Register; /* Flash Pump Access Control Register 1, bits 31:0 */ + struct + { + uint32_t PUMPPWR :1; /*!< Flash Charge Pump Fallback Power Mode, bit 0 */ + uint32_t _FPAC1_Reserved_15_01 :15;/*!< Reserved, bits 15:1 */ + uint32_t PSBEEP :12;/*!< Pump Sleep, bits 27:16 */ + uint32_t _FPAC1_Reserved_31_28 :4; /*!< Reserved, bits 31:28 */ + } FPAC1_BITS; + } Fpac1; + + + uint32_t _Reserved_4C; /* Reserved Address Locations 0x4C */ + + /*! + Defines whole and bit level accesses to the Module Access Control Register - 0x50 + */ + union FMAC + { + uint32_t u32Register; /* Module Access Control Register, bits 31:0 */ + struct + { + uint32_t BANK :3; /*!< Bank Enable, bits 2:0 */ + uint32_t _FMAC_Reserved_31_03 :29; /*!< Reserved, bits 31:3 */ + } FMAC_BITS; + } Fmac; + + /*! + Defines whole and bit level accesses to the Module Status Register - 0x54 + */ + union FMSTAT + { + uint32_t u32Register; /* Module Status Register, bits 31:0 */ + struct + { + uint32_t SLOCK :1; /*!< Sector Lock Status, bit 0 */ + uint32_t PSUSP :1; /*!< Program Suspend, bit 1 */ + uint32_t ESUSP :1; /*!< Erase Suspend, bit 2 */ + uint32_t VOLSTAT :1; /*!< Core Voltage Status, bit 3 */ + uint32_t CSTAT :1; /*!< Command Status, bit 4 */ + uint32_t INVDAT :1; /*!< Invalid Data, bit 5 */ + uint32_t PGM :1; /*!< Program Active, bit 6 */ + uint32_t ERS :1; /*!< Erase Active, bit 7 */ + uint32_t BUSY :1; /*!< Busy, bit 8 */ + uint32_t CV :1; /*!< Compact Verify, bit 9 */ + uint32_t EV :1; /*!< Erase verify, bit 10 */ + uint32_t PCV :1; /*!< Precondidition verify, bit 11 */ + uint32_t PGV :1; /*!< Program verify, bit 12 */ + uint32_t DBT :1; /*!< Disturbance Test Fail, bit 13 */ + uint32_t ILA :1; /*!< Illegal Address, bit 14 */ + uint32_t RVF :1; /*!< Read Verify Failure, bit 15 */ + uint32_t RDVER :1; /*!< Read Verify command currently underway, bit 16 */ + uint32_t RVSUSP :1; /*!< Read Verify Suspend, bit 17 */ + uint32_t _FMSTAT_Reserved_31_18 :14;/*!< Reserved, bits 31:18 */ + } FMSTAT_BITS; + } FmStat; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data MSW Register - 0x58 + */ + union FEMU_DMSW + { + uint32_t u32Register; /* EEPROM Emulation Data MSW Register, bits 31:0 */ + } FemuDmsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data LSW Register - 0x5C + */ + union FEMU_DLSW + { + uint32_t u32Register; /* EEPROM Emulation Data LSW Register, bits 31:0 */ + } FemuDlsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation ECC Register - 0x60 + */ + union FEMU_ECC + { + uint32_t u32Register; /* EEPROM Emulation ECC Register, bits 31:0 */ + struct + { + uint32_t EMU_ECC :8; /*!< EEPROM Emulation ECC, bits 7:0 */ + uint32_t _FEMU_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FEMU_ECC_BITS; + } FemuEcc; + + uint32_t _Reserved_64; /* Reserved Address Locations 0x64 */ + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Address Register - 0x68 + */ + union FEMU_ADDR + { + uint32_t u32Register; /* EEPROM Emulation Address, bits 31:0 */ + struct + { + uint32_t _FEMU_ADDR_Reserved_02_00 :3;/*!< Reserved, bits 02:00 */ + uint32_t EMU_ADDR :29;/*!< EEPROM Emulation Address, bits 31:03 */ + } FEMU_ADDR_BITS; + } FemuAddr; + + /*! + Defines whole and bit level accesses to the Diagnostic Control Register - 0x6C + */ + union FDIAGCTRL + { + uint32_t u32Register; /* Diagnostic Control Register, bits 31:0 */ + struct + { + uint32_t DIAGMODE :3;/*!< Diagnostic Mode, bits 2:0 */ + uint32_t _FDIAGCTRL_Reserved_07_03 :5;/*!< Reserved, bits 7:3 */ + uint32_t DIAG_BUF_SEL :3;/*!< Diagnostic Buffer Select, bits 10:8 */ + uint32_t _FDIAGCTRL_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ + uint32_t DIAG_EN_KEY :4;/*!< Diagnostic Enable Key, bits 19:16 */ + uint32_t _FDIAGCTRL_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t DIAG_TRIG :1;/*!< Diagnostic Trigger, bit 24 */ + uint32_t _FDIAGCTRL_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FDIAGCTRL_BITS; + } FdiagCtrl; + + uint32_t _Reserved_70; /* Reserved Address Locations 0x70 */ + + /*! + Defines whole and bit level accesses to the Uncorrected Raw Data High Register - 0x70 + */ + union FRAW_ADDR + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + struct + { + uint32_t _FRAW_ADDR_Reserved_04_00 :5;/*!< Reserved, bits 04:00 */ + uint32_t RAW_ADDR :27;/*!< EEPROM Emulation Address, bits 31:05 */ + } FRAW_ADDR_BITS; + } FrawAddr; + + uint32_t _Reserved_78; /* Reserved Address Locations 0x78 */ + + /*! + Defines whole and bit level accesses to the Parity Override Register - 0x7C + */ + union FPAR_OVR + { + uint32_t u32Register; /* Parity Override, bits 31:0 */ + struct + { + uint32_t DAT_INV_PAR :8; /*!< Data Odd Parity, bits 7:0 */ + uint32_t _FPAR_OVR_Reserved_08 :1; /*!< Reserved , bit 8 */ + uint32_t PAR_OVR_KEY :3; /*!< Parity Override Key, bits 11:9 */ + uint32_t BUS_PAR_DIS :4; /*!< Disable bus parity, bits 15:12 */ + uint32_t BNK_INV_PAR :1; /*!< Buffer Invert Parity, bit 16 */ + uint32_t _FPAR_OVR_Reserved_31_17 :15;/*!< Reserved, bits 31:17 */ + } FPAR_OVR_BITS; + } FparOvr; + + + uint32_t _Reserved_80_B0[13];/* Reserved Address Locations 0x80 - 0xB0 */ + + /*! + Defines whole and bit level accesses to the Reset Config and JSM Key Valid Register - 0xB4 + */ + union RCR_JSM_VALID + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + struct + { + uint32_t RCR_VALID :1;/*!< RCR Key Valid, bits 0 */ + uint32_t JSM_VALID :1;/*!< JSM Key Valid, bits 1 */ + uint32_t _RCR_JSM_VALID_Reserved_31_02 :30;/*!< Reserved , bits 31:02 */ + } RCR_JSM_VALID_BITS; + } RcrJsmValid; + + /*! + Defines whole and bit level accesses to the Crossbar access time threshold Register - 0xB8 + */ + union ACC_THRESHOLD + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + struct + { + uint32_t ACC_THRESH_CNT :12;/*!< Crossbar access time threshold count, bits 11:00 */ + uint32_t _ACC_THRESHOLD_Reserved_31_12 :20;/*!< Reserved , bits 31:12 */ + } ACC_THRESHOLD_BITS; + } AccThreshold; + + uint32_t _Reserved_BC;/* Reserved Address Locations 0xBC */ + + /*! + Defines whole and bit level accesses to the EEPROM Error Detection Sector Disable Register - 0xC0 + */ + union FEDACSDIS2 + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID2 :6;/*!< Sector ID2 , bits 05:00 */ + uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ + uint32_t SectorID2_inverse :6;/*!< Sector ID2 Inverse, bits 13:08 */ + uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ + uint32_t SectorID3 :6;/*!< Sector ID3 , bits 21:16 */ + uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ + uint32_t SectorID3_inverse :6;/*!< Sector ID3 Inverse, bits 29:24 */ + uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ + } FEDACSDIS_BITS; + } FedAcsDis2; + + uint32_t _Reserved_C4_CC[3];/* Reserved Address Locations 0xC4-0xCC */ + + /*! + Defines whole and bit level accesses to the RCR Lower word - 0xD0 + */ + union RCRVALUE0 + { + uint32_t u32Register; /* RCR Lower word, bits 31:0 */ + } RcrValue0; + + /*! + Defines whole and bit level accesses to the RCR Upper word - 0xD4 + */ + union RCRVALUE1 + { + uint32_t u32Register; /* RCR Upper word, bits 31:0 */ + } RcrValue1; + + uint32_t _Reserved_D8_DC[2];/* Reserved Address Locations 0xD8-0xDC */ + + /*! + Defines whole and bit level accesses to the JSM Key0 - 0xE0 + */ + union JSMKEY0 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey0; + + /*! + Defines whole and bit level accesses to the JSM Key1 - 0xE4 + */ + union JSMKEY1 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey1; + + + /*! + Defines whole and bit level accesses to the JSM Key2 - 0xE8 + */ + union JSMKEY2 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey2; + + + /*! + Defines whole and bit level accesses to the JSM Key3 - 0xEC + */ + union JSMKEY3 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey3; + + uint32_t _Reserved_F0_10C[8];/* Reserved Address Locations 0xF0 - 0x10C */ + + + /*! + Defines whole and bit level accesses to the Bank Addr Register - 0x110 + */ + union FADDR + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } Faddr; + + uint32_t _Reserved_114_118[2]; /* Reserved Address Locations 0x114-0x118 */ + + union FTCTRL + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t Reserved_23_00 :24; + uint32_t AutoCalc_EN :1;/*!< Sector ID3 Inverse, bits 29:24 */ + uint32_t Reserved_31_30 :7;/*!< Reserved bits, 31:30 */ + } FTCTRL_BITS; + } Ftctrl; + + /*! + Defines whole and bit level accesses to the FWPWRITE0 Register - 0x120 + */ + union FWPWRITE0 + { + uint32_t u32Register; /* FWPWRITE0 Register, bits 31:0 */ + } Fwpwrite0; + + /*! + Defines whole and bit level accesses to the FWPWRITE1 Register - 0x124 + */ + union FWPWRITE1 + { + uint32_t u32Register; /* FWPWRITE1 Register, bits 31:0 */ + } Fwpwrite1; + + /*! + Defines whole and bit level accesses to the FWPWRITE2 Register - 0x128 + */ + union FWPWRITE2 + { + uint32_t u32Register; /* FWPWRITE2 Register, bits 31:0 */ + } Fwpwrite2; + + /*! + Defines whole and bit level accesses to the FWPWRITE3 Register - 0x12C + */ + union FWPWRITE3 + { + uint32_t u32Register; /* FWPWRITE3 Register, bits 31:0 */ + } Fwpwrite3; + + /*! + Defines whole and bit level accesses to the FWPWRITE4 Register - 0x130 + */ + union FWPWRITE4 + { + uint32_t u32Register; /* FWPWRITE4 Register, bits 31:0 */ + } Fwpwrite4; + + /*! + Defines whole and bit level accesses to the FWPWRITE5 Register - 0x134 + */ + union FWPWRITE5 + { + uint32_t u32Register; /* FWPWRITE5 Register, bits 31:0 */ + } Fwpwrite5; + + /*! + Defines whole and bit level accesses to the FWPWRITE6 Register - 0x138 + */ + union FWPWRITE6 + { + uint32_t u32Register; /* FWPWRITE6 Register, bits 31:0 */ + } Fwpwrite6; + + /*! + Defines whole and bit level accesses to the FWPWRITE7 Register - 0x13C + */ + union FWPWRITE7 + { + uint32_t u32Register; /* FWPWRITE7 Register, bits 31:0 */ + } Fwpwrite7; + + /*! + Defines whole and bit level accesses to the FWPWRITE_ECC Register - 0x140 + */ + union FWPWRITE_ECC + { + uint32_t u32Register; /* FWPWRITE_ECC Register, bits 31:0 */ + struct + { + uint32_t WPDATA_287_256; /*!< WPDATA[287:256], bits 31:0 */ + } FWPWRITE_ECC_BITS; + struct + { + uint32_t u8Bytes31_24:8; + uint32_t u8Bytes23_16:8; + uint32_t u8Bytes15_08:8; + uint32_t u8Bytes07_00:8; + } FWPWRITE_ECC_BYTES; + } FwpwriteEcc; + + uint32_t _Reserved_144_208[50]; /* Reserved Address Locations 0x144-0x208 */ + + /*! + Defines whole and bit level accesses to the FSM Command Register - 0x20C + */ + union FSM_COMMAND + { + uint32_t u32Register; /* FSM Command, bits 31:0 */ + struct + { + uint32_t FSMCMD :6; /*!< Flash State Machine Command, bits 5:0 */ + uint32_t _FSM_COMMAND_Reserved_31_06 :26;/*!< Reserved, bits 31:6 */ + } FSM_COMMAND_BITS; + } FsmCommand; + + uint32_t _Reserved_210_284[30]; /* Reserved Address Locations 0x210-0x284 */ + + /*! + Defines whole and bit level accesses to the FSM Register Write Enable- 0x288 + */ + union FSM_WR_ENA + { + uint32_t u32Register; /* FSM Register Write Enable, bits 31:0 */ + struct + { + uint32_t WR_ENA :3; /*!< FSM Write Enable, bits 2:0 */ + uint32_t _FSM_WR_ENA_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ + } FSM_WR_ENA_BITS; + } FsmWrEna; + + uint32_t _Reserved_28C_2A0[6]; /* Reserved Address Locations 0x28C-0x2A0 */ + + /*! + Defines whole and bit level accesses to the FSM Sector Register - 0x2A4 + */ + union FSM_SECTOR + { + uint32_t u32Register; /* FSM Sector, bits 31:0 */ + struct + { + uint32_t SEC_OUT :4; /*!< Sector from Address decoder, bits 3:0 */ + uint32_t SECTOR :4; /*!< Current sector used by FSM, bits 7:4 */ + uint32_t FLEE_SECT_ETXN :8; /*!< FLEE Sector Extension bits, bits 15:8 */ + uint32_t SECT_ERASED :16;/*!< Sectors Erased, bits 31:16 */ + } FSM_SECTOR_BITS; + } FsmSector; + + uint32_t _Reserved_2A8_2B0[3]; /* Reserved Address Locations 0x2A8-0x2B0 */ + + + /*! + Defines whole and bit level accesses to the FSM Command Execute Register - 0x2B4 + */ + union FSM_EXECUTE + { + uint32_t u32Register; /* FSM Command Execute, bits 31:0 */ + struct + { + uint32_t FSMEXECUTE :5; /*!< FSM Command Execute, bits 4:0 */ + uint32_t _FSM_EXECUTE_Reserved_15_05 :11;/*!< Reserved, bits 15:5 */ + uint32_t SUSPEND_NOW :4; /*!< FSM Command Suspend, bits 19:16 */ + uint32_t _FSM_EXECUTE_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + } FSM_EXECUTE_BITS; + } FsmExecute; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation configuration Register - 0x2B8 + */ + union EEPROM_CONFIG + { + uint32_t u32Register; /* EEPROM Emulation configuration, bits 31:0 */ + struct + { + uint32_t _EEPROM_CONFIG_Reserved_15_00 :16;/*!< Reserved, bits 15:0 */ + uint32_t EWAIT :4; /*!< EEPROM Wait state Counter, bits 19:16 */ + uint32_t _EEPROM_CONFIG_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + } EEPROM_CONFIG_BITS; + } EepromConfig; + + uint32_t _Reserved_2BC; /* Reserved Address Locations 0x2BC */ + + /*! + Defines whole and bit level accesses to the FSM Sector1 Register - 0x2C0 + */ + union FSM_SECTOR_1 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector1; + + /*! + Defines whole and bit level accesses to the FSM Sector2 Register - 0x2C4 + */ + union FSM_SECTOR_2 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector2; + + uint32_t _Reserved_2C8_3FC[78];/* Reserved Address Locations 0x2C8 - 0x3FC */ + + + /*! + Defines whole and bit level accesses to the FCFG BANK Register - 0x400 + */ + union FCFG_BANK_1 + { + uint32_t u32Register; /* Flash Bank configuration, bits 31:0 */ + struct + { + uint32_t _FCFG_BANK_Reserved_3_0 :4; /*!< Reserved bits 3:0 */ + uint32_t MAIN_BANK_WIDTH :12;/*!< MAIN_BANK_WIDTH, bits 15:4 */ + uint32_t _FCFG_BANK_Reserved_19_16 :4; /*!< Reserved bits 19:16 */ + uint32_t EE_BANK_WIDTH :12;/*!< EE_BANK_WIDTH, bits 31:20 */ + } FCFG_BANK_BITS; + } FcfgBank; + + }Fapi_FmcRegistersType; +#else +typedef volatile struct FMC_REGISTERS +{ + /*! + Defines whole and bit level accesses to the Read Control Register - 0x00 + */ + union FRDCNTL + { + uint32_t u32Register; /* Read Control Register, bits 31:0 */ + struct + { + uint32_t ENPIPE :1;/*!< Read Mode, bit 0 */ + uint32_t _FRDCNTL_Reserved_03_01 :3;/*!< Reserved, bits 3:1 */ + uint32_t ASWSTEN :1;/*!< Address Setup Wait State Enable, bit 4 */ + uint32_t _FRDCNTL_Reserved_07_05 :3;/*!< Reserved, bits 7:5 */ + uint32_t RWAIT :4;/*!< Random Read Wait State, bits 11:8 */ + uint32_t _FRDCNTL_Reserved_31_12 :20;/*!< Reserved, bits 31:12 */ + } FRDCNTRL_BITS; + } FrdCntl; + + uint32_t _Reserved_04; /* Reserved Address Locations 0x04 */ + + /*! + Defines whole and bit level accesses to the Error Correction Control Register1 - 0x08 + */ + union FEDACCTRL1 + { + uint32_t u32Register; /* Error Correction Control Register1, bits 31:0 */ + struct + { + uint32_t EDACEN :4;/*!< Error Detection and Correction Enable, bits 3:0 */ + uint32_t EZCV :1;/*!< Zero Condition Valid, bit 4 */ + uint32_t EOCV :1;/*!< One Condition Valid, bit 5 */ + uint32_t _FEDACCTRL1_Reserved_07_06 :2;/*!< Reserved, bits 7:6 */ + uint32_t EPEN :1;/*!< Error Profiling Enable, bit 8 */ + uint32_t EZFEN :1;/*!< Error on Zero Fail Enable, bit 9 */ + uint32_t EOFEN :1;/*!< Error on One Fail Enable, bit 10 */ + uint32_t _FEDACCTRL1_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ + uint32_t EDACMODE :4;/*!< Error Correction Mode, bits 19:16 */ + uint32_t _FEDACCTRL1_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t SUSP_IGNR :1;/*!< Suspend Ignore, bit 24 */ + uint32_t _FEDACCTRL1_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FEDACCTRL1_BITS; + } FedAcCtrl1; + + /*! + Defines whole and bit level accesses to the Error Correction Control Register2 - 0x0C + */ + union FEDACCTRL2 + { + uint32_t u32Register; /* Error Correction Control Register2, bits 31:0 */ + struct + { + uint32_t SEC_THRESHOLD :16;/*!< Single Error Correction Threshold, bits 15:0 */ + uint32_t _FEDACCTRL2_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FEDACCTRL2_BITS; + } FedAcCtrl2; + + /*! + Defines whole and bit level accesses to the Error Correction Counter Register - 0x10 + */ + union FCOR_ERR_CNT + { + uint32_t u32Register; /* Error Correction Counter Register, bits 31:0 */ + struct + { + uint32_t FERRCNT :16;/*!< Correctable Error Counter, bits 15:0 */ + uint32_t _FCOR_ERR_CNT_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FCOR_ERR_CNT_BITS; + } FcorErrCnt; + + /*! + Defines whole and bit level accesses to the Correctable Error Address Register - 0x14 + */ + union FCOR_ERR_ADD + { + uint32_t u32Register; /* Correctable Error Address Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t COR_ERR_ADD :29;/*!< Correctable Error Address, bits 31:3 */ + } FCOR_ERR_ADD_BITS; + } FcorErrAdd; + + /*! + Defines whole and bit level accesses to the Correctable Error Position Register - 0x18 + */ + union FCOR_ERR_POS + { + uint32_t u32Register; /* Correctable Error Position Register, bits 31:0 */ + struct + { + uint32_t ERR_POS :8; /*!< Single Error Position, bits 7:0 */ + uint32_t TYPE :1; /*!< Error Type, bit 8 */ + uint32_t BUS2 :1; /*!< Bus 2 error position, bit 9 */ + uint32_t _FCOR_ERR_POS_Reserved_31_10 :22;/*!< Reserved, bits 31:10 */ + } FCOR_ERR_POS_BITS; + } FcorErrPos; + + /*! + Defines whole and bit level accesses to the Error Status Register - 0x1C + */ + union FEDACSTATUS + { + uint32_t u32Register; /* Error Status Register, bits 31:0 */ + struct + { + uint32_t ERR_PRF_FLG :1;/*!< Error Profiling Status Flag, bit 0 */ + uint32_t ERR_ZERO_FLG :1;/*!< Error On Zero Fail Status Flag, bit 1 */ + uint32_t ERR_ONE_FLG :1;/*!< Error On One Fail Status Flag, bit 2 */ + uint32_t D_COR_ERR :1;/*!< Diagnostic Correctable Error Status Flag, bit 3 */ + uint32_t _FEDACSTATUS_Reserved_7_4 :4;/*!< Reserved, bits 7:4 */ + uint32_t B1_UNC_ERR :1;/*!< Bus1 Uncorrectable Error Flag, bit 8 */ + uint32_t _FEDACSTATUS_Reserved_9 :1;/*!< Reserved, bit 9 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error, bit 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t D_UNC_ERR :1;/*!< Diagnostic Un-correctable Error Status Flag, bit 12 */ + uint32_t _FEDACSTATUS_Reserved_15_13 :3;/*!< Reserved, bits 15:13 */ + uint32_t B2_COR_ERR :1;/*!< Bus2 Correctable Error, bit 16 */ + uint32_t B2_UNC_ERR :1;/*!< Bus2 Uncorrectable Error, bit 17 */ + uint32_t ECC_B2_MAL_ERR :1;/*!< Bus2 ECC Malfunction Status Flag, bit 18 */ + uint32_t COMB2_MAL_G :1;/*!< Bus2 Compare Malfunction Flag, bit 19 */ + uint32_t _FEDACSTATUS_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t FSM_DONE :1;/*!< FSM is Finished, bit 24 */ + uint32_t _FEDACSTATUS_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FEDACSTATUS_BITS; + } FedAcStatus; + + /*! + Defines whole and bit level accesses to the Un-correctable Error Address Register - 0x20 + */ + union FUNC_ERR_ADD + { + uint32_t u32Register; /* Error Status Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t UNC_ERR_ADD :29;/*!< Un-correctable Error Address, bits 31:3 */ + } FUNC_ERR_ADD_BITS; + } FuncErrAdd; + + /*! + Defines whole and bit level accesses to the Error Detection Sector Disable Register - 0x24 + */ + union FEDACSDIS + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID0 :4;/*!< Sector ID0 , bits 3:0 */ + uint32_t _FEDACSDIS_Reserved_04 :1;/*!< Reserved, bit 4 */ + uint32_t BankID0 :3;/*!< Bank ID0 , bits 7:5 */ + uint32_t SectorID0_inverse :4;/*!< Sector ID0 Inverse, bits 11:8 */ + uint32_t _FEDACSDIS_Reserved_12 :1;/*!< Reserved, bit 12 */ + uint32_t BankID0_inverse :3;/*!< Bank ID0 Inverse, bits 15:13 */ + uint32_t SectorID1 :4;/*!< Sector ID1 , bits 19:16 */ + uint32_t _FEDACSDIS_Reserved_20 :1;/*!< Reserved, bit 20 */ + uint32_t BankID1 :3;/*!< Bank ID1 , bits 23:21 */ + uint32_t SectorID1_inverse :4;/*!< Sector ID1 Inverse, bits 27:24 */ + uint32_t _FEDACSDIS_Reserved_28 :1;/*!< Reserved, bit 28 */ + uint32_t BankID1_inverse :3;/*!< Bank ID1 Inverse, bits 31:29 */ + } FEDACSDIS_BITS; + } FedAcsDis; + + /*! + Defines whole and bit level accesses to the Primary Address Tag Register - 0x28 + */ + union FPRIM_ADD_TAG + { + uint32_t u32Register; /* Primary Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :4;/*!< This field always returns 0000, bits 3:0 */ + uint32_t PRIM_ADD_TAG :28;/*!< Primary Address Tag Register, bits 31:4 */ + } FPRIM_ADD_TAG_BITS; + } FprimAddTag; + + /*! + Defines whole and bit level accesses to the Redundant Address Tag Register - 0x2C + */ + union FDUP_ADD_TAG + { + uint32_t u32Register; /* Duplicate Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :4;/*!< This field always returns 0000, bits 3:0 */ + uint32_t DUP_ADD_TAG :28;/*!< Primary Address Tag Register, bits 31:4 */ + } FDUP_ADD_TAG_BITS; + } FdupAddTag; + + /*! + Defines whole and bit level accesses to the Bank Sector Enable Register - 0x30 + */ + union FBPROT + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t PROTL1DIS :1; /*!< Level 1 Protection Disabled, bit 0 */ + uint32_t _FBPROT_Reserved_31_01 :31;/*!< Reserved, bits 31:1 */ + } FBPROT_BITS; + } Fbprot; + + /*! + Defines whole and bit level accesses to the Bank Protection Register - 0x34 + */ + union FBSE + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t BSE :16;/*!< Bank Sector Enable, bits 15:0 */ + uint32_t _FBSE_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FBSE_BITS; + } Fbse; + + /*! + Defines whole and bit level accesses to the Bank Busy Register - 0x38 + */ + union FBBUSY + { + uint32_t u32Register; /* Bank Busy Register, bits 31:0 */ + struct + { + uint32_t BUSY :8; /*!< Bank Busy, bits 7:0 */ + uint32_t _FBBUSY_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FBPROT_BITS; + } Fbbusy; + + /*! + Defines whole and bit level accesses to the Bank Access Control Register - 0x3C + */ + union FBAC + { + uint32_t u32Register; /* Bank Access Control Register, bits 31:0 */ + struct + { + uint32_t VREADS :8;/*!< VREAD Setup, bits 7:0 */ + uint32_t BAGP :8;/*!< Bank Active Grace Period, bits 15:8 */ + uint32_t OTPPROTDIS :8;/*!< OTP Sector Protection Disable, bits 23:16 */ + uint32_t _FBAC_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBAC_BITS; + } Fbac; + + /*! + Defines whole and bit level accesses to the Bank Fallback Power Register - 0x40 + */ + union FBFALLBACK + { + uint32_t u32Register; /* Bank Fallback Power Register, bits 31:0 */ + struct + { + uint32_t BANKPWR0 :2;/*!< Bank 0 Fallback Power Mode, bits 1:0 */ + uint32_t BANKPWR1 :2;/*!< Bank 1 Fallback Power Mode, bits 3:2 */ + uint32_t BANKPWR2 :2;/*!< Bank 2 Fallback Power Mode, bits 5:4 */ + uint32_t BANKPWR3 :2;/*!< Bank 3 Fallback Power Mode, bits 7:6 */ + uint32_t BANKPWR4 :2;/*!< Bank 4 Fallback Power Mode, bits 9:8 */ + uint32_t BANKPWR5 :2;/*!< Bank 5 Fallback Power Mode, bits 11:10 */ + uint32_t BANKPWR6 :2;/*!< Bank 6 Fallback Power Mode, bits 13:12 */ + uint32_t BANKPWR7 :2;/*!< Bank 7 Fallback Power Mode, bits 15:14 */ + uint32_t REG_PWRSAV :4;/*!< Power saving clocking control, bits 19:16 */ + uint32_t _FBAC_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t FSM_PWRSAV :4;/*!< Power saving clocking control, bits 27:24 */ + uint32_t _FBAC_Reserved_31_28 :4;/*!< Reserved, bits 31:28 */ + } FBFALLBACK_BITS; + } Fbfallback; + + /*! + Defines whole and bit level accesses to the Bank/Pump Ready Register - 0x44 + */ + union FBPRDY + { + uint32_t u32Register; /* Bank/Pump Ready Register, bits 31:0 */ + struct + { + uint32_t BANKRDY :8;/*!< Bank Ready, bits 7:0 */ + uint32_t _FBPRDY_Reserved_14_08 :7;/*!< Reserved, bits 14:8 */ + uint32_t PUMPRDY :1;/*!< Pump Ready, bit 15 */ + uint32_t BANKBUSY :8;/*!< Bank Busy with FSM, SW_INTF, CPU or PMT, bits 23:16 */ + uint32_t _FBPRDY_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBPRDY_BITS; + } Fbprdy; + + /*! + Defines whole and bit level accesses to the Pump Access Control Register 1 - 0x48 + */ + union FPAC1 + { + uint32_t u32Register; /* Flash Pump Access Control Register 1, bits 31:0 */ + struct + { + uint32_t PUMPPWR :1; /*!< Flash Charge Pump Fallback Power Mode, bit 0 */ + uint32_t _FPAC1_Reserved_15_01 :15;/*!< Reserved, bits 15:1 */ + uint32_t PSLEEP :11;/*!< Pump Sleep, bits 26:16 */ + uint32_t _FPAC1_Reserved_31_27 :5; /*!< Reserved, bits 31:27 */ + } FPAC1_BITS; + } Fpac1; + + /*! + Defines whole and bit level accesses to the Pump Access Control Register 2 - 0x4C + */ + union FPAC2 + { + uint32_t u32Register; /* Flash Pump Access Control Register 2, bits 31:0 */ + struct + { + uint32_t PAGP :16;/*!< Pump Active Grace Period, bits 15:0 */ + uint32_t _FPAC2_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FPAC2_BITS; + } Fpac2; + + /*! + Defines whole and bit level accesses to the Module Access Control Register - 0x50 + */ + union FMAC + { + uint32_t u32Register; /* Module Access Control Register, bits 31:0 */ + struct + { + uint32_t BANK :3; /*!< Bank Enable, bits 2:0 */ + uint32_t _FMAC_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ + } FMAC_BITS; + } Fmac; + + /*! + Defines whole and bit level accesses to the Module Status Register - 0x54 + */ + union FMSTAT + { + uint32_t u32Register; /* Module Status Register, bits 31:0 */ + struct + { + uint32_t SLOCK :1; /*!< Sector Lock Status, bit 0 */ + uint32_t PSUSP :1; /*!< Program Suspend, bit 1 */ + uint32_t ESUSP :1; /*!< Erase Suspend, bit 2 */ + uint32_t VOLSTAT :1; /*!< Core Voltage Status, bit 3 */ + uint32_t CSTAT :1; /*!< Command Status, bit 4 */ + uint32_t INVDAT :1; /*!< Invalid Data, bit 5 */ + uint32_t PGM :1; /*!< Program Active, bit 6 */ + uint32_t ERS :1; /*!< Erase Active, bit 7 */ + uint32_t BUSY :1; /*!< Busy, bit 8 */ + uint32_t CV :1; /*!< Compact Verify, bit 9 */ + uint32_t EV :1; /*!< Erase verify, bit 10 */ + uint32_t PCV :1; /*!< Precondidition verify, bit 11 */ + uint32_t PGV :1; /*!< Program verify, bit 12 */ + uint32_t DBT :1; /*!< Disturbance Test Fail, bit 13 */ + uint32_t ILA :1; /*!< Illegal Address, bit 14 */ + uint32_t RVF :1; /*!< Read Verify Failure, bit 15 */ + uint32_t RDVER :1; /*!< Read Verify command currently underway, bit 16 */ + uint32_t RVSUSP :1; /*!< Read Verify Suspend, bit 17 */ + uint32_t _FMSTAT_Reserved_31_18 :14;/*!< Reserved, bits 31:18 */ + } FMSTAT_BITS; + } FmStat; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data MSW Register - 0x58 + */ + union FEMU_DMSW + { + uint32_t u32Register; /* EEPROM Emulation Data MSW Register, bits 31:0 */ + } FemuDmsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data LSW Register - 0x5C + */ + union FEMU_DLSW + { + uint32_t u32Register; /* EEPROM Emulation Data LSW Register, bits 31:0 */ + } FemuDlsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation ECC Register - 0x60 + */ + union FEMU_ECC + { + uint32_t u32Register; /* EEPROM Emulation ECC Register, bits 31:0 */ + struct + { + uint32_t EMU_ECC :8; /*!< EEPROM Emulation ECC, bits 7:0 */ + uint32_t _FEMU_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FEMU_ECC_BITS; + } FemuEcc; + + uint32_t _Reserved_64; /* Reserved Address Locations 0x64 */ + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Address Register - 0x68 + */ + union FEMU_ADDR + { + uint32_t u32Register; /* EEPROM Emulation Address, bits 31:0 */ + struct + { + uint32_t EMU_ADDR :22;/*!< EEPROM Emulation Address, bits 21:0 */ + uint32_t _FEMU_ADDR_Reserved_31_22 :10;/*!< Reserved, bits 31:22 */ + } FEMU_ADDR_BITS; + } FemuAddr; + + /*! + Defines whole and bit level accesses to the Diagnostic Control Register - 0x6C + */ + union FDIAGCTRL + { + uint32_t u32Register; /* Diagnostic Control Register, bits 31:0 */ + struct + { + uint32_t DIAGMODE :3;/*!< Diagnostic Mode, bits 2:0 */ + uint32_t _FDIAGCTRL_Reserved_07_03 :5;/*!< Reserved, bits 7:3 */ + uint32_t DIAG_BUF_SEL :2;/*!< Diagnostic Buffer Select, bits 9:8 */ + uint32_t _FDIAGCTRL_Reserved_11_10 :2;/*!< Reserved, bits 11:10 */ + uint32_t DIAG_ECC_SEL :3;/*!< Diagnostic SECDED Select, bits 14-12 */ + uint32_t _FDIAGCTRL_Reserved_15 :1;/*!< Reserved, bit 15 */ + uint32_t DIAG_EN_KEY :4;/*!< Diagnostic Enable Key, bits 19:16 */ + uint32_t _FDIAGCTRL_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t DIAG_TRIG :1;/*!< Diagnostic Trigger, bit 24 */ + uint32_t _FDIAGCTRL_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FDIAGCTRL_BITS; + } FdiagCtrl; + + /*! + Defines whole and bit level accesses to the Uncorrected Raw Data High Register - 0x70 + */ + union FRAW_DATAH + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + } FrawDatah; + + /*! + Defines whole and bit level accesses to the Uncorrected Raw Data Low Register - 0x74 + */ + union FRAW_DATAL + { + uint32_t u32Register; /* Uncorrected Raw Data Low, bits 31:0 */ + } FrawDatal; + + /*! + Defines whole and bit level accesses to the Uncorrected Raw ECC Register - 0x78 + */ + union FRAW_ECC + { + uint32_t u32Register; /* Uncorrected Raw ECC, bits 31:0 */ + struct + { + uint32_t RAW_ECC :8; /*!< Uncorrected Raw ECC, bits 7:0 */ + uint32_t _FRAW_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FRAW_ECC_BITS; + } FrawEcc; + + /*! + Defines whole and bit level accesses to the Parity Override Register - 0x7C + */ + union FPAR_OVR + { + uint32_t u32Register; /* Parity Override, bits 31:0 */ + struct + { + uint32_t DAT_INV_PAR :8; /*!< Data Odd Parity, bits 7:0 */ + uint32_t ADD_INV_PAR :1; /*!< Address Odd Parity, bit 8 */ + uint32_t PAR_OVR_KEY :3; /*!< Parity Override Key, bits 11:9 */ + uint32_t BUS_PAR_DIS :4; /*!< Disable bus parity, bits 15:12 */ + uint32_t BNK_INV_PAR :1; /*!< Buffer Invert Parity, bit 16 */ + uint32_t _FPAR_OVR_Reserved_31_17 :15;/*!< Reserved, bits 31:17 */ + } FPAR_OVR_BITS; + } FparOvr; + + uint32_t _Reserved_80_BC[16];/* Reserved Address Locations 0x80 - 0xBC */ + + /*! + Defines whole and bit level accesses to the Error Detection Sector Disable2 Register - 0xC0 + */ + union FEDACSDIS2 + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID2 :4;/*!< Sector ID2 , bits 3:0 */ + uint32_t _FEDACSDIS2_Reserved_4 :1;/*!< Reserved, bit 4 */ + uint32_t BankID2 :3;/*!< Bank ID2 , bits 7:5 */ + uint32_t SectorID2_inverse :4;/*!< Sector ID2 Inverse, bits 11:8 */ + uint32_t _FEDACSDIS2_Reserved_12 :1;/*!< Reserved, bit 12 */ + uint32_t BankID2_inverse :3;/*!< Bank ID2 Inverse, bits 15:13 */ + uint32_t SectorID3 :4;/*!< Sector ID3 , bits 19:16 */ + uint32_t _FEDACSDIS2_Reserved_20 :1;/*!< Reserved, bit 20 */ + uint32_t BankID3 :3;/*!< Bank ID3 , bits 23:21 */ + uint32_t SectorID3_inverse :4;/*!< Sector ID3 Inverse, bits 27:24 */ + uint32_t _FEDACSDIS2_Reserved_28 :1;/*!< Reserved, bit 28 */ + uint32_t BankID3_inverse :3;/*!< Bank ID3 Inverse, bits 31:29 */ + } FEDACSDIS2_BITS; + } FedAcsDis2; + + uint32_t _Reserved_C4_10C[19];/* Reserved Address Locations 0xC4 - 0x10C */ + + /*! + Defines whole and bit level accesses to the Bank Addr Register - 0x110 + */ + union FADDR + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } Faddr; + + uint32_t _Reserved_114_118[2]; /* Reserved Address Locations 0x114-0x118 */ + + union FTCTRL + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t Reserved_00 :1;/*!< Reserved bit, 00 */ + uint32_t Test_EN :1;/*!< Test Enable bit 1 */ + uint32_t Reserved_23_02 :14;/*!< Reserved bits, 23:02 */ + uint32_t WKData_Blk_Clr :1;/*!< Block clearing of FWPWRTITE, bit 16 */ + uint32_t Reserved_23_17 :7;/*!< Reserved bits, 23:17 */ + uint32_t AutoCalc_EN :1;/*!< Auto Calc Enable bit 24 */ + uint32_t Reserved_31_25 :7;/*!< Reserved bits, 31:25 */ + } FTCTRL_BITS; + } Ftctrl; + + + + /*! + Defines whole and bit level accesses to the FWPWRITE0 Register - 0x120 + */ + union FWPWRITE0 + { + uint32_t u32Register; /* FWPWRITE0 Register, bits 31:0 */ + } Fwpwrite0; + + /*! + Defines whole and bit level accesses to the FWPWRITE1 Register - 0x124 + */ + union FWPWRITE1 + { + uint32_t u32Register; /* FWPWRITE1 Register, bits 31:0 */ + } Fwpwrite1; + + /*! + Defines whole and bit level accesses to the FWPWRITE2 Register - 0x128 + */ + union FWPWRITE2 + { + uint32_t u32Register; /* FWPWRITE2 Register, bits 31:0 */ + } Fwpwrite2; + + /*! + Defines whole and bit level accesses to the FWPWRITE3 Register - 0x12C + */ + union FWPWRITE3 + { + uint32_t u32Register; /* FWPWRITE3 Register, bits 31:0 */ + } Fwpwrite3; + + /*! + Defines whole and bit level accesses to the FWPWRITE4 Register - 0x130 + */ + union FWPWRITE4 + { + uint32_t u32Register; /* FWPWRITE4 Register, bits 31:0 */ + } Fwpwrite4; + + /*! + Defines whole and bit level accesses to the FWPWRITE5 Register - 0x134 + */ + union FWPWRITE5 + { + uint32_t u32Register; /* FWPWRITE5 Register, bits 31:0 */ + } Fwpwrite5; + + /*! + Defines whole and bit level accesses to the FWPWRITE6 Register - 0x138 + */ + union FWPWRITE6 + { + uint32_t u32Register; /* FWPWRITE6 Register, bits 31:0 */ + } Fwpwrite6; + + /*! + Defines whole and bit level accesses to the FWPWRITE7 Register - 0x13C + */ + union FWPWRITE7 + { + uint32_t u32Register; /* FWPWRITE7 Register, bits 31:0 */ + } Fwpwrite7; + + /*! + Defines whole and bit level accesses to the FWPWRITE_ECC Register - 0x140 + */ + union FWPWRITE_ECC + { + uint32_t u32Register; /* FWPWRITE_ECC Register, bits 31:0 */ + struct + { + uint32_t WPDATA_287_256; /*!< WPDATA[287:256], bits 31:0 */ + } FWPWRITE_ECC_BITS; + struct + { + uint32_t u8Bytes31_24:8; + uint32_t u8Bytes23_16:8; + uint32_t u8Bytes15_08:8; + uint32_t u8Bytes07_00:8; + } FWPWRITE_ECC_BYTES; + } FwpwriteEcc; + + uint32_t _Reserved_144_208[50]; /* Reserved Address Locations 0x144-0x208 */ + + /*! + Defines whole and bit level accesses to the FSM Command Register - 0x20C + */ + union FSM_COMMAND + { + uint32_t u32Register; /* FSM Command, bits 31:0 */ + struct + { + uint32_t FSMCMD :6; /*!< Flash State Machine Command, bits 5:0 */ + uint32_t _FSM_COMMAND_Reserved_31_06 :26;/*!< Reserved, bits 31:6 */ + } FSM_COMMAND_BITS; + } FsmCommand; + + uint32_t _Reserved_210_284[30]; /* Reserved Address Locations 0x210-0x284 */ + + /*! + Defines whole and bit level accesses to the FSM Register Write Enable- 0x288 + */ + union FSM_WR_ENA + { + uint32_t u32Register; /* FSM Register Write Enable, bits 31:0 */ + struct + { + uint32_t WR_ENA :3; /*!< FSM Write Enable, bits 2:0 */ + uint32_t _FSM_WR_ENA_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ + } FSM_WR_ENA_BITS; + } FsmWrEna; + + uint32_t _Reserved_28C_2A0[6]; /* Reserved Address Locations 0x28C-0x2A0 */ + + /*! + Defines whole and bit level accesses to the FSM Sector Register - 0x2A4 + */ + union FSM_SECTOR + { + uint32_t u32Register; /* FSM Sector, bits 31:0 */ + struct + { + uint32_t _FSM_SECTOR_Reserved_15_0 :8; /*!< Reserved, bits 15:8 */ + uint32_t SECT_ERASED :16;/*!< Sectors Erased, bits 31:16 */ + } FSM_SECTOR_BITS; + } FsmSector; + + uint32_t _Reserved_2A8_2B0[3]; /* Reserved Address Locations 0x2A8-0x2B0 */ + + /*! + Defines whole and bit level accesses to the FSM Command Execute Register - 0x2B4 + */ + union FSM_EXECUTE + { + uint32_t u32Register; /* FSM Command Execute, bits 31:0 */ + struct + { + uint32_t FSMEXECUTE :5; /*!< FSM Command Execute, bits 4:0 */ + uint32_t _FSM_EXECUTE_Reserved_15_05 :11; /*!< Reserved, bits 15:5 */ + uint32_t SUSPEND_NOW :4; /*!< FSM Command Suspend, bits 19:16 */ + uint32_t _FSM_EXECUTE_Reserved_31_20 :12; /*!< Reserved, bits 31:20 */ + } FSM_EXECUTE_BITS; + } FsmExecute; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation configuration Register - 0x2B8 + */ + union EEPROM_CONFIG + { + uint32_t u32Register; /* EEPROM Emulation configuration, bits 31:0 */ + struct + { + uint32_t AUTOSTART_GRACE :8; /*!< Auto-suspend Startup Grace Period, bits 7:0 */ + uint32_t AUTOSUSP_EN :1; /*!< Auto-suspend Enable, bit 8 */ + uint32_t _EEPROM_CONFIG_Reserved_15_09 :7; /*!< Reserved, bits 15:9 */ + uint32_t EWAIT :4; /*!< EEPROM Wait state Counter, bits 19:16 */ + uint32_t _EEPROM_CONFIG_Reserved_31_20 :12; /*!< Reserved, bits 31:20 */ + } EEPROM_CONFIG_BITS; + } EepromConfig; + + uint32_t _Reserved_2BC; /* Reserved Address Locations 0x2BC */ + + /*! + Defines whole and bit level accesses to the FSM Sector1 Register - 0x2C0 + */ + union FSM_SECTOR_1 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector1; + + /*! + Defines whole and bit level accesses to the FSM Sector2 Register - 0x2C4 + */ + union FSM_SECTOR_2 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector2; + + uint32_t _Reserved_2C8_304[16];/* Reserved Address Locations 0x2C8 - 0x304 */ + + /*! + Defines whole and bit level accesses to the EEPROM Error Correction Control Register1 - 0x308 + */ + union EE_CTRL1 + { + uint32_t u32Register; /* EEPROM Error Correction Control Register1, bits 31:0 */ + struct + { + uint32_t EE_EDACEN :4;/*!< Error Detection and Correction Enable, bits 3:0 */ + uint32_t EE_ALL0_OK :1;/*!< Zero Condition Valid, bit 4 */ + uint32_t EE_ALL1_OK :1;/*!< One Condition Valid, bit 5 */ + uint32_t _EE_CTRL1_Reserved_07_06 :2;/*!< Reserved, bits 7:6 */ + uint32_t EE_PEN :1;/*!< Error Profiling Enable, bit 8 */ + uint32_t EE_EZFEN :1;/*!< Error on Zero Fail Enable, bit 9 */ + uint32_t EE_EOFEN :1;/*!< Error on One Fail Enable, bit 10 */ + uint32_t _EE_CTRL1_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ + uint32_t EE_EDACMODE :4;/*!< Error Correction Mode, bits 19:16 */ + uint32_t _EE_CTRL1_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + } EE_CTRL1_BITS; + } EeCtrl1; + + /*! + Defines whole and bit level accesses to the EEPROM Error Correction Control Register2 - 0x30C + */ + union EE_CTRL2 + { + uint32_t u32Register; /* EEPROM Error Correction Control Register2, bits 31:0 */ + struct + { + uint32_t EE_SEC_THRESHOLD :16;/*!< EEPROM Single Error Correction Threshold, bits 15:0 */ + uint32_t _EE_CTRL2_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } EE_CTRL2_BITS; + } EeCtrl2; + + /*! + Defines whole and bit level accesses to the EEPROM Error Correction Counter Register - 0x310 + */ + union EE_COR_ERR_CNT + { + uint32_t u32Register; /* EEPROM Error Correction Counter Register, bits 31:0 */ + struct + { + uint32_t EE_ERRCNT :16;/*!< Correctable Error Counter, bits 15:0 */ + uint32_t _EE_COR_ERR_CNT_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } EE_COR_ERR_CNT_BITS; + } EeCorErrCnt; + + /*! + Defines whole and bit level accesses to the EEPROM Correctable Error Address Register - 0x314 + */ + union EE_COR_ERR_ADD + { + uint32_t u32Register; /* Correctable Error Address Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t COR_ERR_ADD :29;/*!< Correctable Error Address, bits 31:3 */ + } EE_COR_ERR_ADD_BITS; + } EeCorErrAdd; + + /*! + Defines whole and bit level accesses to the EEPROM Correctable Error Position Register - 0x318 + */ + union EE_COR_ERR_POS + { + uint32_t u32Register; /* EEPROM Correctable Error Position Register, bits 31:0 */ + struct + { + uint32_t EE_ERR_POS :8; /*!< Single Error Position, bits 7:0 */ + uint32_t TYPE :1; /*!< Error Type, bit 8 */ + uint32_t _EE_COR_ERR_POS_Reserved_31_9 :22;/*!< Reserved, bits 31:9 */ + } EE_COR_ERR_POS_BITS; + } EeCorErrPos; + + /*! + Defines whole and bit level accesses to the EEPROM Error Status Register - 0x31C + */ + union EE_STATUS + { + uint32_t u32Register; /* EEPROM Error Status Register, bits 31:0 */ + struct + { + uint32_t EE_ERR_PRF_FLG :1;/*!< Error Profiling Status Flag, bit 0 */ + uint32_t EE_ERR_ZERO_FLG :1;/*!< Error On Zero Fail Status Flag, bit 1 */ + uint32_t EE_ERR_ONE_FLG :1;/*!< Error On One Fail Status Flag, bit 2 */ + uint32_t EE_D_COR_ERR :1;/*!< Diagnostic Correctable Error Status Flag, bit 3 */ + uint32_t EE_CME :1;/*!< EE ECC Malfunction Status Flag, bit 4 */ + uint32_t _EE_STATUS_Reserved_5 :1;/*!< Reserved, bit 5 */ + uint32_t EE_CMG :1;/*!< EE Compare Malfunction Flag, bit 6 */ + uint32_t _EE_STATUS_Reserved_7 :1;/*!< Reserved, bit 7 */ + uint32_t EE_UNC_ERR :1;/*!< Multiple bit ECC or Parity Error Status Flag, bit 8 */ + uint32_t _EE_STATUS_Reserved_11_9 :3;/*!< Reserved, bits 11:9 */ + uint32_t EE_D_UNC_ERR :1;/*!< Diagnostic Un-correctable Error Status Flag, bit 12 */ + uint32_t _EE_STATUS_Reserved_31_13 :19;/*!< Reserved, bits 31:13 */ + } EE_STATUS_BITS; + } EeStatus; + + /*! + Defines whole and bit level accesses to the Un-correctable Error Address Register - 0x320 + */ + union EE_UNC_ERR_ADD + { + uint32_t u32Register; /* Error Status Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t UNC_ERR_ADD :29;/*!< Un-correctable Error Address, bits 31:3 */ + } EE_UNC_ERR_ADD_BITS; + } EeUncErrAdd; + + uint32_t _Reserved_324_3FC[55];/* Reserved Address Locations 0x324 - 0x3FC */ + + /*! + Defines whole and bit level accesses to the FCFG BANK Register - 0x400 + */ + union FCFG_BANK_1 + { + uint32_t u32Register; /* Flash Bank configuration, bits 31:0 */ + struct + { + uint32_t _FCFG_BANK_Reserved_3_0 :4; /*!< Reserved bits 3:0 */ + uint32_t MAIN_BANK_WIDTH :12;/*!< MAIN_BANK_WIDTH, bits 15:4 */ + uint32_t _FCFG_BANK_Reserved_19_16 :4; /*!< Reserved bits 19:16 */ + uint32_t EE_BANK_WIDTH :12;/*!< EE_BANK_WIDTH, bits 31:20 */ + } FCFG_BANK_BITS; + } FcfgBank; + +} Fapi_FmcRegistersType; +#endif + +#endif /* REGISTERS_LE_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Registers_FMC_LE.h + *********************************************************************************************************************/ Index: firmware/App/Services/FlashAPI/Types.h =================================================================== diff -u --- firmware/App/Services/FlashAPI/Types.h (revision 0) +++ firmware/App/Services/FlashAPI/Types.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,569 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Types.h + * + * Description: Types used by the F021 API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef TYPES_H_ +#define TYPES_H_ + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +/*LDRA_NOANALYSIS*/ +#include +#include +/*LDRA_ANALYSIS*/ + +#if defined(__TI_COMPILER_VERSION__) /* TI CCS Compiler */ +#include "../FlashAPI/CGT.CCS.h" +#elif defined(__ICCARM__) /* IAR EWARM Compiler */ +#include "CGT.IAR.h" +#elif defined(__ghs__) /* GreenHills Compiler */ +#include "CGT.GHS.h" +#elif defined(__ARMCC_VERSION) /* ARM Compiler */ +#include "CGT.ARM.h" +#elif defined(__GNUC__) /* gcc Compiler */ +#include "../FlashAPI/CGT.gcc.h" +#else +#error "A valid code generation compiler type was not determined!" +#endif + +#if !defined(_LITTLE_ENDIAN) && !defined(_BIG_ENDIAN) +#error "Target Endianess is not defined" +#endif + + +/*****************************************************************************/ +/* GLOBAL DEFINITIONS */ +/*****************************************************************************/ +#if !defined(HIGH_BYTE_FIRST) +#define HIGH_BYTE_FIRST 0U +#endif + +#if !defined(LOW_BYTE_FIRST) +#define LOW_BYTE_FIRST 1U +#endif + +#if !defined(CPU_BYTE_ORDER) +#if defined(_LITTLE_ENDIAN) + #define CPU_BYTE_ORDER (LOW_BYTE_FIRST) +#else + #define CPU_BYTE_ORDER (HIGH_BYTE_FIRST) +#endif +#endif + +#if !defined(false) +#define false 0U +#endif +#if !defined(true) +#define true 1U +#endif + +/*****************************************************************************/ +/* TYPE DEFINITIONS */ +/*****************************************************************************/ +typedef unsigned char boolean_t; + +/*! + \brief This is used to indicate which Cpu is being used. +*/ +typedef enum +{ + Fapi_MasterCpu, + Fapi_SlaveCpu0 +} ATTRIBUTE_PACKED Fapi_CpuSelectorType; + +/*! + \brief This is used to indicate what type of Cpu is being used. +*/ +typedef enum +{ + ARM7 = 0U, /* ARM7 core, Legacy placeholder */ + M3 = 1U, /* ARM Cortex M3 core */ + R4 = 2U, /* ARM Cortex R4 core without ECC logic */ + R4F = 3U, /* ARM Cortex R4, R4F, and R5 cores with ECC logic*/ + C28 = 4U, /* TI C28x core */ + Undefined1 = 5U, /* To Be Determined. Future core placeholder */ + Undefined2 = 6U, /* To Be Determined. Future core placeholder */ + Undefined3 = 7U /* To Be Determined. Future core placeholder */ +} ATTRIBUTE_PACKED Fapi_CpuType; + +/*! + \brief This is used to indicate what type of Family is being used. +*/ +typedef enum +{ + Family_FMC = 0x00, + Family_L2FMC = 0x10, + Family_Sonata = 0x20, + Family_Stellaris = 0x30, + Family_Future = 0x40 +} ATTRIBUTE_PACKED Fapi_FamilyType; + +/*! + \brief This is used to indicate what type of Address is being used. +*/ +typedef enum +{ + Fapi_Flash, + Fapi_FlashEcc, + Fapi_Otp, + Fapi_OtpEcc, + Fapi_Undefined +} ATTRIBUTE_PACKED Fapi_AddressMemoryType; + +/*! + \brief This is used to return the information from the engineering row in the TI OTP. +*/ +typedef struct +{ + uint32_t u32AsicId; + uint8_t u8Revision; + uint32_t u32LotNumber; + uint16_t u16FlowCheck; + uint16_t u16WaferNumber; + uint16_t u16XCoordinate; + uint16_t u16YCoordinate; +} ATTRIBUTE_PACKED Fapi_EngineeringRowType; + +typedef struct +{ + uint32_t au32StatusWord[4]; +} ATTRIBUTE_PACKED Fapi_FlashStatusWordType; + +/*! + \brief This contains all the possible modes used in the Fapi_IssueAsyncProgrammingCommand(). +*/ +typedef enum +{ + Fapi_AutoEccGeneration, /* This is the default mode for the command and will auto generate the ECC for the + provided data buffer */ + Fapi_DataOnly, /* Command will only process the data buffer */ + Fapi_EccOnly, /* Command will only process the ecc buffer */ + Fapi_DataAndEcc /* Command will process data and ecc buffers */ +} ATTRIBUTE_PACKED Fapi_FlashProgrammingCommandsType; + +/*! + \brief This is used to indicate which Flash bank is being used. +*/ +typedef enum +{ + Fapi_FlashBank0=0, + Fapi_FlashBank1=1, + Fapi_FlashBank2=2, + Fapi_FlashBank3=3, + Fapi_FlashBank4=4, + Fapi_FlashBank5=5, + Fapi_FlashBank6=6, + Fapi_FlashBank7=7 +} ATTRIBUTE_PACKED Fapi_FlashBankType; + +/*! + \brief This is used to indicate what F021 Bank Technology the bank is +*/ +typedef enum +{ + Fapi_FLEP=0, + Fapi_FLEE=1, + Fapi_FLES=2, + Fapi_FLHV=3 +} ATTRIBUTE_PACKED Fapi_FlashBankTechType; + +/*! + \brief This is used to indicate which Flash sector is being used. +*/ +typedef enum +{ + Fapi_FlashSector0, + Fapi_FlashSector1, + Fapi_FlashSector2, + Fapi_FlashSector3, + Fapi_FlashSector4, + Fapi_FlashSector5, + Fapi_FlashSector6, + Fapi_FlashSector7, + Fapi_FlashSector8, + Fapi_FlashSector9, + Fapi_FlashSector10, + Fapi_FlashSector11, + Fapi_FlashSector12, + Fapi_FlashSector13, + Fapi_FlashSector14, + Fapi_FlashSector15, + Fapi_FlashSector16, + Fapi_FlashSector17, + Fapi_FlashSector18, + Fapi_FlashSector19, + Fapi_FlashSector20, + Fapi_FlashSector21, + Fapi_FlashSector22, + Fapi_FlashSector23, + Fapi_FlashSector24, + Fapi_FlashSector25, + Fapi_FlashSector26, + Fapi_FlashSector27, + Fapi_FlashSector28, + Fapi_FlashSector29, + Fapi_FlashSector30, + Fapi_FlashSector31, + Fapi_FlashSector32, + Fapi_FlashSector33, + Fapi_FlashSector34, + Fapi_FlashSector35, + Fapi_FlashSector36, + Fapi_FlashSector37, + Fapi_FlashSector38, + Fapi_FlashSector39, + Fapi_FlashSector40, + Fapi_FlashSector41, + Fapi_FlashSector42, + Fapi_FlashSector43, + Fapi_FlashSector44, + Fapi_FlashSector45, + Fapi_FlashSector46, + Fapi_FlashSector47, + Fapi_FlashSector48, + Fapi_FlashSector49, + Fapi_FlashSector50, + Fapi_FlashSector51, + Fapi_FlashSector52, + Fapi_FlashSector53, + Fapi_FlashSector54, + Fapi_FlashSector55, + Fapi_FlashSector56, + Fapi_FlashSector57, + Fapi_FlashSector58, + Fapi_FlashSector59, + Fapi_FlashSector60, + Fapi_FlashSector61, + Fapi_FlashSector62, + Fapi_FlashSector63 +} ATTRIBUTE_PACKED Fapi_FlashSectorType; + +/*! + \brief This contains all the possible Flash State Machine commands. +*/ +typedef enum +{ + Fapi_ProgramData = 0x0002, + Fapi_EraseSector = 0x0006, + Fapi_EraseBank = 0x0008, + Fapi_ValidateSector = 0x000E, + Fapi_ClearStatus = 0x0010, + Fapi_ProgramResume = 0x0014, + Fapi_EraseResume = 0x0016, + Fapi_ClearMore = 0x0018 +} ATTRIBUTE_PACKED Fapi_FlashStateCommandsType; + +/*LDRA_INSPECTED 495 S MR: 6.3 "This does have a size indicated. LDRA is incorrect" */ +typedef uint32_t Fapi_FlashStatusType; + +/*! + \brief This contains all the possible Flash State Machine commands. +*/ +typedef enum +{ + Fapi_NormalRead = 0x0, + Fapi_RM0 = 0x1, + Fapi_RM1 = 0x2 +} ATTRIBUTE_PACKED Fapi_FlashReadMarginModeType; + +/*! + \brief This is the master type containing all possible returned status codes. +*/ +typedef enum +{ + Fapi_Status_Success=0, /* Function completed successfully */ + Fapi_Status_FsmBusy, /* FSM is Busy */ + Fapi_Status_FsmReady, /* FSM is Ready */ + Fapi_Error_Fail, /* Generic Function Fail code */ + Fapi_Error_NullPointer, /* One of the pointer parameters is a null pointer */ + Fapi_Error_InvalidCommand, /* Command used is invalid for the function called */ + Fapi_Error_InvalidEccAddress, /* Returned if the ECC Address given to a function is invalid for that function */ + Fapi_Error_OtpChecksumMismatch, /* Returned if OTP checksum does not match expected value */ + Fapi_Error_InvalidHclkValue, /* Returned if FClk is above max FClk value - FClk is a calculated from HClk and + RWAIT/EWAIT */ + Fapi_Error_InvalidBank, /* Returned if the specified bank does not exist */ + Fapi_Error_InvalidAddress, /* Returned if the specified Address does not exist in Flash or OTP */ + Fapi_Error_InvalidReadMode, /* Returned if the specified read mode does not exist */ + Fapi_Error_AsyncIncorrectDataBufferLength, /* Returned if Data buffer size specified exceeds Data bank width */ + Fapi_Error_AsyncIncorrectEccBufferLength, /* Returned if ECC buffer size specified exceeds ECC bank width */ + Fapi_Error_AsyncDataEccBufferLengthMismatch, /* Returned if Data buffer size either is not 64bit aligned or Data + length exceeds amount ECC supplied */ + Fapi_Error_FeatureNotAvailable /* FMC feature is not available on this device */ +} ATTRIBUTE_PACKED Fapi_StatusType; + +/*LDRA_NOANALYSIS*/ +/*LDRA_INSPECTED 42 S MR: 3.5 "Necessary for FMC register definitions" */ +/*LDRA_INSPECTED 74 S MR: 18.4 "Necessary for FMC register definitions" */ +#if defined(_LITTLE_ENDIAN) +typedef union +{ + volatile struct + { +#if defined (_C28X) + uint16_t ChecksumLength:16; /* 0x150 bits 15:0 */ + uint16_t OtpVersion:16; /* 0x150 bits 31:16 */ + uint32_t OtpChecksum; /* 0x154 bits 31:0 */ + uint16_t NumberOfBanks:16; /* 0x158 bits 15:0 */ + uint16_t NumberOfSectors:16; /* 0x158 bits 31:16 */ + uint16_t MemorySize:16; /* 0x15C bits 15:0 */ + uint16_t Package:16; /* 0x15C bits 31:16 */ + uint16_t SiliconRevision:8; /* 0x160 bits 7:0 */ + uint16_t AsicNumber_23_8:8; /* 0x160 bits 31:8 */ + uint16_t AsicNumber_31_24:16; /* 0x160 bits 31:8 */ + uint32_t LotNumber; /* 0x164 bits 31:0 */ + uint16_t WaferNumber:16; /* 0x168 bits 15:0 */ + uint16_t Flowbits:16; /* 0x168 bits 31:16 */ + uint16_t YCoordinate:16; /* 0x16C bits 15:0 */ + uint16_t XCoordinate:16; /* 0x16C bits 31:16 */ + uint16_t EVSU:8; /* 0x170 bits 7:0 */ + uint16_t PVSU:8; /* 0x170 bits 15:8 */ + uint16_t ESU:8; /* 0x170 bits 23:16 */ + uint16_t PSU:8; /* 0x170 bits 31:24 */ + uint16_t CVSU:12; /* 0x174 bits 11:0 */ + uint16_t Add_EXEZSU:4; /* 0x174 bits 15:12 */ + uint16_t PVAcc:8; /* 0x174 bits 23:16 */ + uint16_t RVSU:8; /* 0x174 bits 31:24 */ + uint16_t PVH2:8; /* 0x178 bits 7:0 */ + uint16_t PVH:8; /* 0x178 bits 15:8 */ + uint16_t RH:8; /* 0x178 bits 23:16 */ + uint16_t PH:8; /* 0x178 bits 31:24 */ + uint16_t SmFrequency:12; /* 0x17C bits 11:0 */ + uint16_t VSTAT:4; /* 0x17C bits 15:12 */ + uint16_t Sequence:8; /* 0x17C bits 23:16 */ + uint16_t EH:8; /* 0x17C bits 31:24 */ + uint16_t VHV_EStep:16; /* 0x180 bits 15:0 */ + uint16_t VHV_EStart:16; /* 0x180 bits 31:16 */ + uint16_t MAX_PP:16; /* 0x184 bits 15:0 */ + uint16_t OtpReserved1:16; /* 0x184 bits 31:16 */ + uint16_t PROG_PW:16; /* 0x188 bits 15:0 */ + uint16_t MAX_EP:16; /* 0x188 bits 31:16 */ + uint32_t ERA_PW; /* 0x18C bits 31:0 */ + uint16_t VHV_E:16; /* 0x190 bits 15:0 */ + uint16_t VHV_P:16; /* 0x190 bits 31:16 */ + uint16_t VINH:8; /* 0x194 bits 7:0 */ + uint16_t VCG:8; /* 0x194 bits 15:8 */ + uint16_t VHV_PV:16; /* 0x194 bits 31:16 */ + uint16_t OtpReserved2:8; /* 0x198 bits 7:0 */ + uint16_t VRead:8; /* 0x198 bits 15:8 */ + uint16_t VWL_P:8; /* 0x198 bits 23:16 */ + uint16_t VSL_P:8; /* 0x198 bits 31:24 */ + uint32_t ApiChecksum; /* 0x19C bits 15:0 */ + uint32_t OtpReserved3; /* 0x1A0 bits 31:0 */ + uint32_t OtpReserved4; /* 0x1A4 bits 31:0 */ + uint32_t OtpReserved5; /* 0x1A8 bits 31:0 */ + uint32_t OtpReserved6; /* 0x1AC bits 31:0 */ +#else + uint32_t ChecksumLength:16; /* 0x150 bits 15:0 */ + uint32_t OtpVersion:16; /* 0x150 bits 31:16 */ + uint32_t OtpChecksum; /* 0x154 bits 31:0 */ + uint32_t NumberOfBanks:16; /* 0x158 bits 15:0 */ + uint32_t NumberOfSectors:16; /* 0x158 bits 31:16 */ + uint32_t MemorySize:16; /* 0x15C bits 15:0 */ + uint32_t Package:16; /* 0x15C bits 31:16 */ + uint32_t SiliconRevision:8; /* 0x160 bits 7:0 */ + uint32_t AsicNumber:24; /* 0x160 bits 31:8 */ + uint32_t LotNumber; /* 0x164 bits 31:0 */ + uint32_t WaferNumber:16; /* 0x168 bits 15:0 */ + uint32_t Flowbits:16; /* 0x168 bits 31:16 */ + uint32_t YCoordinate:16; /* 0x16C bits 15:0 */ + uint32_t XCoordinate:16; /* 0x16C bits 31:16 */ + uint32_t EVSU:8; /* 0x170 bits 7:0 */ + uint32_t PVSU:8; /* 0x170 bits 15:8 */ + uint32_t ESU:8; /* 0x170 bits 23:16 */ + uint32_t PSU:8; /* 0x170 bits 31:24 */ + uint32_t CVSU:12; /* 0x174 bits 11:0 */ + uint32_t Add_EXEZSU:4; /* 0x174 bits 15:12 */ + uint32_t PVAcc:8; /* 0x174 bits 23:16 */ + uint32_t RVSU:8; /* 0x174 bits 31:24 */ + uint32_t PVH2:8; /* 0x178 bits 7:0 */ + uint32_t PVH:8; /* 0x178 bits 15:8 */ + uint32_t RH:8; /* 0x178 bits 23:16 */ + uint32_t PH:8; /* 0x178 bits 31:24 */ + uint32_t SmFrequency:12; /* 0x17C bits 11:0 */ + uint32_t VSTAT:4; /* 0x17C bits 15:12 */ + uint32_t Sequence:8; /* 0x17C bits 23:16 */ + uint32_t EH:8; /* 0x17C bits 31:24 */ + uint32_t VHV_EStep:16; /* 0x180 bits 15:0 */ + uint32_t VHV_EStart:16; /* 0x180 bits 31:16 */ + uint32_t MAX_PP:16; /* 0x184 bits 15:0 */ + uint32_t OtpReserved1:16; /* 0x184 bits 31:16 */ + uint32_t PROG_PW:16; /* 0x188 bits 15:0 */ + uint32_t MAX_EP:16; /* 0x188 bits 31:16 */ + uint32_t ERA_PW; /* 0x18C bits 31:0 */ + uint32_t VHV_E:16; /* 0x190 bits 15:0 */ + uint32_t VHV_P:16; /* 0x190 bits 31:16 */ + uint32_t VINH:8; /* 0x194 bits 7:0 */ + uint32_t VCG:8; /* 0x194 bits 15:8 */ + uint32_t VHV_PV:16; /* 0x194 bits 31:16 */ + uint32_t OtpReserved2:8; /* 0x198 bits 7:0 */ + uint32_t VRead:8; /* 0x198 bits 15:8 */ + uint32_t VWL_P:8; /* 0x198 bits 23:16 */ + uint32_t VSL_P:8; /* 0x198 bits 31:24 */ + uint32_t ApiChecksum:32; /* 0x19C bits 31:0 */ + uint32_t OtpReserved3:32; /* 0x1A0 bits 31:0 */ + uint32_t OtpReserved4:32; /* 0x1A4 bits 31:0 */ + uint32_t OtpReserved5:32; /* 0x1A8 bits 31:0 */ + uint32_t OtpReserved6:32; /* 0x1AC bits 31:0 */ +#endif + } OTP_VALUE; + volatile uint8_t au8OtpWord[0x60]; + volatile uint16_t au16OtpWord[0x30]; + volatile uint32_t au32OtpWord[0x18]; +}Fapi_TiOtpBytesType; +#else +typedef union +{ + volatile struct + { + uint32_t OtpVersion:16; /* 0x150 bits 31:16 */ + uint32_t ChecksumLength:16; /* 0x150 bits 15:0 */ + uint32_t OtpChecksum; /* 0x154 bits 31:0 */ + uint32_t NumberOfSectors:16; /* 0x158 bits 31:16 */ + uint32_t NumberOfBanks:16; /* 0x158 bits 15:0 */ + uint32_t Package:16; /* 0x15C bits 31:16 */ + uint32_t MemorySize:16; /* 0x15C bits 15:0 */ + uint32_t AsicNumber:24; /* 0x160 bits 31:8 */ + uint32_t SiliconRevision:8; /* 0x160 bits 7:0 */ + uint32_t LotNumber; /* 0x164 bits 31:0 */ + uint32_t Flowbits:16; /* 0x168 bits 31:16 */ + uint32_t WaferNumber:16; /* 0x168 bits 15:0 */ + uint32_t XCoordinate:16; /* 0x16C bits 31:16 */ + uint32_t YCoordinate:16; /* 0x16C bits 15:0 */ + uint32_t PSU:8; /* 0x170 bits 31:24 */ + uint32_t ESU:8; /* 0x170 bits 23:16 */ + uint32_t PVSU:8; /* 0x170 bits 15:8 */ + uint32_t EVSU:8; /* 0x170 bits 7:0 */ + uint32_t RVSU:8; /* 0x174 bits 31:24 */ + uint32_t PVAcc:8; /* 0x174 bits 23:16 */ + uint32_t Add_EXEZSU:4; /* 0x174 bits 15:12 */ + uint32_t CVSU:12; /* 0x174 bits 11:0 */ + uint32_t PH:8; /* 0x178 bits 31:24 */ + uint32_t RH:8; /* 0x178 bits 23:16 */ + uint32_t PVH:8; /* 0x178 bits 15:8 */ + uint32_t PVH2:8; /* 0x178 bits 7:0 */ + uint32_t EH:8; /* 0x17C bits 31:24 */ + uint32_t Sequence:8; /* 0x17C bits 23:16 */ + uint32_t VSTAT:4; /* 0x17C bits 15:12 */ + uint32_t SmFrequency:12; /* 0x17C bits 11:0 */ + uint32_t VHV_EStart:16; /* 0x180 bits 31:16 */ + uint32_t VHV_EStep:16; /* 0x180 bits 15:0 */ + uint32_t OtpReserved1:16; /* 0x184 bits 31:16 */ + uint32_t MAX_PP:16; /* 0x184 bits 15:0 */ + uint32_t MAX_EP:16; /* 0x188 bits 31:16 */ + uint32_t PROG_PW:16; /* 0x188 bits 15:0 */ + uint32_t ERA_PW; /* 0x18C bits 31:0 */ + uint32_t VHV_P:16; /* 0x190 bits 31:16 */ + uint32_t VHV_E:16; /* 0x190 bits 15:0 */ + uint32_t VHV_PV:16; /* 0x194 bits 31:16 */ + uint32_t VCG:8; /* 0x194 bits 15:8 */ + uint32_t VINH:8; /* 0x194 bits 7:0 */ + uint32_t VSL_P:8; /* 0x198 bits 31:24 */ + uint32_t VWL_P:8; /* 0x198 bits 23:16 */ + uint32_t VRead:8; /* 0x198 bits 15:8 */ + uint32_t OtpReserved2:8; /* 0x198 bits 7:0 */ + uint32_t ApiChecksum:32; /* 0x19C bits 31:0 */ + uint32_t OtpReserved3:32; /* 0x1A0 bits 31:0 */ + uint32_t OtpReserved4:32; /* 0x1A4 bits 31:0 */ + uint32_t OtpReserved5:32; /* 0x1A8 bits 31:0 */ + uint32_t OtpReserved6:32; /* 0x1AC bits 31:0 */ + } OTP_VALUE; + volatile uint8_t au8OtpWord[0x60]; + volatile uint16_t au16OtpWord[0x30]; + volatile uint32_t au32OtpWord[0x18]; +}Fapi_TiOtpBytesType; +#endif +/*LDRA_ANALYSIS*/ + +typedef struct TI_OTP_TYPE +{ + Fapi_TiOtpBytesType aOtpBank[8]; +}Fapi_TiOtpType; + +/*! + \brief +*/ +typedef enum +{ + Alpha_Internal, /* For internal TI use only. Not intended to be used by customers */ + Alpha, /* Early Engineering release. May not be functionally complete */ + Beta_Internal, /* For internal TI use only. Not intended to be used by customers */ + Beta, /* Functionally complete, to be used for testing and validation */ + Production /* Fully validated, functionally complete, ready for production use */ +} ATTRIBUTE_PACKED Fapi_ApiProductionStatusType; + +typedef struct +{ + uint8_t u8ApiMajorVersion; + uint8_t u8ApiMinorVersion; + uint8_t u8ApiRevision; + Fapi_ApiProductionStatusType oApiProductionStatus; + uint32_t u32ApiBuildNumber; + uint8_t u8ApiTechnologyType; + uint8_t u8ApiTechnologyRevision; + uint8_t u8ApiEndianness; + uint32_t u32ApiCompilerVersion; +}Fapi_LibraryInfoType; + +typedef struct +{ +#if defined(_LITTLE_ENDIAN) + uint16_t u16NumberOfBanks; + uint16_t u16Reserved; + uint16_t u16DeviceMemorySize; + uint16_t u16DevicePackage; + uint32_t u32AsicId; + uint32_t u32LotNumber; + uint16_t u16WaferNumber; + uint16_t u16FlowCheck; + uint16_t u16WaferYCoordinate; + uint16_t u16WaferXCoordinate; +#else + uint16_t u16Reserved; + uint16_t u16NumberOfBanks; + uint16_t u16DevicePackage; + uint16_t u16DeviceMemorySize; + uint32_t u32AsicId; + uint32_t u32LotNumber; + uint16_t u16FlowCheck; + uint16_t u16WaferNumber; + uint16_t u16WaferXCoordinate; + uint16_t u16WaferYCoordinate; +#endif +}Fapi_DeviceInfoType; + +typedef struct +{ + Fapi_FlashBankTechType oFlashBankTech; + uint32_t u32NumberOfSectors; + uint32_t u32BankStartAddress; + uint16_t au16SectorSizes[16]; +}Fapi_FlashBankSectorsType; + +#endif /* TYPES_H_*/ + +/********************************************************************************************************************** + * END OF FILE: Types.h + *********************************************************************************************************************/ Index: firmware/App/Services/Interrupts.c =================================================================== diff -u --- firmware/App/Services/Interrupts.c (revision 0) +++ firmware/App/Services/Interrupts.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,53 @@ +/* + * Interrupts.c + * + * Created on: Aug 1, 2024 + * Author: fw + */ + +#include "can.h" +#include "rti.h" +#include "sci.h" +#include "sys_dma.h" + +#include "TaskGeneral.h" +#include "TaskPriority.h" +#include "TaskTimer.h" + + +void initInterrupts( void ) +{ + // TODO fill up +} + + +void rtiNotification( uint32 notification ) +{ + switch ( notification ) + { + case rtiNOTIFICATION_COMPARE0: + taskTimer(); + break; + + case rtiNOTIFICATION_COMPARE1: + taskPriority(); + break; + + case rtiNOTIFICATION_COMPARE3: + taskGeneral(); + break; + + default: + // Do nothing at the moment. + // NOTE: rtiNOTIFICATION_COMPARE2 is not included right now + break; + } +} + +void canMessageNotification( canBASE_t *node, uint32 messageBox ) +{ + if ( node == canREG1 ) + { + // TODO receive CAN and put it in a queue + } +} Index: firmware/App/Services/Interrupts.h =================================================================== diff -u --- firmware/App/Services/Interrupts.h (revision 0) +++ firmware/App/Services/Interrupts.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,14 @@ +/* + * Interrupts.h + * + * Created on: Aug 1, 2024 + * Author: fw + */ + +#ifndef __INTERRUPTS_H__ +#define __INTERRUPTS_H__ + +void initInterrupts( void ); + + +#endif Index: firmware/App/Services/Timers.c =================================================================== diff -u --- firmware/App/Services/Timers.c (revision 0) +++ firmware/App/Services/Timers.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,92 @@ +/* + * Timers.c + * + * Created on: Aug 1, 2024 + * Author: fw + */ + +#include "Timers.h" + + +// ********** private definitions ********** + +// ********** private data ********** + +static volatile U32 msTimerCount; ///< 1ms timer counter incremented by TaskTimer.c. + +/*********************************************************************//** + * @brief + * The initTimers function initializes the Timers module. + * @details Inputs: msTimerCount + * @details Outputs: msTimerCount + * @return none + *************************************************************************/ +void initTimers( void ) +{ + msTimerCount = 0; +} + +/*********************************************************************//** + * @brief + * The incMSTimerCount function increments the ms timer count. + * @details Inputs: msTimerCount + * @details Outputs: msTimerCount + * @return none + *************************************************************************/ +void incMSTimerCount( void ) +{ + msTimerCount++; +} + +/*********************************************************************//** + * @brief + * The getMSTimerCount function returns the current ms timer count. + * @details Inputs: msTimerCount + * @details Outputs: none + * @return msTimerCount as a U32 + *************************************************************************/ +U32 getMSTimerCount( void ) +{ + return msTimerCount; +} + +/*********************************************************************//** + * @brief + * The didTimeout function determines whether a timeout has occurred between + * a given start count and a given timeout period (in ms). + * @details Inputs: msTimerCount + * @details Outputs: none + * @param startMSCount the ms count at the start of the timeout period + * @param timeoutPeriod the period for the timeout (in ms) + * @return TRUE if a timeout has occurred, FALSE if not + *************************************************************************/ +BOOL didTimeout( U32 startMSCount, U32 timeoutPeriod ) +{ + BOOL result = FALSE; + U32 currMSCount = msTimerCount; + + // no wrap + if ( currMSCount >= startMSCount ) + { + if ( ( currMSCount - startMSCount ) >= timeoutPeriod ) + { + result = TRUE; + } + } + // counter wrapped + else + { + U32 deltaMSCount = ( 0xFFFFFFFF - startMSCount ) + currMSCount + 1; + + if ( deltaMSCount >= timeoutPeriod ) + { + result = TRUE; + } + } + + return result; +} + + + + Index: firmware/App/Services/Timers.h =================================================================== diff -u --- firmware/App/Services/Timers.h (revision 0) +++ firmware/App/Services/Timers.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,18 @@ +/* + * Timers.h + * + * Created on: Aug 1, 2024 + * Author: fw + */ + +#ifndef __TIMERS_H__ +#define __TIMERS_H__ + +#include "BLCommon.h" + +void initTimers( void ); +void incMSTimerCount( void ); +U32 getMSTimerCount( void ); +BOOL didTimeout( U32 startMSCount, U32 timeoutPeriod ); + +#endif Index: firmware/App/Services/irqDispatch_a.asm =================================================================== diff -u --- firmware/App/Services/irqDispatch_a.asm (revision 0) +++ firmware/App/Services/irqDispatch_a.asm (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,74 @@ +;------------------------------------------------------------------------------- +; irqDispatch_a.asm +; +; (c) Texas Instruments 2009-2012, All rights reserved. +; + + ; Export Symbols + .def _irqDispatch + + ; Import Symbols + .ref C_irqDispatch + + ; The following should be placed in the .text section + .text + + ; Function: _irqDispatch + .align 4 + .armfunc _irqDispatch + + ; Use ARM mode assembly + .arm + + ; Note: This implementation is for ARMv7-R (Cortex-R4) in ARM mode only. + +_irqDispatch: .asmfunc + ; TI ASM Step 1: + SUB LR, LR, #4 ; construct the return address + SRSDB #31! ; Save LR_irq and SPSR_irq to System mode stack + + ; TI ASM Step 2: + CPS #31 ; Switch to System mode + + ; TI ASM Step 3: + PUSH {R0-R3, R12} ; Store AAPCS registers + + .if __TI_VFPV3D16_SUPPORT__ = 1 ; If VFPV3D16 is used + FMRX R12, FPSCR + STMFD SP!, {R12} + FMRX R12, FPEXC + STMFD SP!, {R12} + FSTMDBD SP!, {D0-D7} + .endif + + ; TI ASM Step 4 + ; Align stack to a 64 Bit boundary + AND R3, SP, #4 ; Calculate Stack adjustment to 64bit boundary + SUB SP, SP, R3 ; Adjust System Stack + PUSH {R3, LR} ; Put Stack adjustment and System Mode LR on Stack + + ; TI ASM Step 5 + BL C_irqDispatch ; Call Second Level IRQ Dispatcher C routine + + ; TI ASM Step 6 + ; Undo stack alignment + POP {R3, LR} ; Get Stack adjustment and System Mode LR from Stack + ADD SP, SP, R3 ; Undo System Stack adjustment + + ; TI ASM Step 7 + .if __TI_VFPV3D16_SUPPORT__ = 1 ; If VFPV3D16 is used + FLDMIAD SP!, {D0-D7} + LDMFD SP!, {R12} + FMXR FPEXC, R12 + LDMFD SP!, {R12} + FMXR FPSCR, R12 + .endif + + POP {R0-R3, R12} ; Restore AAPCS registers + + ; TI ASM Step 7 + RFEIA SP! ; Return using RFE from System mode stack + .endasmfunc + + .end +;------------------------------------------------------------------------------- Index: firmware/App/Services/irqDispatch_c.c =================================================================== diff -u --- firmware/App/Services/irqDispatch_c.c (revision 0) +++ firmware/App/Services/irqDispatch_c.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,223 @@ +/************************************************************************** +* +* Copyright (c) 2020-2024 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file irqDispatch_c.c +* +* @author (last) Sean Nash +* @date (last) 15-Jun-2020 +* +* @author (original) Sean +* @date (original) 17-Feb-2020 +* +***************************************************************************/ + +#if defined(__TI_VIM_128CH__) +#include "sys_common.h" +#include "sys_vim.h" +#elif defined(__TI_VIM_96CH__) +#include "sys_common.h" +#include "sys_vim.h" +#else +#error File irqDispatcher.c requires either __TI_VIM_96CH__ or __TI_VIM_128CH__ to be defined. +#endif + + +/** @typedef vimRAM_t + * @brief Vim Ram Definition + * + * This type is used to access the VIM RAM. + */ + +typedef volatile struct vimRam +{ + t_isrFuncPTR ISR[VIM_CHANNELS + 1]; +} vimRAM_t; + + +/** @var vimRAM_t * const vimRAM + * @brief vimRAM definition + * + * This variable is used to access the VIM RAM. + */ + +static const vimRAM_t * const vimRAM = ((vimRAM_t *)0xFFF82000U); + + +/** @var sint32 s32NestingLevel; + * @brief Variable to store the current level of nesting + * + */ + +static sint32 s32NestingLevel = 0; + + +/** @def MAX_NESTING_LEVEL + * @brief Defines max nesting deep + * + */ + +#define MAX_NESTING_LEVEL 12 + + +/** @fn void C_irqDispatch(void) + * @brief Second Level IRQ Dispatcher C routine + * @note This implementation is limited to the use of the first 96 interrupt priority's. + * + */ + +/* Ensure that the function is coded with ARM mode instructions. */ +#pragma CODE_STATE(C_irqDispatch, 32); +/* Inform the Compiler that the function is called externally, and thus should not be removed. */ +#pragma FUNC_EXT_CALLED(C_irqDispatch); +void C_irqDispatch(void) +{ + /* TI C Step 1 */ + uint32 u32IrqIndex = vimREG->IRQINDEX; /* Read IRQ Index Offset Vector */ + + /* TI C Step 2 */ + t_isrFuncPTR irq_func_pnt = vimRAM->ISR[u32IrqIndex]; /* Read IRQ Interrupt Vector */ + /** Note: + * Do not use the IRQVECREG to readout the vector address, as this could change between Step 1 and 2. + * As an alternative you could read out the vector from the constant table which was used to initialize the VIM RAM. + * This method should be faster than reading the vector address from the VIM RAM, as Flash accesses are faster than peripheral accesses. + */ + + /* IRQIVEC is zero if no interrupt is pending */ + if (0U == u32IrqIndex) + { + /* Phantom Interrupt */ + + /** @todo + * Add custom fault handler, if necessary. + */ + + // while(1); + // TODO - understand why we might get here and decide what we want to do + } + else + { + /* Increment Nesting Level indicator */ + s32NestingLevel++; + + /* If Nesting Level indicator is less than the max level, enable IRQ to allow further preemption */ + if ((MAX_NESTING_LEVEL) > s32NestingLevel) + { + /* TI C Step 3 */ + /* Save VIM REQENASET[0,1,2] Registers for later restore */ + uint32 SaveREQMASKSET0 = vimREG->REQMASKSET0; + uint32 SaveREQMASKSET1 = vimREG->REQMASKSET1; + uint32 SaveREQMASKSET2 = vimREG->REQMASKSET2; +#if defined(__TI_VIM_128CH__) + uint32 SaveREQMASKSET3 = vimREG->REQMASKSET3; +#endif + + /* TI C Step 4 */ + /* Mask out lower priority IRQ's and the current IRQ itself, keep FIQ's enabled */ + if (96U < u32IrqIndex) /* 96-...*/ + { +#if defined(__TI_VIM_128CH__) + /* REG->REQMASKCLR0 = ( 0xFFFFFFFCU & (~vimREG->FIRQPR0)); Higher priority */ + /* REG->REQMASKCLR1 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR1)); Higher priority */ + /* REG->REQMASKCLR2 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR2)); Higher priority */ + vimREG->REQMASKCLR3 = ((0xFFFFFFFFU << (u32IrqIndex - 97U)) & (~vimREG->FIRQPR3)); + vimREG->REQMASKCLR3; /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ +#elif defined(__TI_VIM_96CH__) + /** @todo + * Add custom fault handler, if necessary. + */ + while (1); /* Fault */ +#else +#error File irqDispatcher.c requires either __TI_VIM_96CH__ or __TI_VIM_128CH__ to be defined. +#endif + } + else if (64U < u32IrqIndex) /* 64-96 */ + { + /* REG->REQMASKCLR0 = ( 0xFFFFFFFCU & (~vimREG->FIRQPR0)); Higher priority */ + /* REG->REQMASKCLR1 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR1)); Higher priority */ + vimREG->REQMASKCLR2 = ((0xFFFFFFFFU << (u32IrqIndex - 65U)) & (~vimREG->FIRQPR2)); +#if defined(__TI_VIM_128CH__) + vimREG->REQMASKCLR3 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR3)); + vimREG->REQMASKCLR3; /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ +#elif defined(__TI_VIM_96CH__) + vimREG->REQMASKCLR2; /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ +#else +#error File irqDispatcher.c requires either __TI_VIM_96CH__ or __TI_VIM_128CH__ to be defined. +#endif + } + else if (32U < u32IrqIndex) /* 32-63 */ + { + /* REG->REQMASKCLR0 = ( 0xFFFFFFFCU & (~vimREG->FIRQPR0)); Higher priority */ + vimREG->REQMASKCLR1 = ((0xFFFFFFFFU << (u32IrqIndex - 33U)) & (~vimREG->FIRQPR1)); + vimREG->REQMASKCLR2 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR2)); +#if defined(__TI_VIM_128CH__) + vimREG->REQMASKCLR3 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR3)); + vimREG->REQMASKCLR3; /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ +#elif defined(__TI_VIM_96CH__) + vimREG->REQMASKCLR2; /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ +#else +#error File irqDispatcher.c requires either __TI_VIM_96CH__ or __TI_VIM_128CH__ to be defined. +#endif + } + else if ( 2U < u32IrqIndex) /* 2-31 */ + { + + vimREG->REQMASKCLR0 = ((0xFFFFFFFFU << (u32IrqIndex - 1U)) & (~vimREG->FIRQPR0)); + vimREG->REQMASKCLR1 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR1)); + vimREG->REQMASKCLR2 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR2)); +#if defined(__TI_VIM_128CH__) + vimREG->REQMASKCLR3 = ( 0xFFFFFFFFU & (~vimREG->FIRQPR3)); + vimREG->REQMASKCLR3; /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ +#elif defined(__TI_VIM_96CH__) + vimREG->REQMASKCLR2; /* Readback Mask to ensure that the previous write was finished before enabling interrupts again */ +#else +#error File irqDispatcher.c requires either __TI_VIM_96CH__ or __TI_VIM_128CH__ to be defined. +#endif + } + else /* if (0U < u32IrqIndex) */ /* 0 and 1 */ + { + /* Vectors 0 and 1 are tied to FIQ and this code is thus dead for IRQ. */ + + /** @todo + * Add custom fault handler, if necessary. + */ + + while (1); /* Fault */ + } + + /* TI C Step 5 */ + _enable_IRQ(); /* Enable IRQ, to allow preemption of IRQ routine */ + + /* TI C Step 6 */ + (*irq_func_pnt)(); /* Execute interrupt routine */ + + /* TI C Step 7 */ + _disable_IRQ(); /* Disable IRQ, to protect the remainder of the dispatcher from preemption */ + + /* TI C Step 8 */ + /* Restore VIM REQENASET[0,1,2] Registers */ + vimREG->REQMASKSET0 = SaveREQMASKSET0; + vimREG->REQMASKSET1 = SaveREQMASKSET1; + vimREG->REQMASKSET2 = SaveREQMASKSET2; +#if defined(__TI_VIM_128CH__) + vimREG->REQMASKSET3 = SaveREQMASKSET3; +#endif + } + else + { + /* Do not enable IRQ, because max nesting level was reached */ + (*irq_func_pnt)(); /* Execute interrupt routine */ + } + + if (0 < s32NestingLevel) + { + s32NestingLevel--; + } + } + + /* TI C Step 9 */ + return; /* Return to First Level IRQ Dispatcher Assembly routine */ +} Index: firmware/App/Tasks/TaskBG.c =================================================================== diff -u --- firmware/App/Tasks/TaskBG.c (revision 0) +++ firmware/App/Tasks/TaskBG.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,17 @@ +/* + * TaskBG.c + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +void taskBackground( void ) +{ +#ifndef _VECTORCAST_ // Cannot have infinite loop in unit test tool + while ( 1 ) +#endif + { + + } +} + Index: firmware/App/Tasks/TaskBG.h =================================================================== diff -u --- firmware/App/Tasks/TaskBG.h (revision 0) +++ firmware/App/Tasks/TaskBG.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,13 @@ +/* + * TaskBG.h + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#ifndef __TASKBG_H__ +#define __TASKBG_H__ + +void taskBackground( void ); + +#endif Index: firmware/App/Tasks/TaskGeneral.c =================================================================== diff -u --- firmware/App/Tasks/TaskGeneral.c (revision 0) +++ firmware/App/Tasks/TaskGeneral.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,13 @@ +/* + * TaskGeneral.c + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#include "TaskGeneral.h" + +void taskGeneral( void ) +{ + +} Index: firmware/App/Tasks/TaskGeneral.h =================================================================== diff -u --- firmware/App/Tasks/TaskGeneral.h (revision 0) +++ firmware/App/Tasks/TaskGeneral.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,16 @@ +/* + * TaskGeneral.h + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#ifndef __TASKGENERAL_H__ +#define __TASKGENERAL_H__ + +#define TASK_GENERAL_INTERVAL 50 + +void taskGeneral( void ); + + +#endif Index: firmware/App/Tasks/TaskPriority.c =================================================================== diff -u --- firmware/App/Tasks/TaskPriority.c (revision 0) +++ firmware/App/Tasks/TaskPriority.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,14 @@ +/* + * TaskPriority.c + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#include "TaskPriority.h" + +void taskPriority( void ) +{ + +} + Index: firmware/App/Tasks/TaskPriority.h =================================================================== diff -u --- firmware/App/Tasks/TaskPriority.h (revision 0) +++ firmware/App/Tasks/TaskPriority.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,15 @@ +/* + * TaskPriority.h + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#ifndef __TASKPRIORITY_H__ +#define __TASKPRIORITY_H__ + +#define TASK_PRIORITY_INTERVAL 10 + +void taskPriority( void ); + +#endif Index: firmware/App/Tasks/TaskTimer.c =================================================================== diff -u --- firmware/App/Tasks/TaskTimer.c (revision 0) +++ firmware/App/Tasks/TaskTimer.c (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,15 @@ +/* + * TaskTimer.c + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#include "TaskTimer.h" + +void taskTimer( void ) +{ + +} + + Index: firmware/App/Tasks/TaskTimer.h =================================================================== diff -u --- firmware/App/Tasks/TaskTimer.h (revision 0) +++ firmware/App/Tasks/TaskTimer.h (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -0,0 +1,15 @@ +/* + * TaskTimer.h + * + * Created on: Jul 31, 2024 + * Author: fw + */ + +#ifndef __TASKTIMER_H__ +#define __TASKTIMER_H__ + +#define TASK_TIMER_INTERVAL 1 + +void taskTimer( void ); + +#endif Index: firmware/BL.dil =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/BL.dil (.../BL.dil) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/BL.dil (.../BL.dil) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -1,4 +1,4 @@ -# RM46L852PGE 07/30/24 17:34:33 +# RM46L852PGE 08/01/24 15:58:42 # ARCH=RM46L852PGE # @@ -55,13 +55,13 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=256_KB DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=FIQ DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_RAMPARITYCHECK_ENA.VALUE=0 -DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=220.000 +DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=208.000 DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=220.00 DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81 DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73 @@ -74,10 +74,10 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ @@ -93,7 +93,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_DP_PBISTCHECK_ENA.VALUE=0x00040000 DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A @@ -110,13 +110,13 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=_irqDispatch -DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=1 @@ -131,15 +131,15 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OINC_NONSHARED DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x003fffff -DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=110.0 -DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08001200 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08003000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125 DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117 DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109 @@ -153,8 +153,8 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0xFF000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0 @@ -166,7 +166,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD2_STATE.VALUE=1 -DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_DP_SELECTED.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8 DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=rtiCompare0Interrupt @@ -178,12 +178,12 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=110.000 -DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0 -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x0A +DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=104.000 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=0.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x0F DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110 @@ -194,9 +194,9 @@ DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=64_MB -DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_VALUE_NEW.VALUE=0x00300020 DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=dmaFTCAInterrupt @@ -208,10 +208,10 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE.VALUE=TRUE DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_DP_PBISTCHECK_ENA.VALUE=0x00000000 @@ -222,17 +222,17 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ @@ -249,7 +249,7 @@ DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0 DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=24 DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16 -DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=220.000 +DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=208.000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x1000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80 DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72 @@ -263,8 +263,8 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN5_DP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=0 DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001 DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1 @@ -284,14 +284,14 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x000C DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=rtiCompare1Interrupt DRIVER.SYSTEM.VAR.PMM_MEM_PD3_STATEVALUE.VALUE=0xA DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=2 @@ -300,14 +300,14 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0x08400000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_CPUSELFTEST_ENA.VALUE=0 DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=1 @@ -329,7 +329,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_DP_PBISTCHECK_ENA.VALUE=0x00001000 DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000 @@ -344,8 +344,8 @@ DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7 @@ -354,29 +354,29 @@ DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101 DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=etpwm6TripZoneInterrupt -DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000400 DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3 DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_RAMPARITYCHECK_ENA.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_SP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F @@ -391,8 +391,8 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x17 @@ -405,19 +405,19 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0 -DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08001300 +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08005000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0 @@ -435,7 +435,7 @@ DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11 DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08001500 +DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08005800 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0 @@ -453,11 +453,11 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_VIM1_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=165.0 @@ -512,64 +512,64 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI1_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_SP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SELFCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.ETPWM_OLDCODE.VALUE=1 -DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x11 DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6 DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61 DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255 -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x08001000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x08020000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=STRONGLYORDERED_SHAREABLE DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_DP_PBISTCHECK_ENA.VALUE=0x00000100 DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000 -DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=13.750 -DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=13.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100 DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=etpwm2TripZoneInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt -DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100 -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00002000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300 DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=rtiCompare3Interrupt -DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00001500 +DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00005800 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0xffffffff DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=VCLKA4_DIVR -DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=110.000 -DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=104.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=104.000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93 DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85 DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77 @@ -588,7 +588,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=165 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=156 DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt @@ -602,9 +602,9 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1 @@ -618,22 +618,22 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU2_DP_PBISTCHECK_ENA.VALUE=0x00080000 DRIVER.SYSTEM.VAR.SAFETY_INIT_EMAC_DP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=eqep2Interrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1 -DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002EB00 -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x080017ff +DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002a800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802ffff DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0008 @@ -645,13 +645,13 @@ DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=165 DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0 @@ -680,11 +680,11 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.PMM_AUTO_CLK_WAKE_ENA.VALUE=0 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_HET2_RAMPARITYCHECK_ENA.VALUE=1 @@ -707,9 +707,9 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=165.0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5 DRIVER.SYSTEM.VAR.VIM_PARITY_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE @@ -731,10 +731,10 @@ DRIVER.SYSTEM.VAR.PMM_MEM_PD1_STATEVALUE.VALUE=0x5 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=2_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=64_KB DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ @@ -752,7 +752,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=OSC DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000 @@ -766,11 +766,11 @@ DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_DP_PBISTCHECK_ENA.VALUE=0x00020000 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI4_DP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.SAFETY_INIT_USB_DP_PBISTCHECK_ENA.VALUE=0x00000000 @@ -793,13 +793,13 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29 DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1 DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00140000 -DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00001000 DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0 @@ -808,7 +808,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC2_RAMPARITYCHECK_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0010 DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=etpwm3TripZoneInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt @@ -822,7 +822,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0 DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0 DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=55.0 @@ -836,27 +836,27 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_ESRAM_SELECTED.VALUE=1 -DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=110.000 -DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=104.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=104.000 DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0xfe0001ff DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000 DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1 @@ -873,17 +873,17 @@ DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD4_STATE_AVAIL.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121 DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113 DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESERVED_ENTRY.VALUE=phantomInterrupt -DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ @@ -916,25 +916,25 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_RAMPARITYCHECK_ENA.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800 DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0 -DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08001400 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08005400 DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08001000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE -DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE DRIVER.SYSTEM.VAR.PMM_PMCTRL_PWRDN.VALUE=0 -DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=etpwm4Interrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91 @@ -947,15 +947,15 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP -DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OINC_SHARED DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0803ffff DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD5_STATE.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_DP_PBISTCHECK_ENA.VALUE=0x00000008 DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0 @@ -968,17 +968,17 @@ DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0xFE000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_RAMPARITYCHECK_ENA.VALUE=1 -DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=110.000 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=104.000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60 DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52 DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44 @@ -1001,11 +1001,11 @@ DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort -DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_ADC1_DP_PBISTCHECK_ENA.VALUE=0x00000400 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI3_DP_PBISTCHECK_ENA.VALUE=0x00000080 DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21 @@ -1060,14 +1060,14 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=_svc -DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_RAMPARITYCHECK_ENA.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_FLASHECC_SELFCHECK_ENA.VALUE=0 -DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=0.0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0008 DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=etpwm4TripZoneInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt @@ -1077,10 +1077,10 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.SAFETY_INIT_RTP_DP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1 @@ -1097,15 +1097,15 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_ESRAM_SP_PBISTCHECK_ENA.VALUE=0x08300020 DRIVER.SYSTEM.VAR.SAFETY_INIT_STC_ROM_PBIST_SELFCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_DISABLE.VALUE=1 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OINC_NONSHARED -DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0 @@ -1130,20 +1130,20 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00 -DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08001100 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08002000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300 DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_HET1_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI5_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0 @@ -1166,25 +1166,25 @@ DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=256_KB DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_PARITY_ENABLE_NEW.VALUE=0xA DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN2_RAMPARITYCHECK_ENA.VALUE=1 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=1 -DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL_VAL.VALUE=A400 +DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL_VAL.VALUE=9B00 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=1 DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK -DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=220.00 +DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=208.00 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x1F DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1 -DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100 -DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000400 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00001000 DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef @@ -1199,16 +1199,16 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN1_DP_PBISTCHECK_ENA.VALUE=0x00000004 DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20 DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1 DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ -DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_FRAY_SP_PBISTCHECK_ENA.VALUE=0x00000000 DRIVER.SYSTEM.VAR.OS_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x15 @@ -1231,12 +1231,12 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9 DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=1 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0 -DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0 @@ -1354,7 +1354,7 @@ DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL58_INT_LEVEL.VALUE=0 -DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=148.945 +DRIVER.ESM.VAR.ESM_LOW_TIME.VALUE=157.538 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_ENABLE.VALUE=0 @@ -1390,7 +1390,7 @@ DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL12_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL56_INT_LEVEL.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL48_INT_LEVEL.VALUE=0 -DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=110 +DRIVER.ESM.VAR.ESM_VCLK_FREQ.VALUE=104 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL30_INT_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL22_INT_ENABLE.VALUE=0 DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL14_INT_ENABLE.VALUE=0 @@ -1472,50 +1472,50 @@ DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_INT_LEVEL.VALUE=0 DRIVER.RTI.VAR.RTI_1_COMPARE_2_SOURCE.VALUE=0x00000100 DRIVER.RTI.VAR.RTI_1_COMPARE_3_FREQ.VALUE=0.000100000 -DRIVER.RTI.VAR.RTI_1_FREQ.VALUE=110.000 -DRIVER.RTI.VAR.RTI_1_COMPARE_1_ACTUALTIME.VALUE=5.000 -DRIVER.RTI.VAR.RTI_1_COUNTER_1_UC_COMPARE.VALUE=10 -DRIVER.RTI.VAR.RTI_1_COMPARE_1_TIME.VALUE=5.000 -DRIVER.RTI.VAR.RTI_1_COMPARE_3_UPDATE.VALUE=100000 +DRIVER.RTI.VAR.RTI_1_FREQ.VALUE=104.000 +DRIVER.RTI.VAR.RTI_1_COMPARE_1_ACTUALTIME.VALUE=10.000 +DRIVER.RTI.VAR.RTI_1_COUNTER_1_UC_COMPARE.VALUE=9 +DRIVER.RTI.VAR.RTI_1_COMPARE_1_TIME.VALUE=10.000 +DRIVER.RTI.VAR.RTI_1_COMPARE_3_UPDATE.VALUE=520000 DRIVER.RTI.VAR.RTI_1_CONTINUE_ON_SUSPEND_ENABLE.VALUE=0x00000000 -DRIVER.RTI.VAR.RTI_1_COMPARE_1_INPUT_FREQ.VALUE=10.000000000 +DRIVER.RTI.VAR.RTI_1_COMPARE_1_INPUT_FREQ.VALUE=10.400000000 DRIVER.RTI.VAR.RTI_1_COMPARE_0_SOURCE.VALUE=0x00000000 DRIVER.RTI.VAR.RTI_1_COMPARE_2_TIME.VALUE=8.000 DRIVER.RTI.VAR.RTI_1_COMPARE_0_ACTUALTIME.VALUE=1.000 -DRIVER.RTI.VAR.RTI_1_COUNTER_0_UC_COMPARE.VALUE=10 -DRIVER.RTI.VAR.RTI_1_COMPARE_1_UPDATE.VALUE=50000 -DRIVER.RTI.VAR.RTI_1_COMPARE_3_TIME.VALUE=10.000 +DRIVER.RTI.VAR.RTI_1_COUNTER_0_UC_COMPARE.VALUE=9 +DRIVER.RTI.VAR.RTI_1_COMPARE_1_UPDATE.VALUE=104000 +DRIVER.RTI.VAR.RTI_1_COMPARE_3_TIME.VALUE=50.000 DRIVER.RTI.VAR.RTI_1_COUNTER_0_NTU_SOURCE.VALUE=0 -DRIVER.RTI.VAR.RTI_1_COMPARE_0_INPUT_FREQ.VALUE=10.000000000 +DRIVER.RTI.VAR.RTI_1_COMPARE_0_INPUT_FREQ.VALUE=10.400000000 DRIVER.RTI.VAR.RTI_1_COUNTER_0_RTI_FREQ.VALUE=0.0 -DRIVER.RTI.VAR.RTI_1_COUNTER_0_FREQ.VALUE=10.000000000 +DRIVER.RTI.VAR.RTI_1_COUNTER_0_FREQ.VALUE=10.400000000 DRIVER.RTI.VAR.RTI_1_COUNTER_1_FREQUENCY.VALUE=10.000 -DRIVER.RTI.VAR.RTI_1_COMPARE_3_SOURCE.VALUE=0x00001000 -DRIVER.RTI.VAR.RTI_1_COUNTER_1_FREQ.VALUE=10.000000000 +DRIVER.RTI.VAR.RTI_1_COMPARE_3_SOURCE.VALUE=0x00000000 +DRIVER.RTI.VAR.RTI_1_COUNTER_1_FREQ.VALUE=10.400000000 DRIVER.RTI.VAR.RTI_1_COUNTER_0_NTU_SOURCE_REG.VALUE=0x0 DRIVER.RTI.VAR.RTI_1_COMPARE_1_SOURCE.VALUE=0x00000000 DRIVER.RTI.VAR.RTI_1_NTU_1_FREQ.VALUE=0.0 -DRIVER.RTI.VAR.RTI_1_COMPARE_3_ACTUALTIME.VALUE=10.000 +DRIVER.RTI.VAR.RTI_1_COMPARE_3_ACTUALTIME.VALUE=50.000 DRIVER.RTI.VAR.RTI_1_COMPARE_0_FREQ.VALUE=0.001000000 -DRIVER.RTI.VAR.RTI_1_COMPARE_2_UPDATE.VALUE=80000 +DRIVER.RTI.VAR.RTI_1_COMPARE_2_UPDATE.VALUE=83200 DRIVER.RTI.VAR.RTI_1_BASE.VALUE=0xFFFFFC00 DRIVER.RTI.VAR.RTI_1_NTU_2_FREQ.VALUE=0.0 -DRIVER.RTI.VAR.RTI_1_COMPARE_3_INPUT_FREQ.VALUE=10.000000000 +DRIVER.RTI.VAR.RTI_1_COMPARE_3_INPUT_FREQ.VALUE=10.400000000 DRIVER.RTI.VAR.RTI_1_COMPARE_1_FREQ.VALUE=0.000200000 DRIVER.RTI.VAR.RTI_1_COUNTER_0_CAPTURE_SOURCE_ENABLE.VALUE=0 DRIVER.RTI.VAR.RTI_1_COUNTER_1_CAPTURE_SOURCE_ENABLE.VALUE=0 -DRIVER.RTI.VAR.RTI_1_COMPARE_0_UPDATE.VALUE=10000 +DRIVER.RTI.VAR.RTI_1_COMPARE_0_UPDATE.VALUE=10400 DRIVER.RTI.VAR.RTI_1_NTU_3_FREQ.VALUE=220.000 -DRIVER.RTI.VAR.RTI_1_COMPARE_0.VALUE=10000 +DRIVER.RTI.VAR.RTI_1_COMPARE_0.VALUE=10400 DRIVER.RTI.VAR.RTI_1_COMPARE_2_ACTUALTIME.VALUE=8.000 -DRIVER.RTI.VAR.RTI_1_COMPARE_1.VALUE=50000 -DRIVER.RTI.VAR.RTI_1_COMPARE_2.VALUE=80000 -DRIVER.RTI.VAR.RTI_1_COMPARE_3.VALUE=100000 +DRIVER.RTI.VAR.RTI_1_COMPARE_1.VALUE=104000 +DRIVER.RTI.VAR.RTI_1_COMPARE_2.VALUE=83200 +DRIVER.RTI.VAR.RTI_1_COMPARE_3.VALUE=520000 DRIVER.RTI.VAR.RTI_1_COUNTER_0_NTU_FREQ.VALUE=0.000 DRIVER.RTI.VAR.RTI_1_COMPARE_2_FREQ.VALUE=0.000125000 -DRIVER.RTI.VAR.RTI_1_COMPARE_0_TIME.VALUE=1.000 +DRIVER.RTI.VAR.RTI_1_COMPARE_0_TIME.VALUE=1 DRIVER.RTI.VAR.RTI_1_NTU_4_FREQ.VALUE=0.000 -DRIVER.RTI.VAR.RTI_1_COMPARE_2_INPUT_FREQ.VALUE=10.000000000 +DRIVER.RTI.VAR.RTI_1_COMPARE_2_INPUT_FREQ.VALUE=10.400000000 DRIVER.RTI.VAR.RTI_1_COUNTER_0_FREQUENCY.VALUE=10.000 DRIVER.GIO.VAR.GIO_PORT1_BIT4_PULL.VALUE=1 DRIVER.GIO.VAR.GIO_PORT0_BIT5_DIR.VALUE=0 @@ -1527,8 +1527,8 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT2_POL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT6_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT2_PSL.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT6_DIR.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT2_DOUT.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT6_DIR.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT0_BIT2_DOUT.VALUE=1 DRIVER.GIO.VAR.GIO_PORT0_BIT3_LVL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT4_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT3_POL.VALUE=0 @@ -1542,7 +1542,7 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT4_POL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT2_PULDIS.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT4_PSL.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT0_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT0_BIT0_PULL.VALUE=2 DRIVER.GIO.VAR.GIO_PORT0_BIT3_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT5_LVL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT6_PDR.VALUE=0 @@ -1554,8 +1554,8 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT7_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT6_POL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT0_DOUT.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT6_PSL.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT0_BIT6_PSL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULL.VALUE=2 DRIVER.GIO.VAR.GIO_PORT0_BIT4_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT7_LVL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULDIS.VALUE=0 @@ -1569,12 +1569,12 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT5_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT0_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT5_PULDIS.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT1_BIT0_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT0_DIR.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT2_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULL.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT1_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT6_DOUT.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT1_BIT1_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT1_DIR.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT6_PULDIS.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT2_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT2_DIR.VALUE=0 @@ -1585,7 +1585,7 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT4_PULL.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT3_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT7_DOUT.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT1_BIT3_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT3_DIR.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT0_LVL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT1_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT0_POL.VALUE=0 @@ -1621,7 +1621,7 @@ DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULL.VALUE=1 DRIVER.GIO.VAR.GIO_PORT0_BIT1_DIR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT5_DOUT.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT7_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULDIS.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT3_PSL.VALUE=0 @@ -1630,17 +1630,17 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT2_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT5_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT4_POL.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=1 DRIVER.GIO.VAR.GIO_PORT0_BIT0_DOUT.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT4_PSL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT0_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORTB_ENABLE.VALUE=1 DRIVER.GIO.VAR.GIO_PORT1_BIT5_LVL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT3_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT6_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT5_POL.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT3_DIR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT6_DOUT.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULL.VALUE=1 @@ -1653,7 +1653,7 @@ DRIVER.GIO.VAR.GIO_PORT0_BIT4_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT7_PDR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT6_POL.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT0_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT0_PSL.VALUE=1 DRIVER.GIO.VAR.GIO_PORT0_BIT4_DIR.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULDIS.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT1_DOUT.VALUE=0 @@ -1664,7 +1664,7 @@ DRIVER.GIO.VAR.GIO_PORT1_BIT7_LVL.VALUE=0 DRIVER.GIO.VAR.GIO_PORT0_BIT5_ENA.VALUE=0 DRIVER.GIO.VAR.GIO_PORT1_BIT7_POL.VALUE=0 -DRIVER.GIO.VAR.GIO_PORT0_BIT1_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT1_PSL.VALUE=1 DRIVER.SCI.VAR.SCILIN_TIMMINGMODE.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DIR.VALUE=0 DRIVER.SCI.VAR.SCI_TIMMINGMODE.VALUE=1 @@ -1673,31 +1673,31 @@ DRIVER.SCI.VAR.SCI_PORT_BIT2_PULL.VALUE=2 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DIR.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT0_DIR.VALUE=0 -DRIVER.SCI.VAR.SCI_ACTUALBAUDRATE.VALUE=9602 +DRIVER.SCI.VAR.SCI_ACTUALBAUDRATE.VALUE=116071 DRIVER.SCI.VAR.SCI_EVENPARITY.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_FUN.VALUE=0 -DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCILIN_PORT_BIT2_DIR.VALUE=1 DRIVER.SCI.VAR.SCILIN_RXINTLVL.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT1_DIR.VALUE=0 DRIVER.SCI.VAR.SCI_BASE_PORT.VALUE=0xFFF7E540 -DRIVER.SCI.VAR.SCILIN_PRESCALE.VALUE=715 +DRIVER.SCI.VAR.SCILIN_PRESCALE.VALUE=6 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PDR.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_FUN.VALUE=1 DRIVER.SCI.VAR.SCI_PORT_BIT0_FUN.VALUE=0 -DRIVER.SCI.VAR.SCI_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI_PORT_BIT2_DIR.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PDR.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT0_PDR.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT2_FUN.VALUE=1 DRIVER.SCI.VAR.SCILIN_PEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT1_FUN.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PSL.VALUE=1 -DRIVER.SCI.VAR.SCI_OEINTENA.VALUE=0 -DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI_OEINTENA.VALUE=1 +DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PDR.VALUE=1 DRIVER.SCI.VAR.SCI_PORT_BIT1_PDR.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT2_FUN.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PSL.VALUE=1 DRIVER.SCI.VAR.SCI_PORT_BIT0_PSL.VALUE=1 -DRIVER.SCI.VAR.SCI_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI_PORT_BIT2_PDR.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PSL.VALUE=1 DRIVER.SCI.VAR.SCI_PORT_BIT1_PSL.VALUE=1 DRIVER.SCI.VAR.SCILIN_BREAKINTENA.VALUE=0 @@ -1706,19 +1706,19 @@ DRIVER.SCI.VAR.SCI_PORT_BIT2_PSL.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULDIS.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT1_PULDIS.VALUE=0 -DRIVER.SCI.VAR.SCI_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI_FEINTENA.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_DOUT.VALUE=0 DRIVER.SCI.VAR.SCI_OEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCI_TXINTENA.VALUE=0 DRIVER.SCI.VAR.SCILIN_PARITYENA.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_DOUT.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT0_DOUT.VALUE=0 -DRIVER.SCI.VAR.SCI_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI_BAUDRATE.VALUE=115200 DRIVER.SCI.VAR.SCILIN_BREAKINTLVL.VALUE=0 DRIVER.SCI.VAR.SCI_WAKEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_PORT_BIT0_PULDIS.VALUE=0 DRIVER.SCI.VAR.SCI_BREAKINTLVL.VALUE=0 -DRIVER.SCI.VAR.SCI_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI_STOPBITS.VALUE=1 DRIVER.SCI.VAR.SCI_RXINTENA.VALUE=0 DRIVER.SCI.VAR.SCI_FEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_EVENPARITY.VALUE=0 @@ -1734,7 +1734,7 @@ DRIVER.SCI.VAR.SCILIN_BASE.VALUE=0xFFF7E400 DRIVER.SCI.VAR.SCI_RXINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_FEINTENA.VALUE=0 -DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=715 +DRIVER.SCI.VAR.SCI_PRESCALE.VALUE=55 DRIVER.SCI.VAR.SCILIN_OEINTLVL.VALUE=0 DRIVER.SCI.VAR.SCILIN_TXINTENA.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT2_PULDIS.VALUE=0 @@ -1745,14 +1745,14 @@ DRIVER.SCI.VAR.SCI_LENGTH.VALUE=8 DRIVER.SCI.VAR.SCILIN_CLKMODE.VALUE=1 DRIVER.SCI.VAR.SCILIN_BASE_PORT.VALUE=0xFFF7E440 -DRIVER.SCI.VAR.SCILIN_BAUDRATE.VALUE=9600 -DRIVER.SCI.VAR.SCILIN_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCILIN_BAUDRATE.VALUE=921600 +DRIVER.SCI.VAR.SCILIN_STOPBITS.VALUE=1 DRIVER.SCI.VAR.SCILIN_PORT_BIT2_PULL.VALUE=2 DRIVER.SCI.VAR.SCI_PORT_BIT1_PULL.VALUE=2 DRIVER.SCI.VAR.SCILIN_RXINTENA.VALUE=0 DRIVER.SCI.VAR.SCILIN_LENGTH.VALUE=8 DRIVER.SCI.VAR.SCILIN_FEINTLVL.VALUE=0 -DRIVER.SCI.VAR.SCILIN_ACTUALBAUDRATE.VALUE=9602 +DRIVER.SCI.VAR.SCILIN_ACTUALBAUDRATE.VALUE=928571 DRIVER.SCI.VAR.SCILIN_PORT_BIT1_PULDIS.VALUE=0 DRIVER.SCI.VAR.SCI_PORT_BIT0_PULDIS.VALUE=0 DRIVER.SCI.VAR.SCI_BASE.VALUE=0xFFF7E500 @@ -1790,7 +1790,7 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=19.231 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0 @@ -1839,14 +1839,14 @@ DRIVER.MIBSPI.VAR.MIBSPI3_TG3_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4 DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=9.615 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0 @@ -1855,17 +1855,17 @@ DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4 DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1 @@ -1885,18 +1885,18 @@ DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED -DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0 @@ -1914,7 +1914,7 @@ DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0 @@ -1932,10 +1932,10 @@ DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=20 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=9.615 DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0 @@ -1960,7 +1960,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18 @@ -1988,7 +1988,7 @@ DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_USE_CS_ENCODE.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_TG4_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0 @@ -2086,10 +2086,10 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4 @@ -2136,10 +2136,10 @@ DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=19.231 DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0 @@ -2151,8 +2151,8 @@ DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2 @@ -2162,27 +2162,27 @@ DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4 DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000 -DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0 @@ -2204,7 +2204,7 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG6_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0 @@ -2226,7 +2226,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1 @@ -2248,13 +2248,13 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4 DRIVER.MIBSPI.VAR.MIBSPI1_TG0_CS_ENCODE.VALUE=0xFF @@ -2273,7 +2273,7 @@ DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=9.615 DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4 @@ -2311,7 +2311,7 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED @@ -2336,7 +2336,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=11 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF @@ -2347,7 +2347,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_USE_CS_ENCODE.VALUE=0 @@ -2398,20 +2398,20 @@ DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=109 -DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=103 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0 @@ -2431,15 +2431,15 @@ DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000 DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED -DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0 @@ -2477,7 +2477,7 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF @@ -2509,9 +2509,9 @@ DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1 -DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=19.231 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_NONE DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0 @@ -2546,30 +2546,30 @@ DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000 -DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=109 -DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=103 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=8 DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=109 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=103 DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16 -DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=1 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0 -DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_1 DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0 DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16 @@ -2583,14 +2583,14 @@ DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0 DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0 -DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=9.615 DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT4_DOUT.VALUE=1 DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0 DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2 -DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=0 DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0 DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0 DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0 @@ -2618,15 +2618,15 @@ DRIVER.SPI.VAR.SPI1_PORT_BIT17_DIR.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0 -DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=109 -DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=103 +DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=103 DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT27_DIR.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT19_DIR.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=1 -DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=103 DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1 -DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=103 DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0 DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0 DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618 @@ -2635,7 +2635,7 @@ DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT25_PDR.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT17_PDR.VALUE=0 -DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=19.231 DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0 DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1 DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0 @@ -2714,7 +2714,7 @@ DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT25_PDR.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT17_PDR.VALUE=0 -DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=19.231 DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0 DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0 DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0 @@ -2754,17 +2754,17 @@ DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT5_PDR.VALUE=0 DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000 -DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=103 DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF0E0000 -DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=103 DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16 DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2 -DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=103 DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16 DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0 -DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=103 DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0 -DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=9.615 DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16 DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1 DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16 @@ -2832,7 +2832,7 @@ DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1 -DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=9.615 DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1 DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2 DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0 @@ -2870,7 +2870,7 @@ DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0 DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000 DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0 -DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=19.231 DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000 DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000 DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0 @@ -2912,7 +2912,7 @@ DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000 DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0 DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000 -DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=0 DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1 DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2 DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000 @@ -2924,19 +2924,19 @@ DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800 DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2 DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0 -DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=103 DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1 DRIVER.SPI.VAR.SPI3_PORT_BIT4_DOUT.VALUE=1 DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT25_DOUT.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT17_DOUT.VALUE=0 -DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=103 DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0 DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0 -DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=103 DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0 DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1 -DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=103 DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0 @@ -2958,7 +2958,7 @@ DRIVER.SPI.VAR.SPI5_PORT_BIT27_DOUT.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT19_DOUT.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1 -DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=0 DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2 DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0 DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0 @@ -2977,7 +2977,7 @@ DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16 DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1 DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2 -DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=0 DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0 DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0 @@ -2987,7 +2987,7 @@ DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1 DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0 -DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=9.615 DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00 DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2 @@ -3030,17 +3030,17 @@ DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0 DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0 DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0 -DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=19.231 DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1 DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0 -DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=109 -DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=109 +DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=103 +DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=103 DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0 -DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=103 DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0 -DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=103 DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1 DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0 @@ -3139,7 +3139,7 @@ DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1 DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0 DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0 -DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=9.091 +DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=9.615 DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0 DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0 DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0 @@ -3188,7 +3188,7 @@ DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0 DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0 DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0 -DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=18.182 +DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=19.231 DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0 DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1 DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0 @@ -3207,14 +3207,14 @@ DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT5_DIR.VALUE=1 DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0 -DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=109 +DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=103 DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1 DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0 -DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=109 -DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=109 +DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=103 +DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=103 DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULL.VALUE=2 DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1 -DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=109 +DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=103 DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0 DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000 DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0 @@ -3265,7 +3265,7 @@ DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0 DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0 DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0 -DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=0 DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0 DRIVER.SPI.VAR.SPI1_PORT_BIT5_FUN.VALUE=1 DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0 @@ -3300,7 +3300,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_21_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000 @@ -3334,7 +3334,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=250 DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_63_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_55_RTR.VALUE=0x00000000 @@ -3365,7 +3365,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_51_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 @@ -3392,8 +3392,8 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1 -DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=3 +DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=0 +DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=2 DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000 @@ -3415,7 +3415,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000 @@ -3507,7 +3507,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25 DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17 DRIVER.CAN.VAR.CAN_1_MESSAGE_10_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=4.000 DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=1 @@ -3522,7 +3522,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=3 DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1 DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 @@ -3589,14 +3589,14 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2 DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=11 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=8 DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_58_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=72.727 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=75.000 DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF @@ -3611,7 +3611,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51 DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43 @@ -3695,7 +3695,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_59_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=0 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000 @@ -3735,15 +3735,15 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=250.000 DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5 DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_3_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=4.000 DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_21_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000 @@ -3759,7 +3759,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005 DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0 -DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62 @@ -3768,7 +3768,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46 DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38 DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=11 +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8 @@ -3778,16 +3778,16 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_1_TQ.VALUE=181.818 +DRIVER.CAN.VAR.CAN_1_TQ.VALUE=250.000 DRIVER.CAN.VAR.CAN_3_MESSAGE_63_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_55_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_47_RTR.VALUE=0x00000000 @@ -3851,7 +3851,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_TQ.VALUE=181.818 +DRIVER.CAN.VAR.CAN_2_TQ.VALUE=250.000 DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7 @@ -3878,7 +3878,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64 DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56 @@ -3897,13 +3897,13 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_3_TQ.VALUE=181.818 +DRIVER.CAN.VAR.CAN_3_TQ.VALUE=250.000 DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0 @@ -3982,7 +3982,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_5_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11 -DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=11 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=16 DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 @@ -4002,7 +4002,7 @@ DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1 DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1 DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58 DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75 @@ -4018,8 +4018,8 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000 @@ -4138,7 +4138,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 @@ -4148,17 +4148,17 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8 -DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=5.500 -DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=4.000 +DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=4.000 DRIVER.CAN.VAR.CAN_3_MESSAGE_20_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF @@ -4249,9 +4249,9 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0 -DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1 DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8 @@ -4264,14 +4264,14 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_13_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=72.727 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=75.000 DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=1 -DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005 -DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=3 +DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=2 DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF @@ -4384,7 +4384,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_1_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=0x601 DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8 @@ -4395,8 +4395,8 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0 @@ -4420,9 +4420,9 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_1_BRP.VALUE=19 +DRIVER.CAN.VAR.CAN_1_BRP.VALUE=25 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0 -DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=3 DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF @@ -4440,7 +4440,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_34_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_26_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_18_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=0x602 DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8 @@ -4481,7 +4481,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19 DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0 -DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=1 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_43_EOB.VALUE=0x00000000 @@ -4512,7 +4512,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=0x603 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8 @@ -4523,8 +4523,8 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_15_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0 @@ -4554,7 +4554,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_3_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_BRP.VALUE=19 +DRIVER.CAN.VAR.CAN_2_BRP.VALUE=25 DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0 @@ -4574,7 +4574,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_35_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_27_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_19_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=0x604 DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8 @@ -4645,14 +4645,14 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x80000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21 DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=0x605 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8 @@ -4668,7 +4668,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000080 DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF @@ -4691,7 +4691,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_4_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_3_BRP.VALUE=19 +DRIVER.CAN.VAR.CAN_3_BRP.VALUE=25 DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 @@ -4706,7 +4706,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=3 +DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=6 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30 DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14 @@ -4721,14 +4721,14 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=0x606 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0 DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8 -DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 @@ -4791,7 +4791,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1 -DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=0x607 DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000 @@ -4806,8 +4806,8 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_9_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0 @@ -4931,7 +4931,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8 -DRIVER.CAN.VAR.CAN_1_SJW.VALUE=3 +DRIVER.CAN.VAR.CAN_1_SJW.VALUE=4 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_42_EOB.VALUE=0x00000000 @@ -4987,7 +4987,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50 DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42 @@ -5012,7 +5012,7 @@ DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_59_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000 @@ -5061,7 +5061,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_6_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_SJW.VALUE=3 +DRIVER.CAN.VAR.CAN_2_SJW.VALUE=2 DRIVER.CAN.VAR.CAN_3_MESSAGE_51_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_43_EOB.VALUE=0x00000000 @@ -5086,7 +5086,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8 -DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=2 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 @@ -5145,8 +5145,8 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8 -DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=5.500 -DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=5.500 +DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=4.000 +DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=4.000 DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_2_MESSAGE_64_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000 @@ -5163,7 +5163,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=3 DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF @@ -5179,7 +5179,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_7_RTR.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_3_SJW.VALUE=3 +DRIVER.CAN.VAR.CAN_3_SJW.VALUE=2 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_60_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000 @@ -5212,9 +5212,9 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=72.727 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=62.500 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0 @@ -5238,7 +5238,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8 -DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000 @@ -5250,7 +5250,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_60_RTR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_52_RTR.VALUE=0x00000000 @@ -5321,11 +5321,11 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8 DRIVER.CAN.VAR.CAN_3_MESSAGE_9_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000 -DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=1 DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000080 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0 @@ -5498,7 +5498,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF -DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=1 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_RTR.VALUE=0x00000000 @@ -5524,7 +5524,7 @@ DRIVER.CAN.VAR.CAN_3_MESSAGE_39_EOB.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000 DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 -DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=0 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000 @@ -5536,7 +5536,7 @@ DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8 DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0 DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00002000 DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000 @@ -5551,14 +5551,14 @@ DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000008 DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 -DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=20 DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=1 -DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=20 DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=3.271 DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000 @@ -5572,34 +5572,34 @@ DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=300.00 -DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=384.60 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=2 DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00040000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000800 DRIVER.ADC.VAR.ADC1_BND.VALUE=2 DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=0 DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULDIS.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 -DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000100 +DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000020 +DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=503.22 +DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=3.271 DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT -DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000002 DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300 DRIVER.ADC.VAR.ADC2_BND.VALUE=2 DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_PORT_BIT0_PDR.VALUE=0 -DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=100.00 -DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=96.15 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=2 DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=300.00 DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000 @@ -5615,15 +5615,15 @@ DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=300.00 DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16 -DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=0 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULDIS.VALUE=0 DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00010000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=500.00 DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_PORT_BIT0_PSL.VALUE=1 @@ -5635,14 +5635,14 @@ DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00 -DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=2 DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000040 DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000 DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8 DRIVER.ADC.VAR.ADC1_PORT_BIT0_DOUT.VALUE=0 -DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=919.340 DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16 DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000 @@ -5658,32 +5658,32 @@ DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005 -DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=250.00 DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00400000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00004000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=32 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000010 DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000 DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000 DRIVER.ADC.VAR.ADC1_PORT_BIT0_DIR.VALUE=0 DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005 DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=300.00 -DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32 -DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=384.60 +DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=44 +DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000 @@ -5701,17 +5701,17 @@ DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=10 DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00080000 DRIVER.ADC.VAR.ADC2_PORT_BIT0_DOUT.VALUE=0 DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00 DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=10 +DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=9 DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00001000 DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=300.00 DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200 @@ -5725,26 +5725,26 @@ DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0 DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300 -DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000004 +DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=3.271 +DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=0 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2 -DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300 DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0 -DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=500.00 DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000 DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT -DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 -DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=76.403740 +DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=503.22 DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1 -DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=503.22 DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16 DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000 @@ -5754,25 +5754,25 @@ DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00020000 DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000400 DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=250 DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0 DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000080 DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00 DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT -DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000001 DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00 DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000 -DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=20 DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1 DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 @@ -5791,13 +5791,13 @@ DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00800000 DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=10 -DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=25 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=384.60 DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0 DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULL.VALUE=2 DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64 @@ -5808,8 +5808,8 @@ DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000 -DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000020 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=500.00 DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000 DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000 DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000 @@ -5831,17 +5831,17 @@ DRIVER.LIN.VAR.LIN_BEINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_TOA3WUSINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_PORT_BIT1_DOUT.VALUE=0 -DRIVER.LIN.VAR.LIN_MAXPRESCALE.VALUE=4954 +DRIVER.LIN.VAR.LIN_MAXPRESCALE.VALUE=4680 DRIVER.LIN.VAR.LIN_LENGTH.VALUE=8 DRIVER.LIN.VAR.LIN_PARITYENA.VALUE=0 DRIVER.LIN.VAR.LIN_BREAKINTENA.VALUE=0x00000000 -DRIVER.LIN.VAR.LIN_TX_MASK.VALUE=0xFF -DRIVER.LIN.VAR.LIN_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN_TX_MASK.VALUE=0x00 +DRIVER.LIN.VAR.LIN_MSTMOD.VALUE=0 DRIVER.LIN.VAR.LIN_SDEL.VALUE=1 DRIVER.LIN.VAR.LIN_PORT_BIT2_DOUT.VALUE=0 DRIVER.LIN.VAR.LIN_TOAWUSINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_WAKEINTENA.VALUE=0x00000000 -DRIVER.LIN.VAR.LIN_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN_HGENCTRL.VALUE=0 DRIVER.LIN.VAR.LIN_TOA3WUSINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_PORT_BIT0_DIR.VALUE=0 DRIVER.LIN.VAR.LIN_PORT_BIT0_PULL.VALUE=2 @@ -5852,7 +5852,7 @@ DRIVER.LIN.VAR.LIN_PORT_BIT0_FUN.VALUE=0 DRIVER.LIN.VAR.LIN_PORT_BIT1_PULDIS.VALUE=0 DRIVER.LIN.VAR.LIN_PORT_BIT2_DIR.VALUE=0 -DRIVER.LIN.VAR.LIN_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN_PORT_BIT1_PULL.VALUE=1 DRIVER.LIN.VAR.LIN_WAKEINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_PORT_BIT0_PDR.VALUE=0 DRIVER.LIN.VAR.LIN_OEINTENA.VALUE=0x00000000 @@ -5862,23 +5862,23 @@ DRIVER.LIN.VAR.LIN_PORT_BIT2_FUN.VALUE=4 DRIVER.LIN.VAR.LIN_CEINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_PORT_BIT0_PSL.VALUE=1 -DRIVER.LIN.VAR.LIN_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN_PORT_BIT2_PULL.VALUE=1 DRIVER.LIN.VAR.LIN_PBEINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_PORT_BIT2_PDR.VALUE=0 DRIVER.LIN.VAR.LIN_BASE_PORT.VALUE=0xFFF7E440 -DRIVER.LIN.VAR.LIN_ACTUALBAUDRATE.VALUE=19.985 -DRIVER.LIN.VAR.LIN_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN_ACTUALBAUDRATE.VALUE=20.000 +DRIVER.LIN.VAR.LIN_PORT_BIT1_PSL.VALUE=0 DRIVER.LIN.VAR.LIN_ISFEINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_FEINTENA.VALUE=0x00000000 -DRIVER.LIN.VAR.LIN_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN_PORT_BIT2_PSL.VALUE=0 DRIVER.LIN.VAR.LIN_OEINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_TXINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_NREINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_IDINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_SBREAK.VALUE=13 DRIVER.LIN.VAR.LIN_TOINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_BAUDRATE.VALUE=20.000 -DRIVER.LIN.VAR.LIN_RX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN_RX_MASK.VALUE=0x00 DRIVER.LIN.VAR.LIN_ISFEINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_RXINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_BASE.VALUE=0xFFF7E400 @@ -5888,15 +5888,15 @@ DRIVER.LIN.VAR.LIN_IDINTLVL.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_PEINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_TOINTLVL.VALUE=0x00000000 -DRIVER.LIN.VAR.LIN_MAXBAUDRATE.VALUE=22.204 +DRIVER.LIN.VAR.LIN_MAXBAUDRATE.VALUE=22.222 DRIVER.LIN.VAR.LIN_BEINTENA.VALUE=0x00000000 DRIVER.LIN.VAR.LIN_RXINTLVL.VALUE=0x00000000 -DRIVER.LIN.VAR.LIN_PRESCALE.VALUE=343 +DRIVER.LIN.VAR.LIN_PRESCALE.VALUE=324 DRIVER.LIN.VAR.LIN_PORT_BIT0_PULDIS.VALUE=0 DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=2 DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000 DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0 DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000 @@ -5912,7 +5912,7 @@ DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0 DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3 DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000 @@ -5926,10 +5926,10 @@ DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=9 +DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=12 DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0 DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000 @@ -5942,7 +5942,7 @@ DRIVER.HET.VAR.HET2_BIT11_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT11_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_PWM4_PIN_SELECT.VALUE=16 -DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM4_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET1_RAM_BASE.VALUE=0xFF460000 DRIVER.HET.VAR.HET2_EDGE6_BOTH.VALUE=0 DRIVER.HET.VAR.HET2_PWM2_DUTY_LVL.VALUE=0x00000000 @@ -5977,17 +5977,17 @@ DRIVER.HET.VAR.HET1_BIT29_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT0_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT8_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET1_PWM4_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET2_BIT1_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT12_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM7_ACTION.VALUE=3 -DRIVER.HET.VAR.HET2_PWM4_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET2_PWM4_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET2_BIT18_PULL.VALUE=1 DRIVER.HET.VAR.HET2_BIT16_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM3_DUTY_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM3_POLARITY.VALUE=3 DRIVER.HET.VAR.HET1_BIT0_XORSHARE.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM1_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET2_PWM1_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_BIT6_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_CAP5_PIN_SELECT.VALUE=26 DRIVER.HET.VAR.HET1_BIT28_PSL.VALUE=0x00000000 @@ -5997,10 +5997,10 @@ DRIVER.HET.VAR.HET2_BIT1_PULL.VALUE=1 DRIVER.HET.VAR.HET1_EDGE7_EVENT.VALUE=1 DRIVER.HET.VAR.HET1_EDGE5_BOTH.VALUE=0 -DRIVER.HET.VAR.HET1_PWM5_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET1_PWM5_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_BIT3_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_EDGE7_POLARITY.VALUE=0 -DRIVER.HET.VAR.HET1_EDGE1_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE1_INTENA.VALUE=0x00040000 DRIVER.HET.VAR.HET1_PWM3_DUTY.VALUE=50 DRIVER.HET.VAR.HET1_PWM1_PERIOD_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT14_PDR.VALUE=0x00000000 @@ -6013,13 +6013,13 @@ DRIVER.HET.VAR.HET2_PWM0_PERIOD_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT2_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT5_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM7_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET1_PWM7_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET1_BIT8_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT1_PDR.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_LR_ACTUALTIME.VALUE=1163.636 -DRIVER.HET.VAR.HET1_PWM5_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_LR_ACTUALTIME.VALUE=1230.769 +DRIVER.HET.VAR.HET1_PWM5_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_PWM5_PERIOD_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM4_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_PWM4_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET2_BIT9_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM3_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM0_DUTY_INTENA.VALUE=0x00000000 @@ -6042,13 +6042,13 @@ DRIVER.HET.VAR.HET1_BIT29_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT0_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET_DIS_BLACKBOX.VALUE=0 -DRIVER.HET.VAR.HET2_PWM7_DUTYTIME.VALUE=501.527 -DRIVER.HET.VAR.HET2_HR_ACTUALFREQUENCY.VALUE=110.000 +DRIVER.HET.VAR.HET2_PWM7_DUTYTIME.VALUE=500.923 +DRIVER.HET.VAR.HET2_HR_ACTUALFREQUENCY.VALUE=104.000 DRIVER.HET.VAR.HET2_PWM5_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM4_ACTION.VALUE=3 DRIVER.HET.VAR.HET1_BIT25_PULL.VALUE=1 DRIVER.HET.VAR.HET1_BIT17_PULL.VALUE=1 -DRIVER.HET.VAR.HET1_BIT4_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT4_DIR.VALUE=0x00000010 DRIVER.HET.VAR.HET2_EDGE0_POLARITY.VALUE=0 DRIVER.HET.VAR.HET1_CAP6_POLARITY.VALUE=0 DRIVER.HET.VAR.HET1_BIT20_PULDIS.VALUE=0x00000000 @@ -6059,7 +6059,7 @@ DRIVER.HET.VAR.HET2_INT_X11.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X20.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X12.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM3_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET1_PWM3_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET2_PWM6_ENA.VALUE=0 DRIVER.HET.VAR.HET2_BIT16_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X21.VALUE=0x00000000 @@ -6077,7 +6077,7 @@ DRIVER.HET.VAR.HET2_INT_X31.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X23.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X15.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM3_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET2_PWM3_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET2_INT_X24.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X16.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BASE_PORT.VALUE=0xFFF7B84C @@ -6096,19 +6096,19 @@ DRIVER.HET.VAR.HET2_BIT18_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X28.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM2_PERIOD_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM1_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET1_PWM1_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET2_PWM0_DUTY.VALUE=50 DRIVER.HET.VAR.HET2_BIT18_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET2_INT_X29.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM1_ENA.VALUE=0 DRIVER.HET.VAR.HET2_CAP7_PIN_SELECT.VALUE=6 DRIVER.HET.VAR.HET2_BIT8_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM5_PERIOD.VALUE=1000.000 -DRIVER.HET.VAR.HET1_PWM4_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET1_PWM4_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET1_PWM3_PIN_SELECT.VALUE=14 DRIVER.HET.VAR.HET1_BIT11_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT1_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM0_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM0_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_BIT2_PULL.VALUE=1 DRIVER.HET.VAR.HET1_EDGE6_BOTH.VALUE=0 DRIVER.HET.VAR.HET1_BIT5_DIR.VALUE=0x00000000 @@ -6121,7 +6121,7 @@ DRIVER.HET.VAR.HET1_PIN_ENABLE.VALUE=0 DRIVER.HET.VAR.HET2_BIT16_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT5_DOUT.VALUE=0 -DRIVER.HET.VAR.HET2_PWM0_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_PWM0_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_BIT6_PULL.VALUE=1 DRIVER.HET.VAR.HET2_PWM7_ENA.VALUE=0 DRIVER.HET.VAR.HET1_PWM0_DUTY_INTENA.VALUE=0x00000000 @@ -6143,7 +6143,7 @@ DRIVER.HET.VAR.HET2_BIT9_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT2_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_EDGE0_EVENT.VALUE=1 -DRIVER.HET.VAR.HET1_PWM2_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET1_PWM2_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET1_BIT26_PULL.VALUE=1 DRIVER.HET.VAR.HET1_BIT18_PULL.VALUE=1 DRIVER.HET.VAR.HET1_BIT6_DIR.VALUE=0x00000000 @@ -6153,19 +6153,19 @@ DRIVER.HET.VAR.HET1_CAP4_PIN_SELECT.VALUE=24 DRIVER.HET.VAR.HET1_BIT29_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT0_DOUT.VALUE=0 -DRIVER.HET.VAR.HET2_PWM2_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET2_PWM2_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET2_EDGE3_POLARITY.VALUE=0 DRIVER.HET.VAR.HET1_BIT3_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT2_HRSHARE.VALUE=0x00000002 DRIVER.HET.VAR.HET2_PWM6_PERIOD.VALUE=1000.000 DRIVER.HET.VAR.HET2_BIT8_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM1_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET1_PWM1_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET1_BIT4_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT4_HRSHARE.VALUE=0x00000004 DRIVER.HET.VAR.HET1_BIT25_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT17_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT16_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM1_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET1_PWM1_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_PWM4_PERIOD_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM2_ACTION.VALUE=3 DRIVER.HET.VAR.HET2_PWM1_DUTY.VALUE=50 @@ -6182,7 +6182,7 @@ DRIVER.HET.VAR.HET1_INT_X11.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT3_PULL.VALUE=1 DRIVER.HET.VAR.HET1_EDGE7_BOTH.VALUE=0 -DRIVER.HET.VAR.HET1_EDGE0_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE0_LVL.VALUE=0x00020000 DRIVER.HET.VAR.HET1_BIT7_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X20.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X12.VALUE=0x00000000 @@ -6191,21 +6191,21 @@ DRIVER.HET.VAR.HET1_BIT10_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X21.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X13.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM5_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET2_PWM5_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_BIT18_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT6_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_EDGE4_PIN_SELECT.VALUE=20 DRIVER.HET.VAR.HET1_INT_X30.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X22.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X14.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM3_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM3_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET1_INT_X31.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X23.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X15.VALUE=0x00000000 DRIVER.HET.VAR.HET2_EDGE5_EVENT.VALUE=1 DRIVER.HET.VAR.HET2_PWM1_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM7_PERIOD_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM6_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET1_PWM6_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_BIT7_PULL.VALUE=1 DRIVER.HET.VAR.HET1_INT_X24.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X16.VALUE=0x00000000 @@ -6229,17 +6229,17 @@ DRIVER.HET.VAR.HET2_BIT17_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT14_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_PWM3_PERIOD.VALUE=1000.000 -DRIVER.HET.VAR.HET2_PWM5_DUTY_PRESCALER.VALUE=55296 -DRIVER.HET.VAR.HET1_PWM1_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET2_PWM5_DUTY_PRESCALER.VALUE=52224 +DRIVER.HET.VAR.HET1_PWM1_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET1_BIT10_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_CAP4_POLARITY.VALUE=0 DRIVER.HET.VAR.HET2_BIT8_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT4_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM4_ENA.VALUE=0 DRIVER.HET.VAR.HET1_PWM0_POLARITY.VALUE=3 DRIVER.HET.VAR.HET1_BIT4_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM1_PERIOD_PRESCALER.VALUE=109952 -DRIVER.HET.VAR.HET1_EDGE1_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM1_PERIOD_PRESCALER.VALUE=103936 +DRIVER.HET.VAR.HET1_EDGE1_LVL.VALUE=0x00040000 DRIVER.HET.VAR.HET1_PWM1_PERIOD_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT27_PULL.VALUE=1 DRIVER.HET.VAR.HET1_BIT19_PULL.VALUE=1 @@ -6259,7 +6259,7 @@ DRIVER.HET.VAR.HET1_BIT8_HRSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT4_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET2_EDGE3_PIN_SELECT.VALUE=6 -DRIVER.HET.VAR.HET2_PWM2_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET2_PWM2_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_BIT18_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT11_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT10_PULL.VALUE=1 @@ -6272,11 +6272,11 @@ DRIVER.HET.VAR.HET1_BIT21_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT13_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT5_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM4_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET1_PWM4_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_BIT4_PULL.VALUE=1 -DRIVER.HET.VAR.HET1_EDGE2_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE2_LVL.VALUE=0x00080000 DRIVER.HET.VAR.HET1_PWM2_DUTY_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM2_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET1_PWM2_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_BIT9_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT6_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM6_DUTY.VALUE=50 @@ -6292,17 +6292,17 @@ DRIVER.HET.VAR.HET1_BIT15_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_CAP3_PIN_SELECT.VALUE=6 DRIVER.HET.VAR.HET1_BIT7_PDR.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM6_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM6_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_PWM4_DUTY_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM1_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_PWM1_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET2_BIT12_PULL.VALUE=1 -DRIVER.HET.VAR.HET1_PWM0_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET1_PWM0_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET1_PWM0_ACTION.VALUE=3 DRIVER.HET.VAR.HET1_CAP5_POLARITY.VALUE=0 DRIVER.HET.VAR.HET1_BIT26_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT18_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT15_DOUT.VALUE=0 -DRIVER.HET.VAR.HET2_PWM0_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET2_PWM0_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET1_EDGE4_EVENT.VALUE=1 DRIVER.HET.VAR.HET1_BIT20_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT12_DIR.VALUE=0x00000000 @@ -6333,8 +6333,8 @@ DRIVER.HET.VAR.HET2_BIT2_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT2_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM7_PIN_SELECT.VALUE=19 -DRIVER.HET.VAR.HET1_PWM5_ACTUALPERIOD.VALUE=1000.727 -DRIVER.HET.VAR.HET1_LR_ACTUALTIME.VALUE=1163.636 +DRIVER.HET.VAR.HET1_PWM5_ACTUALPERIOD.VALUE=1000.615 +DRIVER.HET.VAR.HET1_LR_ACTUALTIME.VALUE=1230.769 DRIVER.HET.VAR.HET1_BIT21_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT13_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT11_PULL.VALUE=1 @@ -6345,18 +6345,18 @@ DRIVER.HET.VAR.HET1_BIT22_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT14_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT7_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_HR_ACTUALFREQUENCY.VALUE=110.000 +DRIVER.HET.VAR.HET1_HR_ACTUALFREQUENCY.VALUE=104.000 DRIVER.HET.VAR.HET2_PWM1_ACTION.VALUE=3 DRIVER.HET.VAR.HET2_BIT5_PULL.VALUE=1 DRIVER.HET.VAR.HET1_EDGE4_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_CAP0_POLARITY.VALUE=0 DRIVER.HET.VAR.HET2_BIT4_XORSHARE.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_EDGE2_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE2_INTENA.VALUE=0x00080000 DRIVER.HET.VAR.HET1_PWM7_DUTY.VALUE=50 DRIVER.HET.VAR.HET1_PWM2_DUTY_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT8_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT11_PDR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM7_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET1_PWM7_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_EDGE6_EVENT.VALUE=1 DRIVER.HET.VAR.HET2_MASTER.VALUE=1 DRIVER.HET.VAR.HET1_PWM5_DUTY_LVL.VALUE=0x00000000 @@ -6368,7 +6368,7 @@ DRIVER.HET.VAR.HET1_PWM1_PIN_SELECT.VALUE=10 DRIVER.HET.VAR.HET1_BIT9_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT13_PULL.VALUE=1 -DRIVER.HET.VAR.HET1_PWM7_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET1_PWM7_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_PWM5_PERIOD_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT24_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT16_XORSHARE.VALUE=0x00000000 @@ -6379,7 +6379,7 @@ DRIVER.HET.VAR.HET2_PWM7_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_EDGE0_BOTH.VALUE=0 DRIVER.HET.VAR.HET1_BIT30_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_BIT22_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT22_DIR.VALUE=0x00400000 DRIVER.HET.VAR.HET1_BIT14_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X0.VALUE=0x00000000 DRIVER.HET.VAR.HET2_EDGE2_POLARITY.VALUE=0 @@ -6395,7 +6395,7 @@ DRIVER.HET.VAR.HET1_DIS_BLACKBOX.VALUE=0 DRIVER.HET.VAR.HET2_LR_TIME.VALUE=800.000 DRIVER.HET.VAR.HET1_INT_X3.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM6_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_PWM6_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_EDGE5_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM5_ACTION.VALUE=3 DRIVER.HET.VAR.HET1_BIT29_PULL.VALUE=1 @@ -6405,12 +6405,12 @@ DRIVER.HET.VAR.HET1_BIT21_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT13_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_INT_X5.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM2_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET1_PWM2_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET1_BIT20_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT12_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT3_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_INT_X6.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM0_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET1_PWM0_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET1_INT_X7.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BASE_PORT.VALUE=0xFFF7B94C DRIVER.HET.VAR.HET1_INT_X8.VALUE=0x00000000 @@ -6427,7 +6427,7 @@ DRIVER.HET.VAR.HET2_BIT10_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_CAP2_PIN_SELECT.VALUE=4 DRIVER.HET.VAR.HET1_BIT11_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM2_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM2_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_PWM0_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT31_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT23_DIR.VALUE=0x00000000 @@ -6440,7 +6440,7 @@ DRIVER.HET.VAR.HET1_BIT30_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT22_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT14_ANDSHARE.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_PWM6_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET2_PWM6_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET1_PWM6_PERIOD.VALUE=1000.000 DRIVER.HET.VAR.HET1_BIT31_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT23_DOUT.VALUE=0 @@ -6455,28 +6455,28 @@ DRIVER.HET.VAR.HET1_BIT21_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT13_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM2_PERIOD_LVL.VALUE=0x00000000 -DRIVER.HET.VAR.HET2_BIT0_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM3_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_BIT0_DIR.VALUE=0x00000001 +DRIVER.HET.VAR.HET1_PWM3_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET2_CAP3_POLARITY.VALUE=0 DRIVER.HET.VAR.HET2_BIT0_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM3_PIN_SELECT.VALUE=14 DRIVER.HET.VAR.HET2_PWM6_ACTION.VALUE=3 DRIVER.HET.VAR.HET2_BIT14_PULL.VALUE=1 DRIVER.HET.VAR.HET1_EDGE7_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT17_DOUT.VALUE=0 -DRIVER.HET.VAR.HET1_EDGE2_PIN_SELECT.VALUE=13 +DRIVER.HET.VAR.HET1_EDGE2_PIN_SELECT.VALUE=30 DRIVER.HET.VAR.HET1_BIT20_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT12_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_HR_FREQUENCY.VALUE=110.000 -DRIVER.HET.VAR.HET2_PWM2_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_PWM2_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_EDGE5_EVENT.VALUE=1 DRIVER.HET.VAR.HET1_EDGE1_BOTH.VALUE=0 DRIVER.HET.VAR.HET1_PWM5_PERIOD_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT24_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT16_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM1_POLARITY.VALUE=3 DRIVER.HET.VAR.HET2_BIT18_ANDSHARE.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_EDGE0_INTENA.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE0_INTENA.VALUE=0x00020000 DRIVER.HET.VAR.HET2_BIT0_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_PWM6_PIN_SELECT.VALUE=18 DRIVER.HET.VAR.HET2_EDGE2_EVENT.VALUE=1 @@ -6496,8 +6496,8 @@ DRIVER.HET.VAR.HET1_BIT4_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_EDGE7_PIN_SELECT.VALUE=14 DRIVER.HET.VAR.HET2_PWM7_PERIOD.VALUE=1000.000 -DRIVER.HET.VAR.HET2_PWM3_ACTUALPERIOD.VALUE=1000.727 -DRIVER.HET.VAR.HET1_PWM3_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM3_ACTUALPERIOD.VALUE=1000.615 +DRIVER.HET.VAR.HET1_PWM3_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_EDGE3_BOTH.VALUE=0 DRIVER.HET.VAR.HET1_PWM1_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM2_PERIOD_INTENA.VALUE=0x00000000 @@ -6523,7 +6523,7 @@ DRIVER.HET.VAR.HET1_BIT11_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT24_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT16_DOUT.VALUE=0 -DRIVER.HET.VAR.HET2_PWM5_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM5_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_RAM_BASE.VALUE=0xFF440000 DRIVER.HET.VAR.HET2_PWM3_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT7_PULL.VALUE=1 @@ -6547,23 +6547,23 @@ DRIVER.HET.VAR.HET2_BIT0_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM4_PERIOD.VALUE=1000.000 DRIVER.HET.VAR.HET1_BIT30_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_BIT22_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT22_PSL.VALUE=0x00400000 DRIVER.HET.VAR.HET1_BIT14_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_EDGE1_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM7_PERIOD_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_EDGE2_BOTH.VALUE=0 DRIVER.HET.VAR.HET1_BIT26_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_BIT18_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT18_DIR.VALUE=0x00040000 DRIVER.HET.VAR.HET2_PWM1_DUTY_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT16_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT5_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_RAM_PARITY_ENA.VALUE=0x00000005 DRIVER.HET.VAR.HET1_PWM7_PERIOD_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM0_DUTY.VALUE=50 -DRIVER.HET.VAR.HET2_PWM0_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET2_PWM0_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_BIT1_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_CAP1_PIN_SELECT.VALUE=2 -DRIVER.HET.VAR.HET1_PWM7_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET1_PWM7_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET1_BIT2_PULL.VALUE=1 DRIVER.HET.VAR.HET2_PWM6_PERIOD_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM4_POLARITY.VALUE=3 @@ -6574,13 +6574,13 @@ DRIVER.HET.VAR.HET1_BIT24_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT16_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT5_DOUT.VALUE=0 -DRIVER.HET.VAR.HET2_PWM7_PERIOD_PRESCALER.VALUE=109952 -DRIVER.HET.VAR.HET2_PWM7_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_PWM7_PERIOD_PRESCALER.VALUE=103936 +DRIVER.HET.VAR.HET2_PWM7_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET2_PWM4_ACTION.VALUE=3 DRIVER.HET.VAR.HET2_BIT3_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_EDGE5_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT6_ANDSHARE.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM6_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET1_PWM6_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_EDGE4_BOTH.VALUE=0 DRIVER.HET.VAR.HET2_PWM1_PERIOD_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT11_DIR.VALUE=0x00000000 @@ -6591,20 +6591,20 @@ DRIVER.HET.VAR.HET1_BIT31_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT23_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT15_PSL.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM6_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET1_PWM6_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_EDGE2_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM4_DUTY_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT30_PULL.VALUE=1 DRIVER.HET.VAR.HET1_BIT27_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_BIT22_PULL.VALUE=1 +DRIVER.HET.VAR.HET1_BIT22_PULL.VALUE=2 DRIVER.HET.VAR.HET1_BIT19_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT14_PULL.VALUE=1 DRIVER.HET.VAR.HET2_EDGE2_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM6_DUTY.VALUE=50 DRIVER.HET.VAR.HET2_BIT8_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM4_DUTY_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT9_PULDIS.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_EDGE1_PIN_SELECT.VALUE=11 +DRIVER.HET.VAR.HET1_EDGE1_PIN_SELECT.VALUE=14 DRIVER.HET.VAR.HET1_BIT25_DOUT.VALUE=0 DRIVER.HET.VAR.HET1_BIT17_DOUT.VALUE=0 DRIVER.HET.VAR.HET2_BIT8_PULL.VALUE=1 @@ -6613,7 +6613,7 @@ DRIVER.HET.VAR.HET2_BIT14_ANDSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT2_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM5_PERIOD.VALUE=1000.000 -DRIVER.HET.VAR.HET2_BIT0_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT0_PSL.VALUE=0x00000001 DRIVER.HET.VAR.HET1_PWM5_PIN_SELECT.VALUE=17 DRIVER.HET.VAR.HET1_BIT25_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT17_PDR.VALUE=0x00000000 @@ -6626,7 +6626,7 @@ DRIVER.HET.VAR.HET1_BIT16_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT16_PULL.VALUE=1 DRIVER.HET.VAR.HET2_BIT12_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM4_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET1_PWM4_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_PWM1_ACTION.VALUE=3 DRIVER.HET.VAR.HET2_BIT0_HRSHARE.VALUE=0x00000001 DRIVER.HET.VAR.HET1_EDGE7_POLARITY.VALUE=0 @@ -6639,7 +6639,7 @@ DRIVER.HET.VAR.HET2_EDGE3_LVL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_EDGE6_EVENT.VALUE=1 DRIVER.HET.VAR.HET1_EDGE3_BOTH.VALUE=0 -DRIVER.HET.VAR.HET1_PWM6_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET1_PWM6_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET1_BIT28_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT13_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_PWM5_POLARITY.VALUE=3 @@ -6649,17 +6649,17 @@ DRIVER.HET.VAR.HET2_CAP3_PIN_SELECT.VALUE=6 DRIVER.HET.VAR.HET2_BIT10_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT2_DOUT.VALUE=0 -DRIVER.HET.VAR.HET1_PWM3_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET1_PWM3_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_EDGE3_EVENT.VALUE=1 -DRIVER.HET.VAR.HET2_PWM6_PERIOD_PRESCALER.VALUE=109952 -DRIVER.HET.VAR.HET2_PWM3_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET2_PWM6_PERIOD_PRESCALER.VALUE=103936 +DRIVER.HET.VAR.HET2_PWM3_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET1_BIT3_PULL.VALUE=1 DRIVER.HET.VAR.HET2_PWM1_ENA.VALUE=0 DRIVER.HET.VAR.HET2_BIT1_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT26_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT18_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT6_DOUT.VALUE=0 -DRIVER.HET.VAR.HET2_PWM1_DUTYTIME.VALUE=501.527 +DRIVER.HET.VAR.HET2_PWM1_DUTYTIME.VALUE=500.923 DRIVER.HET.VAR.HET2_BIT5_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM7_POLARITY.VALUE=3 DRIVER.HET.VAR.HET2_BIT16_HRSHARE.VALUE=0x00000000 @@ -6673,7 +6673,7 @@ DRIVER.HET.VAR.HET2_BIT13_DIR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT3_PULDIS.VALUE=0x00000000 DRIVER.HET.VAR.HET1_EDGE0_POLARITY.VALUE=0 -DRIVER.HET.VAR.HET2_PWM7_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET2_PWM7_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_BIT3_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT25_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT17_PSL.VALUE=0x00000000 @@ -6704,18 +6704,18 @@ DRIVER.HET.VAR.HET1_BIT27_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT19_PDR.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT6_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM0_DUTY_PRESCALER.VALUE=55296 +DRIVER.HET.VAR.HET1_PWM0_DUTY_PRESCALER.VALUE=52224 DRIVER.HET.VAR.HET2_EDGE7_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET2_PWM0_POLARITY.VALUE=3 DRIVER.HET.VAR.HET1_BIT26_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT18_XORSHARE.VALUE=0x00000000 DRIVER.HET.VAR.HET2_BIT10_PSL.VALUE=0x00000000 DRIVER.HET.VAR.HET1_EDGE6_PIN_SELECT.VALUE=22 -DRIVER.HET.VAR.HET1_PWM0_ACTUALPERIOD.VALUE=1000.727 +DRIVER.HET.VAR.HET1_PWM0_ACTUALPERIOD.VALUE=1000.615 DRIVER.HET.VAR.HET2_HR_FREQUENCY.VALUE=110.000 DRIVER.HET.VAR.HET2_BIT17_PULL.VALUE=1 DRIVER.HET.VAR.HET2_BIT14_DIR.VALUE=0x00000000 -DRIVER.HET.VAR.HET1_PWM5_PERIOD_PRESCALER.VALUE=109952 +DRIVER.HET.VAR.HET1_PWM5_PERIOD_PRESCALER.VALUE=103936 DRIVER.HET.VAR.HET2_EDGE4_POLARITY.VALUE=0 DRIVER.HET.VAR.HET2_EDGE0_INTENA.VALUE=0x00000000 DRIVER.HET.VAR.HET1_BIT7_PULDIS.VALUE=0x00000000 @@ -7020,18 +7020,18 @@ DRIVER.I2C.VAR.I2C_DATACOUNT.VALUE=8 DRIVER.I2C.VAR.I2C_ADDRMODE.VALUE=7BIT_AMODE DRIVER.I2C.VAR.I2C_PORT_BIT0_FUN.VALUE=0 -DRIVER.I2C.VAR.I2C_PORT_BIT0_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT0_PDR.VALUE=1 DRIVER.I2C.VAR.I2C_BC_VALUE.VALUE=0x0003 DRIVER.I2C.VAR.I2C_PORT_BIT1_FUN.VALUE=0 -DRIVER.I2C.VAR.I2C_RM_ENA.VALUE=0 +DRIVER.I2C.VAR.I2C_RM_ENA.VALUE=1 DRIVER.I2C.VAR.I2C_BC.VALUE=8_BIT -DRIVER.I2C.VAR.I2C_PORT_BIT1_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C_PORT_BIT1_PDR.VALUE=1 DRIVER.I2C.VAR.I2C_TXRX_VALUE.VALUE=0 DRIVER.I2C.VAR.I2C_SCDLVL.VALUE=0 DRIVER.I2C.VAR.I2C_PORT_BIT0_PSL.VALUE=1 DRIVER.I2C.VAR.I2C_STPCND.VALUE=1 DRIVER.I2C.VAR.I2C_ALINTENA.VALUE=0 -DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=13 +DRIVER.I2C.VAR.I2C_PRESCALE.VALUE=12 DRIVER.I2C.VAR.I2C_PORT_BIT1_PSL.VALUE=1 DRIVER.I2C.VAR.I2C_TXRX.VALUE=TRANSMITTER DRIVER.I2C.VAR.I2C_PORT_BIT0_DOUT.VALUE=0 @@ -7043,9 +7043,9 @@ DRIVER.I2C.VAR.I2C_PORT_BIT1_DOUT.VALUE=0 DRIVER.I2C.VAR.I2C_TXDMA.VALUE=0 DRIVER.I2C.VAR.I2C_MSMODE.VALUE=1 -DRIVER.I2C.VAR.I2C_ICCH.VALUE=34 +DRIVER.I2C.VAR.I2C_ICCH.VALUE=35 DRIVER.I2C.VAR.I2C_AASLVL.VALUE=0 -DRIVER.I2C.VAR.I2C_ICCL.VALUE=34 +DRIVER.I2C.VAR.I2C_ICCL.VALUE=35 DRIVER.I2C.VAR.I2C_AAS.VALUE=0 DRIVER.I2C.VAR.I2C_BCM.VALUE=0 DRIVER.I2C.VAR.I2C_ADDRMODE_VALUE.VALUE=0x0001 @@ -7075,36 +7075,36 @@ DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40 DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001 -DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0 -DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=16.0 +DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=792 DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1 -DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=104.000 DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00 DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0 DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002 DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1 -DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=39204 DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0 DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792 DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00 -DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0 -DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=220.0 +DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=257400 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=208.00 DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0 DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5 DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5 DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400 DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA -DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=10 DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204 DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001 DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1 DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0 -DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=544500 +DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=514800 DRIVER.PINMUX.VAR.DMA_EIDXS_28.VALUE=0 DRIVER.PINMUX.VAR.DMA_FIDXD_20.VALUE=0 DRIVER.PINMUX.VAR.DMA_FIDXD_12.VALUE=0 @@ -7125,7 +7125,7 @@ DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0 -DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0 DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0 @@ -7215,7 +7215,7 @@ DRIVER.PINMUX.VAR.DMA_IFT_COUNT_17.VALUE=0 DRIVER.PINMUX.VAR.DMA_INTLFSEN_13.VALUE=1 DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0 -DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_26.VALUE=0 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_18.VALUE=0 @@ -7272,7 +7272,7 @@ DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1 DRIVER.PINMUX.VAR.PINMUX10.VALUE=PINMUX_PIN_86_AD1EVT DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=2 DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001 @@ -7305,7 +7305,7 @@ DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.PINMUX35.VALUE=0 -DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_PIN_32_MIBSPI5NCS_0 +DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_PIN_32_ETPWM4A DRIVER.PINMUX.VAR.PINMUX19.VALUE=PINMUX_PIN_127_HET1_30 DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0 @@ -7407,7 +7407,7 @@ DRIVER.PINMUX.VAR.DMA_FIDXS_7.VALUE=0 DRIVER.PINMUX.VAR.DMA_AIM_7.VALUE=ENABLED DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0 -DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.DMA_FIDXS_8.VALUE=0 DRIVER.PINMUX.VAR.DMA_AIM_8.VALUE=ENABLED DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0 @@ -7422,9 +7422,9 @@ DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0 @@ -7481,7 +7481,7 @@ DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=1 DRIVER.PINMUX.VAR.DMA_TTYPE_31.VALUE=FRAME_TRANSFER DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_31.VALUE=0 DRIVER.PINMUX.VAR.DMA_TTYPE_23.VALUE=FRAME_TRANSFER @@ -7497,7 +7497,7 @@ DRIVER.PINMUX.VAR.DMA_TTYPE_16.VALUE=FRAME_TRANSFER DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_16.VALUE=0 DRIVER.PINMUX.VAR.DMA_STADD_2.VALUE=0 -DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.DMA_TTYPE_25.VALUE=FRAME_TRANSFER DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_25.VALUE=0 @@ -7651,7 +7651,7 @@ DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0 -DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.DMA_ADDMW_3.VALUE=CONSTANT DRIVER.PINMUX.VAR.MUX58_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0 @@ -7668,9 +7668,9 @@ DRIVER.PINMUX.VAR.DMA_ADDMW_6.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_INTFTCEN_2.VALUE=1 DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT @@ -7694,7 +7694,7 @@ DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=2 DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001 @@ -7714,7 +7714,7 @@ DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0 -DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=1 DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1 DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1 DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0 @@ -7746,7 +7746,7 @@ DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=1 DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0 @@ -7756,7 +7756,7 @@ DRIVER.PINMUX.VAR.MUX12_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.MUX100_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_30_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=1 DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23_VALUE.VALUE=0x0001 @@ -7926,7 +7926,7 @@ DRIVER.PINMUX.VAR.DMA_IFT_COUNT_3.VALUE=0 DRIVER.PINMUX.VAR.MUX57_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.MUX49_OPTION5.VALUE=0 -DRIVER.PINMUX.VAR.MUX4_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_4.VALUE=0 DRIVER.PINMUX.VAR.DMA_BYP_10.VALUE=1 DRIVER.PINMUX.VAR.ECAP.VALUE=0 @@ -7945,7 +7945,7 @@ DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0 @@ -7967,7 +7967,7 @@ DRIVER.PINMUX.VAR.MUX18_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_97_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_89_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=1 DRIVER.PINMUX.VAR.DMA_ADDMR_31_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMR_23_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMR_15_VALUE.VALUE=0x0001 @@ -8015,12 +8015,12 @@ DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0 -DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=1 DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=4 DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0 @@ -8058,7 +8058,7 @@ DRIVER.PINMUX.VAR.DMA_PRITY_12_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_INTMP_3_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.ALT_ADC.VALUE=0 -DRIVER.PINMUX.VAR.I2C.VALUE=0 +DRIVER.PINMUX.VAR.I2C.VALUE=1 DRIVER.PINMUX.VAR.MUX104_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.MUX104_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX95_OPTION0.VALUE=0 @@ -8153,7 +8153,7 @@ DRIVER.PINMUX.VAR.DMA_INTEN_3.VALUE=1 DRIVER.PINMUX.VAR.MUX56_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.MUX48_OPTION5.VALUE=0 -DRIVER.PINMUX.VAR.MUX3_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX3_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.DMA_EIDXD_30.VALUE=0 DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_26.VALUE=0 DRIVER.PINMUX.VAR.DMA_EIDXD_22.VALUE=0 @@ -8198,7 +8198,7 @@ DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0 -DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0 @@ -8219,7 +8219,7 @@ DRIVER.PINMUX.VAR.PIN_MUX_95_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_87_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_79_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_4_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_4_SELECT.VALUE=1 DRIVER.PINMUX.VAR.DMA_ADDMR_31.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_EIDXD_27.VALUE=0 DRIVER.PINMUX.VAR.DMA_ADDMR_23.VALUE=CONSTANT @@ -8276,14 +8276,14 @@ DRIVER.PINMUX.VAR.DMA_INTMP_12_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_CHPR_6_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_TRIG_2_VALUE.VALUE=0x0001 -DRIVER.PINMUX.VAR.GIOA.VALUE=0 +DRIVER.PINMUX.VAR.GIOA.VALUE=1 DRIVER.PINMUX.VAR.DMA_ADDMR_28.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_IET_COUNT_24.VALUE=0 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_IET_COUNT_16.VALUE=0 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12.VALUE=8BIT DRIVER.PINMUX.VAR.GIOB.VALUE=0 -DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.DMA_ADDMR_29.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_IET_COUNT_25.VALUE=0 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21.VALUE=8BIT @@ -8300,7 +8300,7 @@ DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=1 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0 @@ -8350,15 +8350,15 @@ DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1 DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0 DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MIBSPI3.VALUE=0 +DRIVER.PINMUX.VAR.MIBSPI3.VALUE=1 DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.OHCI0.VALUE=0 DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.DMA_ADDMW_9_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_TRIG_7_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.MIBSPI5.VALUE=0 DRIVER.PINMUX.VAR.DMM.VALUE=0 -DRIVER.PINMUX.VAR.W2FC.VALUE=0 +DRIVER.PINMUX.VAR.W2FC.VALUE=1 DRIVER.PINMUX.VAR.OHCI1.VALUE=0 DRIVER.PINMUX.VAR.MUX103_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.MUX103_OPTION4.VALUE=0 @@ -8384,7 +8384,7 @@ DRIVER.PINMUX.VAR.MUX9_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.DMA_EIDXD_0.VALUE=0 DRIVER.PINMUX.VAR.DMA_CHPR_10.VALUE=HIGH -DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=1 DRIVER.PINMUX.VAR.PIN_MUX_101_SELECT.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12_VALUE.VALUE=0x0001 @@ -8449,7 +8449,7 @@ DRIVER.PINMUX.VAR.MUX55_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX47_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX39_OPTION4.VALUE=0 -DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.DMA_ADDMW_21.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_ADDMW_13.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_EIDXD_7.VALUE=0 @@ -8466,7 +8466,7 @@ DRIVER.PINMUX.VAR.DMA_IET_COUNT_4.VALUE=0 DRIVER.PINMUX.VAR.DMA_TRIG_10.VALUE=HARDWARE_TRIGGER DRIVER.PINMUX.VAR.MUX2_OPTION2.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=2 DRIVER.PINMUX.VAR.DMA_ADDMW_31.VALUE=CONSTANT DRIVER.PINMUX.VAR.DMA_CHANNEL_31_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMR_29_VALUE.VALUE=0x0001 @@ -8560,8 +8560,8 @@ DRIVER.PINMUX.VAR.MUX20_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=0 -DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=1 +DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=2 DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001 @@ -8609,7 +8609,7 @@ DRIVER.PINMUX.VAR.DMA_CHPR_9.VALUE=HIGH DRIVER.PINMUX.VAR.DMA_TRIG_5.VALUE=HARDWARE_TRIGGER DRIVER.PINMUX.VAR.DMA_INTHBCEN_1.VALUE=1 -DRIVER.PINMUX.VAR.SCI.VALUE=0 +DRIVER.PINMUX.VAR.SCI.VALUE=1 DRIVER.PINMUX.VAR.DMA_INTMP_16.VALUE=GROUP_A DRIVER.PINMUX.VAR.DMA_TRIG_6.VALUE=HARDWARE_TRIGGER DRIVER.PINMUX.VAR.DMA_INTHBCEN_2.VALUE=1 @@ -8641,7 +8641,7 @@ DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL -DRIVER.PINMUX.VAR.ETPWM.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM.VALUE=1 DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL @@ -8685,13 +8685,13 @@ DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0 -DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=1 DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000 DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX62_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX54_OPTION0.VALUE=0 -DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.MUX38_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX8_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX70_OPTION1.VALUE=0 @@ -8737,14 +8737,14 @@ DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0 -DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=1 DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0 DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0 -DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=1 DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0 DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0 @@ -8827,14 +8827,14 @@ DRIVER.PINMUX.VAR.RMII.VALUE=0 DRIVER.PINMUX.VAR.DMA_CHAS_16.VALUE=0 DRIVER.PINMUX.VAR.DMA_INTLFSEN_6.VALUE=1 -DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_MIBSPI3NCS_3 | PINMUX_PIN_4_MIBSPI3NCS_2" +DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_I2C_SCL | PINMUX_PIN_4_I2C_SDA" DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.DMA_INTLFSEN_7.VALUE=1 -DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_HET1_11" +DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_MIBSPI3NCS_4" DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1 -DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5" +DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_ETPWM1A" DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0 DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0 @@ -8846,24 +8846,24 @@ DRIVER.PINMUX.VAR.DMA_INTLFSEN_9.VALUE=1 DRIVER.PINMUX.VAR.DMA_INTMP_5_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.DMA_ACC_1_VALUE.VALUE=0x0001 -DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_PIN_15_HET1_22 | PINMUX_PIN_16_GIOA_6" +DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_PIN_15_W2FC_SE0O | PINMUX_PIN_16_GIOA_6" DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12 -DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03" +DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_PIN_22_ETPWM2A | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03" DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT -DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05" +DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_HET1_05" DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0 DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0 -DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09" +DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A" DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT @@ -8873,15 +8873,15 @@ DRIVER.PINMUX.VAR.DMA_CHANNEL_1.VALUE=CHANNEL0 DRIVER.PINMUX.VAR.DMA_CHPR_3_VALUE.VALUE=0x0001 DRIVER.PINMUX.VAR.ALT_ADC_A.VALUE=0 -DRIVER.PINMUX.VAR.PINMUX7.VALUE="PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_HET1_06" +DRIVER.PINMUX.VAR.PINMUX7.VALUE="PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_SCIRX" DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_24.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_EIDXS_20.VALUE=0 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_16.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_EIDXS_12.VALUE=0 DRIVER.PINMUX.VAR.DMA_CHANNEL_2.VALUE=CHANNEL0 DRIVER.PINMUX.VAR.ALT_ADC_B.VALUE=0 -DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_PIN_39_HET1_13 | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_HET1_15" +DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_PIN_39_SCITX | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_HET1_15" DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0 DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0 @@ -8892,7 +8892,7 @@ DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0 DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0 -DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_PIN_54_MIBSPI3NENA | PINMUX_PIN_55_MIBSPI3NCS_0" +DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_PIN_54_MIBSPI3NCS_5 | PINMUX_PIN_55_MIBSPI3NCS_0" DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0 DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0 @@ -8936,7 +8936,7 @@ DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0 DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0 -DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=1 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29.VALUE=8BIT DRIVER.PINMUX.VAR.DMA_EIDXS_25.VALUE=0 DRIVER.PINMUX.VAR.DMA_EIDXS_17.VALUE=0 @@ -9117,9 +9117,12 @@ DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1 DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0 DRIVER.EMIF.VAR.EMIF_AVAILABLE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_MAX.VALUE=145 DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1 DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_MAX.VALUE=145 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_MAX.VALUE=73 DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1 @@ -9134,6 +9137,7 @@ DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=63 DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_MAX.VALUE=291 DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=7 @@ -9145,6 +9149,7 @@ DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_MAX.VALUE=73 DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=15 DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0 @@ -9157,6 +9162,7 @@ DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=15 DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_MAX.VALUE=73 DRIVER.EMIF.VAR.EMIF_CLK.VALUE=0 DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=15 @@ -9179,6 +9185,7 @@ DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0 DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES_MAX.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=15 DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0 DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001 @@ -9189,12 +9196,15 @@ DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=7 DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_MAX.VALUE=73 DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0 DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_MAX.VALUE=291 DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=63 DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD_MAX.VALUE=0 DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0 DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=7 DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words @@ -9348,19 +9358,19 @@ DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0 DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=1000 -DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=1000.000 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_SOCA_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_INPUT.VALUE=PWMA_RED_FED DRIVER.ETPWM.VAR.ETPWM7_BASE.VALUE=0xFCF79200 -DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM6_DCBEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_DCBEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCA.VALUE=0x0000 @@ -9369,61 +9379,61 @@ DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0 DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL -DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY.VALUE=50 DRIVER.ETPWM.VAR.ETPWM5_DCAEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_DCAEVT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=50.000 -DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=38.709 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_PWMB_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=503.218 DRIVER.ETPWM.VAR.ETPWM3_CBC.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM1_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_OSHT4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_OSHT5.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_INPUT.VALUE=PWMA_RED_FED @@ -9435,12 +9445,12 @@ DRIVER.ETPWM.VAR.ETPWM5_PWMA_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 @@ -9459,17 +9469,17 @@ DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL DRIVER.ETPWM.VAR.ETPWM6_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_RDELAY_SOURCE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_PWMB_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=38.709 DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000 @@ -9481,37 +9491,37 @@ DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000 DRIVER.ETPWM.VAR.ETPWM4_DCAEVT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM3_TB_FREQUENCY.VALUE=110.000 DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3 DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_OSHT4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME_REG.VALUE=3 DRIVER.ETPWM.VAR.ETPWM4_PWMB_POLARITY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL -DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=500.000 -DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=0.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=1000.000 -DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=50.000 -DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=250000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=38.709 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_SOCA_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_OUT.VALUE=0 @@ -9522,12 +9532,12 @@ DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_PWMA_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_OSHT1.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_OSHT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM7_CBC.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_CBC1.VALUE=0x0000 @@ -9537,40 +9547,40 @@ DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=1000.000 -DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=77.418 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CBC6.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_INPUT.VALUE=PWMA_RED_FED DRIVER.ETPWM.VAR.ETPWM6_INTERRUPT_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM1_BASE.VALUE=0xFCF78C00 DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=77.418 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL -DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=80.000 -DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=103.335 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM6_SOCB_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=38.709 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_DCAEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_DCAEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_OST.VALUE=0x0000 @@ -9579,15 +9589,15 @@ DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_PWMA_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 -DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=500.000 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=503.218 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000 DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_PWMA_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_PWMB_POLARITY.VALUE=0 @@ -9604,7 +9614,7 @@ DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0 @@ -9615,36 +9625,36 @@ DRIVER.ETPWM.VAR.ETPWM7_TB_FREQUENCY.VALUE=110.000 DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCA.VALUE=DCAEVT1 DRIVER.ETPWM.VAR.ETPWM3_OSHT3.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=38.709 DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCB.VALUE=DCBEVT1 -DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM3_OSHT4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH.VALUE=100 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY.VALUE=50 DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_PWMB_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM3_OSHT5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_OST.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=500.000 -DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=0.000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=1000 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=25833 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000 DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1 DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1 -DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000 @@ -9655,7 +9665,7 @@ DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000 @@ -9664,53 +9674,53 @@ DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY_NEW.VALUE=50.0 DRIVER.ETPWM.VAR.ETPWM4_PWMA_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_BASE.VALUE=0xFCF78E00 -DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=38.709 DRIVER.ETPWM.VAR.ETPWM2_RDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY.VALUE=9.091 -DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=1000.000 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=996.758 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT -DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_SOCA_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_OST.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_INVERT.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_INVERT.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000 DRIVER.ETPWM.VAR.ETPWM3_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000 @@ -9719,19 +9729,19 @@ DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0 DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=50.000 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=38.709 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=100 -DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=77.418 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000 DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED -DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00 DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 @@ -9743,33 +9753,33 @@ DRIVER.ETPWM.VAR.ETPWM1_DCAEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_OSHT4.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=102 DRIVER.ETPWM.VAR.ETPWM4_OSHT5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_OSHT6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=1000.000 -DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=250002.419 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL DRIVER.ETPWM.VAR.ETPWM2_INTERRUPT_PERIOD.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM2_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY.VALUE=9.091 -DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=50 -DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=52 DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME_REG.VALUE=3 DRIVER.ETPWM.VAR.ETPWM1_DCBEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD.VALUE=100.000 DRIVER.ETPWM.VAR.ETPWM1_DCBEVT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=103.335 DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCA.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCB.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV.VALUE=0 @@ -9786,10 +9796,10 @@ DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=250002.419 DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1 DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000 @@ -9799,86 +9809,86 @@ DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50 DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM7_DCAEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTY.VALUE=50 DRIVER.ETPWM.VAR.ETPWM7_DCAEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV.VALUE=0 DRIVER.ETPWM.VAR.ETPWM5_CLKDIV_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL DRIVER.ETPWM.VAR.ETPWM1_INTERRUPT_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCA.VALUE=DCAEVT1 DRIVER.ETPWM.VAR.ETPWM5_SELECT_EVENT.VALUE=NO_EVENT DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCB.VALUE=DCBEVT1 DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH.VALUE=100 -DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM6_PWMA_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY_NEW.VALUE=50.0 -DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=77.418 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM7_DCBEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_MODE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_DCBEVT2.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=100.000 -DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=77.418 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_CBC1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM5_TB_FREQUENCY.VALUE=110.000 DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCA.VALUE=DCAEVT1 DRIVER.ETPWM.VAR.ETPWM7_CBC2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCB.VALUE=DCBEVT1 DRIVER.ETPWM.VAR.ETPWM7_CBC3.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=102 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY.VALUE=50 DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM7_CBC4.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM7_CBC5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM7_CBC6.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_POLARITY.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=52 DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=25833 DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091 DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100 -DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=0.000 DRIVER.ETPWM.VAR.ETPWM6_PWMB_ENA.VALUE=1 DRIVER.ETPWM.VAR.ETPWM5_OSHT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 -DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM5_OSHT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_INPUT.VALUE=PWMA_RED_FED -DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=996.758 DRIVER.ETPWM.VAR.ETPWM5_OSHT3.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_OSHT4.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM2_SELECT_EVENT.VALUE=NO_EVENT DRIVER.ETPWM.VAR.ETPWM5_OSHT5.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTY.VALUE=50 DRIVER.ETPWM.VAR.ETPWM5_OSHT6.VALUE=0x0000 -DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=77.418 DRIVER.ETPWM.VAR.ETPWM6_CLKDIV.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=1 DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0 -DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=250000 DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000 DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0 DRIVER.ETPWM.VAR.ETPWM6_SOCA_PERIOD.VALUE=1 DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000 DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0 DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0 -DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=0.000 DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0 DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0 DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000 @@ -10322,7 +10332,7 @@ DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_ENABLE.VALUE=STD_ON DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_BANK.VALUE=7 DRIVER.FEE.VAR.FEE_DATASELECT_BITS.VALUE=0 -DRIVER.FEE.VAR.FEE_OPERATING_FREQ.VALUE=220.000 +DRIVER.FEE.VAR.FEE_OPERATING_FREQ.VALUE=208.000 DRIVER.FEE.VAR.FEE_TOTAL_SECTORS.VALUE=4 DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_NUMBER.VALUE=16 DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_WRITE_CYCLES.VALUE=0x8 @@ -10373,5 +10383,6 @@ DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_0.VALUE=0xED DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_1.VALUE=0xC0 DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_PATTERN_TO_SCAN.VALUE=NONE DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_0.VALUE=0xEFFDFFFF DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_1.VALUE=0xFFFFFFFF Index: firmware/BL.hcg =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/BL.hcg (.../BL.hcg) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/BL.hcg (.../BL.hcg) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -236,9 +236,7 @@ lin.h - - lin.c - + reg_mibspi.h @@ -254,9 +252,7 @@ spi.h - - spi.c - + reg_can.h @@ -290,15 +286,15 @@ het.h + + het.c + reg_htu.h htu.h - - het.c - @@ -341,36 +337,26 @@ mdio.h - - emac.c - - - mdio.c - - - phy_dp83640.c - phy_dp83640.h + + + reg_dcc.h dcc.h - - dcc.c - + reg_pom.h pom.h - - pom.c - + usbcdc.h @@ -413,9 +399,7 @@ crc.h - - crc.c - + reg_etpwm.h @@ -431,18 +415,14 @@ ecap.h - - ecap.c - + reg_eqep.h eqep.h - - eqep.c - + Device_RM46.h @@ -546,7 +526,7 @@ include\lin.h - source\lin.c + @@ -572,7 +552,7 @@ include\spi.h - source\spi.c + @@ -613,15 +593,15 @@ include\het.h + + source\het.c + include\reg_htu.h include\htu.h - - source\het.c - @@ -670,18 +650,18 @@ include\mdio.h + + include\phy_dp83640.h + - source\emac.c + - source\mdio.c + - source\phy_dp83640.c + - - include\phy_dp83640.h - @@ -693,7 +673,7 @@ include\dcc.h - source\dcc.c + @@ -706,7 +686,7 @@ include\pom.h - source\pom.c + @@ -777,7 +757,7 @@ include\crc.h - source\crc.c + @@ -803,7 +783,7 @@ include\ecap.h - source\ecap.c + @@ -816,7 +796,7 @@ include\eqep.h - source\eqep.c + Index: firmware/include/adc.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/adc.h (.../adc.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/adc.h (.../adc.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -230,53 +230,30 @@ }adc_config_reg_t; #define ADC1_OPMODECR_CONFIGVALUE 0x81140001U -#define ADC1_CLOCKCR_CONFIGVALUE (10U) +#define ADC1_CLOCKCR_CONFIGVALUE (25U) #define ADC1_G0MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U) -#define ADC1_G1MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U) +#define ADC1_G1MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000020U | (uint32)0x00000000U | (uint32)0x00000000U) #define ADC1_G2MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U) #define ADC1_G0SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT) #define ADC1_G1SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT) #define ADC1_G2SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC1_EVENT) -#define ADC1_BNDCR_CONFIGVALUE ((uint32)((uint32)8U << 16U)|(8U + 8U)) +#define ADC1_BNDCR_CONFIGVALUE ((uint32)((uint32)0U << 16U)|(0U + 10U)) #define ADC1_BNDEND_CONFIGVALUE (2U) -#define ADC1_G0SAMP_CONFIGVALUE (1U) -#define ADC1_G1SAMP_CONFIGVALUE (1U) -#define ADC1_G2SAMP_CONFIGVALUE (1U) +#define ADC1_G0SAMP_CONFIGVALUE (0U) +#define ADC1_G1SAMP_CONFIGVALUE (0U) +#define ADC1_G2SAMP_CONFIGVALUE (0U) #define ADC1_G0SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) #define ADC1_G1SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) #define ADC1_G2SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) #define ADC1_PARCR_CONFIGVALUE (0x00000005U) -#define ADC2_OPMODECR_CONFIGVALUE 0x81140001U -#define ADC2_CLOCKCR_CONFIGVALUE (10U) -#define ADC2_G0MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U) -#define ADC2_G1MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U) -#define ADC2_G2MODECR_CONFIGVALUE ((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U) - -#define ADC2_G0SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC2_EVENT) -#define ADC2_G1SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC2_EVENT) -#define ADC2_G2SRC_CONFIGVALUE ((uint32)0x00000000U | (uint32)ADC2_EVENT) - -#define ADC2_BNDCR_CONFIGVALUE ((uint32)((uint32)8U << 16U)|(8U + 8U)) -#define ADC2_BNDEND_CONFIGVALUE (2U) - -#define ADC2_G0SAMP_CONFIGVALUE (1U) -#define ADC2_G1SAMP_CONFIGVALUE (1U) -#define ADC2_G2SAMP_CONFIGVALUE (1U) - -#define ADC2_G0SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) -#define ADC2_G1SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) -#define ADC2_G2SAMPDISEN_CONFIGVALUE ((uint32)((uint32)0U << 8U) | 0x00000000U) - -#define ADC2_PARCR_CONFIGVALUE (0x00000005U) - /** * @defgroup ADC ADC * @brief Analog To Digital Converter Module. Index: firmware/include/can.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/can.h (.../can.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/can.h (.../can.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -635,9 +635,9 @@ | (uint32)((uint32)0x00000005U << 10U) | 0x00020002U) #define CAN1_ES_CONFIGVALUE 0x00000007U #define CAN1_BTR_CONFIGVALUE ((uint32)((uint32)0U << 16U) \ - | (uint32)((uint32)(3U - 1U) << 12U) \ - | (uint32)((uint32)((4U + 3U) - 1U) << 8U) \ - | (uint32)((uint32)(3U - 1U) << 6U) | (uint32)19U) + | (uint32)((uint32)(6U - 1U) << 12U) \ + | (uint32)((uint32)((3U + 6U) - 1U) << 8U) \ + | (uint32)((uint32)(4U - 1U) << 6U) | (uint32)25U) #define CAN1_TEST_CONFIGVALUE 0x00000080U #define CAN1_ABOTR_CONFIGVALUE ((uint32)(0U)) #define CAN1_INTMUX0_CONFIGVALUE ((uint32)0x00000000U \ @@ -722,190 +722,6 @@ |(uint32)((uint32)0U << 1U )) -/* Configuration registers initial value for CAN2*/ -#define CAN2_CTL_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)((uint32)0x00000005U << 10U) | 0x00020002U) -#define CAN2_ES_CONFIGVALUE 0x00000007U -#define CAN2_BTR_CONFIGVALUE ((uint32)((uint32)0U << 16U) \ - | (uint32)((uint32)(3U - 1U) << 12U) \ - | (uint32)((uint32)((4U + 3U) - 1U) << 8U) \ - | (uint32)((uint32)(3U - 1U) << 6U) | (uint32)19U) -#define CAN2_TEST_CONFIGVALUE 0x00000080U -#define CAN2_ABOTR_CONFIGVALUE ((uint32)(0U)) -#define CAN2_INTMUX0_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define CAN2_INTMUX1_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define CAN2_INTMUX2_CONFIGVALUE 0x00000000U -#define CAN2_INTMUX3_CONFIGVALUE 0x00000000U -#define CAN2_TIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \ - |(uint32)((uint32)0U << 17U ) \ - |(uint32)((uint32)0U << 16U )\ - |(uint32)((uint32)1U << 3U ) \ - |(uint32)((uint32)1U << 2U ) \ - |(uint32)((uint32)1U << 1U )) -#define CAN2_RIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \ - |(uint32)((uint32)0U << 17U ) \ - |(uint32)((uint32)0U << 16U )\ - |(uint32)((uint32)1U << 3U ) \ - |(uint32)((uint32)0U << 2U ) \ - |(uint32)((uint32)0U << 1U )) - -/* Configuration registers initial value for CAN3*/ -#define CAN3_CTL_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)((uint32)0x00000005U << 10U) | 0x00020002U) -#define CAN3_ES_CONFIGVALUE 0x00000007U -#define CAN3_BTR_CONFIGVALUE ((uint32)((uint32)0U << 16U) \ - | (uint32)((uint32)(3U - 1U) << 12U) \ - | (uint32)((uint32)((4U + 3U) - 1U) << 8U) \ - | (uint32)((uint32)(3U - 1U) << 6U) | (uint32)19U) -#define CAN3_TEST_CONFIGVALUE 0x00000080U -#define CAN3_ABOTR_CONFIGVALUE ((uint32)(0U)) -#define CAN3_INTMUX0_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define CAN3_INTMUX1_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define CAN3_INTMUX2_CONFIGVALUE 0x00000000U -#define CAN3_INTMUX3_CONFIGVALUE 0x00000000U -#define CAN3_TIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \ - |(uint32)((uint32)0U << 17U ) \ - |(uint32)((uint32)0U << 16U )\ - |(uint32)((uint32)1U << 3U ) \ - |(uint32)((uint32)1U << 2U ) \ - |(uint32)((uint32)1U << 1U )) -#define CAN3_RIOC_CONFIGVALUE ((uint32)((uint32)1U << 18U ) \ - |(uint32)((uint32)0U << 17U ) \ - |(uint32)((uint32)0U << 16U )\ - |(uint32)((uint32)1U << 3U ) \ - |(uint32)((uint32)0U << 2U ) \ - |(uint32)((uint32)0U << 1U )) - /** * @defgroup CAN CAN * @brief Controller Area Network Module. @@ -947,8 +763,6 @@ uint32 canGetID(canBASE_t *node, uint32 messageBox); void canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal); void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type); -void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type); -void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type); /** @fn void canErrorNotification(canBASE_t *node, uint32 notification) * @brief Error notification Index: firmware/include/dcc.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/dcc.h (.../dcc.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/dcc.h (.../dcc.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -252,31 +252,6 @@ uint32 CONFIG_CNT0CLKSRC; } dcc_config_reg_t; - -/* Configuration registers initial value */ -#define DCC1_GCTRL_CONFIGVALUE ( (uint32)0xAU \ - | (uint32)((uint32)0xAU << 4U) \ - | (uint32)((uint32)0x5U << 8U) \ - | (uint32)((uint32)0xAU << 12U)) - -#define DCC1_CNT0SEED_CONFIGVALUE 39204U -#define DCC1_VALID0SEED_CONFIGVALUE 792U -#define DCC1_CNT1SEED_CONFIGVALUE 544500U -#define DCC1_CNT1CLKSRC_CONFIGVALUE ((uint32)((uint32)10U << 12U) | (uint32)DCC1_CNT1_PLL1) -/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ -#define DCC1_CNT0CLKSRC_CONFIGVALUE ((uint32)DCC1_CNT0_OSCIN) - -#define DCC2_GCTRL_CONFIGVALUE ( (uint32)0xAU \ - | (uint32)((uint32)0xAU << 4U) \ - | (uint32)((uint32)0x5U << 8U) \ - | (uint32)((uint32)0xAU << 12U)) -#define DCC2_CNT0SEED_CONFIGVALUE 0U -#define DCC2_VALID0SEED_CONFIGVALUE 0U -#define DCC2_CNT1SEED_CONFIGVALUE 0U -#define DCC2_CNT1CLKSRC_CONFIGVALUE ((uint32)((uint32)0xAU << 12U) | (uint32)DCC2_CNT1_VCLK) -/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ -#define DCC2_CNT0CLKSRC_CONFIGVALUE ((uint32)DCC2_CNT0_OSCIN) - /* USER CODE BEGIN (1) */ /* USER CODE END */ Index: firmware/include/etpwm.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/etpwm.h (.../etpwm.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/etpwm.h (.../etpwm.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -468,13 +468,13 @@ #define ETPWM1_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM1_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM1_TBPRD_CONFIGVALUE 1000U +#define ETPWM1_TBPRD_CONFIGVALUE 25833U #define ETPWM1_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM1_CMPA_CONFIGVALUE 50U -#define ETPWM1_CMPB_CONFIGVALUE 50U +#define ETPWM1_CMPA_CONFIGVALUE 0U +#define ETPWM1_CMPB_CONFIGVALUE 0U #define ETPWM1_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM1_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM1_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM1_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM1_DBRED_CONFIGVALUE 1U #define ETPWM1_DBFED_CONFIGVALUE 1U #define ETPWM1_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -483,7 +483,7 @@ #define ETPWM1_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM1_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM1_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM1_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM1_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM1_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM1_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM1_DCBCTL_CONFIGVALUE 0x00000000U @@ -494,13 +494,13 @@ #define ETPWM2_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM2_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM2_TBPRD_CONFIGVALUE 1000U +#define ETPWM2_TBPRD_CONFIGVALUE 25833U #define ETPWM2_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM2_CMPA_CONFIGVALUE 50U -#define ETPWM2_CMPB_CONFIGVALUE 50U +#define ETPWM2_CMPA_CONFIGVALUE 0U +#define ETPWM2_CMPB_CONFIGVALUE 0U #define ETPWM2_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM2_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM2_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM2_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM2_DBRED_CONFIGVALUE 1U #define ETPWM2_DBFED_CONFIGVALUE 1U #define ETPWM2_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -509,7 +509,7 @@ #define ETPWM2_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM2_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM2_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM2_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM2_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM2_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM2_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM2_DCBCTL_CONFIGVALUE 0x00000000U @@ -520,13 +520,13 @@ #define ETPWM3_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM3_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM3_TBPRD_CONFIGVALUE 1000U +#define ETPWM3_TBPRD_CONFIGVALUE 25833U #define ETPWM3_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM3_CMPA_CONFIGVALUE 50U -#define ETPWM3_CMPB_CONFIGVALUE 50U +#define ETPWM3_CMPA_CONFIGVALUE 0U +#define ETPWM3_CMPB_CONFIGVALUE 0U #define ETPWM3_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM3_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM3_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM3_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM3_DBRED_CONFIGVALUE 1U #define ETPWM3_DBFED_CONFIGVALUE 1U #define ETPWM3_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -535,7 +535,7 @@ #define ETPWM3_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM3_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM3_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM3_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM3_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM3_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM3_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM3_DCBCTL_CONFIGVALUE 0x00000000U @@ -546,13 +546,13 @@ #define ETPWM4_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM4_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM4_TBPRD_CONFIGVALUE 1000U +#define ETPWM4_TBPRD_CONFIGVALUE 25833U #define ETPWM4_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM4_CMPA_CONFIGVALUE 50U -#define ETPWM4_CMPB_CONFIGVALUE 50U +#define ETPWM4_CMPA_CONFIGVALUE 0U +#define ETPWM4_CMPB_CONFIGVALUE 0U #define ETPWM4_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM4_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM4_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM4_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM4_DBRED_CONFIGVALUE 1U #define ETPWM4_DBFED_CONFIGVALUE 1U #define ETPWM4_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -561,7 +561,7 @@ #define ETPWM4_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM4_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM4_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM4_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM4_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM4_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM4_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM4_DCBCTL_CONFIGVALUE 0x00000000U @@ -572,10 +572,10 @@ #define ETPWM5_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM5_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM5_TBPRD_CONFIGVALUE 1000U +#define ETPWM5_TBPRD_CONFIGVALUE 102U #define ETPWM5_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM5_CMPA_CONFIGVALUE 50U -#define ETPWM5_CMPB_CONFIGVALUE 50U +#define ETPWM5_CMPA_CONFIGVALUE 52U +#define ETPWM5_CMPB_CONFIGVALUE 52U #define ETPWM5_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM5_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) #define ETPWM5_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) @@ -587,7 +587,7 @@ #define ETPWM5_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM5_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM5_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM5_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM5_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM5_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM5_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM5_DCBCTL_CONFIGVALUE 0x00000000U @@ -598,13 +598,13 @@ #define ETPWM6_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM6_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM6_TBPRD_CONFIGVALUE 1000U +#define ETPWM6_TBPRD_CONFIGVALUE 25833U #define ETPWM6_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM6_CMPA_CONFIGVALUE 50U -#define ETPWM6_CMPB_CONFIGVALUE 50U +#define ETPWM6_CMPA_CONFIGVALUE 0U +#define ETPWM6_CMPB_CONFIGVALUE 0U #define ETPWM6_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM6_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM6_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM6_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM6_DBRED_CONFIGVALUE 1U #define ETPWM6_DBFED_CONFIGVALUE 1U #define ETPWM6_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -613,7 +613,7 @@ #define ETPWM6_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM6_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM6_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM6_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM6_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM6_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM6_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM6_DCBCTL_CONFIGVALUE 0x00000000U @@ -624,13 +624,13 @@ #define ETPWM7_TBCTL_CONFIGVALUE ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U)) #define ETPWM7_TBPHS_CONFIGVALUE 0x00000000U -#define ETPWM7_TBPRD_CONFIGVALUE 1000U +#define ETPWM7_TBPRD_CONFIGVALUE 25833U #define ETPWM7_CMPCTL_CONFIGVALUE 0x00000000U -#define ETPWM7_CMPA_CONFIGVALUE 50U -#define ETPWM7_CMPB_CONFIGVALUE 50U +#define ETPWM7_CMPA_CONFIGVALUE 0U +#define ETPWM7_CMPB_CONFIGVALUE 0U #define ETPWM7_AQCTLA_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U)) #define ETPWM7_AQCTLB_CONFIGVALUE ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U)) -#define ETPWM7_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) +#define ETPWM7_DBCTL_CONFIGVALUE ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) #define ETPWM7_DBRED_CONFIGVALUE 1U #define ETPWM7_DBFED_CONFIGVALUE 1U #define ETPWM7_TZSEL_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U) @@ -639,7 +639,7 @@ #define ETPWM7_TZEINT_CONFIGVALUE (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U) #define ETPWM7_ETSEL_CONFIGVALUE ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U)) #define ETPWM7_ETPS_CONFIGVALUE ((uint16)1U | (uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)) -#define ETPWM7_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) +#define ETPWM7_PCCTL_CONFIGVALUE ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U)) #define ETPWM7_DCTRIPSEL_CONFIGVALUE 0x00000000U #define ETPWM7_DCACTL_CONFIGVALUE 0x00000000U #define ETPWM7_DCBCTL_CONFIGVALUE 0x00000000U Index: firmware/include/gio.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/gio.h (.../gio.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/gio.h (.../gio.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -123,12 +123,12 @@ | (uint32)((uint32)0U << 14U)\ | (uint32)((uint32)0U << 15U)) -#define GIO_PORTADIR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) +#define GIO_PORTADIR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U)) #define GIO_PORTAPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) -#define GIO_PORTAPSL_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) -#define GIO_PORTAPULDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) +#define GIO_PORTAPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U)) +#define GIO_PORTAPULDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U)) -#define GIO_PORTBDIR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) +#define GIO_PORTBDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) #define GIO_PORTBPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) #define GIO_PORTBPSL_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) #define GIO_PORTBPULDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U)) Index: firmware/include/het.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/het.h (.../het.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/het.h (.../het.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -341,10 +341,11 @@ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ + | (uint32)0x00400000U \ | (uint32)0x00000000U \ - | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ + | (uint32)0x00040000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ @@ -358,11 +359,10 @@ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ + | (uint32)0x00000010U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ | (uint32)0x00000000U) #define HET1_PDR_CONFIGVALUE ((uint32)0x00000000U \ @@ -440,8 +440,8 @@ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ + | (uint32)0x00400000U \ | (uint32)0x00000000U \ - | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ @@ -534,13 +534,13 @@ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ + | (uint32)0x00020000U \ + | (uint32)0x00040000U \ + | (uint32)0x00080000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ | (uint32)0x00000000U) #define HET1_INTENAC_CONFIGVALUE ((uint32)0x00000000U \ @@ -559,13 +559,13 @@ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ + | (uint32)0x00020000U \ + | (uint32)0x00040000U \ + | (uint32)0x00080000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ | (uint32)0x00000000U) #define HET1_INTENAS_CONFIGVALUE ((uint32)0x00000000U \ @@ -584,213 +584,21 @@ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ + | (uint32)0x00020000U \ + | (uint32)0x00040000U \ + | (uint32)0x00080000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ | (uint32)0x00000000U) #define HET1_PCR_CONFIGVALUE ((uint32)0x00000005U) #define HET1_GCR_CONFIGVALUE 0x00030001U -/* Configuration registers initial value for HET2*/ -#define HET2_DIR_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) -#define HET2_PDR_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_PULDIS_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_PSL_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_HRSH_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000008U \ - | (uint32)0x00000004U \ - | (uint32)0x00000002U \ - | (uint32)0x00000001U) -#define HET2_AND_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_XOR_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_PFR_CONFIGVALUE (((uint32)7U << 8U) | (uint32)0U) - - -#define HET2_PRY_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_INTENAC_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_INTENAS_CONFIGVALUE ((uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U \ - | (uint32)0x00000000U) - -#define HET2_PCR_CONFIGVALUE ((uint32)0x00000005U) -#define HET2_GCR_CONFIGVALUE 0x00030001U - - - /** * @defgroup HET HET * @brief HighEnd Timer Module. @@ -836,7 +644,6 @@ void hetResetTimestamp(hetRAMBASE_t * hetRAM); uint32 hetGetTimestamp(hetRAMBASE_t * hetRAM); void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type); -void het2GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type); /** @fn void hetNotification(hetBASE_t *het, uint32 offset) * @brief het interrupt callback Index: firmware/include/i2c.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/i2c.h (.../i2c.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/i2c.h (.../i2c.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -173,28 +173,28 @@ | ((uint32)0U << 1U) \ | ((uint32)0U)) -#define I2C_CLKL_CONFIGVALUE 34U -#define I2C_CLKH_CONFIGVALUE 34U +#define I2C_CLKL_CONFIGVALUE 35U +#define I2C_CLKH_CONFIGVALUE 35U #define I2C_CNT_CONFIGVALUE 8U #define I2C_SAR_CONFIGVALUE 0x000003FFU #define I2C_MDR_CONFIGVALUE ((uint32)0x00000000U \ | (uint32)((uint32)1U <<11U) \ | (uint32)((uint32)1U <<10U) \ | (uint32)((uint32)I2C_TRANSMITTER) \ | (uint32)((uint32)I2C_7BIT_AMODE) \ - | (uint32)((uint32)0U << 7U) \ + | (uint32)((uint32)1U << 7U) \ | (uint32)((uint32)0U) \ | (uint32)((uint32)I2C_8_BIT) \ | (uint32)I2C_RESET_OUT) #define I2C_EMDR_CONFIGVALUE 0U -#define I2C_PSC_CONFIGVALUE 13U +#define I2C_PSC_CONFIGVALUE 12U #define I2C_DMAC_CONFIGVALUE 0x00000000U #define I2C_FUN_CONFIGVALUE 0U #define I2C_DIR_CONFIGVALUE ((uint32)((uint32)0U << 1U) \ | (uint32)((uint32)0U)) -#define I2C_ODR_CONFIGVALUE ((uint32)((uint32)0U << 1U) \ - | (uint32)((uint32)0U)) +#define I2C_ODR_CONFIGVALUE ((uint32)((uint32)1U << 1U) \ + | (uint32)((uint32)1U)) #define I2C_PD_CONFIGVALUE ((uint32)((uint32)0U << 1U) \ | (uint32)((uint32)0U)) #define I2C_PSL_CONFIGVALUE ((uint32)((uint32)1U << 1U) \ Index: firmware/include/lin.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/lin.h (.../lin.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/lin.h (.../lin.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -224,9 +224,9 @@ /* Configuration registers initial value for LIN*/ #define LIN_GCR0_CONFIGVALUE 0x00000001U #define LIN_GCR1_CONFIGVALUE (0x03000CC0U \ - | (uint32)((uint32)1U << 12U) \ + | (uint32)((uint32)0U << 12U) \ | (uint32)((uint32)0U << 2U)\ - | (uint32)((uint32)1U << 5U)) + | (uint32)((uint32)0U << 5U)) #define LIN_GCR2_CONFIGVALUE 0x00000000U #define LIN_SETINTLVL_CONFIGVALUE (0x00000000U \ | 0x00000000U \ @@ -263,15 +263,15 @@ | 0x00000000U) #define LIN_FORMAT_CONFIGVALUE ((uint32)((uint32)(8U - 1U) << 16U)) -#define LIN_BRSR_CONFIGVALUE (343U) +#define LIN_BRSR_CONFIGVALUE (324U) #define LIN_COMP_CONFIGVALUE ((uint32)((uint32)(1U - 1U) << 8U) | (13U - 13U)) -#define LIN_MASK_CONFIGVALUE ((uint32)((uint32)0xFFU << 16U) | 0xFFU) -#define LIN_MBRSR_CONFIGVALUE (4954U) +#define LIN_MASK_CONFIGVALUE ((uint32)((uint32)0x00U << 16U) | 0x00U) +#define LIN_MBRSR_CONFIGVALUE (4680U) #define LIN_FUN_CONFIGVALUE (4U | 2U | 0U) #define LIN_DIR_CONFIGVALUE (0U | 0U | 0U) #define LIN_ODR_CONFIGVALUE (0U | 0U | 0U) #define LIN_PD_CONFIGVALUE (0U | 0U | 0U) -#define LIN_PSL_CONFIGVALUE (4U | 2U | 1U) +#define LIN_PSL_CONFIGVALUE (0U | 0U | 1U) /** * @defgroup LIN LIN Index: firmware/include/mibspi.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/mibspi.h (.../mibspi.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/mibspi.h (.../mibspi.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -192,18 +192,18 @@ #define MIBSPI1_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) #define MIBSPI1_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) -#define MIBSPI1_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U)) -#define MIBSPI1_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U)) +#define MIBSPI1_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U)) +#define MIBSPI1_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U)) #define MIBSPI1_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U)) #define MIBSPI1_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U)) #define MIBSPI1_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U)) #define MIBSPI1_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U)) -#define MIBSPI1_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI1_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI1_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI1_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI1_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI1_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI1_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI1_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) #define MIBSPI1_MIBSPIE_CONFIGVALUE 1U #define MIBSPI1_LTGPEND_CONFIGVALUE ((uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U)) @@ -221,52 +221,52 @@ #define MIBSPI3_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U) -#define MIBSPI3_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) +#define MIBSPI3_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 0U)) #define MIBSPI3_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) -#define MIBSPI3_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U)) +#define MIBSPI3_PCFUN_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U)) #define MIBSPI3_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) #define MIBSPI3_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) #define MIBSPI3_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) #define MIBSPI3_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U)) #define MIBSPI3_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U)) -#define MIBSPI3_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI3_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI3_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI3_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI3_FMT0_CONFIGVALUE ((uint32)((uint32)20U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)8U << 0U)) +#define MIBSPI3_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI3_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI3_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) #define MIBSPI3_MIBSPIE_CONFIGVALUE 1U -#define MIBSPI3_LTGPEND_CONFIGVALUE ((uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U)) +#define MIBSPI3_LTGPEND_CONFIGVALUE ((uint32)((uint32)((11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U)) #define MIBSPI3_TGCTRL0_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U))) -#define MIBSPI3_TGCTRL1_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)8U << 8U))) -#define MIBSPI3_TGCTRL2_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U) << 8U))) -#define MIBSPI3_TGCTRL3_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U) << 8U))) -#define MIBSPI3_TGCTRL4_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U) << 8U))) -#define MIBSPI3_TGCTRL5_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U))) -#define MIBSPI3_TGCTRL6_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U))) -#define MIBSPI3_TGCTRL7_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL1_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)11U << 8U))) +#define MIBSPI3_TGCTRL2_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U) << 8U))) +#define MIBSPI3_TGCTRL3_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL4_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL5_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL6_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U))) +#define MIBSPI3_TGCTRL7_CONFIGVALUE (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U))) #define MIBSPI3_UERRCTRL_CONFIGVALUE (0x00000005U) #define MIBSPI5_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U) #define MIBSPI5_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) #define MIBSPI5_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) -#define MIBSPI5_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U)) -#define MIBSPI5_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U)) +#define MIBSPI5_PCFUN_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U)) +#define MIBSPI5_PCDIR_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U)) #define MIBSPI5_PCPDR_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U)) #define MIBSPI5_PCDIS_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U)) -#define MIBSPI5_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U)) +#define MIBSPI5_PCPSL_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U)) #define MIBSPI5_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U)) -#define MIBSPI5_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI5_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI5_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define MIBSPI5_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI5_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI5_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI5_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) +#define MIBSPI5_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)103U << 8U) | (uint32)((uint32)16U << 0U)) #define MIBSPI5_MIBSPIE_CONFIGVALUE 1U #define MIBSPI5_LTGPEND_CONFIGVALUE ((uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U)) Index: firmware/include/pom.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/pom.h (.../pom.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/pom.h (.../pom.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -209,106 +209,6 @@ } pom_config_reg_t; -/* Configuration registers initial value for POM*/ -#define POM_POMGLBCTRL_CONFIGVALUE ((uint32)INTERNAL_RAM | 0x00000005U) -#define POM_POMPROGSTART0_CONFIGVALUE (0x00000000U & 0x003FFFFFU) -#define POM_POMOVLSTART0_CONFIGVALUE (0x00000000U & 0x003FFFFFU) -/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ -#define POM_POMREGSIZE0_CONFIGVALUE ((uint32)SIZE_64BYTES) -#define POM_POMPROGSTART1_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART1_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE1_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART2_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART2_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE2_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART3_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART3_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE3_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART4_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART4_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE4_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART5_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART5_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE5_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART6_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART6_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE6_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART7_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART7_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE7_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART8_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART8_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE8_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART9_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART9_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE9_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART10_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART10_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE10_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART11_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART11_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE11_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART12_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART12_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE12_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART13_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART13_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE13_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART14_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART14_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE14_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART15_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART15_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE15_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART16_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART16_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE16_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART17_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART17_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE17_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART18_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART18_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE18_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART19_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART19_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE19_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART20_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART20_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE20_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART21_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART21_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE21_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART22_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART22_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE22_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART23_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART23_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE23_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART24_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART24_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE24_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART25_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART25_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE25_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART26_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART26_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE26_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART27_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART27_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE27_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART28_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART28_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE28_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART29_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART29_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE29_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART30_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART30_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE30_CONFIGVALUE 0x00000000U -#define POM_POMPROGSTART31_CONFIGVALUE 0x00000000U -#define POM_POMOVLSTART31_CONFIGVALUE 0x00000000U -#define POM_POMREGSIZE31_CONFIGVALUE 0x00000000U - /** * @defgroup POM POM * @brief Parameter Overlay Module. Index: firmware/include/rti.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/rti.h (.../rti.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/rti.h (.../rti.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -254,11 +254,11 @@ #define RTI_GCTRL_CONFIGVALUE ((uint32)((uint32)0x0U << 16U) | 0x00000000U) #define RTI_TBCTRL_CONFIGVALUE 0x00000000U #define RTI_CAPCTRL_CONFIGVALUE (0U | 0U) -#define RTI_COMPCTRL_CONFIGVALUE (0x00001000U | 0x00000100U | 0x00000000U | 0x00000000U) -#define RTI_UDCP0_CONFIGVALUE 10000U -#define RTI_UDCP1_CONFIGVALUE 50000U -#define RTI_UDCP2_CONFIGVALUE 80000U -#define RTI_UDCP3_CONFIGVALUE 100000U +#define RTI_COMPCTRL_CONFIGVALUE (0x00000000U | 0x00000100U | 0x00000000U | 0x00000000U) +#define RTI_UDCP0_CONFIGVALUE 10400U +#define RTI_UDCP1_CONFIGVALUE 104000U +#define RTI_UDCP2_CONFIGVALUE 83200U +#define RTI_UDCP3_CONFIGVALUE 520000U /** Index: firmware/include/sci.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/sci.h (.../sci.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/sci.h (.../sci.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -115,7 +115,7 @@ /* Configuration registers initial value for SCI*/ #define SCI_GCR0_CONFIGVALUE 0x00000001U #define SCI_GCR1_CONFIGVALUE ((uint32)((uint32)1U << 5U) \ - |(uint32)((uint32)(2U-1U) << 4U) \ + |(uint32)((uint32)(1U-1U) << 4U) \ |(uint32)((uint32)0U << 3U) \ |(uint32)((uint32)0U << 2U) \ |(uint32)((uint32)1U << 1U) \ @@ -130,24 +130,58 @@ |(uint32)((uint32)0U << 1U) \ |(uint32)((uint32)0U << 0U)) -#define SCI_SETINT_CONFIGVALUE ((uint32)((uint32)0U << 26U) \ - |(uint32)((uint32)0U << 25U) \ +#define SCI_SETINT_CONFIGVALUE ((uint32)((uint32)1U << 26U) \ + |(uint32)((uint32)1U << 25U) \ |(uint32)((uint32)0U << 24U) \ |(uint32)((uint32)0U << 9U) \ |(uint32)((uint32)0U << 1U) \ |(uint32)((uint32)0U << 0U)) #define SCI_FORMAT_CONFIGVALUE (8U - 1U) -#define SCI_BRS_CONFIGVALUE (715U) +#define SCI_BRS_CONFIGVALUE (55U) #define SCI_PIO0_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)1U << 1U)) -#define SCI_PIO1_CONFIGVALUE ((uint32)((uint32)0U << 2U ) | (uint32)((uint32)0U << 1U)) -#define SCI_PIO6_CONFIGVALUE ((uint32)((uint32)0U << 2U ) | (uint32)((uint32)0U << 1U)) +#define SCI_PIO1_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)0U << 1U)) +#define SCI_PIO6_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)0U << 1U)) #define SCI_PIO7_CONFIGVALUE ((uint32)((uint32)0U << 2U ) | (uint32)((uint32)0U << 1U)) #define SCI_PIO8_CONFIGVALUE ((uint32)((uint32)1U << 2U ) | (uint32)((uint32)1U << 1U)) +/* Configuration registers initial value for SCI*/ +#define SCILIN_GCR0_CONFIGVALUE 0x00000001U +#define SCILIN_GCR1_CONFIGVALUE ((uint32)((uint32)1U << 5U) \ + |(uint32)((uint32)(1U-1U) << 4U) \ + |(uint32)((uint32)0U << 3U) \ + |(uint32)((uint32)0U << 2U) \ + |(uint32)((uint32)1U << 1U) \ + |(uint32)((uint32)0U << 2U) \ + |(uint32)(0x03000080U)) + +#define SCILIN_SETINTLVL_CONFIGVALUE ((uint32)((uint32)0U << 26U) \ + |(uint32)((uint32)0U << 25U) \ + |(uint32)((uint32)0U << 24U) \ + |(uint32)((uint32)0U << 9U) \ + |(uint32)((uint32)0U << 8U) \ + |(uint32)((uint32)0U << 1U) \ + |(uint32)((uint32)0U)) +#define SCILIN_SETINT_CONFIGVALUE ((uint32)((uint32)0U << 26U) \ + |(uint32)((uint32)0U << 25U) \ + |(uint32)((uint32)0U << 24U) \ + |(uint32)((uint32)0U << 9U) \ + |(uint32)((uint32)0U << 1U) \ + |(uint32)((uint32)0U << 0U)) + +#define SCILIN_FORMAT_CONFIGVALUE (8U - 1U) +#define SCILIN_BRS_CONFIGVALUE (6U) +#define SCILIN_PIO0_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U)) +#define SCILIN_PIO1_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 1U)) +#define SCILIN_PIO6_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 1U)) +#define SCILIN_PIO7_CONFIGVALUE ((uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U)) +#define SCILIN_PIO8_CONFIGVALUE ((uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U)) + + + /** * @defgroup SCI SCI * @brief Serial Communication Interface Module. @@ -182,6 +216,7 @@ void sciEnterResetState(sciBASE_t *sci); void sciExitResetState(sciBASE_t *sci); void sciGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type); +void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type); /** @fn void sciNotification(sciBASE_t *sci, uint32 flags) * @brief Interrupt callback * @param[in] sci - sci module base address Index: firmware/include/spi.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/spi.h (.../spi.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/spi.h (.../spi.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -157,26 +157,9 @@ -#define SPI4_GCR1_CONFIGVALUE (0x01000000U | (uint32)((uint32)1U << 1U) | 1U) -#define SPI4_INT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) -#define SPI4_LVL_CONFIGVALUE ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U)) -#define SPI4_PC0_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U)) -#define SPI4_PC1_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) -#define SPI4_PC6_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) -#define SPI4_PC7_CONFIGVALUE ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U)) -#define SPI4_PC8_CONFIGVALUE ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U)) -#define SPI4_DELAY_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U)) - -#define SPI4_FMT0_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define SPI4_FMT1_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define SPI4_FMT2_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) -#define SPI4_FMT3_CONFIGVALUE ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)109U << 8U) | (uint32)((uint32)16U << 0U)) - - - /** * @defgroup SPI SPI * @brief Serial Peripheral Interface Module. @@ -207,7 +190,6 @@ void spiDisableLoopback(spiBASE_t *spi); SpiDataStatus_t SpiTxStatus(spiBASE_t *spi); SpiDataStatus_t SpiRxStatus(spiBASE_t *spi); -void spi4GetConfigValue(spi_config_reg_t *config_reg, config_value_type_t type); /** @fn void spiNotification(spiBASE_t *spi, uint32 flags) * @brief Interrupt callback Index: firmware/include/sys_core.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/sys_core.h (.../sys_core.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/sys_core.h (.../sys_core.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -72,7 +72,7 @@ * * @note: Use this macro for SVC Mode Stack length (in bytes) */ -#define SVC_STACK_LENGTH 0x00000100U +#define SVC_STACK_LENGTH 0x00001000U /** @def FIQ_STACK_LENGTH * @brief FIQ Mode Stack length (in bytes) @@ -81,7 +81,7 @@ * * @note: Use this macro for FIQ Mode Stack length (in bytes) */ -#define FIQ_STACK_LENGTH 0x00000100U +#define FIQ_STACK_LENGTH 0x00001000U /** @def IRQ_STACK_LENGTH * @brief IRQ Mode Stack length (in bytes) @@ -90,7 +90,7 @@ * * @note: Use this macro for IRQ Mode Stack length (in bytes) */ -#define IRQ_STACK_LENGTH 0x00000100U +#define IRQ_STACK_LENGTH 0x00002000U /** @def ABORT_STACK_LENGTH * @brief ABORT Mode Stack length (in bytes) @@ -99,7 +99,7 @@ * * @note: Use this macro for ABORT Mode Stack length (in bytes) */ -#define ABORT_STACK_LENGTH 0x00000100U +#define ABORT_STACK_LENGTH 0x00000400U /** @def UNDEF_STACK_LENGTH * @brief UNDEF Mode Stack length (in bytes) @@ -108,7 +108,7 @@ * * @note: Use this macro for UNDEF Mode Stack length (in bytes) */ -#define UNDEF_STACK_LENGTH 0x00000100U +#define UNDEF_STACK_LENGTH 0x00000400U /* System Core Interface Functions */ Index: firmware/include/sys_vim.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/sys_vim.h (.../sys_vim.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/sys_vim.h (.../sys_vim.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -90,6 +90,14 @@ extern void esmHighInterrupt(void); extern void phantomInterrupt(void); +extern void rtiCompare0Interrupt(void); +extern void rtiCompare1Interrupt(void); +extern void rtiCompare3Interrupt(void); +extern void linHighLevelInterrupt(void); +extern void can1HighLevelInterrupt(void); +extern void can1LowLevelInterrupt(void); +extern void dmaBTCAInterrupt(void); +extern void sciHighLevelInterrupt(void); /* USER CODE BEGIN (3) */ /* USER CODE END */ @@ -124,7 +132,7 @@ /* Configuration registers initial value */ #define VIM_FIRQPR0_CONFIGVALUE ( (uint32)((uint32)SYS_FIQ << 0U)\ | (uint32)((uint32)SYS_FIQ << 1U)\ - | (uint32)((uint32)SYS_IRQ << 2U)\ + | (uint32)((uint32)SYS_FIQ << 2U)\ | (uint32)((uint32)SYS_IRQ << 3U)\ | (uint32)((uint32)SYS_IRQ << 4U)\ | (uint32)((uint32)SYS_IRQ << 5U)\ @@ -256,21 +264,21 @@ #define VIM_REQMASKSET0_CONFIGVALUE ( (uint32)((uint32)1U << 0U)\ | (uint32)((uint32)1U << 1U)\ - | (uint32)((uint32)0U << 2U)\ - | (uint32)((uint32)0U << 3U)\ + | (uint32)((uint32)1U << 2U)\ + | (uint32)((uint32)1U << 3U)\ | (uint32)((uint32)0U << 4U)\ - | (uint32)((uint32)0U << 5U)\ + | (uint32)((uint32)1U << 5U)\ | (uint32)((uint32)0U << 6U)\ | (uint32)((uint32)0U << 7U)\ | (uint32)((uint32)0U << 8U)\ | (uint32)((uint32)0U << 9U)\ | (uint32)((uint32)0U << 10U)\ | (uint32)((uint32)0U << 11U)\ | (uint32)((uint32)0U << 12U)\ - | (uint32)((uint32)0U << 13U)\ + | (uint32)((uint32)1U << 13U)\ | (uint32)((uint32)0U << 14U)\ | (uint32)((uint32)0U << 15U)\ - | (uint32)((uint32)0U << 16U)\ + | (uint32)((uint32)1U << 16U)\ | (uint32)((uint32)0U << 17U)\ | (uint32)((uint32)0U << 18U)\ | (uint32)((uint32)0U << 19U)\ @@ -283,7 +291,7 @@ | (uint32)((uint32)0U << 26U)\ | (uint32)((uint32)0U << 27U)\ | (uint32)((uint32)0U << 28U)\ - | (uint32)((uint32)0U << 29U)\ + | (uint32)((uint32)1U << 29U)\ | (uint32)((uint32)0U << 30U)\ | (uint32)((uint32)0U << 31U)) @@ -295,7 +303,7 @@ | (uint32)((uint32)0U << 5U)\ | (uint32)((uint32)0U << 6U)\ | (uint32)((uint32)0U << 7U)\ - | (uint32)((uint32)0U << 8U)\ + | (uint32)((uint32)1U << 8U)\ | (uint32)((uint32)0U << 9U)\ | (uint32)((uint32)0U << 10U)\ | (uint32)((uint32)0U << 11U)\ @@ -320,7 +328,7 @@ | (uint32)((uint32)0U << 30U)\ | (uint32)((uint32)0U << 31U)) -#define VIM_REQMASKSET2_CONFIGVALUE ( (uint32)((uint32)0U << 0U)\ +#define VIM_REQMASKSET2_CONFIGVALUE ( (uint32)((uint32)1U << 0U)\ | (uint32)((uint32)0U << 1U)\ | (uint32)((uint32)0U << 2U)\ | (uint32)((uint32)0U << 3U)\ Index: firmware/include/system.h =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/include/system.h (.../system.h) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/include/system.h (.../system.h) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -115,7 +115,7 @@ * * PLL 1 clock source exported from HALCoGen GUI */ -#define PLL1_FREQ 220.00F +#define PLL1_FREQ 208.00F /** @def LPO_LF_FREQ * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI @@ -143,28 +143,28 @@ * * GCLK domain frequency exported from HALCoGen GUI */ -#define GCLK_FREQ 220.000F +#define GCLK_FREQ 208.000F /** @def HCLK_FREQ * @brief HCLK domain frequency exported from HALCoGen GUI * * HCLK domain frequency exported from HALCoGen GUI */ -#define HCLK_FREQ 220.000F +#define HCLK_FREQ 208.000F /** @def RTI_FREQ * @brief RTI Clock frequency exported from HALCoGen GUI * * RTI Clock frequency exported from HALCoGen GUI */ -#define RTI_FREQ 110.000F +#define RTI_FREQ 104.000F /** @def AVCLK1_FREQ * @brief AVCLK1 Domain frequency exported from HALCoGen GUI * * AVCLK Domain frequency exported from HALCoGen GUI */ -#define AVCLK1_FREQ 110.000F +#define AVCLK1_FREQ 104.000F /** @def AVCLK2_FREQ * @brief AVCLK2 Domain frequency exported from HALCoGen GUI @@ -178,42 +178,42 @@ * * AVCLK3 Domain frequency exported from HALCoGen GUI */ -#define AVCLK3_FREQ 110.000F +#define AVCLK3_FREQ 104.000F /** @def AVCLK4_FREQ * @brief AVCLK4 Domain frequency exported from HALCoGen GUI * * AVCLK4 Domain frequency exported from HALCoGen GUI */ -#define AVCLK4_FREQ 110.000F +#define AVCLK4_FREQ 104.000F /** @def VCLK1_FREQ * @brief VCLK1 Domain frequency exported from HALCoGen GUI * * VCLK1 Domain frequency exported from HALCoGen GUI */ -#define VCLK1_FREQ 110.000F +#define VCLK1_FREQ 104.000F /** @def VCLK2_FREQ * @brief VCLK2 Domain frequency exported from HALCoGen GUI * * VCLK2 Domain frequency exported from HALCoGen GUI */ -#define VCLK2_FREQ 110.000F +#define VCLK2_FREQ 104.000F /** @def VCLK3_FREQ * @brief VCLK3 Domain frequency exported from HALCoGen GUI * * VCLK3 Domain frequency exported from HALCoGen GUI */ -#define VCLK3_FREQ 110.000F +#define VCLK3_FREQ 104.000F /** @def VCLK4_FREQ * @brief VCLK4 Domain frequency exported from HALCoGen GUI * * VCLK4 Domain frequency exported from HALCoGen GUI */ -#define VCLK4_FREQ 110.000F +#define VCLK4_FREQ 104.000F /** @def SYS_PRE1 @@ -337,7 +337,7 @@ | (uint32)((uint32)0x1FU << 24U) \ | (uint32)0x00000000U \ | (uint32)((uint32)(6U - 1U)<< 16U)\ - | (uint32)(0xA400U)) + | (uint32)(0x9B00U)) #define SYS_PLLCTL1_CONFIGVALUE_2 (((SYS_PLLCTL1_CONFIGVALUE_1) & 0xE0FFFFFFU) | (uint32)((uint32)(1U - 1U) << 24U)) Index: firmware/source/adc.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/adc.c (.../adc.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/adc.c (.../adc.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -83,10 +83,10 @@ adcREG1->OPMODECR |= 0x80000000U; /** - Setup prescaler */ - adcREG1->CLOCKCR = 10U; + adcREG1->CLOCKCR = 25U; /** - Setup memory boundaries */ - adcREG1->BNDCR = (uint32)((uint32)8U << 16U) | (8U + 8U); + adcREG1->BNDCR = (uint32)((uint32)0U << 16U) | (0U + 10U); adcREG1->BNDEND = (adcREG1->BNDEND & 0xFFFF0000U) | (2U); /** - Setup event group conversion mode @@ -106,7 +106,7 @@ | (uint32)ADC1_EVENT; /** - Setup event group sample window */ - adcREG1->EVSAMP = 1U; + adcREG1->EVSAMP = 0U; /** - Setup event group sample discharge * - Setup discharge prescaler @@ -121,8 +121,8 @@ * - Enable/Disable continuous conversion */ adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT + | (uint32)0x00000020U | (uint32)0x00000000U - | (uint32)0x00000000U | (uint32)0x00000000U; /** - Setup group 1 hardware trigger @@ -133,7 +133,7 @@ | (uint32)ADC1_EVENT; /** - Setup group 1 sample window */ - adcREG1->G1SAMP = 1U; + adcREG1->G1SAMP = 0U; /** - Setup group 1 sample discharge * - Setup discharge prescaler @@ -160,7 +160,7 @@ | (uint32)ADC1_EVENT; /** - Setup group 2 sample window */ - adcREG1->G2SAMP = 1U; + adcREG1->G2SAMP = 0U; /** - Setup group 2 sample discharge * - Setup discharge prescaler @@ -197,135 +197,6 @@ adcREG1->PARCR = 0x00000005U; - - /** @b Initialize @b ADC2: */ - - /** - Reset ADC module */ - adcREG2->RSTCR = 1U; - adcREG2->RSTCR = 0U; - - /** - Enable 12-BIT ADC */ - adcREG2->OPMODECR |= 0x80000000U; - - /** - Setup prescaler */ - adcREG2->CLOCKCR = 10U; - - /** - Setup memory boundaries */ - adcREG2->BNDCR = (uint32)((uint32)8U << 16U) | (8U + 8U); - adcREG2->BNDEND = (adcREG2->BNDEND & 0xFFFF0000U) | (2U); - - /** - Setup event group conversion mode - * - Setup data format - * - Enable/Disable channel id in conversion result - * - Enable/Disable continuous conversion - */ - adcREG2->GxMODECR[0U] = (uint32)ADC_12_BIT - | (uint32)0x00000000U - | (uint32)0x00000000U; - - /** - Setup event group hardware trigger - * - Setup hardware trigger edge - * - Setup hardware trigger source - */ - adcREG2->EVSRC = (uint32)0x00000000U - | (uint32)ADC2_EVENT; - - /** - Setup event group sample window */ - adcREG2->EVSAMP = 1U; - - /** - Setup event group sample discharge - * - Setup discharge prescaler - * - Enable/Disable discharge - */ - adcREG2->EVSAMPDISEN = (uint32)((uint32)0U << 8U) - | (uint32)0x00000000U; - - /** - Setup group 1 conversion mode - * - Setup data format - * - Enable/Disable channel id in conversion result - * - Enable/Disable continuous conversion - */ - adcREG2->GxMODECR[1U] = (uint32)ADC_12_BIT - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - /** - Setup group 1 hardware trigger - * - Setup hardware trigger edge - * - Setup hardware trigger source - */ - adcREG2->G1SRC = (uint32)0x00000000U - | (uint32)ADC2_EVENT; - - - /** - Setup group 1 sample window */ - adcREG2->G1SAMP = 1U; - - /** - Setup group 1 sample discharge - * - Setup discharge prescaler - * - Enable/Disable discharge - */ - adcREG2->G1SAMPDISEN = (uint32)((uint32)0U << 8U) - | (uint32)0x00000000U; - - /** - Setup group 2 conversion mode - * - Setup data format - * - Enable/Disable channel id in conversion result - * - Enable/Disable continuous conversion - */ - adcREG2->GxMODECR[2U] = (uint32)ADC_12_BIT - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - /** - Setup group 2 hardware trigger - * - Setup hardware trigger edge - * - Setup hardware trigger source - */ - adcREG2->G2SRC = (uint32)0x00000000U - | (uint32)ADC2_EVENT; - - /** - Setup group 2 sample window */ - adcREG2->G2SAMP = 1U; - - /** - Setup group 2 sample discharge - * - Setup discharge prescaler - * - Enable/Disable discharge - */ - adcREG2->G2SAMPDISEN = (uint32)((uint32)0U << 8U) - | (uint32)0x00000000U; - - - /** - ADC2 EVT pin output value */ - adcREG2->EVTOUT = 0U; - - /** - ADC2 EVT pin direction */ - adcREG2->EVTDIR = 0U; - - /** - ADC2 EVT pin open drain enable */ - adcREG2->EVTPDR = 0U; - - /** - ADC2 EVT pin pullup / pulldown selection */ - adcREG2->EVTPSEL = 1U; - - /** - ADC2 EVT pin pullup / pulldown enable*/ - adcREG2->EVTDIS = 0U; - - /** - Enable ADC module */ - adcREG2->OPMODECR |= 0x80140001U; - - /** - Wait for buffer initialization complete */ - /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ - while (((adcREG2->BNDEND & 0xFFFF0000U) >> 16U) != 0U) - { - } /* Wait */ - - /** - Setup parity */ - adcREG2->PARCR = 0x00000005U; - - /** @note This function has to be called before the driver can be used.\n - * This function has to be executed in privileged mode.\n - */ /* USER CODE BEGIN (4) */ /* USER CODE END */ } @@ -361,10 +232,30 @@ 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000001U | + 0x00000002U | + 0x00000004U | + 0x00000008U | + 0x00000010U | + 0x00000020U | + 0x00000040U | + 0x00000080U | + 0x00000100U | 0x00000000U | + 0x00000400U | + 0x00000800U | + 0x00001000U | + 0x00002000U | + 0x00004000U | 0x00000000U | + 0x00010000U | + 0x00020000U | + 0x00040000U | + 0x00080000U | 0x00000000U | 0x00000000U | + 0x00400000U | + 0x00800000U, 0x00000000U | 0x00000000U | 0x00000000U | @@ -384,30 +275,10 @@ 0x00000000U | 0x00000000U | 0x00000000U | - 0x00000000U, 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | - 0x00000000U | 0x00000000U}, {0x00000000U | 0x00000000U | @@ -462,11 +333,11 @@ /** - s_adcFiFoSize is used as constant table for channel selection */ static const uint32 s_adcFiFoSize[2U][3U] = { + {0U, + 20U, + 32U}, {16U, 16U, - 16U}, - {16U, - 16U, 16U} }; @@ -1107,68 +978,6 @@ } } -/** @fn void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current -* value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') -* of the configuration registers to the struct pointed by config_reg -* -*/ -/* SourceId : ADC_SourceId_013 */ -/* DesignId : ADC_DesignId_012 */ -/* Requirements : HL_SR203 */ -void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_OPMODECR = ADC2_OPMODECR_CONFIGVALUE; - config_reg->CONFIG_CLOCKCR = ADC2_CLOCKCR_CONFIGVALUE; - config_reg->CONFIG_GxMODECR[0U] = ADC2_G0MODECR_CONFIGVALUE; - config_reg->CONFIG_GxMODECR[1U] = ADC2_G1MODECR_CONFIGVALUE; - config_reg->CONFIG_GxMODECR[2U] = ADC2_G2MODECR_CONFIGVALUE; - config_reg->CONFIG_G0SRC = ADC2_G0SRC_CONFIGVALUE; - config_reg->CONFIG_G1SRC = ADC2_G1SRC_CONFIGVALUE; - config_reg->CONFIG_G2SRC = ADC2_G2SRC_CONFIGVALUE; - config_reg->CONFIG_BNDCR = ADC2_BNDCR_CONFIGVALUE; - config_reg->CONFIG_BNDEND = ADC2_BNDEND_CONFIGVALUE; - config_reg->CONFIG_G0SAMP = ADC2_G0SAMP_CONFIGVALUE; - config_reg->CONFIG_G1SAMP = ADC2_G1SAMP_CONFIGVALUE; - config_reg->CONFIG_G2SAMP = ADC2_G2SAMP_CONFIGVALUE; - config_reg->CONFIG_G0SAMPDISEN = ADC2_G0SAMPDISEN_CONFIGVALUE; - config_reg->CONFIG_G1SAMPDISEN = ADC2_G1SAMPDISEN_CONFIGVALUE; - config_reg->CONFIG_G2SAMPDISEN = ADC2_G2SAMPDISEN_CONFIGVALUE; - config_reg->CONFIG_PARCR = ADC2_PARCR_CONFIGVALUE; - } - else - { - /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ - config_reg->CONFIG_OPMODECR = adcREG2->OPMODECR; - config_reg->CONFIG_CLOCKCR = adcREG2->CLOCKCR; - config_reg->CONFIG_GxMODECR[0U] = adcREG2->GxMODECR[0U]; - config_reg->CONFIG_GxMODECR[1U] = adcREG2->GxMODECR[1U]; - config_reg->CONFIG_GxMODECR[2U] = adcREG2->GxMODECR[2U]; - config_reg->CONFIG_G0SRC = adcREG2->EVSRC; - config_reg->CONFIG_G1SRC = adcREG2->G1SRC; - config_reg->CONFIG_G2SRC = adcREG2->G2SRC; - config_reg->CONFIG_BNDCR = adcREG2->BNDCR; - config_reg->CONFIG_BNDEND = adcREG2->BNDEND; - config_reg->CONFIG_G0SAMP = adcREG2->EVSAMP; - config_reg->CONFIG_G1SAMP = adcREG2->G1SAMP; - config_reg->CONFIG_G2SAMP = adcREG2->G2SAMP; - config_reg->CONFIG_G0SAMPDISEN = adcREG2->EVSAMPDISEN; - config_reg->CONFIG_G1SAMPDISEN = adcREG2->G1SAMPDISEN; - config_reg->CONFIG_G2SAMPDISEN = adcREG2->G2SAMPDISEN; - config_reg->CONFIG_PARCR = adcREG2->PARCR; - } -} /* USER CODE BEGIN (35) */ /* USER CODE END */ @@ -1178,5 +987,3 @@ - - Index: firmware/source/can.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/can.c (.../can.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/can.c (.../can.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -182,326 +182,140 @@ /** - Setup auto bus on timer period */ canREG1->ABOTR = (uint32)0U; - /** - Setup IF1 for data transmission + /** - Initialize message 1 * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration * - Set IF1 control byte + * - Set IF1 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ while ((canREG1->IF1STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG1->IF1CMD = 0x87U; - /** - Setup IF2 for reading data - * - Wait until IF1 is ready for use - * - Set IF1 control byte + + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x601U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 1U; + + /** - Initialize message 2 + * - Wait until IF2 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF2 control byte + * - Set IF2 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ while ((canREG1->IF2STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG1->IF2CMD = 0x17U; - /** - Setup bit timing - * - Setup baud rate prescaler extension - * - Setup TSeg2 - * - Setup TSeg1 - * - Setup sample jump width - * - Setup baud rate prescaler - */ - canREG1->BTR = (uint32)((uint32)0U << 16U) | - (uint32)((uint32)(3U - 1U) << 12U) | - (uint32)((uint32)((4U + 3U) - 1U) << 8U) | - (uint32)((uint32)(3U - 1U) << 6U) | - (uint32)19U; + canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x602U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2CMD = (uint8) 0xF8U; + canREG1->IF2NO = 2U; - - /** - CAN1 Port output values */ - canREG1->TIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)1U << 2U ) - | (uint32)((uint32)1U << 1U ); - - canREG1->RIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)0U << 2U ) - | (uint32)((uint32)0U <<1U ); - - /** - Leave configuration and initialization mode */ - canREG1->CTL &= ~(uint32)(0x00000041U); - - - /** @b Initialize @b CAN2: */ - - /** - Setup control register - * - Disable automatic wakeup on bus activity - * - Local power down mode disabled - * - Disable DMA request lines - * - Enable global Interrupt Line 0 and 1 - * - Disable debug mode - * - Release from software reset - * - Enable/Disable parity or ECC - * - Enable/Disable auto bus on timer - * - Setup message completion before entering debug state - * - Setup normal operation mode - * - Request write access to the configuration registers - * - Setup automatic retransmission of messages - * - Disable error interrupts - * - Disable status interrupts - * - Enter initialization mode + /** - Initialize message 3 + * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF1 control byte + * - Set IF1 message number */ - canREG2->CTL = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)((uint32)0x00000005U << 10U) - | 0x00020043U; + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ - /** - Clear all pending error flags and reset current status */ - canREG2->ES |= 0xFFFFFFFFU; + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x603U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 3U; - /** - Assign interrupt level for messages */ - canREG2->INTMUXx[0U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - canREG2->INTMUXx[1U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - - /** - Setup auto bus on timer period */ - canREG2->ABOTR = (uint32)0U; - - - /** - Setup IF1 for data transmission - * - Wait until IF1 is ready for use - * - Set IF1 control byte + /** - Initialize message 4 + * - Wait until IF2 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF2 control byte + * - Set IF2 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG2->IF1STAT & 0x80U) ==0x80U) + while ((canREG1->IF2STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG2->IF1CMD = 0x87U; - /** - Setup IF2 for reading data + canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x604U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2CMD = (uint8) 0xF8U; + canREG1->IF2NO = 4U; + + /** - Initialize message 5 * - Wait until IF1 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration * - Set IF1 control byte + * - Set IF1 message number */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG2->IF2STAT & 0x80U) ==0x80U) + while ((canREG1->IF1STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG2->IF2CMD = 0x17U; - /** - Setup bit timing - * - Setup baud rate prescaler extension - * - Setup TSeg2 - * - Setup TSeg1 - * - Setup sample jump width - * - Setup baud rate prescaler - */ - canREG2->BTR = (uint32)((uint32)0U << 16U) | - (uint32)((uint32)(3U - 1U) << 12U) | - (uint32)((uint32)((4U + 3U) - 1U) << 8U) | - (uint32)((uint32)(3U - 1U) << 6U) | - (uint32)19U; + canREG1->IF1MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x605U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF1CMD = (uint8) 0xF8U; + canREG1->IF1NO = 5U; - - /** - CAN2 Port output values */ - canREG2->TIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)1U << 2U ) - | (uint32)((uint32)1U << 1U ); - - canREG2->RIOC = (uint32)((uint32)1U << 18U ) - | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) - | (uint32)((uint32)1U << 3U ) - | (uint32)((uint32)0U << 2U ) - | (uint32)((uint32)0U <<1U ); - - /** - Leave configuration and initialization mode */ - canREG2->CTL &= ~(uint32)(0x00000041U); - - /** @b Initialize @b CAN3: */ - - /** - Setup control register - * - Disable automatic wakeup on bus activity - * - Local power down mode disabled - * - Disable DMA request lines - * - Enable global Interrupt Line 0 and 1 - * - Disable debug mode - * - Release from software reset - * - Enable/Disable parity or ECC - * - Enable/Disable auto bus on timer - * - Setup message completion before entering debug state - * - Setup normal operation mode - * - Request write access to the configuration registers - * - Setup automatic retransmission of messages - * - Disable error interrupts - * - Disable status interrupts - * - Enter initialization mode + /** - Initialize message 8 + * - Wait until IF2 is ready for use + * - Set message mask + * - Set message control word + * - Set message arbitration + * - Set IF2 control byte + * - Set IF2 message number */ - canREG3->CTL = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)((uint32)0x00000005U << 10U) - | 0x00020043U; + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF2STAT & 0x80U) ==0x80U) + { + } /* Wait */ - /** - Clear all pending error flags and reset current status */ - canREG3->ES |= 0xFFFFFFFFU; + canREG1->IF2MSK = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2ARB = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)8U & (uint32)0x1FFFFFFFU) << (uint32)0U); + canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U; + canREG1->IF2CMD = (uint8) 0xF8U; + canREG1->IF2NO = 8U; - /** - Assign interrupt level for messages */ - canREG3->INTMUXx[0U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - canREG3->INTMUXx[1U] = (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U - | (uint32)0x00000000U; - - /** - Setup auto bus on timer period */ - canREG3->ABOTR = (uint32)0U; - /** - Setup IF1 for data transmission * - Wait until IF1 is ready for use * - Set IF1 control byte */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG3->IF1STAT & 0x80U) ==0x80U) + while ((canREG1->IF1STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG3->IF1CMD = 0x87U; + canREG1->IF1CMD = 0x87U; /** - Setup IF2 for reading data * - Wait until IF1 is ready for use * - Set IF1 control byte */ /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ - while ((canREG3->IF2STAT & 0x80U) ==0x80U) + while ((canREG1->IF2STAT & 0x80U) ==0x80U) { } /* Wait */ - canREG3->IF2CMD = 0x17U; + canREG1->IF2CMD = 0x17U; /** - Setup bit timing * - Setup baud rate prescaler extension @@ -510,31 +324,34 @@ * - Setup sample jump width * - Setup baud rate prescaler */ - canREG3->BTR = (uint32)((uint32)0U << 16U) | - (uint32)((uint32)(3U - 1U) << 12U) | - (uint32)((uint32)((4U + 3U) - 1U) << 8U) | - (uint32)((uint32)(3U - 1U) << 6U) | - (uint32)(uint32)19U; + canREG1->BTR = (uint32)((uint32)0U << 16U) | + (uint32)((uint32)(6U - 1U) << 12U) | + (uint32)((uint32)((3U + 6U) - 1U) << 8U) | + (uint32)((uint32)(4U - 1U) << 6U) | + (uint32)25U; - /** - CAN3 Port output values */ - canREG3->TIOC = (uint32)((uint32)1U << 18U ) + /** - CAN1 Port output values */ + canREG1->TIOC = (uint32)((uint32)1U << 18U ) | (uint32)((uint32)0U << 17U ) - | (uint32)((uint32)0U << 16U ) + | (uint32)((uint32)0U << 16U ) | (uint32)((uint32)1U << 3U ) | (uint32)((uint32)1U << 2U ) | (uint32)((uint32)1U << 1U ); - canREG3->RIOC = (uint32)((uint32)1U << 18U ) + canREG1->RIOC = (uint32)((uint32)1U << 18U ) | (uint32)((uint32)0U << 17U ) | (uint32)((uint32)0U << 16U ) | (uint32)((uint32)1U << 3U ) | (uint32)((uint32)0U << 2U ) - | (uint32)((uint32)0U << 1U ); + | (uint32)((uint32)0U <<1U ); /** - Leave configuration and initialization mode */ - canREG3->CTL &= ~(uint32)(0x00000041U); + canREG1->CTL &= ~(uint32)(0x00000041U); + + + /** @note This function has to be called before the driver can be used.\n * This function has to be executed in privileged mode.\n */ @@ -1500,110 +1317,105 @@ config_reg->CONFIG_RIOC = canREG1->RIOC; } } -/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the CAN2 configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current -* value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') -* of the configuration registers to the struct pointed by config_reg -* + +/* USER CODE BEGIN (40) */ +/* USER CODE END */ +/** @fn void can1HighLevelInterrupt(void) +* @brief CAN1 Level 0 Interrupt Handler */ -/* SourceId : CAN_SourceId_018 */ -/* DesignId : CAN_DesignId_017 */ -/* Requirements : HL_SR224 */ -void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + +/* SourceId : CAN_SourceId_020 */ +/* DesignId : CAN_DesignId_018 */ +/* Requirements : HL_SR221, HL_SR222, HL_SR223 */ +void can1HighLevelInterrupt(void) { - if (type == InitialValue) + uint32 value = canREG1->INT; + uint32 ES_value; + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ + + if (value == 0x8000U) { - config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE; - config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE; - config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE; - config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE; - config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE; - config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE; - config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE; - config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE; - config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE; + /* Read Error and Status Register*/ + ES_value = canREG1->ES; + + /* Check for Error (PES, Boff, EWarn & EPass) captured */ + if((ES_value & 0x1E0U) != 0U) + { + canErrorNotification(canREG1, ES_value & 0x1E0U); + } + else + { + /* Call General Can notification incase of RxOK, TxOK, PDA, WakeupPnd Interrupt */ + canStatusChangeNotification(canREG1, ES_value & 0x618U); + } } else { - /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ - config_reg->CONFIG_CTL = canREG2->CTL; - config_reg->CONFIG_ES = canREG2->ES; - config_reg->CONFIG_BTR = canREG2->BTR; - config_reg->CONFIG_TEST = canREG2->TEST; - config_reg->CONFIG_ABOTR = canREG2->ABOTR; - config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[0]; - config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[1]; - config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[2]; - config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[3]; - config_reg->CONFIG_TIOC = canREG2->TIOC; - config_reg->CONFIG_RIOC = canREG2->RIOC; + /** - Setup IF1 for clear pending interrupt flag */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + + canREG1->IF1CMD = 0x08U; + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + canREG1->IF1NO = (uint8) value; + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + + canMessageNotification(canREG1, value); } + +/* USER CODE BEGIN (42) */ +/* USER CODE END */ + } -/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the CAN3 configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current -* value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') -* of the configuration registers to the struct pointed by config_reg -* + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +/** @fn void can1LowLevelInterrupt(void) +* @brief CAN1 Level 1 Interrupt Handler */ -/* SourceId : CAN_SourceId_019 */ -/* DesignId : CAN_DesignId_017 */ -/* Requirements : HL_SR224 */ -void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + +/* SourceId : CAN_SourceId_021 */ +/* DesignId : CAN_DesignId_019 */ +/* Requirements : HL_SR221, HL_SR223 */ +void can1LowLevelInterrupt(void) { - if (type == InitialValue) - { - config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE; - config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE; - config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE; - config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE; - config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE; - config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE; - config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE; - config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE; - config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE; - config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE; - } - else - { - /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ - config_reg->CONFIG_CTL = canREG3->CTL; - config_reg->CONFIG_ES = canREG3->ES; - config_reg->CONFIG_BTR = canREG3->BTR; - config_reg->CONFIG_TEST = canREG3->TEST; - config_reg->CONFIG_ABOTR = canREG3->ABOTR; - config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[0]; - config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[1]; - config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[2]; - config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[3]; - config_reg->CONFIG_TIOC = canREG3->TIOC; - config_reg->CONFIG_RIOC = canREG3->RIOC; - } -} + uint32 messageBox = canREG1->INT >> 16U; +/* USER CODE BEGIN (44) */ +/* USER CODE END */ + /** - Setup IF1 for clear pending interrupt flag */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF1CMD = 0x08U; + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + canREG1->IF1NO = (uint8) messageBox; + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status check for execution sequence" */ + while ((canREG1->IF1STAT & 0x80U) ==0x80U) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + canMessageNotification(canREG1, messageBox); +/* USER CODE BEGIN (45) */ +/* USER CODE END */ +} + + Fisheye: Tag abb9687e52d9db5df1abe7626ba04a6d431ba823 refers to a dead (removed) revision in file `firmware/source/dcc.c'. Fisheye: No comparison available. Pass `N' to diff? Index: firmware/source/etpwm.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/etpwm.c (.../etpwm.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/etpwm.c (.../etpwm.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -82,13 +82,13 @@ etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG1->TBPRD = 1000U; + etpwmREG1->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG1->CMPA = 50U; + etpwmREG1->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG1->CMPB = 50U; + etpwmREG1->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG1->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -107,7 +107,7 @@ | (uint16)((uint16)0u << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -122,7 +122,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG1->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ @@ -177,13 +177,13 @@ etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG2->TBPRD = 1000U; + etpwmREG2->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG2->CMPA = 50U; + etpwmREG2->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG2->CMPB = 50U; + etpwmREG2->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -202,7 +202,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -217,7 +217,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG2->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ @@ -272,13 +272,13 @@ etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG3->TBPRD = 1000U; + etpwmREG3->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG3->CMPA = 50U; + etpwmREG3->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG3->CMPB = 50U; + etpwmREG3->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -297,7 +297,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -312,7 +312,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG3->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U)); /* Chopping Clock Frequency */ @@ -368,13 +368,13 @@ etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG4->TBPRD = 1000U; + etpwmREG4->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG4->CMPA = 50U; + etpwmREG4->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG4->CMPB = 50U; + etpwmREG4->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) @@ -393,7 +393,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -408,7 +408,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ @@ -454,102 +454,6 @@ etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM5 */ - - /** - Sets high speed time-base clock prescale bits */ - etpwmREG5->TBCTL = (uint16)0U << 7U; - - /** - Sets time-base clock prescale bits */ - etpwmREG5->TBCTL |= (uint16)((uint16)0U << 10U); - - /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG5->TBPRD = 1000U; - - /** - Setup the duty cycle for PWMA */ - etpwmREG5->CMPA = 50U; - - /** - Setup the duty cycle for PWMB */ - etpwmREG5->CMPB = 50U; - - /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ - etpwmREG5->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 4U)); - - /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ - etpwmREG5->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 8U)); - - /** - Mode setting for Dead Band Module - * -Select the input mode for Dead Band Module - * -Select the output mode for Dead Band Module - * -Select Polarity of the output PWMs - */ - etpwmREG5->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ - | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ - | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ - - /** - Set the rising edge delay */ - etpwmREG5->DBRED = 1U; - - /** - Set the falling edge delay */ - etpwmREG5->DBFED = 1U; - - /** - Enable the chopper module for ETPWMx - * -Sets the One shot pulse width in a chopper modulated wave - * -Sets the dutycycle for the subsequent pulse train - * -Sets the period for the subsequent pulse train - */ - etpwmREG5->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ - | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ - | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ - - - /** - Set trip source enable */ - etpwmREG5->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ - | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ - - /** - Set interrupt enable */ - etpwmREG5->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable one-shot interrupt generation */ - | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ - - /** - Sets up the event for interrupt */ - etpwmREG5->ETSEL = (uint16)NO_EVENT; - - if ((etpwmREG5->ETSEL & 0x0007U) != 0U) - { - etpwmREG5->ETSEL |= 0x0008U; - } - /** - Setup the frequency of the interrupt generation */ - etpwmREG5->ETPS = 1U; - - /** - Sets up the ADC SOC interrupt */ - etpwmREG5->ETSEL |= (uint16)(0x0000U) - | (uint16)(0x0000U) - | (uint16)((uint16)DCAEVT1 << 8U) - | (uint16)((uint16)DCBEVT1 << 12U); - - /** - Sets up the ADC SOC period */ - etpwmREG5->ETPS |= ((uint16)((uint16)1U << 8U) - | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM6 */ /** - Sets high speed time-base clock prescale bits */ @@ -559,13 +463,13 @@ etpwmREG6->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG6->TBPRD = 1000U; + etpwmREG6->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG6->CMPA = 50U; + etpwmREG6->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG6->CMPB = 50U; + etpwmREG6->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ @@ -585,7 +489,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -600,7 +504,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG6->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ @@ -657,13 +561,13 @@ etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG7->TBPRD = 1000U; + etpwmREG7->TBPRD = 25833U; /** - Setup the duty cycle for PWMA */ - etpwmREG7->CMPA = 50U; + etpwmREG7->CMPA = 0U; /** - Setup the duty cycle for PWMB */ - etpwmREG7->CMPB = 50U; + etpwmREG7->CMPB = 0U; /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ @@ -683,7 +587,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -698,7 +602,7 @@ * -Sets the period for the subsequent pulse train */ etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)1U << 1U) /* One-shot Pulse Width */ + | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ Index: firmware/source/gio.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/gio.c (.../gio.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/gio.c (.../gio.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -73,7 +73,7 @@ /** - Port A output values */ gioPORTA->DOUT = (uint32)((uint32)0U << 0U) /* Bit 0 */ | (uint32)((uint32)0U << 1U) /* Bit 1 */ - | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)1U << 2U) /* Bit 2 */ | (uint32)((uint32)0U << 3U) /* Bit 3 */ | (uint32)((uint32)0U << 4U) /* Bit 4 */ | (uint32)((uint32)0U << 5U) /* Bit 5 */ @@ -83,11 +83,11 @@ /** - Port A direction */ gioPORTA->DIR = (uint32)((uint32)0U << 0U) /* Bit 0 */ | (uint32)((uint32)0U << 1U) /* Bit 1 */ - | (uint32)((uint32)0U << 2U) /* Bit 2 */ + | (uint32)((uint32)1U << 2U) /* Bit 2 */ | (uint32)((uint32)0U << 3U) /* Bit 3 */ | (uint32)((uint32)0U << 4U) /* Bit 4 */ | (uint32)((uint32)0U << 5U) /* Bit 5 */ - | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)1U << 6U) /* Bit 6 */ | (uint32)((uint32)0U << 7U); /* Bit 7 */ /** - Port A open drain enable */ @@ -101,13 +101,13 @@ | (uint32)((uint32)0U << 7U); /* Bit 7 */ /** - Port A pullup / pulldown selection */ - gioPORTA->PSL = (uint32)((uint32)0U << 0U) /* Bit 0 */ - | (uint32)((uint32)0U << 1U) /* Bit 1 */ + gioPORTA->PSL = (uint32)((uint32)1U << 0U) /* Bit 0 */ + | (uint32)((uint32)1U << 1U) /* Bit 1 */ | (uint32)((uint32)0U << 2U) /* Bit 2 */ | (uint32)((uint32)0U << 3U) /* Bit 3 */ | (uint32)((uint32)0U << 4U) /* Bit 4 */ | (uint32)((uint32)0U << 5U) /* Bit 5 */ - | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)1U << 6U) /* Bit 6 */ | (uint32)((uint32)0U << 7U); /* Bit 7 */ /** - Port A pullup / pulldown enable*/ @@ -117,7 +117,7 @@ | (uint32)((uint32)0U << 3U) /* Bit 3 */ | (uint32)((uint32)0U << 4U) /* Bit 4 */ | (uint32)((uint32)0U << 5U) /* Bit 5 */ - | (uint32)((uint32)0U << 6U) /* Bit 6 */ + | (uint32)((uint32)1U << 6U) /* Bit 6 */ | (uint32)((uint32)0U << 7U); /* Bit 7 */ /** @b initialize @b Port @b B */ @@ -133,10 +133,10 @@ | (uint32)((uint32)0U << 7U); /* Bit 7 */ /** - Port B direction */ - gioPORTB->DIR = (uint32)((uint32)0U << 0U) /* Bit 0 */ - | (uint32)((uint32)0U << 1U) /* Bit 1 */ + gioPORTB->DIR = (uint32)((uint32)1U << 0U) /* Bit 0 */ + | (uint32)((uint32)1U << 1U) /* Bit 1 */ | (uint32)((uint32)0U << 2U) /* Bit 2 */ - | (uint32)((uint32)0U << 3U) /* Bit 3 */ + | (uint32)((uint32)1U << 3U) /* Bit 3 */ | (uint32)((uint32)0U << 4U) /* Bit 4 */ | (uint32)((uint32)0U << 5U) /* Bit 5 */ | (uint32)((uint32)0U << 6U) /* Bit 6 */ Index: firmware/source/het.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/het.c (.../het.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/het.c (.../het.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -60,17 +60,6 @@ 3U, }; -static const uint32 s_het2pwmPolarity[8U] = -{ - 3U, - 3U, - 3U, - 3U, - 3U, - 3U, - 3U, - 3U, -}; /*----------------------------------------------------------------------------*/ /* Default Program */ @@ -378,13 +367,13 @@ * - Next instruction = 18 * - Conditional next instruction = 18 * - Interrupt = 17 - * - Pin = 9 + * - Pin = 12 */ { /* Program */ 0x00025440U, /* Control */ - (0x00024007U | (uint32)((uint32)9U << 8U) | (uint32)((uint32)1U << 4U)), + (0x00024007U | (uint32)((uint32)12U << 8U) | (uint32)((uint32)1U << 4U)), /* Data */ 0x00000000U, /* Reserved */ @@ -395,13 +384,13 @@ * - Next instruction = 19 * - Conditional next instruction = 19 * - Interrupt = 18 - * - Pin = 11 + * - Pin = 14 */ { /* Program */ 0x00027440U, /* Control */ - (0x00026007U | (uint32)((uint32)11U << 8U) | (uint32)((uint32)1U << 4U)), + (0x00026007U | (uint32)((uint32)14U << 8U) | (uint32)((uint32)1U << 4U)), /* Data */ 0x00000000U, /* Reserved */ @@ -412,13 +401,13 @@ * - Next instruction = 20 * - Conditional next instruction = 20 * - Interrupt = 19 - * - Pin = 13 + * - Pin = 30 */ { /* Program */ 0x00029440U, /* Control */ - (0x00028007U | (uint32)((uint32)13U << 8U) | (uint32)((uint32)1U << 4U)), + (0x00028007U | (uint32)((uint32)30U << 8U) | (uint32)((uint32)1U << 4U)), /* Data */ 0x00000000U, /* Reserved */ @@ -794,7 +783,7 @@ /* Control */ (0x00004007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -811,7 +800,7 @@ /* Control */ (0x00052007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -828,7 +817,7 @@ /* Control */ (0x00008007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -845,7 +834,7 @@ /* Control */ (0x00056007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -862,7 +851,7 @@ /* Control */ (0x0000C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -879,7 +868,7 @@ /* Control */ (0x0005A007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -896,7 +885,7 @@ /* Control */ (0x00010007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -913,7 +902,7 @@ /* Control */ (0x0005E007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -930,7 +919,7 @@ /* Control */ (0x00014007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -947,7 +936,7 @@ /* Control */ (0x00062007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -964,7 +953,7 @@ /* Control */ (0x00018007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -981,7 +970,7 @@ /* Control */ (0x00066007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -998,7 +987,7 @@ /* Control */ (0x0001C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -1015,7 +1004,7 @@ /* Control */ (0x0006A007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -1032,7 +1021,7 @@ /* Control */ (0x00020007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)), /* Data */ - 55296U, + 52224U, /* Reserved */ 0x00000000U }, @@ -1049,7 +1038,7 @@ /* Control */ (0x0006E007U), /* Data */ - 109952U, + 103936U, /* Reserved */ 0x00000000U }, @@ -1074,1008 +1063,7 @@ }; -/*----------------------------------------------------------------------------*/ -/* Default Program */ -/** @var static const hetINSTRUCTION_t het2PROGRAM[58] -* @brief Default Program -* -* Het program running after initialization. -*/ - -static const hetINSTRUCTION_t het2PROGRAM[58U] = -{ - /* CNT: Timebase - * - Instruction = 0 - * - Next instruction = 1 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = na - * - Reg = T - */ - { - /* Program */ - 0x00002C80U, - /* Control */ - 0x01FFFFFFU, - /* Data */ - 0xFFFFFF80U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 0 -> Duty Cycle - * - Instruction = 1 - * - Next instruction = 2 - * - Conditional next instruction = 2 - * - Interrupt = 1 - * - Pin = 8 - */ - { - /* Program */ - 0x000055C0U, - /* Control */ - (0x00004006U | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 0 -> Period - * - Instruction = 2 - * - Next instruction = 3 - * - Conditional next instruction = 41 - * - Interrupt = 2 - * - Pin = na - */ - { - /* Program */ - 0x00007480U, - /* Control */ - 0x00052006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 1 -> Duty Cycle - * - Instruction = 3 - * - Next instruction = 4 - * - Conditional next instruction = 4 - * - Interrupt = 3 - * - Pin = 10 - */ - { - /* Program */ - 0x000095C0U, - /* Control */ - (0x00008006U | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 1 -> Period - * - Instruction = 4 - * - Next instruction = 5 - * - Conditional next instruction = 43 - * - Interrupt = 4 - * - Pin = na - */ - { - /* Program */ - 0x0000B480U, - /* Control */ - 0x00056006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 2 -> Duty Cycle - * - Instruction = 5 - * - Next instruction = 6 - * - Conditional next instruction = 6 - * - Interrupt = 5 - * - Pin = 12 - */ - { - /* Program */ - 0x0000D5C0U, - /* Control */ - (0x0000C006U | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 2 -> Period - * - Instruction = 6 - * - Next instruction = 7 - * - Conditional next instruction = 45 - * - Interrupt = 6 - * - Pin = na - */ - { - /* Program */ - 0x0000F480U, - /* Control */ - 0x0005A006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 3 -> Duty Cycle - * - Instruction = 7 - * - Next instruction = 8 - * - Conditional next instruction = 8 - * - Interrupt = 7 - * - Pin = 14 - */ - { - /* Program */ - 0x000115C0U, - /* Control */ - (0x00010006U | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 3 -> Period - * - Instruction = 8 - * - Next instruction = 9 - * - Conditional next instruction = 47 - * - Interrupt = 8 - * - Pin = na - */ - { - /* Program */ - 0x00013480U, - /* Control */ - 0x0005E006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 4 -> Duty Cycle - * - Instruction = 9 - * - Next instruction = 10 - * - Conditional next instruction = 10 - * - Interrupt = 9 - * - Pin = 16 - */ - { - /* Program */ - 0x000155C0U, - /* Control */ - (0x00014006U | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 4 -> Period - * - Instruction = 10 - * - Next instruction = 11 - * - Conditional next instruction = 49 - * - Interrupt = 10 - * - Pin = na - */ - { - /* Program */ - 0x00017480U, - /* Control */ - 0x00062006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 5 -> Duty Cycle - * - Instruction = 11 - * - Next instruction = 12 - * - Conditional next instruction = 12 - * - Interrupt = 11 - * - Pin = 17 - */ - { - /* Program */ - 0x000195C0U, - /* Control */ - (0x00018006U | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 5 -> Period - * - Instruction = 12 - * - Next instruction = 13 - * - Conditional next instruction = 51 - * - Interrupt = 12 - * - Pin = na - */ - { - /* Program */ - 0x0001B480U, - /* Control */ - 0x00066006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 6 -> Duty Cycle - * - Instruction = 13 - * - Next instruction = 14 - * - Conditional next instruction = 14 - * - Interrupt = 13 - * - Pin = 18 - */ - { - /* Program */ - 0x0001D5C0U, - /* Control */ - (0x0001C006U | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 6 -> Period - * - Instruction = 14 - * - Next instruction = 15 - * - Conditional next instruction = 53 - * - Interrupt = 14 - * - Pin = na - */ - { - /* Program */ - 0x0001F480U, - /* Control */ - 0x0006A006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PWCNT: PWM 7 -> Duty Cycle - * - Instruction = 15 - * - Next instruction = 16 - * - Conditional next instruction = 16 - * - Interrupt = 15 - * - Pin = 19 - */ - { - /* Program */ - 0x000215C0U, - /* Control */ - (0x00020006U | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* DJZ: PWM 7 -> Period - * - Instruction = 16 - * - Next instruction = 17 - * - Conditional next instruction = 55 - * - Interrupt = 16 - * - Pin = na - */ - { - /* Program */ - 0x00023480U, - /* Control */ - 0x0006E006U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 0 - * - Instruction = 17 - * - Next instruction = 18 - * - Conditional next instruction = 18 - * - Interrupt = 17 - * - Pin = 0 - */ - { - /* Program */ - 0x00025440U, - /* Control */ - (0x00024007U | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 1 - * - Instruction = 18 - * - Next instruction = 19 - * - Conditional next instruction = 19 - * - Interrupt = 18 - * - Pin = 2 - */ - { - /* Program */ - 0x00027440U, - /* Control */ - (0x00026007U | (uint32)((uint32)2U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 2 - * - Instruction = 19 - * - Next instruction = 20 - * - Conditional next instruction = 20 - * - Interrupt = 19 - * - Pin = 4 - */ - { - /* Program */ - 0x00029440U, - /* Control */ - (0x00028007U | (uint32)((uint32)4U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 3 - * - Instruction = 20 - * - Next instruction = 21 - * - Conditional next instruction = 21 - * - Interrupt = 20 - * - Pin = 6 - */ - { - /* Program */ - 0x0002B440U, - /* Control */ - (0x0002A007U | (uint32)((uint32)6U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 4 - * - Instruction = 21 - * - Next instruction = 22 - * - Conditional next instruction = 22 - * - Interrupt = 21 - * - Pin = 8 - */ - { - /* Program */ - 0x0002D440U, - /* Control */ - (0x0002C007U | (uint32)((uint32)8U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 5 - * - Instruction = 22 - * - Next instruction = 23 - * - Conditional next instruction = 23 - * - Interrupt = 22 - * - Pin = 10 - */ - { - /* Program */ - 0x0002F440U, - /* Control */ - (0x0002E007U | (uint32)((uint32)10U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 6 - * - Instruction = 23 - * - Next instruction = 24 - * - Conditional next instruction = 24 - * - Interrupt = 23 - * - Pin = 12 - */ - { - /* Program */ - 0x00031440U, - /* Control */ - (0x00030007U | (uint32)((uint32)12U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* ECNT: CCU Edge 7 - * - Instruction = 24 - * - Next instruction = 25 - * - Conditional next instruction = 25 - * - Interrupt = 24 - * - Pin = 14 - */ - { - /* Program */ - 0x00033440U, - /* Control */ - (0x00032007U | (uint32)((uint32)14U << 8U) | (uint32)((uint32)1U << 4U)), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 0 - * - Instruction = 25 - * - Next instruction = 26 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 0 - */ - { - /* Program */ - 0x00034E00U | (uint32)((uint32)0U << 6U) | (uint32)(0U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 0 - * - Instruction = 26 - * - Next instruction = 27 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 0 + 1 - */ - { - /* Program */ - 0x00036E80U | (uint32)((uint32)0U << 6U) | (uint32)((0U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 1 - * - Instruction = 27 - * - Next instruction = 28 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 2 - */ - { - /* Program */ - 0x00038E00U | (uint32)((uint32)0U << 6U) | (uint32)(2U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 1 - * - Instruction = 28 - * - Next instruction = 29 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 2 + 1 - */ - { - /* Program */ - 0x0003AE80U | (uint32)((uint32)0U << 6U) | (uint32)((2U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 2 - * - Instruction = 29 - * - Next instruction = 30 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 4 - */ - { - /* Program */ - 0x0003CE00U | (uint32)((uint32)0U << 6U) | (uint32)(4U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 2 - * - Instruction = 30 - * - Next instruction = 31 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 4 + 1 - */ - { - /* Program */ - 0x0003EE80U | (uint32)((uint32)0U << 6U) | (uint32)((4U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 3 - * - Instruction = 31 - * - Next instruction = 32 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 6 - */ - { - /* Program */ - 0x00040E00U | (uint32)((uint32)0U << 6U) | (uint32)(6U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 3 - * - Instruction = 32 - * - Next instruction = 33 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 6 + 1 - */ - { - /* Program */ - 0x00042E80U | (uint32)((uint32)0U << 6U) | (uint32)((6U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 4 - * - Instruction = 33 - * - Next instruction = 34 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 0 - */ - { - /* Program */ - 0x00044E00U | (uint32)((uint32)0U << 6U) | (uint32)(0U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 4 - * - Instruction = 34 - * - Next instruction = 35 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 0 + 1 - */ - { - /* Program */ - 0x00046E80U | (uint32)((uint32)0U << 6U) | (uint32)((0U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 5 - * - Instruction = 35 - * - Next instruction = 36 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 2 - */ - { - /* Program */ - 0x00048E00U | (uint32)((uint32)0U << 6U) | (uint32)(2U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 5 - * - Instruction = 36 - * - Next instruction = 37 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 2 + 1 - */ - { - /* Program */ - 0x0004AE80U | (uint32)((uint32)0U << 6U) | (uint32)((2U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 6 - * - Instruction = 37 - * - Next instruction = 38 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 4 - */ - { - /* Program */ - 0x0004CE00U | (uint32)((uint32)0U << 6U) | (uint32)(4U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 6 - * - Instruction = 38 - * - Next instruction = 39 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 4 + 1 - */ - { - /* Program */ - 0x0004EE80U | (uint32)((uint32)0U << 6U) | (uint32)((4U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Duty 7 - * - Instruction = 39 - * - Next instruction = 40 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 6 - */ - { - /* Program */ - 0x00050E00U | (uint32)((uint32)0U << 6U) | (uint32)(6U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* PCNT: Capture Period 7 - * - Instruction = 40 - * - Next instruction = 57 - * - Conditional next instruction = na - * - Interrupt = na - * - Pin = 6 + 1 - */ - { - /* Program */ - 0x00072E80U | (uint32)((uint32)0U << 6U) | (uint32)((6U) + 1U), - /* Control */ - 0x00000000U, - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 0 -> Duty Cycle Update - * - Instruction = 41 - * - Next instruction = 42 - * - Conditional next instruction = 2 - * - Interrupt = 1 - * - Pin = 8 - */ - { - /* Program */ - 0x00054201U, - /* Control */ - (0x00004007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)8U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 0 -> Period Update - * - Instruction = 42 - * - Next instruction = 3 - * - Conditional next instruction = 41 - * - Interrupt = 2 - * - Pin = na - */ - { - /* Program */ - 0x00006202U, - /* Control */ - (0x00052007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 1 -> Duty Cycle Update - * - Instruction = 43 - * - Next instruction = 44 - * - Conditional next instruction = 4 - * - Interrupt = 3 - * - Pin = 10 - */ - { - /* Program */ - 0x00058203U, - /* Control */ - (0x00008007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)10U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 1 -> Period Update - * - Instruction = 44 - * - Next instruction = 5 - * - Conditional next instruction = 43 - * - Interrupt = 4 - * - Pin = na - */ - { - /* Program */ - 0x0000A204U, - /* Control */ - (0x00056007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 2 -> Duty Cycle Update - * - Instruction = 45 - * - Next instruction = 46 - * - Conditional next instruction = 6 - * - Interrupt = 5 - * - Pin = 12 - */ - { - /* Program */ - 0x0005C205U, - /* Control */ - (0x0000C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)12U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 2 -> Period Update - * - Instruction = 46 - * - Next instruction = 7 - * - Conditional next instruction = 45 - * - Interrupt = 6 - * - Pin = na - */ - { - /* Program */ - 0x0000E206U, - /* Control */ - (0x0005A007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 3 -> Duty Cycle Update - * - Instruction = 47 - * - Next instruction = 48 - * - Conditional next instruction = 8 - * - Interrupt = 7 - * - Pin = 14 - */ - { - /* Program */ - 0x00060207U, - /* Control */ - (0x00010007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)14U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 3 -> Period Update - * - Instruction = 48 - * - Next instruction = 9 - * - Conditional next instruction = 47 - * - Interrupt = 8 - * - Pin = na - */ - { - /* Program */ - 0x00012208U, - /* Control */ - (0x0005E007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 4 -> Duty Cycle Update - * - Instruction = 49 - * - Next instruction = 50 - * - Conditional next instruction = 10 - * - Interrupt = 9 - * - Pin = 16 - */ - { - /* Program */ - 0x00064209U, - /* Control */ - (0x00014007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)16U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 4 -> Period Update - * - Instruction = 50 - * - Next instruction = 11 - * - Conditional next instruction = 49 - * - Interrupt = 10 - * - Pin = na - */ - { - /* Program */ - 0x0001620AU, - /* Control */ - (0x00062007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 5 -> Duty Cycle Update - * - Instruction = 51 - * - Next instruction = 52 - * - Conditional next instruction = 12 - * - Interrupt = 11 - * - Pin = 17 - */ - { - /* Program */ - 0x0006820BU, - /* Control */ - (0x00018007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)17U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 5 -> Period Update - * - Instruction = 52 - * - Next instruction = 13 - * - Conditional next instruction = 51 - * - Interrupt = 12 - * - Pin = na - */ - { - /* Program */ - 0x0001A20CU, - /* Control */ - (0x00066007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 6 -> Duty Cycle Update - * - Instruction = 53 - * - Next instruction = 54 - * - Conditional next instruction = 14 - * - Interrupt = 13 - * - Pin = 18 - */ - { - /* Program */ - 0x0006C20DU, - /* Control */ - (0x0001C007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)18U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 6 -> Period Update - * - Instruction = 54 - * - Next instruction = 15 - * - Conditional next instruction = 53 - * - Interrupt = 14 - * - Pin = na - */ - { - /* Program */ - 0x0001E20EU, - /* Control */ - (0x0006A007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 7 -> Duty Cycle Update - * - Instruction = 55 - * - Next instruction = 56 - * - Conditional next instruction = 16 - * - Interrupt = 15 - * - Pin = 19 - */ - { - /* Program */ - 0x0007020FU, - /* Control */ - (0x00020007U | (uint32)((uint32)0U << 22U) | (uint32)((uint32)19U << 8U) | (uint32)((uint32)3U << 3U)), - /* Data */ - 55296U, - /* Reserved */ - 0x00000000U - }, - /* MOV64: PWM 7 -> Period Update - * - Instruction = 56 - * - Next instruction = 17 - * - Conditional next instruction = 55 - * - Interrupt = 16 - * - Pin = na - */ - { - /* Program */ - 0x00022210U, - /* Control */ - (0x0006E007U), - /* Data */ - 109952U, - /* Reserved */ - 0x00000000U - }, - /* WCAP: Capture timestamp - * - Instruction = 57 - * - Next instruction = 0 - * - Conditional next instruction = 0 - * - Interrupt = na - * - Pin = na - * - Reg = T - */ - { - /* Program */ - 0x00001600U, - /* Control */ - (0x00000004U), - /* Data */ - 0x00000000U, - /* Reserved */ - 0x00000000U - }, -}; - - /** @fn void hetInit(void) * @brief Initializes the het Driver * @@ -2132,9 +1120,11 @@ | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U + | (uint32) 0x00400000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U + | (uint32) 0x00040000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U @@ -2148,12 +1138,10 @@ | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U + | (uint32) 0x00000010U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U | (uint32) 0x00000000U; /** - Set HET pins open drain enable */ @@ -2234,6 +1222,7 @@ | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U + | (uint32) 0x00400000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U @@ -2255,7 +1244,6 @@ | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U - | (uint32) 0x00000000U | (uint32) 0x00000000U; /** - Set HET pins high resolution share */ @@ -2378,13 +1366,13 @@ | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U + | (uint32) 0x00020000U + | (uint32) 0x00040000U + | (uint32) 0x00080000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U | (uint32) 0x00000000U; /** - Enable interrupts @@ -2430,13 +1418,13 @@ | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U + | (uint32) 0x00020000U + | (uint32) 0x00040000U + | (uint32) 0x00080000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U | (uint32) 0x00000000U; @@ -2452,302 +1440,6 @@ | (0x00020000U)); - /** @b initialize @b HET 2 */ - - /** - Set HET pins default output value */ - hetREG2->DOUT = (uint32)((uint32)0U << 18U) - | (uint32)((uint32)0U << 17U) - | (uint32)((uint32)0U << 16U) - | (uint32)((uint32)0U << 15U) - | (uint32)((uint32)0U << 14U) - | (uint32)((uint32)0U << 13U) - | (uint32)((uint32)0U << 12U) - | (uint32)((uint32)0U << 11U) - | (uint32)((uint32)0U << 10U) - | (uint32)((uint32)0U << 9U) - | (uint32)((uint32)0U << 8U) - | (uint32)((uint32)0U << 7U) - | (uint32)((uint32)0U << 6U) - | (uint32)((uint32)0U << 5U) - | (uint32)((uint32)0U << 4U) - | (uint32)((uint32)0U << 3U) - | (uint32)((uint32)0U << 2U) - | (uint32)((uint32)0U << 1U) - | (uint32)((uint32)0U << 0U); - - /** - Set HET pins direction */ - hetREG2->DIR = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - - /** - Set HET pins open drain enable */ - hetREG2->PDR = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - - /** - Set HET pins pullup/down enable */ - hetREG2->PULDIS = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - - /** - Set HET pins pullup/down select */ - hetREG2->PSL = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - - /** - Set HET pins high resolution share */ - hetREG2->HRSH = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000008U - | (uint32) 0x00000004U - | (uint32) 0x00000002U - | (uint32) 0x00000001U; - - /** - Set HET pins AND share */ - hetREG2->AND = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - - /** - Set HET pins XOR share */ - hetREG2->XOR = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - -/* USER CODE BEGIN (2) */ -/* USER CODE END */ - - /** - Setup prescaler values - * - Loop resolution prescaler - * - High resolution prescaler - */ - hetREG2->PFR = (uint32)((uint32) 7U << 8U) - | ((uint32) 0U); - - /** - Parity control register - * - Enable/Disable Parity check - */ - hetREG2->PCR = (uint32) 0x00000005U; - - /** - Fill HET RAM with opcodes and Data */ - -/* USER CODE BEGIN (3) */ -/* USER CODE END */ - - /** - Release from reset */ - /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ - /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ - /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ - /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */ - (void)memcpy((void *)hetRAM2, (const void *)het2PROGRAM, sizeof(het2PROGRAM)); - - /** - Setup prescaler values - * - Loop resolution prescaler - * - High resolution prescaler - */ - hetREG2->PFR = (uint32)((uint32) 7U << 8U) - | ((uint32) 0U); - - /** - Setup interrupt priority level - * - PWM 0 end of duty level - * - PWM 0 end of period level - * - PWM 1 end of duty level - * - PWM 1 end of period level - * - PWM 2 end of duty level - * - PWM 2 end of period level - * - PWM 3 end of duty level - * - PWM 3 end of period level - * - PWM 4 end of duty level - * - PWM 4 end of period level - * - PWM 5 end of duty level - * - PWM 5 end of period level - * - PWM 6 end of duty level - * - PWM 6 end of period level - * - PWM 7 end of duty level - * - PWM 7 end of period level - - * - CCU Edge Detection 0 level - * - CCU Edge Detection 1 level - * - CCU Edge Detection 2 level - * - CCU Edge Detection 3 level - * - CCU Edge Detection 4 level - * - CCU Edge Detection 5 level - * - CCU Edge Detection 6 level - * - CCU Edge Detection 7 level - */ - hetREG2->PRY = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - - /** - Enable interrupts - * - PWM 0 end of duty - * - PWM 0 end of period - * - PWM 1 end of duty - * - PWM 1 end of period - * - PWM 2 end of duty - * - PWM 2 end of period - * - PWM 3 end of duty - * - PWM 3 end of period - * - PWM 4 end of duty - * - PWM 4 end of period - * - PWM 5 end of duty - * - PWM 5 end of period - * - PWM 6 end of duty - * - PWM 6 end of period - * - PWM 7 end of duty - * - PWM 7 end of period - * - CCU Edge Detection 0 - * - CCU Edge Detection 1 - * - CCU Edge Detection 2 - * - CCU Edge Detection 3 - * - CCU Edge Detection 4 - * - CCU Edge Detection 5 - * - CCU Edge Detection 6 - * - CCU Edge Detection 7 - */ - hetREG2->INTENAC = 0xFFFFFFFFU; - hetREG2->INTENAS = (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U - | (uint32) 0x00000000U; - - - - /** - Setup control register - * - Enable output buffers - * - Ignore software breakpoints - * - Master or Slave Clock Mode - * - Enable HET - */ - hetREG2->GCR = ( 0x00000001U - | (uint32)((uint32)0U << 24U) - | (uint32)((uint32)1U << 16U) - | (0x00020000U)); - - /** @note This function has to be called before the driver can be used.\n - * This function has to be executed in privileged mode.\n - */ - - } /** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm) * @brief Start pwm signal @@ -2836,7 +1528,6 @@ } else { - pwmPolarity = s_het2pwmPolarity[pwm]; } if (pwmDuty == 0U) { @@ -2887,13 +1578,11 @@ if(hetRAM == hetRAM1) { - pwmPeriod = (signal.period * 1000.0F) / 1163.636F; + pwmPeriod = (signal.period * 1000.0F) / 1230.769F; pwmPolarity = s_het1pwmPolarity[pwm]; } else { - pwmPeriod = (signal.period * 1000.0F) / 1163.636F; - pwmPolarity = s_het2pwmPolarity[pwm]; } if (signal.duty == 0U) { @@ -2947,11 +1636,11 @@ if(hetRAM == hetRAM1) { - signal->period = ((float64)pwmPeriod * 1163.636F) / 1000.0F; + signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F; } else { - signal->period = ((float64)pwmPeriod * 1163.636F) / 1000.0F; + signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F; } } @@ -3145,11 +1834,11 @@ if( hetRAM == hetRAM1) { - signal->period = ((float64)pwmPeriod * 1163.636F) / 1000.0F; + signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F; } else { - signal->period = ((float64)pwmPeriod * 1163.636F) / 1000.0F; + signal->period = ((float64)pwmPeriod * 1230.769F) / 1000.0F; } } @@ -3243,62 +1932,5 @@ } } -/** @fn void het2GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) -* @brief Get the initial or current values of the HET2 configuration registers -* -* @param[in] *config_reg: pointer to the struct to which the initial or current -* value of the configuration registers need to be stored -* @param[in] type: whether initial or current value of the configuration registers need to be stored -* - InitialValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* - CurrentValue: initial value of the configuration registers will be stored -* in the struct pointed by config_reg -* -* This function will copy the initial or current value (depending on the parameter 'type') -* of the configuration registers to the struct pointed by config_reg -* -*/ -/* SourceId : HET_SourceId_017 */ -/* DesignId : HET_DesignId_016 */ -/* Requirements : HL_SR379 */ -void het2GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) -{ - if (type == InitialValue) - { - config_reg->CONFIG_GCR = HET2_GCR_CONFIGVALUE; - config_reg->CONFIG_PFR = HET2_PFR_CONFIGVALUE; - config_reg->CONFIG_INTENAS = HET2_INTENAS_CONFIGVALUE; - config_reg->CONFIG_INTENAC = HET2_INTENAC_CONFIGVALUE; - config_reg->CONFIG_PRY = HET2_PRY_CONFIGVALUE; - config_reg->CONFIG_AND = HET2_AND_CONFIGVALUE; - config_reg->CONFIG_HRSH = HET2_HRSH_CONFIGVALUE; - config_reg->CONFIG_XOR = HET2_XOR_CONFIGVALUE; - config_reg->CONFIG_DIR = HET2_DIR_CONFIGVALUE; - config_reg->CONFIG_PDR = HET2_PDR_CONFIGVALUE; - config_reg->CONFIG_PULDIS = HET2_PULDIS_CONFIGVALUE; - config_reg->CONFIG_PSL = HET2_PSL_CONFIGVALUE; - config_reg->CONFIG_PCR = HET2_PCR_CONFIGVALUE; - } - else - { - /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ - config_reg->CONFIG_GCR = hetREG2->GCR; - config_reg->CONFIG_PFR = hetREG2->PFR; - config_reg->CONFIG_INTENAS = hetREG2->INTENAS; - config_reg->CONFIG_INTENAC = hetREG2->INTENAC; - config_reg->CONFIG_PRY = hetREG2->PRY; - config_reg->CONFIG_AND = hetREG2->AND; - config_reg->CONFIG_HRSH = hetREG2->HRSH; - config_reg->CONFIG_XOR = hetREG2->XOR; - config_reg->CONFIG_DIR = hetREG2->DIR; - config_reg->CONFIG_PDR = hetREG2->PDR; - config_reg->CONFIG_PULDIS = hetREG2->PULDIS; - config_reg->CONFIG_PSL = hetREG2->PSL; - config_reg->CONFIG_PCR = hetREG2->PCR; - } -} - - - Index: firmware/source/i2c.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/i2c.c (.../i2c.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/i2c.c (.../i2c.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -89,7 +89,7 @@ | (uint32)((uint32)1U <<10U) /* Master/Slave mode */ | (uint32)((uint32)I2C_TRANSMITTER) /* Transmitter/receiver */ | (uint32)((uint32)I2C_7BIT_AMODE) /* xpanded address */ - | (uint32)((uint32)0U << 7U) /* repeat mode */ + | (uint32)((uint32)1U << 7U) /* repeat mode */ | (uint32)((uint32)0U << 6U) /* digital loop back */ | (uint32)((uint32)0U << 4U) /* start byte - master only */ | (uint32)((uint32)0U << 3U) /* free data format */ @@ -109,11 +109,11 @@ i2cREG1->IMR = 0x00U; /** - set prescale */ - i2cREG1->PSC = 13U; + i2cREG1->PSC = 12U; /** - set clock rate */ - i2cREG1->CKH = 34U; - i2cREG1->CKL = 34U; + i2cREG1->CKH = 35U; + i2cREG1->CKL = 35U; /** - set i2c pins functional mode */ i2cREG1->PFNC = (0U); @@ -127,8 +127,8 @@ | (uint32)(0U); /* scl pin */ /** - set i2c pins open drain enable */ - i2cREG1->PDR = (uint32)((uint32)0U << 1U) /* sda pin */ - | (uint32)(0U); /* scl pin */ + i2cREG1->PDR = (uint32)((uint32)1U << 1U) /* sda pin */ + | (uint32)(1U); /* scl pin */ /** - set i2c pins pullup/pulldown enable */ i2cREG1->PDIS = (uint32)((uint32)0U << 1U) /* sda pin */ @@ -202,7 +202,7 @@ uint32 prescale; uint32 d; uint32 ck; - float64 vclk = 110.000F * 1000000.0F; + float64 vclk = 104.000F * 1000000.0F; float64 divider= 0.0F; uint32 temp = 0U; Index: firmware/source/mibspi.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/mibspi.c (.../mibspi.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/mibspi.c (.../mibspi.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -94,7 +94,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 1 */ @@ -105,7 +105,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 2 */ @@ -116,7 +116,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 3 */ @@ -127,7 +127,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Default Chip Select */ @@ -477,7 +477,7 @@ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ - | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ @@ -537,7 +537,7 @@ | (uint32)((uint32)0U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ - | (uint32)((uint32)1U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 25U); /* SOMI[1] */ @@ -570,15 +570,15 @@ | (uint32)((uint32)0U << 0U); /* C2EDELAY */ /** - Data Format 0 */ - mibspiREG3->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ + mibspiREG3->FMT0 = (uint32)((uint32)20U << 24U) /* wdelay */ | (uint32)((uint32)0U << 23U) /* parity Polarity */ | (uint32)((uint32)0U << 22U) /* parity enable */ | (uint32)((uint32)0U << 21U) /* wait on enable */ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ - | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ - | (uint32)((uint32)16U << 0U); /* data word length */ + | (uint32)((uint32)1U << 16U) /* clock phase */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ + | (uint32)((uint32)8U << 0U); /* data word length */ /** - Data Format 1 */ mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ @@ -588,7 +588,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 2 */ @@ -599,7 +599,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 3 */ @@ -610,7 +610,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Default Chip Select */ @@ -636,67 +636,67 @@ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)8U << 8U); /* start buffer */ + | (uint32)((uint32)11U << 8U); /* start buffer */ mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */ | (uint32)((uint32)0U << 29U) /* pcurrent reset */ | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ - | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ - mibspiREG3->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U; + mibspiREG3->TGCTRL[8U] = (uint32)(11U+0U+0U+0U+0U+0U+0U+0U) << 8U; - mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); /** - initialize buffer ram */ { i = 0U; -#if (8U > 0U) +#if (11U > 0U) { -#if (8U > 1U) +#if (11U > 1U) - while (i < (8U-1U)) + while (i < (11U-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ - | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)1U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ i++; } #endif @@ -705,7 +705,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ i++; @@ -717,15 +717,15 @@ #if (0U > 1U) - while (i < ((8U+0U)-1U)) + while (i < ((11U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -735,7 +735,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -746,15 +746,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U)-1U)) + while (i < ((11U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -764,7 +764,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -775,15 +775,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -793,7 +793,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -804,15 +804,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -822,7 +822,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -833,15 +833,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -851,7 +851,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -862,15 +862,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -880,7 +880,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -891,15 +891,15 @@ #if (0U > 1U) - while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U)) + while (i < ((11U+0U+0U+0U+0U+0U+0U+0U)-1U)) { mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ | (uint16)((uint16)0U << 12U) /* chip select hold */ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 11U) /* lock transmission */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } @@ -909,7 +909,7 @@ | (uint16)((uint16)0U << 10U) /* enable WDELAY */ | (uint16)((uint16)0U << 8U) /* data format */ /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ - | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ i++; } #endif @@ -932,12 +932,12 @@ mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U) | (uint32)((uint32)0U << 9U) /* TXINT */ | (uint32)((uint32)0U << 8U) /* RXINT */ - | (uint32)((uint32)0U << 6U) /* OVRNINT */ - | (uint32)((uint32)0U << 4U) /* BITERR */ - | (uint32)((uint32)0U << 3U) /* DESYNC */ - | (uint32)((uint32)0U << 2U) /* PARERR */ - | (uint32)((uint32)0U << 1U) /* TIMEOUT */ - | (uint32)((uint32)0U << 0U); /* DLENERR */ + | (uint32)((uint32)1U << 6U) /* OVRNINT */ + | (uint32)((uint32)1U << 4U) /* BITERR */ + | (uint32)((uint32)1U << 3U) /* DESYNC */ + | (uint32)((uint32)1U << 2U) /* PARERR */ + | (uint32)((uint32)1U << 1U) /* TIMEOUT */ + | (uint32)((uint32)1U << 0U); /* DLENERR */ /** @b initialize @b MIBSPI3 @b Port */ @@ -1005,12 +1005,12 @@ /* MIBSPI3 set all pins to functional */ - mibspiREG3->PC0 = (uint32)((uint32)1U << 0U) /* SCS[0] */ - | (uint32)((uint32)0U << 1U) /* SCS[1] */ + mibspiREG3->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ | (uint32)((uint32)0U << 4U) /* SCS[4] */ - | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO */ @@ -1051,7 +1051,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 1 */ @@ -1062,7 +1062,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 2 */ @@ -1073,7 +1073,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Data Format 3 */ @@ -1084,7 +1084,7 @@ | (uint32)((uint32)0U << 20U) /* shift direction */ | (uint32)((uint32)0U << 17U) /* clock polarity */ | (uint32)((uint32)0U << 16U) /* clock phase */ - | (uint32)((uint32)109U << 8U) /* baudrate prescale */ + | (uint32)((uint32)103U << 8U) /* baudrate prescale */ | (uint32)((uint32)16U << 0U); /* data word length */ /** - Default Chip Select */ @@ -1436,10 +1436,10 @@ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ - | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ - | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)1U << 11U) /* SOMI[0] */ | (uint32)((uint32)0U << 17U) /* SIMO[1] */ | (uint32)((uint32)0U << 18U) /* SIMO[2] */ | (uint32)((uint32)0U << 19U) /* SIMO[3] */ @@ -1468,7 +1468,7 @@ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ - | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ @@ -1500,10 +1500,10 @@ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ - | (uint32)((uint32)1U << 8U) /* ENA */ - | (uint32)((uint32)1U << 9U) /* CLK */ - | (uint32)((uint32)1U << 10U) /* SIMO[0] */ - | (uint32)((uint32)1U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ | (uint32)((uint32)1U << 17U) /* SIMO[1] */ | (uint32)((uint32)1U << 18U) /* SIMO[2] */ | (uint32)((uint32)1U << 19U) /* SIMO[3] */ Index: firmware/source/notification.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/notification.c (.../notification.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/notification.c (.../notification.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -53,20 +53,13 @@ #include "adc.h" #include "can.h" #include "gio.h" -#include "lin.h" #include "mibspi.h" #include "sci.h" -#include "spi.h" #include "het.h" #include "rti.h" -#include "dcc.h" #include "i2c.h" -#include "crc.h" #include "etpwm.h" -#include "eqep.h" -#include "ecap.h" #include "sys_dma.h" -#include "emac.h" /* USER CODE BEGIN (0) */ /* USER CODE END */ @@ -156,16 +149,6 @@ /* USER CODE BEGIN (16) */ /* USER CODE END */ -#pragma WEAK(dccNotification) -void dccNotification(dccBASE_t *dcc,uint32 flags) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (17) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (18) */ -/* USER CODE END */ #pragma WEAK(gioNotification) void gioNotification(gioPORT_t *port, uint32 bit) { @@ -186,16 +169,6 @@ /* USER CODE BEGIN (22) */ /* USER CODE END */ -#pragma WEAK(linNotification) -void linNotification(linBASE_t *lin, uint32 flags) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (23) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (24) */ -/* USER CODE END */ #pragma WEAK(mibspiNotification) void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) { @@ -226,27 +199,7 @@ /* USER CODE BEGIN (30) */ /* USER CODE END */ -#pragma WEAK(spiNotification) -void spiNotification(spiBASE_t *spi, uint32 flags) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (31) */ -/* USER CODE END */ -} -/* USER CODE BEGIN (32) */ -/* USER CODE END */ -#pragma WEAK(spiEndNotification) -void spiEndNotification(spiBASE_t *spi) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (33) */ -/* USER CODE END */ -} - -/* USER CODE BEGIN (34) */ -/* USER CODE END */ - #pragma WEAK(pwmNotification) void pwmNotification(hetBASE_t * hetREG,uint32 pwm, uint32 notification) { @@ -278,15 +231,6 @@ /* USER CODE BEGIN (40) */ /* USER CODE END */ -#pragma WEAK(crcNotification) -void crcNotification(crcBASE_t *crc, uint32 flags) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (41) */ -/* USER CODE END */ -} -/* USER CODE BEGIN (42) */ -/* USER CODE END */ /* USER CODE BEGIN (43) */ /* USER CODE END */ @@ -312,28 +256,10 @@ /* USER CODE BEGIN (47) */ /* USER CODE END */ -#pragma WEAK(eqepNotification) -void eqepNotification(eqepBASE_t *eqep,uint16 flags) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (48) */ -/* USER CODE END */ -} -/* USER CODE BEGIN (49) */ -/* USER CODE END */ /* USER CODE BEGIN (50) */ /* USER CODE END */ -#pragma WEAK(ecapNotification) -void ecapNotification(ecapBASE_t *ecap,uint16 flags) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (51) */ -/* USER CODE END */ -} -/* USER CODE BEGIN (52) */ -/* USER CODE END */ /* USER CODE BEGIN (53) */ /* USER CODE END */ @@ -350,23 +276,9 @@ /* USER CODE BEGIN (56) */ /* USER CODE END */ -#pragma WEAK(emacTxNotification) -void emacTxNotification(hdkif_t *hdkif) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (57) */ -/* USER CODE END */ -} /* USER CODE BEGIN (58) */ /* USER CODE END */ -#pragma WEAK(emacRxNotification) -void emacRxNotification(hdkif_t *hdkif) -{ -/* enter user code between the USER CODE BEGIN and USER CODE END. */ -/* USER CODE BEGIN (59) */ -/* USER CODE END */ -} /* USER CODE BEGIN (60) */ /* USER CODE END */ Index: firmware/source/pinmux.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/pinmux.c (.../pinmux.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/pinmux.c (.../pinmux.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -168,25 +168,25 @@ /* USER CODE BEGIN (2) */ /* USER CODE END */ - pinMuxReg->PINMMR0 = PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_MIBSPI3NCS_3 | PINMUX_PIN_4_MIBSPI3NCS_2; + pinMuxReg->PINMMR0 = PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_I2C_SCL | PINMUX_PIN_4_I2C_SDA; - pinMuxReg->PINMMR1 = PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_HET1_11; + pinMuxReg->PINMMR1 = PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_MIBSPI3NCS_4; - pinMuxReg->PINMMR2 = PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5; + pinMuxReg->PINMMR2 = PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_ETPWM1A; - pinMuxReg->PINMMR3 = PINMUX_PIN_15_HET1_22 | PINMUX_PIN_16_GIOA_6; + pinMuxReg->PINMMR3 = PINMUX_PIN_15_W2FC_SE0O | PINMUX_PIN_16_GIOA_6; - pinMuxReg->PINMMR4 = PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03; + pinMuxReg->PINMMR4 = PINMUX_PIN_22_ETPWM2A | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03; - pinMuxReg->PINMMR5 = PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05; + pinMuxReg->PINMMR5 = PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_HET1_05; - pinMuxReg->PINMMR6 = PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09; + pinMuxReg->PINMMR6 = PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A; - pinMuxReg->PINMMR7 = PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_HET1_06; + pinMuxReg->PINMMR7 = PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_SCIRX; - pinMuxReg->PINMMR8 = PINMUX_PIN_39_HET1_13 | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_HET1_15; + pinMuxReg->PINMMR8 = PINMUX_PIN_39_SCITX | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_HET1_15; - pinMuxReg->PINMMR9 = ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_MIBSPI3NENA | PINMUX_PIN_55_MIBSPI3NCS_0; + pinMuxReg->PINMMR9 = ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_MIBSPI3NCS_5 | PINMUX_PIN_55_MIBSPI3NCS_0; pinMuxReg->PINMMR10 = PINMUX_PIN_86_AD1EVT; @@ -224,7 +224,7 @@ /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ pinMuxReg->PINMMR26 = ((~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U); - pinMuxReg->PINMMR27 = PINMUX_PIN_32_MIBSPI5NCS_0; + pinMuxReg->PINMMR27 = PINMUX_PIN_32_ETPWM4A; pinMuxReg->PINMMR29 = 0x01010101U; Fisheye: Tag abb9687e52d9db5df1abe7626ba04a6d431ba823 refers to a dead (removed) revision in file `firmware/source/pom.c'. Fisheye: No comparison available. Pass `N' to diff? Index: firmware/source/rti.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/rti.c (.../rti.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/rti.c (.../rti.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -87,7 +87,7 @@ rtiREG1->CAPCTRL = 0U | 0U; /** - Setup input source compare 0-3 */ - rtiREG1->COMPCTRL = 0x00001000U | 0x00000100U | 0x00000000U | 0x00000000U; + rtiREG1->COMPCTRL = 0x00000000U | 0x00000100U | 0x00000000U | 0x00000000U; /** - Reset up counter 0 */ rtiREG1->CNT[0U].UCx = 0x00000000U; @@ -99,7 +99,7 @@ * - 0x00000000: Divide by 2^32 * - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1) */ - rtiREG1->CNT[0U].CPUCx = 10U; + rtiREG1->CNT[0U].CPUCx = 9U; /** - Reset up counter 1 */ rtiREG1->CNT[1U].UCx = 0x00000000U; @@ -111,31 +111,31 @@ * - 0x00000000: Divide by 2^32 * - 0x00000001-0xFFFFFFFF: Divide by (CPUC1 + 1) */ - rtiREG1->CNT[1U].CPUCx = 10U; + rtiREG1->CNT[1U].CPUCx = 9U; /** - Setup compare 0 value. This value is compared with selected free running counter. */ - rtiREG1->CMP[0U].COMPx = 10000U; + rtiREG1->CMP[0U].COMPx = 10400U; /** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */ - rtiREG1->CMP[0U].UDCPx = 10000U; + rtiREG1->CMP[0U].UDCPx = 10400U; /** - Setup compare 1 value. This value is compared with selected free running counter. */ - rtiREG1->CMP[1U].COMPx = 50000U; + rtiREG1->CMP[1U].COMPx = 104000U; /** - Setup update compare 1 value. This value is added to the compare 1 value on each compare match. */ - rtiREG1->CMP[1U].UDCPx = 50000U; + rtiREG1->CMP[1U].UDCPx = 104000U; /** - Setup compare 2 value. This value is compared with selected free running counter. */ - rtiREG1->CMP[2U].COMPx = 80000U; + rtiREG1->CMP[2U].COMPx = 83200U; /** - Setup update compare 2 value. This value is added to the compare 2 value on each compare match. */ - rtiREG1->CMP[2U].UDCPx = 80000U; + rtiREG1->CMP[2U].UDCPx = 83200U; /** - Setup compare 3 value. This value is compared with selected free running counter. */ - rtiREG1->CMP[3U].COMPx = 100000U; + rtiREG1->CMP[3U].COMPx = 520000U; /** - Setup update compare 3 value. This value is added to the compare 3 value on each compare match. */ - rtiREG1->CMP[3U].UDCPx = 100000U; + rtiREG1->CMP[3U].UDCPx = 520000U; /** - Clear all pending interrupts */ rtiREG1->INTFLAG = 0x0007000FU; @@ -844,9 +844,85 @@ } } +/* USER CODE BEGIN (73) */ +/* USER CODE END */ +/** @fn void rtiCompare0Interrupt(void) +* @brief RTI1 Compare 0 Interrupt Handler +* +* RTI1 Compare 0 interrupt handler +* +*/ +#pragma CODE_STATE(rtiCompare0Interrupt, 32) +#pragma INTERRUPT(rtiCompare0Interrupt, FIQ) +/* SourceId : RTI_SourceId_022 */ +/* DesignId : RTI_DesignId_022 */ +/* Requirements : HL_SR95 */ +void rtiCompare0Interrupt(void) +{ +/* USER CODE BEGIN (74) */ +/* USER CODE END */ + rtiREG1->INTFLAG = 1U; + rtiNotification(rtiNOTIFICATION_COMPARE0); +/* USER CODE BEGIN (75) */ +/* USER CODE END */ +} +/* USER CODE BEGIN (76) */ +/* USER CODE END */ +/** @fn void rtiCompare1Interrupt(void) +* @brief RTI1 Compare 1 Interrupt Handler +* +* RTI1 Compare 1 interrupt handler +* +*/ + +/* SourceId : RTI_SourceId_023 */ +/* DesignId : RTI_DesignId_022 */ +/* Requirements : HL_SR95 */ +void rtiCompare1Interrupt(void) +{ +/* USER CODE BEGIN (77) */ +/* USER CODE END */ + + rtiREG1->INTFLAG = 2U; + rtiNotification(rtiNOTIFICATION_COMPARE1); + +/* USER CODE BEGIN (78) */ +/* USER CODE END */ +} + + + +/* USER CODE BEGIN (82) */ +/* USER CODE END */ + +/** @fn void rtiCompare3Interrupt(void) +* @brief RTI1 Compare 3 Interrupt Handler +* +* RTI1 Compare 3 interrupt handler +* +*/ + +/* SourceId : RTI_SourceId_025 */ +/* DesignId : RTI_DesignId_022 */ +/* Requirements : HL_SR95 */ +void rtiCompare3Interrupt(void) +{ +/* USER CODE BEGIN (83) */ +/* USER CODE END */ + + rtiREG1->INTFLAG = 8U; + rtiNotification(rtiNOTIFICATION_COMPARE3); + +/* USER CODE BEGIN (84) */ +/* USER CODE END */ +} + + + + Index: firmware/source/sci.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sci.c (.../sci.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sci.c (.../sci.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -90,13 +90,13 @@ sciREG->GCR1 = (uint32)((uint32)1U << 25U) /* enable transmit */ | (uint32)((uint32)1U << 24U) /* enable receive */ | (uint32)((uint32)1U << 5U) /* internal clock (device has no clock pin) */ - | (uint32)((uint32)(2U-1U) << 4U) /* number of stop bits */ + | (uint32)((uint32)(1U-1U) << 4U) /* number of stop bits */ | (uint32)((uint32)0U << 3U) /* even parity, otherwise odd */ | (uint32)((uint32)0U << 2U) /* enable parity */ | (uint32)((uint32)1U << 1U); /* asynchronous timing mode */ /** - set baudrate */ - sciREG->BRS = 715U; /* baudrate */ + sciREG->BRS = 55U; /* baudrate */ /** - transmission length */ sciREG->FORMAT = 8U - 1U; /* length */ @@ -110,11 +110,11 @@ | (uint32)((uint32)0U << 1U); /* rx pin */ /** - set SCI pins output direction */ - sciREG->PIO1 = (uint32)((uint32)0U << 2U) /* tx pin */ + sciREG->PIO1 = (uint32)((uint32)1U << 2U) /* tx pin */ | (uint32)((uint32)0U << 1U); /* rx pin */ /** - set SCI pins open drain enable */ - sciREG->PIO6 = (uint32)((uint32)0U << 2U) /* tx pin */ + sciREG->PIO6 = (uint32)((uint32)1U << 2U) /* tx pin */ | (uint32)((uint32)0U << 1U); /* rx pin */ /** - set SCI pins pullup/pulldown enable */ @@ -135,8 +135,8 @@ | (uint32)((uint32)0U << 0U); /* Break detect */ /** - set interrupt enable */ - sciREG->SETINT = (uint32)((uint32)0U << 26U) /* Framing error */ - | (uint32)((uint32)0U << 25U) /* Overrun error */ + sciREG->SETINT = (uint32)((uint32)1U << 26U) /* Framing error */ + | (uint32)((uint32)1U << 25U) /* Overrun error */ | (uint32)((uint32)0U << 24U) /* Parity error */ | (uint32)((uint32)0U << 9U) /* Receive */ | (uint32)((uint32)0U << 1U) /* Wakeup */ @@ -151,6 +151,87 @@ sciREG->GCR1 |= 0x80U; + + /** @b initialize @b SCILIN */ + + /** - bring SCI out of reset */ + scilinREG->GCR0 = 0U; + scilinREG->GCR0 = 1U; + + /** - Disable all interrupts */ + scilinREG->CLEARINT = 0xFFFFFFFFU; + scilinREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + scilinREG->GCR1 = (uint32)((uint32)1U << 25U) /* enable transmit */ + | (uint32)((uint32)1U << 24U) /* enable receive */ + | (uint32)((uint32)1U << 5U) /* internal clock (device has no clock pin) */ + | (uint32)((uint32)(1U-1U) << 4U) /* number of stop bits */ + | (uint32)((uint32)0U << 3U) /* even parity, otherwise odd */ + | (uint32)((uint32)0U << 2U) /* enable parity */ + | (uint32)((uint32)1U << 1U); /* asynchronous timing mode */ + + /** - set baudrate */ + scilinREG->BRS = 6U; /* baudrate */ + + /** - transmission length */ + scilinREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + scilinREG->PIO0 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)1U << 1U); /* rx pin */ + + + /** - set SCI pins default output value */ + scilinREG->PIO3 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins output direction */ + scilinREG->PIO1 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins open drain enable */ + scilinREG->PIO6 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins pullup/pulldown enable */ + scilinREG->PIO7 = (uint32)((uint32)0U << 2U) /* tx pin */ + | (uint32)((uint32)0U << 1U); /* rx pin */ + + + /** - set SCI pins pullup/pulldown select */ + scilinREG->PIO8 = (uint32)((uint32)1U << 2U) /* tx pin */ + | (uint32)((uint32)1U << 1U); /* rx pin */ + + + /** - set interrupt level */ + scilinREG->SETINTLVL = (uint32)((uint32)0U << 26U) /* Framing error */ + | (uint32)((uint32)0U << 25U) /* Overrun error */ + | (uint32)((uint32)0U << 24U) /* Parity error */ + | (uint32)((uint32)0U << 9U) /* Receive */ + | (uint32)((uint32)0U << 8U) /* Transmit */ + | (uint32)((uint32)0U << 1U) /* Wakeup */ + | (uint32)((uint32)0U); /* Break detect */ + + /** - set interrupt enable */ + scilinREG->SETINT = (uint32)((uint32)0U << 26U) /* Framing error */ + | (uint32)((uint32)0U << 25U) /* Overrun error */ + | (uint32)((uint32)0U << 24U) /* Parity error */ + | (uint32)((uint32)0U << 9U) /* Receive */ + | (uint32)((uint32)0U << 1U) /* Wakeup */ + | (uint32)((uint32)0U); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[1U].mode = (uint32)0U << 8U; + g_sciTransfer_t[1U].tx_length = 0U; + g_sciTransfer_t[1U].rx_length = 0U; + + /** - Finaly start SCILIN */ + scilinREG->GCR1 |= 0x80U; + /* USER CODE BEGIN (3) */ /* USER CODE END */ } @@ -192,7 +273,7 @@ /* Requirements : HL_SR232 */ void sciSetBaudrate(sciBASE_t *sci, uint32 baud) { - float64 vclk = 110.000 * 1000000.0; + float64 vclk = 104.000 * 1000000.0; uint32 f = ((sci->GCR1 & 2U) == 2U) ? 16U : 1U; uint32 temp; float64 temp2; @@ -661,8 +742,212 @@ } } +/** @fn void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the SCILIN ( SCI2) configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : SCI_SourceId_017 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : HL_SR247 */ +void scilinGetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR0 = SCILIN_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCILIN_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCILIN_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCILIN_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCILIN_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCILIN_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCILIN_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCILIN_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCILIN_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCILIN_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCILIN_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR0 = scilinREG->GCR0; + config_reg->CONFIG_GCR1 = scilinREG->GCR1; + config_reg->CONFIG_SETINT = scilinREG->SETINT; + config_reg->CONFIG_SETINTLVL = scilinREG->SETINTLVL; + config_reg->CONFIG_FORMAT = scilinREG->FORMAT; + config_reg->CONFIG_BRS = scilinREG->BRS; + config_reg->CONFIG_PIO0 = scilinREG->PIO0; + config_reg->CONFIG_PIO1 = scilinREG->PIO1; + config_reg->CONFIG_PIO6 = scilinREG->PIO6; + config_reg->CONFIG_PIO7 = scilinREG->PIO7; + config_reg->CONFIG_PIO8 = scilinREG->PIO8; + } +} +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +/** @fn void sciHighLevelInterrupt(void) +* @brief Level 0 Interrupt for SCI +*/ + +/* SourceId : SCI_SourceId_018 */ +/* DesignId : SCI_DesignId_017 */ +/* Requirements : HL_SR245, HL_SR246 */ +void sciHighLevelInterrupt(void) +{ + uint32 vec = sciREG->INTVECT0; + uint8 byte; +/* USER CODE BEGIN (28) */ +/* USER CODE END */ + + switch (vec) + { + case 1U: + sciNotification(sciREG, (uint32)SCI_WAKE_INT); + break; + case 3U: + sciNotification(sciREG, (uint32)SCI_PE_INT); + break; + case 6U: + sciNotification(sciREG, (uint32)SCI_FE_INT); + break; + case 7U: + sciNotification(sciREG, (uint32)SCI_BREAK_INT); + break; + case 9U: + sciNotification(sciREG, (uint32)SCI_OE_INT); + break; + + case 11U: + /* receive */ + byte = (uint8)(sciREG->RD & 0x000000FFU); + + if (g_sciTransfer_t[0U].rx_length > 0U) + { + *g_sciTransfer_t[0U].rx_data = byte; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[0U].rx_data++; + g_sciTransfer_t[0U].rx_length--; + if (g_sciTransfer_t[0U].rx_length == 0U) + { + sciNotification(sciREG, (uint32)SCI_RX_INT); + } + } + break; + + case 12U: + /* transmit */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in Transmit/Receive polling and Interrupt mode" */ + --g_sciTransfer_t[0U].tx_length; + if (g_sciTransfer_t[0U].tx_length > 0U) + { + uint8 txdata = *g_sciTransfer_t[0U].tx_data; + sciREG->TD = (uint32)(txdata); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[0U].tx_data++; + } + else + { + sciREG->CLEARINT = (uint32)SCI_TX_INT; + sciNotification(sciREG, (uint32)SCI_TX_INT); + } + break; + + default: + /* phantom interrupt, clear flags and return */ + sciREG->FLR = ~sciREG->SETINTLVL & 0x07000303U; + break; + } +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +} + + +/** @fn void linHighLevelInterrupt(void) +* @brief Level 0 Interrupt for SCILIN +*/ + +/* SourceId : SCI_SourceId_021 */ +/* DesignId : SCI_DesignId_017 */ +/* Requirements : HL_SR245, HL_SR246 */ +void linHighLevelInterrupt(void) +{ + uint32 vec = scilinREG->INTVECT0; + uint8 byte; +/* USER CODE BEGIN (35) */ +/* USER CODE END */ + + switch (vec) + { + case 1U: + sciNotification(scilinREG, (uint32)SCI_WAKE_INT); + break; + case 3U: + sciNotification(scilinREG, (uint32)SCI_PE_INT); + break; + case 6U: + sciNotification(scilinREG, (uint32)SCI_FE_INT); + break; + case 7U: + sciNotification(scilinREG, (uint32)SCI_BREAK_INT); + break; + case 9U: + sciNotification(scilinREG, (uint32)SCI_OE_INT); + break; + + case 11U: + /* receive */ + byte = (uint8)(scilinREG->RD & 0x000000FFU); + + if (g_sciTransfer_t[1U].rx_length > 0U) + { + *g_sciTransfer_t[1U].rx_data = byte; + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[1U].rx_data++; + g_sciTransfer_t[1U].rx_length--; + if (g_sciTransfer_t[1U].rx_length == 0U) + { + sciNotification(scilinREG, (uint32)SCI_RX_INT); + } + } + break; + + case 12U: + /* transmit */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in Transmit/Receive polling and Interrupt mode" */ + --g_sciTransfer_t[1U].tx_length; + if (g_sciTransfer_t[1U].tx_length > 0U) + { + uint8 txdata = *g_sciTransfer_t[1U].tx_data; + scilinREG->TD = (uint32)(txdata); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[1U].tx_data++; + } + else + { + scilinREG->CLEARINT = (uint32)SCI_TX_INT; + sciNotification(scilinREG, (uint32)SCI_TX_INT); + } + break; + + default: + /* phantom interrupt, clear flags and return */ + scilinREG->FLR = ~scilinREG->SETINTLVL & 0x07000303U; + break; + } +/* USER CODE BEGIN (36) */ +/* USER CODE END */ +} /* USER CODE BEGIN (37) */ /* USER CODE END */ Fisheye: Tag abb9687e52d9db5df1abe7626ba04a6d431ba823 refers to a dead (removed) revision in file `firmware/source/spi.c'. Fisheye: No comparison available. Pass `N' to diff? Index: firmware/source/sys_core.asm =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_core.asm (.../sys_core.asm) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_core.asm (.../sys_core.asm) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -161,11 +161,11 @@ bx lr userSp .word 0x08000000+0x00001000 -svcSp .word 0x08000000+0x00001000+0x00000100 -fiqSp .word 0x08000000+0x00001000+0x00000100+0x00000100 -irqSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100 -abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100 -undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100 +svcSp .word 0x08000000+0x00001000+0x00001000 +fiqSp .word 0x08000000+0x00001000+0x00001000+0x00001000 +irqSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000 +abortSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000+0x00000400 +undefSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000+0x00000400+0x00000400 .endasmfunc Index: firmware/source/sys_dma.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_dma.c (.../sys_dma.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_dma.c (.../sys_dma.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -447,3 +447,30 @@ + +/** @fn void dmaBTCAInterrupt(void) +* @brief DMA Interrupt Handler +* +* Frame transfer complete Interrupt handler for DMA channel routed to Group A +* +*/ + +/* SourceId : DMA_SourceId_019 */ +/* DesignId : DMA_DesignId_016 */ +/* Requirements: HL_SR181, HL_SR182 */ +void dmaBTCAInterrupt(void) +{ + uint32 offset = dmaREG->BTCAOFFSET; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + + if (offset != 0U) + { + dmaGroupANotification(BTC, offset - 1U); + } + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +} Index: firmware/source/sys_intvecs.asm =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_intvecs.asm (.../sys_intvecs.asm) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_intvecs.asm (.../sys_intvecs.asm) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -43,6 +43,7 @@ .ref _c_int00 .ref _dabort + .ref _irqDispatch .ref phantomInterrupt .def resetEntry @@ -59,8 +60,8 @@ b prefetchEntry b _dabort b phantomInterrupt + b _irqDispatch ldr pc,[pc,#-0x1b0] - ldr pc,[pc,#-0x1b0] ;------------------------------------------------------------------------------- Index: firmware/source/sys_link.cmd =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_link.cmd (.../sys_link.cmd) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -56,8 +56,8 @@ { VECTORS (X) : origin=0x00000000 length=0x00000020 FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 - STACKS (RW) : origin=0x08000000 length=0x00001500 - RAM (RW) : origin=0x08001500 length=0x0002EB00 + STACKS (RW) : origin=0x08000000 length=0x00005800 + RAM (RW) : origin=0x08005800 length=0x0002a800 /* USER CODE BEGIN (2) */ /* USER CODE END */ Index: firmware/source/sys_main.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_main.c (.../sys_main.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_main.c (.../sys_main.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -43,13 +43,27 @@ /* USER CODE BEGIN (0) */ + +static void initProcessor( void ); +static void initSoftware( void ); +static void initTasks( void ); /* USER CODE END */ /* Include Files */ #include "sys_common.h" /* USER CODE BEGIN (1) */ +#include "system.h" +#include "sys_dma.h" +#include "can.h" +#include "sci.h" +#include "rti.h" + +#include "BLCommon.h" +#include "Interrupts.h" +#include "TaskBG.h" +#include "Timers.h" /* USER CODE END */ /** @fn void main(void) @@ -63,17 +77,44 @@ /* USER CODE BEGIN (2) */ /* USER CODE END */ -uint8 emacAddress[6U] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; -uint32 emacPhyAddress = 0U; - int main(void) { /* USER CODE BEGIN (3) */ + initProcessor(); + initSoftware(); + initTasks(); + + taskBackground(); /* USER CODE END */ return 0; } /* USER CODE BEGIN (4) */ +static void initProcessor( void ) +{ + canInit(); + sciInit(); + dmaEnable(); +} + +static void initSoftware( void ) +{ + initInterrupts(); + initTimers(); +} + +static void initTasks( void ) +{ + // Initialize RTI to setup the 3 tasks + rtiInit(); + rtiEnableNotification( rtiNOTIFICATION_COMPARE0 | rtiNOTIFICATION_COMPARE1 | rtiNOTIFICATION_COMPARE3 ); + rtiStartCounter( rtiCOUNTER_BLOCK0 ); + // The timer task requires FIQ enabled + _enable_FIQ(); + // The general and priority tasks require IRQ enabled + _enable_IRQ(); +} + /* USER CODE END */ Index: firmware/source/sys_mpu.asm =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_mpu.asm (.../sys_mpu.asm) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_mpu.asm (.../sys_mpu.asm) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -164,10 +164,10 @@ mcr p15, #0, r0, c6, c2, #0 ldr r0, r11Base mcr p15, #0, r0, c6, c1, #0 - mov r0, #0x0008 + mov r0, #0x000C orr r0, r0, #0x1100 mcr p15, #0, r0, c6, c1, #4 - movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0A << 1) + (0)) + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x0F << 1) + (0)) mcr p15, #0, r0, c6, c1, #2 ; Setup region 12 mov r0, #11 @@ -203,7 +203,7 @@ r8Base .word 0xFC000000 r9Base .word 0xFE000000 r10Base .word 0xFF000000 -r11Base .word 0x08001000 +r11Base .word 0x08020000 r12Base .word 0x20000000 .endasmfunc Index: firmware/source/sys_startup.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_startup.c (.../sys_startup.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_startup.c (.../sys_startup.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -64,6 +64,7 @@ #include "errata_SSWF021_45.h" /* USER CODE BEGIN (1) */ +#include "reg_crc.h" /* USER CODE END */ @@ -417,18 +418,6 @@ /* USER CODE BEGIN (40) */ /* USER CODE END */ - - /* Test the CPU ECC mechanism for RAM accesses. - * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses - * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error - * in the ECC causes a data abort exception. The data abort handler is written to look for - * deliberately caused exception and to return the code execution to the instruction - * following the one that caused the abort. - */ - checkRAMECC(); - -/* USER CODE BEGIN (41) */ -/* USER CODE END */ /* USER CODE BEGIN (43) */ /* USER CODE END */ @@ -616,9 +605,6 @@ /* USER CODE BEGIN (72) */ /* USER CODE END */ - /* Enable IRQ offset via Vic controller */ - _coreEnableIrqVicOffset_(); - /* USER CODE BEGIN (73) */ /* USER CODE END */ @@ -627,6 +613,14 @@ vimInit(); /* USER CODE BEGIN (74) */ + // Shuffle IRQ priorities per design requirements + vimChannelMap( 3, 40, &rtiCompare1Interrupt ); + vimChannelMap( 5, 64, &rtiCompare3Interrupt ); + vimChannelMap( 13, 5, &linHighLevelInterrupt ); + vimChannelMap( 16, 15, &can1HighLevelInterrupt ); + vimChannelMap( 29, 13, &can1LowLevelInterrupt ); + vimChannelMap( 40, 10, &dmaBTCAInterrupt ); + vimChannelMap( 64, 16, &sciHighLevelInterrupt ); /* USER CODE END */ /* Configure system response to error conditions signaled to the ESM group1 */ Index: firmware/source/sys_vim.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/sys_vim.c (.../sys_vim.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/sys_vim.c (.../sys_vim.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -71,21 +71,21 @@ &phantomInterrupt, &esmHighInterrupt, /* Channel 0 */ &phantomInterrupt, /* Channel 1 */ - &phantomInterrupt, /* Channel 2 */ - &phantomInterrupt, /* Channel 3 */ + &rtiCompare0Interrupt, /* Channel 2 */ + &rtiCompare1Interrupt, /* Channel 3 */ &phantomInterrupt, /* Channel 4 */ - &phantomInterrupt, /* Channel 5 */ + &rtiCompare3Interrupt, /* Channel 5 */ &phantomInterrupt, /* Channel 6 */ &phantomInterrupt, /* Channel 7 */ &phantomInterrupt, /* Channel 8 */ &phantomInterrupt, /* Channel 9 */ &phantomInterrupt, /* Channel 10 */ &phantomInterrupt, /* Channel 11 */ &phantomInterrupt, /* Channel 12 */ - &phantomInterrupt, /* Channel 13 */ + &linHighLevelInterrupt, /* Channel 13 */ &phantomInterrupt, /* Channel 14 */ &phantomInterrupt, /* Channel 15 */ - &phantomInterrupt, /* Channel 16 */ + &can1HighLevelInterrupt, /* Channel 16 */ &phantomInterrupt, /* Channel 17 */ &phantomInterrupt, /* Channel 18 */ &phantomInterrupt, /* Channel 19 */ @@ -98,7 +98,7 @@ &phantomInterrupt, /* Channel 26 */ &phantomInterrupt, /* Channel 27 */ &phantomInterrupt, /* Channel 28 */ - &phantomInterrupt, /* Channel 29 */ + &can1LowLevelInterrupt, /* Channel 29 */ &phantomInterrupt, /* Channel 30 */ &phantomInterrupt, /* Channel 31 */ &phantomInterrupt, /* Channel 32 */ @@ -109,7 +109,7 @@ &phantomInterrupt, /* Channel 37 */ &phantomInterrupt, /* Channel 38 */ &phantomInterrupt, /* Channel 39 */ - &phantomInterrupt, /* Channel 40 */ + &dmaBTCAInterrupt, /* Channel 40 */ &phantomInterrupt, /* Channel 41 */ &phantomInterrupt, /* Channel 42 */ &phantomInterrupt, /* Channel 43 */ @@ -133,7 +133,7 @@ &phantomInterrupt, /* Channel 61 */ &phantomInterrupt, /* Channel 62 */ &phantomInterrupt, /* Channel 63 */ - &phantomInterrupt, /* Channel 64 */ + &sciHighLevelInterrupt, /* Channel 64 */ &phantomInterrupt, /* Channel 65 */ &phantomInterrupt, /* Channel 66 */ &phantomInterrupt, /* Channel 67 */ @@ -229,7 +229,7 @@ /* set IRQ/FIQ priorities */ vimREG->FIRQPR0 = (uint32)((uint32)SYS_FIQ << 0U) | (uint32)((uint32)SYS_FIQ << 1U) - | (uint32)((uint32)SYS_IRQ << 2U) + | (uint32)((uint32)SYS_FIQ << 2U) | (uint32)((uint32)SYS_IRQ << 3U) | (uint32)((uint32)SYS_IRQ << 4U) | (uint32)((uint32)SYS_IRQ << 5U) @@ -364,21 +364,21 @@ /* enable interrupts */ vimREG->REQMASKSET0 = (uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) - | (uint32)((uint32)0U << 2U) - | (uint32)((uint32)0U << 3U) + | (uint32)((uint32)1U << 2U) + | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) - | (uint32)((uint32)0U << 5U) + | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 12U) - | (uint32)((uint32)0U << 13U) + | (uint32)((uint32)1U << 13U) | (uint32)((uint32)0U << 14U) | (uint32)((uint32)0U << 15U) - | (uint32)((uint32)0U << 16U) + | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) @@ -391,7 +391,7 @@ | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U) | (uint32)((uint32)0U << 28U) - | (uint32)((uint32)0U << 29U) + | (uint32)((uint32)1U << 29U) | (uint32)((uint32)0U << 30U) | (uint32)((uint32)0U << 31U); @@ -403,7 +403,7 @@ | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U) - | (uint32)((uint32)0U << 8U) + | (uint32)((uint32)1U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 11U) @@ -428,7 +428,7 @@ | (uint32)((uint32)0U << 30U) | (uint32)((uint32)0U << 31U); - vimREG->REQMASKSET2 = (uint32)((uint32)0U << 0U) + vimREG->REQMASKSET2 = (uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) Index: firmware/source/system.c =================================================================== diff -u -r792764062d7b7826af10e030277f18379af4fcd1 -rabb9687e52d9db5df1abe7626ba04a6d431ba823 --- firmware/source/system.c (.../system.c) (revision 792764062d7b7826af10e030277f18379af4fcd1) +++ firmware/source/system.c (.../system.c) (revision abb9687e52d9db5df1abe7626ba04a6d431ba823) @@ -104,7 +104,7 @@ | (uint32)((uint32)0x1FU << 24U) | (uint32)0x00000000U | (uint32)((uint32)(6U - 1U)<< 16U) - | (uint32)(0xA400U); + | (uint32)(0x9B00U); /** - Setup pll control register 2 * - Setup spreading rate