Index: firmware/App/Common.h =================================================================== diff -u -r5645305f9349c5c64be5560982bdf1abd5edb0fb -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/App/Common.h (.../Common.h) (revision 5645305f9349c5c64be5560982bdf1abd5edb0fb) +++ firmware/App/Common.h (.../Common.h) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -21,7 +21,7 @@ #define CAN_MESSAGE_FRAME_NIBBLE_BYTES 4 ///< CAN message frame nibble in bytes. #define FIRMWARE_START_ADDRESS 0x00010000 ///< Firmware start address. #define FIRMWARE_CRC_TABLE_ADDRESS 0x10020 ///< The starting address of CRC table for firmware image. -#define SW_UPDATE_FLASH_BUFFER_SIZE 256 ///< Software update flash buffer bytes. +#define SW_UPDATE_FLASH_BUFFER_SIZE 512 ///< Software update flash buffer bytes. #define MASK_OFF_MSB 0x00FF ///< Bits to mask off the most significant byte of a 2-byte word. #define MASK_OFF_LSB 0xFF00 ///< Bits to mask off the least significant byte of a 2-byte word. #define SHIFT_8_BITS_FOR_BYTE_SHIFT 8 ///< Number of bits to shift in order to shift a byte. Index: firmware/App/Services/CopyFlashAPI2RAM.asm =================================================================== diff -u -r0c085209bea23f66011059a7c19796c1e4b246fa -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/App/Services/CopyFlashAPI2RAM.asm (.../CopyFlashAPI2RAM.asm) (revision 0c085209bea23f66011059a7c19796c1e4b246fa) +++ firmware/App/Services/CopyFlashAPI2RAM.asm (.../CopyFlashAPI2RAM.asm) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -28,3 +28,6 @@ bx lr .endasmfunc + + + Index: firmware/App/Services/Download.c =================================================================== diff -u -rab214e8ea52d8433b7cee58f5aaff49fc759310d -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/App/Services/Download.c (.../Download.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) +++ firmware/App/Services/Download.c (.../Download.c) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -67,6 +67,7 @@ } SW_UPDATE_FFU_BROADCAST_STATUS_T; static SW_UPDATE_RCV_STATUS_T SWUpdateRCVStatus; ///< Software update receive status. +static SW_UPDATE_CMD_STATUS_T SWUpdateCmdStatus; ///< Software update command status. static U32 fpgaPayloadLengthBytes; ///< FPGA payload length in bytes. static SW_UPDATE_SPECS_T SWUpdateSpecs; ///< Software update specifications. static U32 SWUpdateLastBroadcastTimeMS; ///< Software update last broadcast time stamp in milliseconds. @@ -164,12 +165,12 @@ * @param ack or nack status to be sent * @return none *************************************************************************/ -void sendFPGAAckNackStatus( ACK_NACK_STATUS_T ackNackStatus ) +void sendFPGAAckNackStatus( ACK_NACK_STATUS_T ackNackStatus, BOOL isAckForUpdate ) { - SW_UPDATE_CAN_MAIL_BOX_T thisStackMailBox = RECEIVE_MSG_ID[ BL_STACK_ID ][ FW_STACKS_RCV_MAIL_BOX_INDEX ]; + U16 msgID = ( TRUE == isAckForUpdate ? SWUpdateRCVStatus.msgID : SWUpdateCmdStatus.msgID ); - prepareAndSendBootLoaderResponseMessage( SWUpdateRCVStatus.msgID, ackNackStatus ); - clearCommBuffer( thisStackMailBox ); + prepareAndSendBootLoaderResponseMessage( msgID, ackNackStatus ); + clearSWUpdateBuffer(); } /*********************************************************************//** @@ -215,7 +216,7 @@ if ( TRUE == isMessageComplete( mailBox ) ) { // If the command buffer has been received, get it from the comm buffer and process it - SW_UPDATE_CMD_STATUS_T SWUpdateCmdStatus; + //SW_UPDATE_CMD_STATUS_T SWUpdateCmdStatus; getCommBuffer( mailBox, (U08*)&SWUpdateCmdStatus, sizeof( SW_UPDATE_CMD_STATUS_T ) ); @@ -242,8 +243,12 @@ } } - // Send the result of the command received - prepareAndSendBootLoaderResponseMessage( msgID, ackStatus ); + if ( SWUpdateSpecs.dest != UPDATE_FPGA ) + { + // Send the result of the command received + prepareAndSendBootLoaderResponseMessage( msgID, ackStatus ); + } + clearCommBuffer( mailBox ); } } @@ -275,7 +280,7 @@ payloadLength = SWUpdateRCVStatus.updatePayloadLen; // Create a local buffer and copy the header into the buffer excluding the CRC so only 4 bytes of ID, Destination, and payload length - memcpy( bufferWithNoCRC, (U08*)&SWUpdateRCVStatus, sizeof( U32 ) ); + memcpy( &bufferWithNoCRC, (U08*)&SWUpdateRCVStatus, sizeof( U32 ) ); // Copy the entire update buffer that is going either to firmware or FPGA into the local buffer. memcpy( &bufferWithNoCRC[ sizeof( U32 ) ], SWUpdateRCVStatus.SWUpdateBuffer, payloadLength ); // Calculate the CRC of the local copied buffer and compare it against the message CRC @@ -288,31 +293,29 @@ BOOL test = TRUE; // TODO remove for testing } - if ( TRUE == hasCRCPassed ) { // CRC passed, call the corresponding the handlers to update either FPGA or firmware switch ( SWUpdateSpecs.dest ) { case UPDATE_FIRMWARE: ackStatus = handleFirmwareUpdate(); - // Send the ack/nack status immediately because the other processes are blocked + // For firmware update, send the ack status since in firmware flash all the other processes are halted prepareAndSendBootLoaderResponseMessage( msgID, ackStatus ); + clearCommBuffer( mailBox ); + clearSWUpdateBuffer(); break; case UPDATE_FPGA: ackStatus = handleFPGAUpdate(); - // Do not send the ack/nack immediately. FPGA takes longer to respond and it will through other functions + // For FPGA update, do not send the ack status immediately since the jobs are queued break; default: // Do nothing break; } } - - clearCommBuffer( mailBox ); - clearSWUpdateBuffer(); } } @@ -418,27 +421,36 @@ static ACK_NACK_STATUS_T handleFPGAUpdate( void ) { ACK_NACK_STATUS_T ackStatus = NACK; + BOOL status = FALSE; - // TODO why the firmware handler is slightly different? Make them consistent. +//#define SW_UPDATE_FINAL_MSG_INDEX 0xFFFF // TODO: Remove. NOTE: once FPGA is ready investigate and remove 0xFFFF -#define SW_UPDATE_FINAL_MSG_INDEX 0xFFFF // TODO: Remove. NOTE: once FPGA is ready investigate and remove 0xFFFF - - if ( SWUpdateRCVStatus.updatePayloadLen != SW_UPDATE_FINAL_MSG_INDEX ) - { + //if ( SWUpdateRCVStatus.updatePayloadLen != SW_UPDATE_FINAL_MSG_INDEX ) // TODO remove + //{ fpgaPayloadLengthBytes = SWUpdateRCVStatus.updatePayloadLen; REMOVETHEVAR += fpgaPayloadLengthBytes; - signalFPGAToWriteToFlash( SWUpdateRCVStatus.SWUpdateBuffer, fpgaPayloadLengthBytes ); + status = signalFPGAToWriteToFlash( SWUpdateRCVStatus.SWUpdateBuffer, fpgaPayloadLengthBytes ); if ( fpgaPayloadLengthBytes < SW_UPDATE_FLASH_BUFFER_SIZE ) { + // TODO this should be a command and not the last buffer because what if the last payload is 256 bytes? signalFPGAToSelfConfigure(); } - } - else - { - prepareAndSendBootLoaderResponseMessage( SWUpdateRCVStatus.msgID, ACK ); - } + if ( TRUE == status ) + { + // The update payload has been enqueued successfully, clear the buffers + SW_UPDATE_CAN_MAIL_BOX_T thisStackMailBox = RECEIVE_MSG_ID[ BL_STACK_ID ][ FW_STACKS_RCV_MAIL_BOX_INDEX ]; + + clearCommBuffer( thisStackMailBox ); + //clearSWUpdateBuffer(); // TODO remove? + } + //} + //else + //{ + // prepareAndSendBootLoaderResponseMessage( SWUpdateRCVStatus.msgID, ACK ); + //} + return ackStatus; } Index: firmware/App/Services/Download.h =================================================================== diff -u -rab214e8ea52d8433b7cee58f5aaff49fc759310d -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/App/Services/Download.h (.../Download.h) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) +++ firmware/App/Services/Download.h (.../Download.h) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -27,7 +27,7 @@ void clearSWUpdateSpecs( void ); -void sendFPGAAckNackStatus( ACK_NACK_STATUS_T ackNackStatus ); +void sendFPGAAckNackStatus( ACK_NACK_STATUS_T ackNackStatus, BOOL isAckForUpdate ); U32 getLastBroadcastMessageTimeStampMS( void ); Index: firmware/App/Services/FPGA.c =================================================================== diff -u -rab214e8ea52d8433b7cee58f5aaff49fc759310d -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -50,7 +50,6 @@ #define FPGA_READ_CMD_CODE 0x5A ///< FPGA read command code. #define FPGA_READ_CMD_ACK 0xAA ///< FPGA read command ACK code. #define FPGA_HEADER_START_ADDR 0x0000 ///< Start address for FPGA header data. -#define FPGA_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. // TODO does this vary? #if BL_STACK_ID == 1 #define FPGA_FLASH_CONTROL_REG_ADDR 0x120E ///< FPGA flash control register address. @@ -64,22 +63,19 @@ #define FPGA_FLASH_DATA_REG_ADDR 0x0A00 ///< FPGA flash data register address. #endif -#define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remvoe -#define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remvoe +#define FPGA_FLASH_STATUS_REG_ADDR 0x0900 ///< FPGA flash status register address. // TODO remove +#define FPGA_FIFO_COUNT_REG_ADDR 0x0902 ///< FPGA FIFO count register address. // TODO remove -#define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) ///< FPGA update register address. -#define FPGA_UPDATE_REQUEST_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA update request index. // TODO Get this value from Noe, make sure the index is the same in all of the stacks -#define FPGA_FLASH_STATUS_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA flash status index. -#define FPGA_FIFO_COUNT_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA FIFO count index. +#define FPGA_WRITE_START_ADDR 0x000B ///< Start address for FPGA continuous priority writes. // TODO remove +#define FPGA_UPDATE_REGISTER_ADDR ( FPGA_WRITE_START_ADDR + 4 ) ///< FPGA update register address. // TODO remove since FFU will broadcast +#define FPGA_UPDATE_REQUEST_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA update request index. // TODO remove +#define FPGA_FLASH_STATUS_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA flash status index. // TODO remove +#define FPGA_FIFO_COUNT_INDEX ( FPGA_READ_RSP_HDR_LEN + 1 ) ///< FPGA FIFO count index. // TODO remove +#define UPDATE_REQUESTED_VALUE 1 // TODO remove FFU will broadcast ///< The value that indicates and update has been requested. -#define UPDATE_REQUESTED_VALUE 1 ///< The value that indicates and update has been requested. - #define FPGA_FIFO_SIZE_BYTES 1024 ///< FPGA FIFO size in bytes. #define FPGA_FIFO_COUNT_MASK 0x03FF ///< FPGA FIFO count in FIFO mask. - -#define FPGA_ERASE_FIFO_CMD_OK ( 1 << 11 ) ///< FPGA erase FIFO command status ok value. -#define FPGA_FLASH_STATUS_OK ( 1 << 15 ) ///< FPGA flash status status ok value. - +#define FPGA_INIT_STAGE_TIMEOUT_MS 6000 ///< FPGA initialization stage timeout in milliseconds. #define FPGA_PRE_SELF_CONFIG_TIMEOUT_MS 10000 ///< FPGA pre self configure timeout in milliseconds. /// FPGA communication status enumeration @@ -93,12 +89,21 @@ NUM_OF_FPGA_COMM_STATUS ///< Number of FPGA communication status. } FPGA_COMM_STATE_T; +typedef enum +{ + FPGA_UPDATE_STAGE_INIT = 0, + FPGA_UPDATE_STAGE_CHECK_UPDATE_INIT, + FPGA_UPDATE_STAGE_UPDATE, + FPGA_UPDATE_STAGE_SELF_CONFIGURE, + NUM_OF_FPGA_UPDATE_STAGES +} FPGA_UPDATE_STAGE_T; + /// FPGA queue jobs enumeration typedef enum { FPGA_READ_HEADER = 0, ///< FPGA read header. - FPGA_READ_UPDATE_REG, // TODO remove? ///< FPGA read update request register. - FPGA_WRITE_UPDATE_REG, ///< FPGA write to update request register. + FPGA_READ_UPDATE_REG, // TODO remove related to using FPGA as communication but FFU will broadcast ///< FPGA read update request register. + FPGA_WRITE_UPDATE_REG, // TODO remove related to using FPGA as communication but FFU will broadcast ///< FPGA write to update request register. FPGA_RESET_FLASH, ///< FPGA reset flash. FPGA_ERASE_FIFO, ///< FPGA erase FIFO. FPGA_ENABLE_FLASH, ///< FPGA enable flash. @@ -119,14 +124,14 @@ NUM_OF_FPGA_STATES ///< Number of FPGA states. } FPGA_STATE_T; -#pragma pack(push,1) +//#pragma pack(push,1) /// FPGA queue job specification structure typedef struct { U16 fpgaJobAddress; ///< FPGA job address. U16 fpgaJobSize; ///< FPGA job size. + BOOL fpgaIsJobWrite; ///< FPGA boolean flag to indicate this is a write job or not. U08* fpgaWriteStartAddress; ///< FPGA write buffer start address. - U08 fpgaIsJobWrite; ///< FPGA boolean flag to indicate this is a write job or not. } FPGA_JOB_SPECS_T; /// FPGA jobs queue status structure @@ -156,14 +161,16 @@ /// FPGA flash status structure typedef struct { - BOOL hasUpdateRegsBeenRqstd; ///< Flag to indicate whether update registers request has been requested. - U16 fifoRemainingCount; ///< FIFO empty space remaining count. - BOOL isFIFOEraseOk; ///< Flag to indicate whether FIFO has been erased or not. - BOOL isFlashStatusOk; ///< Flag to indicate whether flash status is okay or not. - BOOL isFPGAFlashComplete; ///< Flag to indicate whether flash update has been completed. - U16 flashStatusBits; ///< Flash status. + U16 fpgaRemainingFIFOCountBytes; ///< Remaining FIFO size in bytes. + U16 fpgaInitStatus; + U16 fpgaCheckIDStatus; + U16 fpgaEraseStatus; + U16 fpgaProgramImageStatus; + U16 fpgaReadyForDataStatus; + FPGA_UPDATE_STAGE_T fpgaUpdateStage; + U32 preSelfConfigureStartTimeMS; ///< Pre self configure start time in milliseconds. - U32 startTime; ///< Start time in milliseconds. + U32 startTimeMS; ///< Start time in milliseconds. } FPGA_FLASH_STATUS_T; /// Record structure for FPGA header read. @@ -174,7 +181,7 @@ U08 fpgaRevMajor; ///< Reg 2. FPGA revision (major) being reported. U08 fpgaRevLab; ///< Reg 3. FPGA revision (lab) being reported. } FPGA_HEADER_T; // Read only on FPGA -#pragma pack(pop) +//#pragma pack(pop) // ********** private data ********** @@ -192,47 +199,63 @@ static FPGA_HEADER_T fpgaHeader; ///< Record of last received FPGA header data. static FPGA_STATE_T fpgaState; ///< FPGA current state. -static U08 fpgaUpdateRegisterStatus; ///< FPGA update register status. +static U08 fpgaUpdateRegisterStatus; // TODO remove FFU will broadcast ///< FPGA update register status. static FPGA_JOBS_Q_STATUS_T fpgaJobsQStatus; ///< FPGA jobs queue status. static FPGA_FLASH_STATUS_T fpgaFlashStatus; ///< FPGA flash status. static FPGA_READ_REGS_T fpgaReadRegsStatus; ///< FGPA read registers status. +static U32 fpgaOperationStartTimeMS; ///< FPGA operation start time in milliseconds (read/write). static U08 fpgaDataToWriteBuffer[ SW_UPDATE_FLASH_BUFFER_SIZE ]; ///< FPGA data to write to FPGA flash buffer. static U32 fpgaDataLenToWrite; ///< FPGA data length to write to FPGA. -static U32 TESTREMOVE = 0; // TODO remove -static U32 countRemove = 0; // TODO remove -static U08 tempACkStatus = 0; // TODO remove +static U08 tempPrevJob; +static U16 tempPrevFlash; +static U16 tempPrevFIFO; /// FPGA stack ID for TD, DD -static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61 }; // TODO update with the real FPGA IDs // TODO remove +//static const U08 STACK_FPGA_ID[ NUM_OF_FW_STACKS ] = { 0x5A, 0x61 }; // TODO update with the real FPGA IDs // TODO remove // TODO what is this value? 0? -static const U16 DISABLE_UPDATE_REG_CMD = 5; ///< FPGA disable update register command. // TODO remove +//static const U16 DISABLE_UPDATE_REG_CMD = 5; ///< FPGA disable update register command. // TODO remove FFU will broadcast + + static const U08 FPGA_RESET_FLASH_CMD = 0x01; ///< FPGA reset flash command. static const U08 FPGA_ERASE_FIFO_CMD = 0x08; ///< FPGA erase FIFO command. static const U08 FPGA_ENABLE_FLASH_CMD = 0x00; ///< FPGA enable flash command. static const U08 FPGA_SELF_CONFIG_CMD = 0x03; ///< FPGA self configure command. +static const U08 DUMMY_ADDRESS1 = 0x03; +static const U08 DUMMY_ADDRESS2 = 0x03; +static const U08 DUMMY_ADDRESS3 = 0x03; +static const U08 DUMMY_ADDRESS4 = 0x03; + +static const U32 FPGA_FLASH_INIT_STATUS = ( 1 << 8 ); +static const U32 FPGA_FLASH_ERASE_STATUS = ( 1 << 11 ); +static const U32 FPGA_FLASH_PROG_IMAGE_STATUS = ( 1 << 12 ); +static const U32 FPGA_FLASH_READY_FOR_UPDATE_STATUS = ( 1 << 15 ); + /// FPGA jobs specifications. static const FPGA_JOB_SPECS_T JOBS_SPECS[ NUM_OF_FPGA_JOBS ] = { - { FPGA_HEADER_START_ADDR, sizeof( FPGA_HEADER_T ), 0, FALSE }, // FPGA_READ_HEADER - { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, 0, FALSE }, // TODO remove // FPGA_READ_UPDATE_REG - { FPGA_UPDATE_REGISTER_ADDR, sizeof( U16 ), (U08*)&DISABLE_UPDATE_REG_CMD, TRUE }, // FPGA_WRITE_UPDATE_REG + { FPGA_HEADER_START_ADDR, sizeof( FPGA_HEADER_T ), FALSE, (U08*)&DUMMY_ADDRESS1, }, // FPGA_READ_HEADER - { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_RESET_FLASH_CMD, TRUE }, // FPGA_RESET_FLASH + { FPGA_BULK_READ_START_ADDR, FPGA_MAX_READ_SIZE, FALSE, (U08*)&DUMMY_ADDRESS1, }, // TODO remove with the enum at the top // FPGA_READ_UPDATE_REG + { FPGA_UPDATE_REGISTER_ADDR, sizeof( U16 ), TRUE , (U08*)&DUMMY_ADDRESS1, }, // TODO remove // FPGA_WRITE_UPDATE_REG - { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ERASE_FIFO_CMD, TRUE }, // FPGA_ERASE_FIFO - { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_ENABLE_FLASH_CMD, TRUE }, // FPGA_ENABLE_FLASH - { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( FPGA_READ_REGS_T ), 0, FALSE }, // FPGA_READ_MULTI_BOOT_STATUS - { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, fpgaDataToWriteBuffer, TRUE }, // FPGA_FLASH_WRITE_DATA - { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), (U08*)&FPGA_SELF_CONFIG_CMD, TRUE } // FPGA_SELF_CONFIGURE + { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), TRUE , (U08*)&FPGA_RESET_FLASH_CMD, }, // FPGA_RESET_FLASH + + { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), TRUE , (U08*)&FPGA_ERASE_FIFO_CMD, }, // FPGA_ERASE_FIFO + { FPGA_FLASH_CONTROL_REG_ADDR, sizeof( U08 ), TRUE , (U08*)&FPGA_ENABLE_FLASH_CMD, }, // FPGA_ENABLE_FLASH + + { FPGA_MULTI_BOOT_STATUS_ADDR, sizeof( FPGA_READ_REGS_T ), FALSE, (U08*)&DUMMY_ADDRESS1, }, // FPGA_READ_MULTI_BOOT_STATUS + + { FPGA_FLASH_DATA_REG_ADDR, SW_UPDATE_FLASH_BUFFER_SIZE, TRUE , (U08*)&fpgaDataToWriteBuffer, }, // FPGA_FLASH_WRITE_DATA + { FPGA_ICAP2_REG_ADDR, sizeof( U08 ), TRUE , (U08*)&FPGA_SELF_CONFIG_CMD, } // FPGA_SELF_CONFIGURE }; // ********** private function prototypes ********** static void initDMA( void ); static void consumeUnexpectedData( void ); -static void requestFlashRegistersStatus( void ); static void processFPGAFlashRegistersRead( void ); +static void processFPGAUpdateInitStatus( void ); static void setupDMAForReadResp( U32 bytes2Receive ); static void setupDMAForReadCmd( U32 bytes2Transmit ); @@ -249,6 +272,8 @@ static FPGA_JOBS_T peekFromQueue( void ); static BOOL isQueueFull( void ); +static void publishDataTemp( void ); + static FPGA_STATE_T handleFPGAIdleState( void ); static FPGA_STATE_T handleFPGAWriteToFPGAState( void ); @@ -266,24 +291,32 @@ *************************************************************************/ void initFPGA( void ) { - memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); - memset( &fpgaJobsQStatus, 0x0, sizeof( FPGA_JOBS_Q_STATUS_T ) ); - memset( &fpgaFlashStatus, 0x0, sizeof( FPGA_FLASH_STATUS_T ) ); + memset( &fpgaHeader, 0x0, sizeof( FPGA_HEADER_T ) ); + memset( &fpgaJobsQStatus, 0x0, sizeof( FPGA_JOBS_Q_STATUS_T ) ); + memset( &fpgaFlashStatus, 0x0, sizeof( FPGA_FLASH_STATUS_T ) ); + memset( &fpgaReadRegsStatus, 0x0, sizeof( FPGA_READ_REGS_T ) ); + memset( &fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE ); // initialize fpga comm buffers memset( &fpgaWriteCmdBuffer, 0, FPGA_WRITE_CMD_BUFFER_LEN ); memset( &fpgaReadCmdBuffer, 0, FPGA_READ_CMD_BUFFER_LEN ); memset( &fpgaWriteResponseBuffer, 0, FPGA_WRITE_RSP_BUFFER_LEN ); memset( &fpgaReadResponseBuffer, 0, FPGA_READ_RSP_BUFFER_LEN ); + fpgaState = FPGA_IDLE_STATE; + fpgaUpdateRegisterStatus = 0; + fpgaOperationStartTimeMS = 0; + fpgaDataLenToWrite = 0; + + tempPrevJob = 0; + tempPrevFlash = 0; + tempPrevFIFO = 0; + initDMA(); consumeUnexpectedData(); enqueue( FPGA_READ_HEADER ); enqueue( FPGA_READ_MULTI_BOOT_STATUS ); - - fpgaState = FPGA_IDLE_STATE; - fpgaUpdateRegisterStatus = 0; } /*********************************************************************//** @@ -295,19 +328,6 @@ *************************************************************************/ void execFPGA( void ) { - // TODO test code remove - U08 data[8]; - data[0] = GET_LSB_OF_WORD( getCurrentUpdateMessageID() ); - data[1] = GET_MSB_OF_WORD( getCurrentUpdateMessageID() ); - data[2] = GET_LSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); - data[3] = GET_MSB_OF_WORD( fpgaFlashStatus.fifoRemainingCount ); - data[4] = GET_LSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); - data[5] = GET_MSB_OF_WORD( fpgaFlashStatus.flashStatusBits ); - data[6] = fpgaJobsQStatus.fpgaCurrentJob; - data[7] = (U08)fpgaState; - broadcastDataTestRemove(data); - // TODO test code remove - switch( fpgaState ) { case FPGA_IDLE_STATE: @@ -334,6 +354,8 @@ // Do nothing break; } + + publishDataTemp(); } /*********************************************************************//** @@ -388,8 +410,10 @@ *************************************************************************/ BOOL isFPGAIDValid( void ) { - BOOL status = ( STACK_FPGA_ID[ BL_STACK_ID ] == fpgaHeader.fpgaId ? TRUE : FALSE ); + //BOOL status = ( STACK_FPGA_ID[ BL_STACK_ID ] == fpgaHeader.fpgaId ? TRUE : FALSE ); + BOOL status = FALSE; + return status; } @@ -403,7 +427,9 @@ *************************************************************************/ BOOL isFPGAFlashComplete( void ) { - return fpgaFlashStatus.isFPGAFlashComplete; + //return fpgaFlashStatus.isFPGAFlashComplete; // TODO clean this up + + return TRUE; } /*********************************************************************//** @@ -430,19 +456,34 @@ * job if the queue is not full. * @details \b Inputs: none * @details \b Outputs: fpgaDataLenToWrite, fpgaDataToWriteBuffer - * @return none + * @return TURE if the buffer was enqueued successfully otherwise, FALSE *************************************************************************/ -void signalFPGAToWriteToFlash( U08* data, U32 len ) +BOOL signalFPGAToWriteToFlash( U08* data, U32 len ) { - if ( FALSE == isQueueFull() ) + BOOL status = FALSE; + BOOL isFIFOReady = FALSE; + + // Check if the next job in the queue is a flash write. + // If there is a flash write, only dequeue it if: + // 1. There are enough number of bytes available in the FIFO for the next data (e.g. 256) + // 2. The flash status is okay + if ( ( fpgaFlashStatus.fpgaRemainingFIFOCountBytes > SW_UPDATE_FLASH_BUFFER_SIZE ) && + ( FPGA_FLASH_READY_FOR_UPDATE_STATUS == fpgaFlashStatus.fpgaReadyForDataStatus ) ) { - memset( fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE ); + isFIFOReady = TRUE; + } + if ( ( FALSE == isQueueFull() ) && ( TRUE == isFIFOReady ) ) + { fpgaDataLenToWrite = len; - memcpy( fpgaDataToWriteBuffer, data, len ); + status = TRUE; + memset( &fpgaDataToWriteBuffer, 0x0, SW_UPDATE_FLASH_BUFFER_SIZE ); + memcpy( &fpgaDataToWriteBuffer, data, len ); enqueue( FPGA_FLASH_WRITE_DATA ); } + + return status; } /*********************************************************************//** @@ -584,83 +625,42 @@ /*********************************************************************//** * @brief - * The requestFlashRegistersStatus function requests the FPGA flash readings - * status. - * @details \b Inputs: none - * @details \b Outputs: fpgaReadCmdBuffer[], fpgaJobsQStatus, fpgaFlashStatus - * @return none - *************************************************************************/ -static void requestFlashRegistersStatus( void ) -{ - U16 jobAddress = JOBS_SPECS[ FPGA_READ_MULTI_BOOT_STATUS ].fpgaJobAddress; - U08 jobSize = JOBS_SPECS[ FPGA_READ_MULTI_BOOT_STATUS ].fpgaJobSize; - U16 crc = 0; - - // Construct read command to read 3 registers starting at address 0 - fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE; - fpgaReadCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); - fpgaReadCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); -#if BL_STACK_ID == 1 - fpgaReadCmdBuffer[ 3 ] = GET_LSB_OF_WORD( jobSize ); - fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( jobSize ); -#else - fpgaReadCmdBuffer[ 3 ] = jobSize; -#endif - crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); -#if BL_STACK_ID == 1 - fpgaReadCmdBuffer[ 5 ] = GET_MSB_OF_WORD( crc ); - fpgaReadCmdBuffer[ 6 ] = GET_LSB_OF_WORD( crc ); -#else - fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc ); - fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc ); -#endif - // Prep DMA for sending the read cmd and receiving the response - fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_IN_PROGRESS; - fpgaFlashStatus.hasUpdateRegsBeenRqstd = TRUE; - - setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + jobSize + sizeof( U16 ) ); - setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + sizeof( U16 ) ); - startDMAReceiptOfReadResp(); - startDMAReadCmd(); -} - -/*********************************************************************//** - * @brief * The processFPGAFlashRegistersRead function processes the read flash readings. * @details \b Inputs: fpgaReadResponseBuffer[] * @details \b Outputs: fpgaFlashStatus * @return none *************************************************************************/ static void processFPGAFlashRegistersRead( void ) { - if ( FPGA_READ_CMD_ACK == fpgaReadResponseBuffer[ 0 ] ) + fpgaFlashStatus.fpgaRemainingFIFOCountBytes = FPGA_FIFO_SIZE_BYTES - ( fpgaReadRegsStatus.fifoCount & FPGA_FIFO_COUNT_MASK ); + fpgaFlashStatus.fpgaInitStatus = fpgaReadRegsStatus.flashStatus & FPGA_FLASH_INIT_STATUS; + fpgaFlashStatus.fpgaEraseStatus = fpgaReadRegsStatus.flashStatus & FPGA_FLASH_ERASE_STATUS; + fpgaFlashStatus.fpgaProgramImageStatus = fpgaReadRegsStatus.flashStatus & FPGA_FLASH_PROG_IMAGE_STATUS; + fpgaFlashStatus.fpgaReadyForDataStatus = fpgaReadRegsStatus.flashStatus & FPGA_FLASH_READY_FOR_UPDATE_STATUS; +} + +static void processFPGAUpdateInitStatus( void ) +{ + if ( TRUE == didTimeout( fpgaFlashStatus.startTimeMS, FPGA_INIT_STAGE_TIMEOUT_MS ) ) { - U32 rspSize = FPGA_READ_RSP_HDR_LEN + JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaJobSize; - U32 crcPos = rspSize; - U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] ); + BOOL initStatus = TRUE; + ACK_NACK_STATUS_T ackStatus = NACK; - // Does the FPGA response CRC check out? - if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) ) - { - U16 flashStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX ], fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX - 1 ] ); - U16 fifoStatus = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) ], - fpgaReadResponseBuffer[ FPGA_FLASH_STATUS_INDEX + sizeof( U16 ) - 1 ] ); + fpgaFlashStatus.fpgaUpdateStage = FPGA_UPDATE_STAGE_INIT; - fpgaFlashStatus.fifoRemainingCount = FPGA_FIFO_SIZE_BYTES - ( FPGA_FIFO_COUNT_MASK & fifoStatus ); - fpgaFlashStatus.hasUpdateRegsBeenRqstd = FALSE; - fpgaFlashStatus.flashStatusBits = flashStatus; - fpgaFlashStatus.isFlashStatusOk = FALSE; + initStatus &= ( FPGA_FLASH_INIT_STATUS == fpgaFlashStatus.fpgaInitStatus ? TRUE : FALSE ); + initStatus &= ( FPGA_FLASH_READY_FOR_UPDATE_STATUS == fpgaFlashStatus.fpgaReadyForDataStatus ? TRUE : FALSE ); + initStatus &= ( fpgaFlashStatus.fpgaRemainingFIFOCountBytes > SW_UPDATE_FLASH_BUFFER_SIZE ? TRUE : FALSE ); - if ( ( flashStatus & FPGA_ERASE_FIFO_CMD_OK ) == FPGA_ERASE_FIFO_CMD_OK ) - { - fpgaFlashStatus.isFIFOEraseOk = TRUE; - } - - if ( ( flashStatus & FPGA_FLASH_STATUS_OK ) == FPGA_FLASH_STATUS_OK ) - { - fpgaFlashStatus.isFlashStatusOk = TRUE; - } + if ( TRUE == initStatus ) + { + ackStatus = ACK; + fpgaFlashStatus.fpgaUpdateStage = FPGA_UPDATE_STAGE_UPDATE; } + + ackStatus = ( TRUE == initStatus ? ACK : NACK ); + + sendFPGAAckNackStatus( ackStatus, FALSE ); } } @@ -897,6 +897,29 @@ return isFull; } +static void publishDataTemp( void ) +{ + // TODO test code remove + //if ( ( tempPrevJob != fpgaJobsQStatus.fpgaCurrentJob ) || ( tempPrevFlash != fpgaReadRegsStatus.flashStatus ) || ( tempPrevFIFO != fpgaFlashStatus.fpgaRemainingFIFOCountBytes ) ) + { + U08 data[8]; + data[0] = GET_MSB_OF_WORD( getCurrentUpdateMessageID() ); + data[1] = GET_LSB_OF_WORD( getCurrentUpdateMessageID() ); + data[2] = GET_MSB_OF_WORD( fpgaFlashStatus.fpgaRemainingFIFOCountBytes ); + data[3] = GET_LSB_OF_WORD( fpgaFlashStatus.fpgaRemainingFIFOCountBytes ); + data[4] = GET_MSB_OF_WORD( fpgaReadRegsStatus.flashStatus ); + data[5] = GET_LSB_OF_WORD( fpgaReadRegsStatus.flashStatus ); + data[6] = fpgaJobsQStatus.fpgaCurrentJob; + data[7] = (U08)fpgaState; + broadcastDataTestRemove(data); + + //tempPrevJob = fpgaJobsQStatus.fpgaCurrentJob; + //tempPrevFlash = fpgaReadRegsStatus.flashStatus; + //tempPrevFIFO = fpgaFlashStatus.fpgaRemainingFIFOCountBytes; + } + // TODO test code remove +} + /*********************************************************************//** * @brief * The handleFPGAIdleState function handles the FPGA idle state. This state @@ -910,36 +933,51 @@ { FPGA_STATE_T state = FPGA_IDLE_STATE; + switch( fpgaFlashStatus.fpgaUpdateStage ) + { + case FPGA_UPDATE_STAGE_CHECK_UPDATE_INIT: + processFPGAUpdateInitStatus(); + break; + } + + if ( FALSE == isQueueFull() ) + { + // If queue is not full enqueue a multi-boot status read + enqueue( FPGA_READ_MULTI_BOOT_STATUS ); + } + if ( fpgaJobsQStatus.fpgaJobsQueueCount > 0 ) { BOOL isDequeueAllowed = TRUE; - if ( FPGA_FLASH_WRITE_DATA == peekFromQueue() ) - { - // Check if the next job in the queue is a flash write. - // If there is a flash write, only dequeue it if: - // 1. There are at least 256 bytes available in the FIFO - // 2. The flash status is okay - // 3. The FIFO erase is okay - if ( ( fpgaFlashStatus.fifoRemainingCount < SW_UPDATE_FLASH_BUFFER_SIZE ) || - ( FALSE == fpgaFlashStatus.isFlashStatusOk ) || - ( FALSE == fpgaFlashStatus.isFIFOEraseOk ) ) - { - isDequeueAllowed = FALSE; - } - } + // TODO remove + //if ( FPGA_FLASH_WRITE_DATA == peekFromQueue() ) + //{ + // // Check if the next job in the queue is a flash write. + // // If there is a flash write, only dequeue it if: + // // 1. There are at least 256 bytes available in the FIFO + // // 2. The flash status is okay + // // 3. The FIFO erase is okay + // if ( ( fpgaFlashStatus.fpgaRemainingFIFOCountBytes < SW_UPDATE_FLASH_BUFFER_SIZE ) || + // ( FALSE == fpgaFlashStatus.isFlashStatusOk ) || + // ( FALSE == fpgaFlashStatus.isFIFOEraseOk ) ) + // { + // isDequeueAllowed = FALSE; + // } + //} - if ( FPGA_SELF_CONFIGURE == peekFromQueue() ) - { - // Check if the next job in the queue is the self configure. Then make sure: - // 1. The delay has timed out - // 2. The flash status is okay - if ( ( FALSE == didTimeout( fpgaFlashStatus.preSelfConfigureStartTimeMS, FPGA_PRE_SELF_CONFIG_TIMEOUT_MS ) ) || - ( FALSE == fpgaFlashStatus.isFlashStatusOk ) ) - { - isDequeueAllowed = FALSE; - } - } + // TODO remove + //if ( FPGA_SELF_CONFIGURE == peekFromQueue() ) + //{ + // // Check if the next job in the queue is the self configure. Then make sure: + // // 1. The delay has timed out + // // 2. The flash status is okay + // if ( ( FALSE == didTimeout( fpgaFlashStatus.preSelfConfigureStartTimeMS, FPGA_PRE_SELF_CONFIG_TIMEOUT_MS ) ) || + // ( FALSE == fpgaFlashStatus.isFlashStatusOk ) ) + // { + // isDequeueAllowed = FALSE; + // } + //} if ( TRUE == isDequeueAllowed ) { @@ -949,7 +987,6 @@ } } - //requestFlashRegistersStatus(); // TODO remove return state; } @@ -980,23 +1017,23 @@ { // Once self configure is sent the FPGA will be unresponsive so there will be no ack back // Signal FPGA is completed - state = FPGA_IDLE_STATE; - fpgaFlashStatus.isFPGAFlashComplete = TRUE; + state = FPGA_IDLE_STATE; } U08* value2Write = JOBS_SPECS[ fpgaJobsQStatus.fpgaCurrentJob ].fpgaWriteStartAddress; U16 firstCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize; U16 secondCRCIndex = FPGA_WRITE_CMD_HDR_LEN + jobSize + 1; + memset( &fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this memcpy( &fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ], value2Write, jobSize ); // Construct bulk read command to read sensor data registers starting at address 8 fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE; fpgaWriteCmdBuffer[ 1 ] = GET_LSB_OF_WORD( jobAddress ); fpgaWriteCmdBuffer[ 2 ] = GET_MSB_OF_WORD( jobAddress ); #if BL_STACK_ID == 1 - fpgaWriteCmdBuffer[ 3 ] = GET_LSB_OF_WORD( jobSize % SW_UPDATE_FLASH_BUFFER_SIZE ); - fpgaWriteCmdBuffer[ 4 ] = GET_MSB_OF_WORD( jobSize % SW_UPDATE_FLASH_BUFFER_SIZE ); + fpgaWriteCmdBuffer[ 3 ] = GET_LSB_OF_WORD( jobSize ); + fpgaWriteCmdBuffer[ 4 ] = GET_MSB_OF_WORD( jobSize ); #else fpgaWriteCmdBuffer[ 3 ] = jobSize % SW_UPDATE_FLASH_BUFFER_SIZE; #endif @@ -1042,13 +1079,16 @@ // Does the FPGA response CRC checkout? if ( crc == crc16( fpgaWriteResponseBuffer, rspSize ) ) { + // TODO switch case or a function here if ( FPGA_FLASH_WRITE_DATA == fpgaJobsQStatus.fpgaCurrentJob ) { - sendFPGAAckNackStatus( ACK ); - tempACkStatus = ACK; // TODO remove + sendFPGAAckNackStatus( ACK, TRUE ); + } - TESTREMOVE += fpgaDataLenToWrite;// TODO REMOVE - countRemove += 1;// TODO REMOVE + if ( FPGA_ENABLE_FLASH == fpgaJobsQStatus.fpgaCurrentJob ) + { + fpgaFlashStatus.fpgaUpdateStage = FPGA_UPDATE_STAGE_CHECK_UPDATE_INIT; + fpgaFlashStatus.startTimeMS = getMSTimerCount(); } // CRC passed @@ -1057,14 +1097,11 @@ else { // TODO error handling + BOOL test = FALSE; } } - - memset( fpgaWriteCmdBuffer, 0x0, FPGA_WRITE_CMD_BUFFER_LEN ); // TODO a better place for this } - //requestFlashRegistersStatus(); - return state; } @@ -1104,7 +1141,7 @@ // Prep DMA for sending the read cmd and receiving the response fpgaJobsQStatus.fpgaCommRead = FPGA_COMM_READ_IN_PROGRESS; - fpgaFlashStatus.startTime = getMSTimerCount(); + fpgaOperationStartTimeMS = getMSTimerCount(); setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + jobSize + sizeof( U16 ) ); setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + sizeof( U16 ) ); @@ -1151,24 +1188,22 @@ case FPGA_READ_MULTI_BOOT_STATUS: memcpy( &fpgaReadRegsStatus, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], jobSize ); + processFPGAFlashRegistersRead(); break; default: // Do nothing break; } - memset( fpgaReadResponseBuffer, 0x0, FPGA_READ_RSP_BUFFER_LEN ); - - enqueue( FPGA_READ_MULTI_BOOT_STATUS ); + memset( &fpgaReadResponseBuffer, 0x0, FPGA_READ_RSP_BUFFER_LEN ); state = FPGA_IDLE_STATE; } } } - if ( TRUE == didTimeout( fpgaFlashStatus.startTime, 100 ) ) + if ( TRUE == didTimeout( fpgaFlashStatus.startTimeMS, 100 ) ) { - // TODO a request multiboot here state = FPGA_IDLE_STATE; } Index: firmware/App/Services/FPGA.h =================================================================== diff -u -r0c085209bea23f66011059a7c19796c1e4b246fa -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/App/Services/FPGA.h (.../FPGA.h) (revision 0c085209bea23f66011059a7c19796c1e4b246fa) +++ firmware/App/Services/FPGA.h (.../FPGA.h) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -33,7 +33,7 @@ BOOL isFPGAFlashComplete( void ); void signalFPGAToPrepareForUpdate( void ); -void signalFPGAToWriteToFlash( U08* data, U32 len ); +BOOL signalFPGAToWriteToFlash( U08* data, U32 len ); void signalFPGAToSelfConfigure( void ); /**@}*/ Index: firmware/App/Services/NVDataMgmt.c =================================================================== diff -u -r292265111b911fa79c52bb4589911dfb60c921bf -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/App/Services/NVDataMgmt.c (.../NVDataMgmt.c) (revision 292265111b911fa79c52bb4589911dfb60c921bf) +++ firmware/App/Services/NVDataMgmt.c (.../NVDataMgmt.c) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -157,7 +157,7 @@ BOOL crcVerifyStatus = FALSE; // Create a buffer of 1 byte and write 0xFFFFFFFF to it - memset( erasedFlashedValue, VALUE_OF_AN_ERASED_FLASH, sizeof( erasedFlashedValue ) ); + memset( &erasedFlashedValue, VALUE_OF_AN_ERASED_FLASH, sizeof( erasedFlashedValue ) ); // Verify the value is not 0xFFFFFFFF reading from the firmware start address crcVerifyStatus = Fapi_doVerify( (U32*)FIRMWARE_CRC_TABLE_ADDRESS, NUM_OF_FIRMWARE_CRC_TABLE_BYTES, Index: firmware/BL.dil =================================================================== diff -u -rab214e8ea52d8433b7cee58f5aaff49fc759310d -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/BL.dil (.../BL.dil) (revision ab214e8ea52d8433b7cee58f5aaff49fc759310d) +++ firmware/BL.dil (.../BL.dil) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -1,4 +1,4 @@ -# RM46L852PGE 03/14/26 14:33:06 +# RM46L852PGE 03/25/26 18:39:11 # ARCH=RM46L852PGE # @@ -139,7 +139,7 @@ DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=110.0 -DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08002800 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08003000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125 DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117 DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109 @@ -407,7 +407,7 @@ DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0 -DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08002c00 +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08005000 DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt @@ -435,7 +435,7 @@ DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11 DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0 -DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08003400 +DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08005800 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0 @@ -502,7 +502,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATEVALUE.VALUE=0x5 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=1 -DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00002000 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00001000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0 @@ -549,14 +549,14 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt -DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000400 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00002000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300 DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=rtiCompare3Interrupt -DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00003400 +DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00005800 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4 @@ -628,7 +628,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0 DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1 -DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002cc00 +DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002a800 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802ffff DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0 @@ -793,7 +793,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29 DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1 DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00140000 -DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000400 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00001000 DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0 @@ -925,8 +925,8 @@ DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800 DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0 -DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08003000 -DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08002000 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08005400 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08001000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=0 DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ @@ -1134,7 +1134,7 @@ DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=1 DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00 -DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08002400 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08002000 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300 DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000 @@ -1184,7 +1184,7 @@ DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1 DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000400 -DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000400 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00001000 DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef Index: firmware/include/sys_core.h =================================================================== diff -u -r0c085209bea23f66011059a7c19796c1e4b246fa -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/include/sys_core.h (.../sys_core.h) (revision 0c085209bea23f66011059a7c19796c1e4b246fa) +++ firmware/include/sys_core.h (.../sys_core.h) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -64,7 +64,7 @@ * * @note: Use this macro for USER Mode Stack length (in bytes) */ -#define USER_STACK_LENGTH 0x00002000U +#define USER_STACK_LENGTH 0x00001000U /** @def SVC_STACK_LENGTH * @brief SVC Mode Stack length (in bytes) @@ -73,7 +73,7 @@ * * @note: Use this macro for SVC Mode Stack length (in bytes) */ -#define SVC_STACK_LENGTH 0x00000400U +#define SVC_STACK_LENGTH 0x00001000U /** @def FIQ_STACK_LENGTH * @brief FIQ Mode Stack length (in bytes) @@ -82,7 +82,7 @@ * * @note: Use this macro for FIQ Mode Stack length (in bytes) */ -#define FIQ_STACK_LENGTH 0x00000400U +#define FIQ_STACK_LENGTH 0x00001000U /** @def IRQ_STACK_LENGTH * @brief IRQ Mode Stack length (in bytes) @@ -91,7 +91,7 @@ * * @note: Use this macro for IRQ Mode Stack length (in bytes) */ -#define IRQ_STACK_LENGTH 0x00000400U +#define IRQ_STACK_LENGTH 0x00002000U /** @def ABORT_STACK_LENGTH * @brief ABORT Mode Stack length (in bytes) Index: firmware/source/sys_core.asm =================================================================== diff -u -r0c085209bea23f66011059a7c19796c1e4b246fa -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/source/sys_core.asm (.../sys_core.asm) (revision 0c085209bea23f66011059a7c19796c1e4b246fa) +++ firmware/source/sys_core.asm (.../sys_core.asm) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -160,12 +160,12 @@ ldr sp, userSp bx lr -userSp .word 0x08000000+0x00002000 -svcSp .word 0x08000000+0x00002000+0x00000400 -fiqSp .word 0x08000000+0x00002000+0x00000400+0x00000400 -irqSp .word 0x08000000+0x00002000+0x00000400+0x00000400+0x00000400 -abortSp .word 0x08000000+0x00002000+0x00000400+0x00000400+0x00000400+0x00000400 -undefSp .word 0x08000000+0x00002000+0x00000400+0x00000400+0x00000400+0x00000400+0x00000400 +userSp .word 0x08000000+0x00001000 +svcSp .word 0x08000000+0x00001000+0x00001000 +fiqSp .word 0x08000000+0x00001000+0x00001000+0x00001000 +irqSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000 +abortSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000+0x00000400 +undefSp .word 0x08000000+0x00001000+0x00001000+0x00001000+0x00002000+0x00000400+0x00000400 .endasmfunc Index: firmware/source/sys_link.cmd =================================================================== diff -u -r0c085209bea23f66011059a7c19796c1e4b246fa -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 0c085209bea23f66011059a7c19796c1e4b246fa) +++ firmware/source/sys_link.cmd (.../sys_link.cmd) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -56,8 +56,8 @@ { VECTORS (X) : origin=0x00000000 length=0x00000020 FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 - STACKS (RW) : origin=0x08000000 length=0x00003400 - RAM (RW) : origin=0x08003400 length=0x0002cc00 + STACKS (RW) : origin=0x08000000 length=0x00005800 + RAM (RW) : origin=0x08005800 length=0x0002a800 /* USER CODE BEGIN (2) */ /* USER CODE END */ Index: firmware/source/sys_main.c =================================================================== diff -u -r0c085209bea23f66011059a7c19796c1e4b246fa -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/source/sys_main.c (.../sys_main.c) (revision 0c085209bea23f66011059a7c19796c1e4b246fa) +++ firmware/source/sys_main.c (.../sys_main.c) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -77,6 +77,9 @@ */ /* USER CODE BEGIN (2) */ +extern U32 apiLoadStart; +extern U32 apiRunStart; +extern U32 apiLoadSize; /* * For reference: * https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/403240/change-load-address-when-debugging-with-tm4c129cnczad @@ -90,6 +93,9 @@ int main(void) { /* USER CODE BEGIN (3) */ + memcpy(&apiRunStart, &apiLoadStart, (uint32)&apiLoadSize); + + initProcessor(); initSoftware(); initTasks(); Index: firmware/source/sys_startup.c =================================================================== diff -u -r0c085209bea23f66011059a7c19796c1e4b246fa -rf6fd9dfd1a30412e237ff45ebee44854f0e2d4b2 --- firmware/source/sys_startup.c (.../sys_startup.c) (revision 0c085209bea23f66011059a7c19796c1e4b246fa) +++ firmware/source/sys_startup.c (.../sys_startup.c) (revision f6fd9dfd1a30412e237ff45ebee44854f0e2d4b2) @@ -629,7 +629,7 @@ /* initialize copy table */ __TI_auto_init(); /* USER CODE BEGIN (75) */ - _copyAPI2RAM_(); + // _copyAPI2RAM_(); /* USER CODE END */ /* call the application */