/*!< Cortex-M3 processor and core peripherals */
+#include "system_ADuCM360.h" /*!< ADUCM360 System */
+
+/** @addtogroup Device_Peripheral_Registers
+ * @{
+ */
+
+
+
+/* ADCCON[ADCEN] - Enable Bit */
+#define ADCCON_ADCEN_MSK (0x1 << 19 )
+#define ADCCON_ADCEN (0x1 << 19 )
+#define ADCCON_ADCEN_DIS (0x0 << 19 ) /* DIS */
+#define ADCCON_ADCEN_EN (0x1 << 19 ) /* EN */
+
+/* ADCCON[ADCCODE] - ADC Output Coding bits */
+#define ADCCON_ADCCODE_MSK (0x1 << 18 )
+#define ADCCON_ADCCODE (0x1 << 18 )
+#define ADCCON_ADCCODE_INT (0x0 << 18 ) /* INT */
+#define ADCCON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
+
+/* ADCCON[BUFPOWN] - Negative buffer power down */
+#define ADCCON_BUFPOWN_MSK (0x1 << 17 )
+#define ADCCON_BUFPOWN (0x1 << 17 )
+#define ADCCON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
+#define ADCCON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
+
+/* ADCCON[BUFPOWP] - Positive buffer power down */
+#define ADCCON_BUFPOWP_MSK (0x1 << 16 )
+#define ADCCON_BUFPOWP (0x1 << 16 )
+#define ADCCON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
+#define ADCCON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
+
+/* ADCCON[BUFBYPP] - Positive buffer bypass */
+#define ADCCON_BUFBYPP_MSK (0x1 << 15 )
+#define ADCCON_BUFBYPP (0x1 << 15 )
+#define ADCCON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
+#define ADCCON_BUFBYPP_EN (0x1 << 15 ) /* EN */
+
+/* ADCCON[BUFBYPN] - Negative buffer bypass */
+#define ADCCON_BUFBYPN_MSK (0x1 << 14 )
+#define ADCCON_BUFBYPN (0x1 << 14 )
+#define ADCCON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
+#define ADCCON_BUFBYPN_EN (0x1 << 14 ) /* EN */
+
+/* ADCCON[ADCREF] - Reference selection */
+#define ADCCON_ADCREF_MSK (0x3 << 12 )
+#define ADCCON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
+#define ADCCON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
+#define ADCCON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
+#define ADCCON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
+
+/* ADCCON[ADCDIAG] - Diagnostic Current bits bits */
+#define ADCCON_ADCDIAG_MSK (0x3 << 10 )
+#define ADCCON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
+#define ADCCON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
+#define ADCCON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
+#define ADCCON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
+
+/* ADCCON[ADCCP] - AIN+ bits */
+#define ADCCON_ADCCP_MSK (0x1F << 5 )
+#define ADCCON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
+#define ADCCON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
+#define ADCCON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
+#define ADCCON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
+#define ADCCON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
+#define ADCCON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
+#define ADCCON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
+#define ADCCON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
+#define ADCCON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
+#define ADCCON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
+#define ADCCON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
+#define ADCCON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
+#define ADCCON_ADCCP_DAC (0xC << 5 ) /* DAC */
+#define ADCCON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
+#define ADCCON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
+#define ADCCON_ADCCP_AGND (0xF << 5 ) /* AGND */
+#define ADCCON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
+
+/* ADCCON[ADCCN] - AIN- bits */
+#define ADCCON_ADCCN_MSK (0x1F << 0 )
+#define ADCCON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
+#define ADCCON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
+#define ADCCON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
+#define ADCCON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
+#define ADCCON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
+#define ADCCON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
+#define ADCCON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
+#define ADCCON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
+#define ADCCON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
+#define ADCCON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
+#define ADCCON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
+#define ADCCON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
+#define ADCCON_ADCCN_DAC (0xC << 0 ) /* DAC */
+#define ADCCON_ADCCN_AGND (0xF << 0 ) /* AGND */
+#define ADCCON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
+
+/* ADCMDE[PGA] - PGA Gain Select bit */
+#define ADCMDE_PGA_MSK (0xF << 4 )
+#define ADCMDE_PGA_G1 (0x0 << 4 ) /* G1 */
+#define ADCMDE_PGA_G2 (0x1 << 4 ) /* G2 */
+#define ADCMDE_PGA_G4 (0x2 << 4 ) /* G4 */
+#define ADCMDE_PGA_G8 (0x3 << 4 ) /* G8 */
+#define ADCMDE_PGA_G16 (0x4 << 4 ) /* G16 */
+#define ADCMDE_PGA_G32 (0x5 << 4 ) /* G32 */
+#define ADCMDE_PGA_G64 (0x6 << 4 ) /* G64 */
+#define ADCMDE_PGA_G128 (0x7 << 4 ) /* G128 */
+
+/* ADCMDE[ADCMOD2] - ADC modulator gain of 2 control bits */
+#define ADCMDE_ADCMOD2_MSK (0x1 << 3 )
+#define ADCMDE_ADCMOD2 (0x1 << 3 )
+#define ADCMDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
+#define ADCMDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
+
+/* ADCMDE[ADCMD] - ADC Mode bits */
+#define ADCMDE_ADCMD_MSK (0x7 << 0 )
+#define ADCMDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
+#define ADCMDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
+#define ADCMDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
+#define ADCMDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
+#define ADCMDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
+#define ADCMDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
+#define ADCMDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
+#define ADCMDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
+
+/* ADCMSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
+#define ADCMSKI_ATHEX_MSK (0x1 << 3 )
+#define ADCMSKI_ATHEX (0x1 << 3 )
+#define ADCMSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
+#define ADCMSKI_ATHEX_EN (0x1 << 3 ) /* EN */
+
+/* ADCMSKI[THEX] - ADC comparator threshold mask */
+#define ADCMSKI_THEX_MSK (0x1 << 2 )
+#define ADCMSKI_THEX (0x1 << 2 )
+#define ADCMSKI_THEX_DIS (0x0 << 2 ) /* DIS */
+#define ADCMSKI_THEX_EN (0x1 << 2 ) /* EN */
+
+/* ADCMSKI[OVR] - ADC overrange bit mask. */
+#define ADCMSKI_OVR_MSK (0x1 << 1 )
+#define ADCMSKI_OVR (0x1 << 1 )
+#define ADCMSKI_OVR_DIS (0x0 << 1 ) /* DIS */
+#define ADCMSKI_OVR_EN (0x1 << 1 ) /* EN */
+
+/* ADCMSKI[RDY] - valid conversion result mask */
+#define ADCMSKI_RDY_MSK (0x1 << 0 )
+#define ADCMSKI_RDY (0x1 << 0 )
+#define ADCMSKI_RDY_DIS (0x0 << 0 ) /* DIS */
+#define ADCMSKI_RDY_EN (0x1 << 0 ) /* EN */
+
+/* ADCFLT[CHOP] - Enables System-Chopping bits */
+#define ADCFLT_CHOP_MSK (0x1 << 15 )
+#define ADCFLT_CHOP (0x1 << 15 )
+#define ADCFLT_CHOP_OFF (0x0 << 15 ) /* OFF */
+#define ADCFLT_CHOP_ON (0x1 << 15 ) /* ON */
+
+/* ADCFLT[RAVG2] - Enables a running Average-By-2 bits */
+#define ADCFLT_RAVG2_MSK (0x1 << 14 )
+#define ADCFLT_RAVG2 (0x1 << 14 )
+#define ADCFLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
+#define ADCFLT_RAVG2_ON (0x1 << 14 ) /* ON */
+
+/* ADCFLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
+#define ADCFLT_SINC4EN_MSK (0x1 << 12 )
+#define ADCFLT_SINC4EN (0x1 << 12 )
+#define ADCFLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
+#define ADCFLT_SINC4EN_EN (0x1 << 12 ) /* EN */
+
+/* ADCFLT[AF] - Averaging filter */
+#define ADCFLT_AF_MSK (0xF << 8 )
+
+/* ADCFLT[NOTCH2] - Inserts a notch at FNOTCH2 */
+#define ADCFLT_NOTCH2_MSK (0x1 << 7 )
+#define ADCFLT_NOTCH2 (0x1 << 7 )
+#define ADCFLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
+#define ADCFLT_NOTCH2_EN (0x1 << 7 ) /* EN */
+
+/* ADCFLT[SF] - SINC Filter value */
+#define ADCFLT_SF_MSK (0x7F << 0 )
+
+/* TCON[EVENTEN] - Enable time capture of an event */
+#define TCON_EVENTEN_MSK (0x1 << 12 )
+#define TCON_EVENTEN (0x1 << 12 )
+#define TCON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
+#define TCON_EVENTEN_EN (0x1 << 12 ) /* EN */
+
+/* TCON[EVENT] - Event Select, selects 1 of the available events. */
+#define TCON_EVENT_MSK (0xF << 8 )
+
+/* TCON[RLD] - Timer reload on write to clear register */
+#define TCON_RLD_MSK (0x1 << 7 )
+#define TCON_RLD (0x1 << 7 )
+#define TCON_RLD_DIS (0x0 << 7 ) /* DIS */
+#define TCON_RLD_EN (0x1 << 7 ) /* EN */
+
+/* TCON[CLK] - Clock Select */
+#define TCON_CLK_MSK (0x3 << 5 )
+#define TCON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
+#define TCON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
+#define TCON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
+#define TCON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
+
+/* TCON[ENABLE] - Enable */
+#define TCON_ENABLE_MSK (0x1 << 4 )
+#define TCON_ENABLE (0x1 << 4 )
+#define TCON_ENABLE_DIS (0x0 << 4 ) /* DIS */
+#define TCON_ENABLE_EN (0x1 << 4 ) /* EN */
+
+/* TCON[MOD] - Mode */
+#define TCON_MOD_MSK (0x1 << 3 )
+#define TCON_MOD (0x1 << 3 )
+#define TCON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
+#define TCON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
+
+/* TCON[UP] - Count-up */
+#define TCON_UP_MSK (0x1 << 2 )
+#define TCON_UP (0x1 << 2 )
+#define TCON_UP_DIS (0x0 << 2 ) /* DIS */
+#define TCON_UP_EN (0x1 << 2 ) /* EN */
+
+/* TCON[PRE] - Prescaler */
+#define TCON_PRE_MSK (0x3 << 0 )
+#define TCON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
+#define TCON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
+#define TCON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
+#define TCON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
+
+/* TCLRI[CAP] - Clear captured event interrupt */
+#define TCLRI_CAP_MSK (0x1 << 1 )
+#define TCLRI_CAP (0x1 << 1 )
+#define TCLRI_CAP_CLR (0x1 << 1 ) /* CLR */
+
+/* TCLRI[TMOUT] - Clear timeout interrupt */
+#define TCLRI_TMOUT_MSK (0x1 << 0 )
+#define TCLRI_TMOUT (0x1 << 0 )
+#define TCLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
+
+/* TSTA[CLRI] - Value updated in the timer clock domain */
+#define TSTA_CLRI_MSK (0x1 << 7 )
+#define TSTA_CLRI (0x1 << 7 )
+#define TSTA_CLRI_CLR (0x0 << 7 ) /* CLR */
+#define TSTA_CLRI_SET (0x1 << 7 ) /* SET */
+
+/* TSTA[CON] - Ready to receive commands */
+#define TSTA_CON_MSK (0x1 << 6 )
+#define TSTA_CON (0x1 << 6 )
+#define TSTA_CON_CLR (0x0 << 6 ) /* CLR */
+#define TSTA_CON_SET (0x1 << 6 ) /* SET */
+
+/* TSTA[CAP] - Capture event pending */
+#define TSTA_CAP_MSK (0x1 << 1 )
+#define TSTA_CAP (0x1 << 1 )
+#define TSTA_CAP_CLR (0x0 << 1 ) /* CLR */
+#define TSTA_CAP_SET (0x1 << 1 ) /* SET */
+
+/* TSTA[TMOUT] - Time out event occurred */
+#define TSTA_TMOUT_MSK (0x1 << 0 )
+#define TSTA_TMOUT (0x1 << 0 )
+#define TSTA_TMOUT_CLR (0x0 << 0 ) /* CLR */
+#define TSTA_TMOUT_SET (0x1 << 0 ) /* SET */
+
+/* GPCON[CON7] - Configuration bits for P0.7 */
+#define GPCON_CON7_MSK (0x3 << 14 )
+
+/* GPCON[CON6] - Configuration bits for P0.6 */
+#define GPCON_CON6_MSK (0x3 << 12 )
+
+/* GPCON[CON5] - Configuration bits for P0.5 */
+#define GPCON_CON5_MSK (0x3 << 10 )
+
+/* GPCON[CON4] - Configuration bits for P0.4 */
+#define GPCON_CON4_MSK (0x3 << 8 )
+
+/* GPCON[CON3] - Configuration bits for P0.3 */
+#define GPCON_CON3_MSK (0x3 << 6 )
+
+/* GPCON[CON2] - Configuration bits for P0.2 */
+#define GPCON_CON2_MSK (0x3 << 4 )
+
+/* GPCON[CON1] - Configuration bits for P0.1 */
+#define GPCON_CON1_MSK (0x3 << 2 )
+
+/* GPCON[CON0] - Configuration bits for P0.0 */
+#define GPCON_CON0_MSK (0x3 << 0 )
+
+/* GPOEN[OEN7] - Direction for port pin */
+#define GPOEN_OEN7_MSK (0x1 << 7 )
+#define GPOEN_OEN7 (0x1 << 7 )
+#define GPOEN_OEN7_IN (0x0 << 7 ) /* IN */
+#define GPOEN_OEN7_OUT (0x1 << 7 ) /* OUT */
+
+/* GPOEN[OEN6] - Direction for port pin */
+#define GPOEN_OEN6_MSK (0x1 << 6 )
+#define GPOEN_OEN6 (0x1 << 6 )
+#define GPOEN_OEN6_IN (0x0 << 6 ) /* IN */
+#define GPOEN_OEN6_OUT (0x1 << 6 ) /* OUT */
+
+/* GPOEN[OEN5] - Direction for port pin */
+#define GPOEN_OEN5_MSK (0x1 << 5 )
+#define GPOEN_OEN5 (0x1 << 5 )
+#define GPOEN_OEN5_IN (0x0 << 5 ) /* IN */
+#define GPOEN_OEN5_OUT (0x1 << 5 ) /* OUT */
+
+/* GPOEN[OEN4] - Direction for port pin */
+#define GPOEN_OEN4_MSK (0x1 << 4 )
+#define GPOEN_OEN4 (0x1 << 4 )
+#define GPOEN_OEN4_IN (0x0 << 4 ) /* IN */
+#define GPOEN_OEN4_OUT (0x1 << 4 ) /* OUT */
+
+/* GPOEN[OEN3] - Direction for port pin */
+#define GPOEN_OEN3_MSK (0x1 << 3 )
+#define GPOEN_OEN3 (0x1 << 3 )
+#define GPOEN_OEN3_IN (0x0 << 3 ) /* IN */
+#define GPOEN_OEN3_OUT (0x1 << 3 ) /* OUT */
+
+/* GPOEN[OEN2] - Direction for port pin */
+#define GPOEN_OEN2_MSK (0x1 << 2 )
+#define GPOEN_OEN2 (0x1 << 2 )
+#define GPOEN_OEN2_IN (0x0 << 2 ) /* IN */
+#define GPOEN_OEN2_OUT (0x1 << 2 ) /* OUT */
+
+/* GPOEN[OEN1] - Direction for port pin */
+#define GPOEN_OEN1_MSK (0x1 << 1 )
+#define GPOEN_OEN1 (0x1 << 1 )
+#define GPOEN_OEN1_IN (0x0 << 1 ) /* IN */
+#define GPOEN_OEN1_OUT (0x1 << 1 ) /* OUT */
+
+/* GPOEN[OEN0] - Direction for port pin */
+#define GPOEN_OEN0_MSK (0x1 << 0 )
+#define GPOEN_OEN0 (0x1 << 0 )
+#define GPOEN_OEN0_IN (0x0 << 0 ) /* IN */
+#define GPOEN_OEN0_OUT (0x1 << 0 ) /* OUT */
+
+/* GPIN[IN7] - Input for port pin */
+#define GPIN_IN7_MSK (0x1 << 7 )
+#define GPIN_IN7 (0x1 << 7 )
+#define GPIN_IN7_LOW (0x0 << 7 ) /* LOW */
+#define GPIN_IN7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GPIN[IN6] - Input for port pin */
+#define GPIN_IN6_MSK (0x1 << 6 )
+#define GPIN_IN6 (0x1 << 6 )
+#define GPIN_IN6_LOW (0x0 << 6 ) /* LOW */
+#define GPIN_IN6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GPIN[IN5] - Input for port pin */
+#define GPIN_IN5_MSK (0x1 << 5 )
+#define GPIN_IN5 (0x1 << 5 )
+#define GPIN_IN5_LOW (0x0 << 5 ) /* LOW */
+#define GPIN_IN5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GPIN[IN4] - Input for port pin */
+#define GPIN_IN4_MSK (0x1 << 4 )
+#define GPIN_IN4 (0x1 << 4 )
+#define GPIN_IN4_LOW (0x0 << 4 ) /* LOW */
+#define GPIN_IN4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GPIN[IN3] - Input for port pin */
+#define GPIN_IN3_MSK (0x1 << 3 )
+#define GPIN_IN3 (0x1 << 3 )
+#define GPIN_IN3_LOW (0x0 << 3 ) /* LOW */
+#define GPIN_IN3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GPIN[IN2] - Input for port pin */
+#define GPIN_IN2_MSK (0x1 << 2 )
+#define GPIN_IN2 (0x1 << 2 )
+#define GPIN_IN2_LOW (0x0 << 2 ) /* LOW */
+#define GPIN_IN2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GPIN[IN1] - Input for port pin */
+#define GPIN_IN1_MSK (0x1 << 1 )
+#define GPIN_IN1 (0x1 << 1 )
+#define GPIN_IN1_LOW (0x0 << 1 ) /* LOW */
+#define GPIN_IN1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GPIN[IN0] - Input for port pin */
+#define GPIN_IN0_MSK (0x1 << 0 )
+#define GPIN_IN0 (0x1 << 0 )
+#define GPIN_IN0_LOW (0x0 << 0 ) /* LOW */
+#define GPIN_IN0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* GPOUT[OUT7] - Output for port pin */
+#define GPOUT_OUT7_MSK (0x1 << 7 )
+#define GPOUT_OUT7 (0x1 << 7 )
+#define GPOUT_OUT7_LOW (0x0 << 7 ) /* LOW */
+#define GPOUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GPOUT[OUT6] - Output for port pin */
+#define GPOUT_OUT6_MSK (0x1 << 6 )
+#define GPOUT_OUT6 (0x1 << 6 )
+#define GPOUT_OUT6_LOW (0x0 << 6 ) /* LOW */
+#define GPOUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GPOUT[OUT5] - Output for port pin */
+#define GPOUT_OUT5_MSK (0x1 << 5 )
+#define GPOUT_OUT5 (0x1 << 5 )
+#define GPOUT_OUT5_LOW (0x0 << 5 ) /* LOW */
+#define GPOUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GPOUT[OUT4] - Output for port pin */
+#define GPOUT_OUT4_MSK (0x1 << 4 )
+#define GPOUT_OUT4 (0x1 << 4 )
+#define GPOUT_OUT4_LOW (0x0 << 4 ) /* LOW */
+#define GPOUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GPOUT[OUT3] - Output for port pin */
+#define GPOUT_OUT3_MSK (0x1 << 3 )
+#define GPOUT_OUT3 (0x1 << 3 )
+#define GPOUT_OUT3_LOW (0x0 << 3 ) /* LOW */
+#define GPOUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GPOUT[OUT2] - Output for port pin */
+#define GPOUT_OUT2_MSK (0x1 << 2 )
+#define GPOUT_OUT2 (0x1 << 2 )
+#define GPOUT_OUT2_LOW (0x0 << 2 ) /* LOW */
+#define GPOUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GPOUT[OUT1] - Output for port pin */
+#define GPOUT_OUT1_MSK (0x1 << 1 )
+#define GPOUT_OUT1 (0x1 << 1 )
+#define GPOUT_OUT1_LOW (0x0 << 1 ) /* LOW */
+#define GPOUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GPOUT[OUT0] - Output for port pin */
+#define GPOUT_OUT0_MSK (0x1 << 0 )
+#define GPOUT_OUT0 (0x1 << 0 )
+#define GPOUT_OUT0_LOW (0x0 << 0 ) /* LOW */
+#define GPOUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* GPSET[SET7] - Set Output High for port pin */
+#define GPSET_SET7_MSK (0x1 << 7 )
+#define GPSET_SET7 (0x1 << 7 )
+#define GPSET_SET7_SET (0x1 << 7 ) /* SET */
+
+/* GPSET[SET6] - Set Output High for port pin */
+#define GPSET_SET6_MSK (0x1 << 6 )
+#define GPSET_SET6 (0x1 << 6 )
+#define GPSET_SET6_SET (0x1 << 6 ) /* SET */
+
+/* GPSET[SET5] - Set Output High for port pin */
+#define GPSET_SET5_MSK (0x1 << 5 )
+#define GPSET_SET5 (0x1 << 5 )
+#define GPSET_SET5_SET (0x1 << 5 ) /* SET */
+
+/* GPSET[SET4] - Set Output High for port pin */
+#define GPSET_SET4_MSK (0x1 << 4 )
+#define GPSET_SET4 (0x1 << 4 )
+#define GPSET_SET4_SET (0x1 << 4 ) /* SET */
+
+/* GPSET[SET3] - Set Output High for port pin */
+#define GPSET_SET3_MSK (0x1 << 3 )
+#define GPSET_SET3 (0x1 << 3 )
+#define GPSET_SET3_SET (0x1 << 3 ) /* SET */
+
+/* GPSET[SET2] - Set Output High for port pin */
+#define GPSET_SET2_MSK (0x1 << 2 )
+#define GPSET_SET2 (0x1 << 2 )
+#define GPSET_SET2_SET (0x1 << 2 ) /* SET */
+
+/* GPSET[SET1] - Set Output High for port pin */
+#define GPSET_SET1_MSK (0x1 << 1 )
+#define GPSET_SET1 (0x1 << 1 )
+#define GPSET_SET1_SET (0x1 << 1 ) /* SET */
+
+/* GPSET[SET0] - Set Output High for port pin */
+#define GPSET_SET0_MSK (0x1 << 0 )
+#define GPSET_SET0 (0x1 << 0 )
+#define GPSET_SET0_SET (0x1 << 0 ) /* SET */
+
+/* GPCLR[CLR7] - Set Output Low for port pin */
+#define GPCLR_CLR7_MSK (0x1 << 7 )
+#define GPCLR_CLR7 (0x1 << 7 )
+#define GPCLR_CLR7_CLR (0x1 << 7 ) /* CLR */
+
+/* GPCLR[CLR6] - Set Output Low for port pin */
+#define GPCLR_CLR6_MSK (0x1 << 6 )
+#define GPCLR_CLR6 (0x1 << 6 )
+#define GPCLR_CLR6_CLR (0x1 << 6 ) /* CLR */
+
+/* GPCLR[CLR5] - Set Output Low for port pin */
+#define GPCLR_CLR5_MSK (0x1 << 5 )
+#define GPCLR_CLR5 (0x1 << 5 )
+#define GPCLR_CLR5_CLR (0x1 << 5 ) /* CLR */
+
+/* GPCLR[CLR4] - Set Output Low for port pin */
+#define GPCLR_CLR4_MSK (0x1 << 4 )
+#define GPCLR_CLR4 (0x1 << 4 )
+#define GPCLR_CLR4_CLR (0x1 << 4 ) /* CLR */
+
+/* GPCLR[CLR3] - Set Output Low for port pin */
+#define GPCLR_CLR3_MSK (0x1 << 3 )
+#define GPCLR_CLR3 (0x1 << 3 )
+#define GPCLR_CLR3_CLR (0x1 << 3 ) /* CLR */
+
+/* GPCLR[CLR2] - Set Output Low for port pin */
+#define GPCLR_CLR2_MSK (0x1 << 2 )
+#define GPCLR_CLR2 (0x1 << 2 )
+#define GPCLR_CLR2_CLR (0x1 << 2 ) /* CLR */
+
+/* GPCLR[CLR1] - Set Output Low for port pin */
+#define GPCLR_CLR1_MSK (0x1 << 1 )
+#define GPCLR_CLR1 (0x1 << 1 )
+#define GPCLR_CLR1_CLR (0x1 << 1 ) /* CLR */
+
+/* GPCLR[CLR0] - Set Output Low for port pin */
+#define GPCLR_CLR0_MSK (0x1 << 0 )
+#define GPCLR_CLR0 (0x1 << 0 )
+#define GPCLR_CLR0_CLR (0x1 << 0 ) /* CLR */
+
+/* GPTGL[TGL7] - Toggle Output for port pin */
+#define GPTGL_TGL7_MSK (0x1 << 7 )
+#define GPTGL_TGL7 (0x1 << 7 )
+#define GPTGL_TGL7_TGL (0x1 << 7 ) /* TGL */
+
+/* GPTGL[TGL6] - Toggle Output for port pin */
+#define GPTGL_TGL6_MSK (0x1 << 6 )
+#define GPTGL_TGL6 (0x1 << 6 )
+#define GPTGL_TGL6_TGL (0x1 << 6 ) /* TGL */
+
+/* GPTGL[TGL5] - Toggle Output for port pin */
+#define GPTGL_TGL5_MSK (0x1 << 5 )
+#define GPTGL_TGL5 (0x1 << 5 )
+#define GPTGL_TGL5_TGL (0x1 << 5 ) /* TGL */
+
+/* GPTGL[TGL4] - Toggle Output for port pin */
+#define GPTGL_TGL4_MSK (0x1 << 4 )
+#define GPTGL_TGL4 (0x1 << 4 )
+#define GPTGL_TGL4_TGL (0x1 << 4 ) /* TGL */
+
+/* GPTGL[TGL3] - Toggle Output for port pin */
+#define GPTGL_TGL3_MSK (0x1 << 3 )
+#define GPTGL_TGL3 (0x1 << 3 )
+#define GPTGL_TGL3_TGL (0x1 << 3 ) /* TGL */
+
+/* GPTGL[TGL2] - Toggle Output for port pin */
+#define GPTGL_TGL2_MSK (0x1 << 2 )
+#define GPTGL_TGL2 (0x1 << 2 )
+#define GPTGL_TGL2_TGL (0x1 << 2 ) /* TGL */
+
+/* GPTGL[TGL1] - Toggle Output for port pin */
+#define GPTGL_TGL1_MSK (0x1 << 1 )
+#define GPTGL_TGL1 (0x1 << 1 )
+#define GPTGL_TGL1_TGL (0x1 << 1 ) /* TGL */
+
+/* GPTGL[TGL0] - Toggle Output for port pin */
+#define GPTGL_TGL0_MSK (0x1 << 0 )
+#define GPTGL_TGL0 (0x1 << 0 )
+#define GPTGL_TGL0_TGL (0x1 << 0 ) /* TGL */
+
+/* SPIDIV[BCRST] - Bit counter reset */
+#define SPIDIV_BCRST_MSK (0x1 << 7 )
+#define SPIDIV_BCRST (0x1 << 7 )
+#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
+#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
+
+/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
+#define SPIDIV_DIV_MSK (0x3F << 0 )
+
+/* SPICON[MOD] - SPI IRQ Mode bits */
+#define SPICON_MOD_MSK (0x3 << 14 )
+#define SPICON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
+#define SPICON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
+#define SPICON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
+#define SPICON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
+
+/* SPICON[TFLUSH] - TX FIFO Flush Enable bit */
+#define SPICON_TFLUSH_MSK (0x1 << 13 )
+#define SPICON_TFLUSH (0x1 << 13 )
+#define SPICON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
+#define SPICON_TFLUSH_EN (0x1 << 13 ) /* EN */
+
+/* SPICON[RFLUSH] - RX FIFO Flush Enable bit */
+#define SPICON_RFLUSH_MSK (0x1 << 12 )
+#define SPICON_RFLUSH (0x1 << 12 )
+#define SPICON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
+#define SPICON_RFLUSH_EN (0x1 << 12 ) /* EN */
+
+/* SPICON[CON] - Continuous transfer enable */
+#define SPICON_CON_MSK (0x1 << 11 )
+#define SPICON_CON (0x1 << 11 )
+#define SPICON_CON_DIS (0x0 << 11 ) /* DIS */
+#define SPICON_CON_EN (0x1 << 11 ) /* EN */
+
+/* SPICON[LOOPBACK] - Loopback enable bit */
+#define SPICON_LOOPBACK_MSK (0x1 << 10 )
+#define SPICON_LOOPBACK (0x1 << 10 )
+#define SPICON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
+#define SPICON_LOOPBACK_EN (0x1 << 10 ) /* EN */
+
+/* SPICON[SOEN] - Slave MISO output enable bit */
+#define SPICON_SOEN_MSK (0x1 << 9 )
+#define SPICON_SOEN (0x1 << 9 )
+#define SPICON_SOEN_DIS (0x0 << 9 ) /* DIS */
+#define SPICON_SOEN_EN (0x1 << 9 ) /* EN */
+
+/* SPICON[RXOF] - RX Oveflow Overwrite enable */
+#define SPICON_RXOF_MSK (0x1 << 8 )
+#define SPICON_RXOF (0x1 << 8 )
+#define SPICON_RXOF_DIS (0x0 << 8 ) /* DIS */
+#define SPICON_RXOF_EN (0x1 << 8 ) /* EN */
+
+/* SPICON[ZEN] - Transmit zeros when empty */
+#define SPICON_ZEN_MSK (0x1 << 7 )
+#define SPICON_ZEN (0x1 << 7 )
+#define SPICON_ZEN_DIS (0x0 << 7 ) /* DIS */
+#define SPICON_ZEN_EN (0x1 << 7 ) /* EN */
+
+/* SPICON[TIM] - Transfer and interrupt mode */
+#define SPICON_TIM_MSK (0x1 << 6 )
+#define SPICON_TIM (0x1 << 6 )
+#define SPICON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
+#define SPICON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
+
+/* SPICON[LSB] - LSB First Transfer enable */
+#define SPICON_LSB_MSK (0x1 << 5 )
+#define SPICON_LSB (0x1 << 5 )
+#define SPICON_LSB_DIS (0x0 << 5 ) /* DIS */
+#define SPICON_LSB_EN (0x1 << 5 ) /* EN */
+
+/* SPICON[WOM] - Wired OR enable */
+#define SPICON_WOM_MSK (0x1 << 4 )
+#define SPICON_WOM (0x1 << 4 )
+#define SPICON_WOM_DIS (0x0 << 4 ) /* DIS */
+#define SPICON_WOM_EN (0x1 << 4 ) /* EN */
+
+/* SPICON[CPOL] - Clock polarity mode */
+#define SPICON_CPOL_MSK (0x1 << 3 )
+#define SPICON_CPOL (0x1 << 3 )
+#define SPICON_CPOL_LOW (0x0 << 3 ) /* LOW */
+#define SPICON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
+
+/* SPICON[CPHA] - Clock phase mode */
+#define SPICON_CPHA_MSK (0x1 << 2 )
+#define SPICON_CPHA (0x1 << 2 )
+#define SPICON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
+#define SPICON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
+
+/* SPICON[MASEN] - Master enable */
+#define SPICON_MASEN_MSK (0x1 << 1 )
+#define SPICON_MASEN (0x1 << 1 )
+#define SPICON_MASEN_DIS (0x0 << 1 ) /* DIS */
+#define SPICON_MASEN_EN (0x1 << 1 ) /* EN */
+
+/* SPICON[ENABLE] - SPI Enable bit */
+#define SPICON_ENABLE_MSK (0x1 << 0 )
+#define SPICON_ENABLE (0x1 << 0 )
+#define SPICON_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define SPICON_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* SPIDMA[IENRXDMA] - Enable receive DMA request */
+#define SPIDMA_IENRXDMA_MSK (0x1 << 2 )
+#define SPIDMA_IENRXDMA (0x1 << 2 )
+#define SPIDMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
+#define SPIDMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
+
+/* SPIDMA[IENTXDMA] - Enable transmit DMA request */
+#define SPIDMA_IENTXDMA_MSK (0x1 << 1 )
+#define SPIDMA_IENTXDMA (0x1 << 1 )
+#define SPIDMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
+#define SPIDMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
+
+/* SPIDMA[ENABLE] - Enable DMA for data transfer */
+#define SPIDMA_ENABLE_MSK (0x1 << 0 )
+#define SPIDMA_ENABLE (0x1 << 0 )
+#define SPIDMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define SPIDMA_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* SPISTA[CSERR] - Detected an abrupt CS deassertion */
+#define SPISTA_CSERR_MSK (0x1 << 12 )
+#define SPISTA_CSERR (0x1 << 12 )
+#define SPISTA_CSERR_CLR (0x0 << 12 ) /* CLR */
+#define SPISTA_CSERR_SET (0x1 << 12 ) /* SET */
+
+/* SPISTA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
+#define SPISTA_RXS_MSK (0x1 << 11 )
+#define SPISTA_RXS (0x1 << 11 )
+#define SPISTA_RXS_CLR (0x0 << 11 ) /* CLR */
+#define SPISTA_RXS_SET (0x1 << 11 ) /* SET */
+
+/* SPISTA[RXFSTA] - Receive FIFO Status */
+#define SPISTA_RXFSTA_MSK (0x7 << 8 )
+#define SPISTA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
+#define SPISTA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
+#define SPISTA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
+#define SPISTA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
+#define SPISTA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
+
+/* SPISTA[RXOF] - Receive FIFO overflow */
+#define SPISTA_RXOF_MSK (0x1 << 7 )
+#define SPISTA_RXOF (0x1 << 7 )
+#define SPISTA_RXOF_CLR (0x0 << 7 ) /* CLR */
+#define SPISTA_RXOF_SET (0x1 << 7 ) /* SET */
+
+/* SPISTA[RX] - Set when a receive interrupt occurs */
+#define SPISTA_RX_MSK (0x1 << 6 )
+#define SPISTA_RX (0x1 << 6 )
+#define SPISTA_RX_CLR (0x0 << 6 ) /* CLR */
+#define SPISTA_RX_SET (0x1 << 6 ) /* SET */
+
+/* SPISTA[TX] - Set when a transmit interrupt occurs */
+#define SPISTA_TX_MSK (0x1 << 5 )
+#define SPISTA_TX (0x1 << 5 )
+#define SPISTA_TX_CLR (0x0 << 5 ) /* CLR */
+#define SPISTA_TX_SET (0x1 << 5 ) /* SET */
+
+/* SPISTA[TXUR] - Transmit FIFO underflow */
+#define SPISTA_TXUR_MSK (0x1 << 4 )
+#define SPISTA_TXUR (0x1 << 4 )
+#define SPISTA_TXUR_CLR (0x0 << 4 ) /* CLR */
+#define SPISTA_TXUR_SET (0x1 << 4 ) /* SET */
+
+/* SPISTA[TXFSTA] - transmit FIFO Status */
+#define SPISTA_TXFSTA_MSK (0x7 << 1 )
+#define SPISTA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
+#define SPISTA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
+#define SPISTA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
+#define SPISTA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
+#define SPISTA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
+
+/* SPISTA[IRQ] - Interrupt status bit */
+#define SPISTA_IRQ_MSK (0x1 << 0 )
+#define SPISTA_IRQ (0x1 << 0 )
+#define SPISTA_IRQ_CLR (0x0 << 0 ) /* CLR */
+#define SPISTA_IRQ_SET (0x1 << 0 ) /* SET */
+
+/* SPIDIV[BCRST] - Bit counter reset */
+#define SPIDIV_BCRST_MSK (0x1 << 7 )
+#define SPIDIV_BCRST (0x1 << 7 )
+#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
+#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
+
+/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
+#define SPIDIV_DIV_MSK (0x3F << 0 )
+// ------------------------------------------------------------------------------------------------
+// ----- T0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Timer 0 (pADI_TM0)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_TM0 Structure */
+ __IO uint16_t
+ LD; /*!< 16-bit load value */
+ __I uint16_t RESERVED0;
+ __IO uint16_t
+ VAL; /*!< "16-bit timer value, read only." */
+ __I uint16_t RESERVED1;
+ __IO uint16_t
+ CON; /*!< Control Register */
+ __I uint16_t RESERVED2;
+ __IO uint16_t
+ CLRI; /*!< Clear interrupt register */
+ __I uint16_t RESERVED3;
+ __IO uint16_t
+ CAP; /*!< Capture Register */
+ __I uint16_t RESERVED4[5];
+ __IO uint16_t
+ STA; /*!< Status Register */
+} ADI_TIMER_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define T0LD (*(volatile unsigned short int *) 0x40000000)
+#define T0VAL (*(volatile unsigned short int *) 0x40000004)
+#define T0CON (*(volatile unsigned short int *) 0x40000008)
+#define T0CLRI (*(volatile unsigned short int *) 0x4000000C)
+#define T0CAP (*(volatile unsigned short int *) 0x40000010)
+#define T0STA (*(volatile unsigned short int *) 0x4000001C)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for T0LD*/
+#define T0LD_RVAL 0x0
+
+/* T0LD[VALUE] - Load value */
+#define T0LD_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T0VAL*/
+#define T0VAL_RVAL 0x0
+
+/* T0VAL[VALUE] - Current value */
+#define T0VAL_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T0CON*/
+#define T0CON_RVAL 0xA
+
+/* T0CON[EVENTEN] - Enable time capture of an event */
+#define T0CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42000130)
+#define T0CON_EVENTEN_MSK (0x1 << 12 )
+#define T0CON_EVENTEN (0x1 << 12 )
+#define T0CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
+#define T0CON_EVENTEN_EN (0x1 << 12 ) /* EN */
+
+/* T0CON[EVENT] - Event Select, selects 1 of the available events. */
+#define T0CON_EVENT_MSK (0xF << 8 )
+#define T0CON_EVENT_T2 (0x0 << 8 ) /* T2 - Wakeup Timer */
+#define T0CON_EVENT_EXT0 (0x1 << 8 ) /* EXT0 - External interrupt 0 */
+#define T0CON_EVENT_EXT1 (0x2 << 8 ) /* EXT1 - External interrupt 1 */
+#define T0CON_EVENT_EXT2 (0x3 << 8 ) /* EXT2 - External interrupt 2 */
+#define T0CON_EVENT_EXT3 (0x4 << 8 ) /* EXT3 - External interrupt 3 */
+#define T0CON_EVENT_EXT4 (0x5 << 8 ) /* EXT4 - External interrupt 4 */
+#define T0CON_EVENT_EXT5 (0x6 << 8 ) /* EXT5 - External interrupt 5 */
+#define T0CON_EVENT_EXT6 (0x7 << 8 ) /* EXT6 - External interrupt 6 */
+#define T0CON_EVENT_EXT7 (0x8 << 8 ) /* EXT7 - External interrupt 7 */
+#define T0CON_EVENT_T3 (0x9 << 8 ) /* T3 - Watchdog timer */
+#define T0CON_EVENT_T1 (0xA << 8 ) /* T1 - Timer1 */
+#define T0CON_EVENT_ADC0 (0xB << 8 ) /* ADC0 - ADC0 */
+#define T0CON_EVENT_ADC1 (0xC << 8 ) /* ADC1 - ADC1 */
+#define T0CON_EVENT_STEP (0xD << 8 ) /* STEP - STEP */
+#define T0CON_EVENT_DMADONE (0xE << 8 ) /* DMADONE */
+#define T0CON_EVENT_FEE (0xF << 8 ) /* FEE - Flash controller */
+
+/* T0CON[RLD] - Timer reload on write to clear register */
+#define T0CON_RLD_BBA (*(volatile unsigned long *) 0x4200011C)
+#define T0CON_RLD_MSK (0x1 << 7 )
+#define T0CON_RLD (0x1 << 7 )
+#define T0CON_RLD_DIS (0x0 << 7 ) /* DIS */
+#define T0CON_RLD_EN (0x1 << 7 ) /* EN */
+
+/* T0CON[CLK] - Clock Select */
+#define T0CON_CLK_MSK (0x3 << 5 )
+#define T0CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
+#define T0CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
+#define T0CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
+#define T0CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
+
+/* T0CON[ENABLE] - Enable */
+#define T0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42000110)
+#define T0CON_ENABLE_MSK (0x1 << 4 )
+#define T0CON_ENABLE (0x1 << 4 )
+#define T0CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
+#define T0CON_ENABLE_EN (0x1 << 4 ) /* EN */
+
+/* T0CON[MOD] - Mode */
+#define T0CON_MOD_BBA (*(volatile unsigned long *) 0x4200010C)
+#define T0CON_MOD_MSK (0x1 << 3 )
+#define T0CON_MOD (0x1 << 3 )
+#define T0CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
+#define T0CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
+
+/* T0CON[UP] - Count-up */
+#define T0CON_UP_BBA (*(volatile unsigned long *) 0x42000108)
+#define T0CON_UP_MSK (0x1 << 2 )
+#define T0CON_UP (0x1 << 2 )
+#define T0CON_UP_DIS (0x0 << 2 ) /* DIS */
+#define T0CON_UP_EN (0x1 << 2 ) /* EN */
+
+/* T0CON[PRE] - Prescaler */
+#define T0CON_PRE_MSK (0x3 << 0 )
+#define T0CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
+#define T0CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
+#define T0CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
+#define T0CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
+
+/* Reset Value for T0CLRI*/
+#define T0CLRI_RVAL 0x0
+
+/* T0CLRI[CAP] - Clear captured event interrupt */
+#define T0CLRI_CAP_BBA (*(volatile unsigned long *) 0x42000184)
+#define T0CLRI_CAP_MSK (0x1 << 1 )
+#define T0CLRI_CAP (0x1 << 1 )
+#define T0CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
+
+/* T0CLRI[TMOUT] - Clear timeout interrupt */
+#define T0CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42000180)
+#define T0CLRI_TMOUT_MSK (0x1 << 0 )
+#define T0CLRI_TMOUT (0x1 << 0 )
+#define T0CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
+
+/* Reset Value for T0CAP*/
+#define T0CAP_RVAL 0x0
+
+/* T0CAP[VALUE] - Capture value */
+#define T0CAP_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T0STA*/
+#define T0STA_RVAL 0x0
+
+/* T0STA[CLRI] - Value updated in the timer clock domain */
+#define T0STA_CLRI_BBA (*(volatile unsigned long *) 0x4200039C)
+#define T0STA_CLRI_MSK (0x1 << 7 )
+#define T0STA_CLRI (0x1 << 7 )
+#define T0STA_CLRI_CLR (0x0 << 7 ) /* CLR */
+#define T0STA_CLRI_SET (0x1 << 7 ) /* SET */
+
+/* T0STA[CON] - Ready to receive commands */
+#define T0STA_CON_BBA (*(volatile unsigned long *) 0x42000398)
+#define T0STA_CON_MSK (0x1 << 6 )
+#define T0STA_CON (0x1 << 6 )
+#define T0STA_CON_CLR (0x0 << 6 ) /* CLR */
+#define T0STA_CON_SET (0x1 << 6 ) /* SET */
+
+/* T0STA[CAP] - Capture event pending */
+#define T0STA_CAP_BBA (*(volatile unsigned long *) 0x42000384)
+#define T0STA_CAP_MSK (0x1 << 1 )
+#define T0STA_CAP (0x1 << 1 )
+#define T0STA_CAP_CLR (0x0 << 1 ) /* CLR */
+#define T0STA_CAP_SET (0x1 << 1 ) /* SET */
+
+/* T0STA[TMOUT] - Time out event occurred */
+#define T0STA_TMOUT_BBA (*(volatile unsigned long *) 0x42000380)
+#define T0STA_TMOUT_MSK (0x1 << 0 )
+#define T0STA_TMOUT (0x1 << 0 )
+#define T0STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
+#define T0STA_TMOUT_SET (0x1 << 0 ) /* SET */
+#if (__NO_MMR_STRUCTS__==1)
+
+#define T1LD (*(volatile unsigned short int *) 0x40000400)
+#define T1VAL (*(volatile unsigned short int *) 0x40000404)
+#define T1CON (*(volatile unsigned short int *) 0x40000408)
+#define T1CLRI (*(volatile unsigned short int *) 0x4000040C)
+#define T1CAP (*(volatile unsigned short int *) 0x40000410)
+#define T1STA (*(volatile unsigned short int *) 0x4000041C)
+#endif // (__NO_MMR_STRUCTS__==1)
+
+/* Reset Value for T1LD*/
+#define T1LD_RVAL 0x0
+
+/* T1LD[VALUE] - Load value */
+#define T1LD_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T1VAL*/
+#define T1VAL_RVAL 0x0
+
+/* T1VAL[VALUE] - Current value */
+#define T1VAL_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T1CON*/
+#define T1CON_RVAL 0xA
+
+/* T1CON[EVENTEN] - Enable time capture of an event */
+#define T1CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42008130)
+#define T1CON_EVENTEN_MSK (0x1 << 12 )
+#define T1CON_EVENTEN (0x1 << 12 )
+#define T1CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
+#define T1CON_EVENTEN_EN (0x1 << 12 ) /* EN */
+
+/* T1CON[EVENT] - Event Select, selects 1 of the available events. */
+#define T1CON_EVENT_MSK (0xF << 8 )
+#define T1CON_EVENT_COM (0x0 << 8 ) /* COM */
+#define T1CON_EVENT_T0 (0x1 << 8 ) /* T0 - Timer0 */
+#define T1CON_EVENT_SPI0 (0x2 << 8 ) /* SPI0 */
+#define T1CON_EVENT_SPI1 (0x3 << 8 ) /* SPI1 */
+#define T1CON_EVENT_I2CS (0x4 << 8 ) /* I2CS */
+#define T1CON_EVENT_I2CM (0x5 << 8 ) /* I2CM */
+#define T1CON_EVENT_DMAERR (0x6 << 8 ) /* DMAERR */
+#define T1CON_EVENT_DMADONE (0x7 << 8 ) /* DMADONE */
+#define T1CON_EVENT_EXT1 (0x8 << 8 ) /* EXT1 */
+#define T1CON_EVENT_EXT2 (0x9 << 8 ) /* EXT2 */
+#define T1CON_EVENT_EXT3 (0xA << 8 ) /* EXT3 */
+#define T1CON_EVENT_PWMTRIP (0xB << 8 ) /* PWMTRIP */
+#define T1CON_EVENT_PWM0 (0xC << 8 ) /* PWM0 */
+#define T1CON_EVENT_PWM1 (0xD << 8 ) /* PWM1 */
+#define T1CON_EVENT_PWM2 (0xE << 8 ) /* PWM2 */
+#define T1CON_EVENT_ADC0 (0xF << 8 ) /* ADC0 */
+
+/* T1CON[RLD] - Timer reload on write to clear register */
+#define T1CON_RLD_BBA (*(volatile unsigned long *) 0x4200811C)
+#define T1CON_RLD_MSK (0x1 << 7 )
+#define T1CON_RLD (0x1 << 7 )
+#define T1CON_RLD_DIS (0x0 << 7 ) /* DIS */
+#define T1CON_RLD_EN (0x1 << 7 ) /* EN */
+
+/* T1CON[CLK] - Clock Select */
+#define T1CON_CLK_MSK (0x3 << 5 )
+#define T1CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
+#define T1CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
+#define T1CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
+#define T1CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
+
+/* T1CON[ENABLE] - Enable */
+#define T1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42008110)
+#define T1CON_ENABLE_MSK (0x1 << 4 )
+#define T1CON_ENABLE (0x1 << 4 )
+#define T1CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
+#define T1CON_ENABLE_EN (0x1 << 4 ) /* EN */
+
+/* T1CON[MOD] - Mode */
+#define T1CON_MOD_BBA (*(volatile unsigned long *) 0x4200810C)
+#define T1CON_MOD_MSK (0x1 << 3 )
+#define T1CON_MOD (0x1 << 3 )
+#define T1CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
+#define T1CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
+
+/* T1CON[UP] - Count-up */
+#define T1CON_UP_BBA (*(volatile unsigned long *) 0x42008108)
+#define T1CON_UP_MSK (0x1 << 2 )
+#define T1CON_UP (0x1 << 2 )
+#define T1CON_UP_DIS (0x0 << 2 ) /* DIS */
+#define T1CON_UP_EN (0x1 << 2 ) /* EN */
+
+/* T1CON[PRE] - Prescaler */
+#define T1CON_PRE_MSK (0x3 << 0 )
+#define T1CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
+#define T1CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
+#define T1CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
+#define T1CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
+
+/* Reset Value for T1CLRI*/
+#define T1CLRI_RVAL 0x0
+
+/* T1CLRI[CAP] - Clear captured event interrupt */
+#define T1CLRI_CAP_BBA (*(volatile unsigned long *) 0x42008184)
+#define T1CLRI_CAP_MSK (0x1 << 1 )
+#define T1CLRI_CAP (0x1 << 1 )
+#define T1CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
+
+/* T1CLRI[TMOUT] - Clear timeout interrupt */
+#define T1CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42008180)
+#define T1CLRI_TMOUT_MSK (0x1 << 0 )
+#define T1CLRI_TMOUT (0x1 << 0 )
+#define T1CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
+
+/* Reset Value for T1CAP*/
+#define T1CAP_RVAL 0x0
+
+/* T1CAP[VALUE] - Capture value */
+#define T1CAP_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T1STA*/
+#define T1STA_RVAL 0x0
+
+/* T1STA[CLRI] - Value updated in the timer clock domain */
+#define T1STA_CLRI_BBA (*(volatile unsigned long *) 0x4200839C)
+#define T1STA_CLRI_MSK (0x1 << 7 )
+#define T1STA_CLRI (0x1 << 7 )
+#define T1STA_CLRI_CLR (0x0 << 7 ) /* CLR */
+#define T1STA_CLRI_SET (0x1 << 7 ) /* SET */
+
+/* T1STA[CON] - Ready to receive commands */
+#define T1STA_CON_BBA (*(volatile unsigned long *) 0x42008398)
+#define T1STA_CON_MSK (0x1 << 6 )
+#define T1STA_CON (0x1 << 6 )
+#define T1STA_CON_CLR (0x0 << 6 ) /* CLR */
+#define T1STA_CON_SET (0x1 << 6 ) /* SET */
+
+/* T1STA[CAP] - Capture event pending */
+#define T1STA_CAP_BBA (*(volatile unsigned long *) 0x42008384)
+#define T1STA_CAP_MSK (0x1 << 1 )
+#define T1STA_CAP (0x1 << 1 )
+#define T1STA_CAP_CLR (0x0 << 1 ) /* CLR */
+#define T1STA_CAP_SET (0x1 << 1 ) /* SET */
+
+/* T1STA[TMOUT] - Time out event occurred */
+#define T1STA_TMOUT_BBA (*(volatile unsigned long *) 0x42008380)
+#define T1STA_TMOUT_MSK (0x1 << 0 )
+#define T1STA_TMOUT (0x1 << 0 )
+#define T1STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
+#define T1STA_TMOUT_SET (0x1 << 0 ) /* SET */
+// ------------------------------------------------------------------------------------------------
+// ----- PWM -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Pulse Width Modulation (pADI_PWM)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_PWM Structure */
+ __IO uint16_t
+ PWMCON0; /*!< PWM Control register */
+ __I uint16_t RESERVED0;
+ __IO uint8_t
+ PWMCON1; /*!< Trip control register */
+ __I uint8_t RESERVED1[3];
+ __IO uint16_t
+ PWMCLRI; /*!< PWM interrupt clear. Write to this register clears the latched PWM interrupt. */
+ __I uint16_t RESERVED2[3];
+ __IO uint16_t
+ PWM0COM0; /*!< Compare Register 0 for PWM0 and PWM1 */
+ __I uint16_t RESERVED3;
+ __IO uint16_t
+ PWM0COM1; /*!< Compare Register 1 for PWM0 and PWM1 */
+ __I uint16_t RESERVED4;
+ __IO uint16_t
+ PWM0COM2; /*!< Compare Register 2 for PWM0 and PWM1 */
+ __I uint16_t RESERVED5;
+ __IO uint16_t
+ PWM0LEN; /*!< Period Value register for PWM0 and PWM1 */
+ __I uint16_t RESERVED6;
+ __IO uint16_t
+ PWM1COM0; /*!< Compare Register 0 for PWM2 and PWM3 */
+ __I uint16_t RESERVED7;
+ __IO uint16_t
+ PWM1COM1; /*!< Compare Register 1 for PWM2 and PWM3 */
+ __I uint16_t RESERVED8;
+ __IO uint16_t
+ PWM1COM2; /*!< Compare Register 2 for PWM2 and PWM3 */
+ __I uint16_t RESERVED9;
+ __IO uint16_t
+ PWM1LEN; /*!< Period Value register for PWM2 and PWM3 */
+ __I uint16_t RESERVED10;
+ __IO uint16_t
+ PWM2COM0; /*!< Compare Register 0 for PWM4 and PWM5 */
+ __I uint16_t RESERVED11;
+ __IO uint16_t
+ PWM2COM1; /*!< Compare Register 1 for PWM4 and PWM5 */
+ __I uint16_t RESERVED12;
+ __IO uint16_t
+ PWM2COM2; /*!< Compare Register 2 for PWM4 and PWM5 */
+ __I uint16_t RESERVED13;
+ __IO uint16_t
+ PWM2LEN; /*!< Period Value register for PWM4 and PWM5 */
+} ADI_PWM_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define PWMCON0 (*(volatile unsigned short int *) 0x40001000)
+#define PWMCON1 (*(volatile unsigned char *) 0x40001004)
+#define PWMCLRI (*(volatile unsigned short int *) 0x40001008)
+#define PWM0COM0 (*(volatile unsigned short int *) 0x40001010)
+#define PWM0COM1 (*(volatile unsigned short int *) 0x40001014)
+#define PWM0COM2 (*(volatile unsigned short int *) 0x40001018)
+#define PWM0LEN (*(volatile unsigned short int *) 0x4000101C)
+#define PWM1COM0 (*(volatile unsigned short int *) 0x40001020)
+#define PWM1COM1 (*(volatile unsigned short int *) 0x40001024)
+#define PWM1COM2 (*(volatile unsigned short int *) 0x40001028)
+#define PWM1LEN (*(volatile unsigned short int *) 0x4000102C)
+#define PWM2COM0 (*(volatile unsigned short int *) 0x40001030)
+#define PWM2COM1 (*(volatile unsigned short int *) 0x40001034)
+#define PWM2COM2 (*(volatile unsigned short int *) 0x40001038)
+#define PWM2LEN (*(volatile unsigned short int *) 0x4000103C)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for PWMCON0*/
+#define PWMCON0_RVAL 0x12
+
+/* PWMCON0[SYNC] - PWM Synchronization */
+#define PWMCON0_SYNC_BBA (*(volatile unsigned long *) 0x4202003C)
+#define PWMCON0_SYNC_MSK (0x1 << 15 )
+#define PWMCON0_SYNC (0x1 << 15 )
+#define PWMCON0_SYNC_DIS (0x0 << 15 ) /* DIS */
+#define PWMCON0_SYNC_EN (0x1 << 15 ) /* EN */
+
+/* PWMCON0[PWM5INV] - Inversion of PWM output */
+#define PWMCON0_PWM5INV_BBA (*(volatile unsigned long *) 0x42020034)
+#define PWMCON0_PWM5INV_MSK (0x1 << 13 )
+#define PWMCON0_PWM5INV (0x1 << 13 )
+#define PWMCON0_PWM5INV_DIS (0x0 << 13 ) /* DIS */
+#define PWMCON0_PWM5INV_EN (0x1 << 13 ) /* EN */
+
+/* PWMCON0[PWM3INV] - Inversion of PWM output */
+#define PWMCON0_PWM3INV_BBA (*(volatile unsigned long *) 0x42020030)
+#define PWMCON0_PWM3INV_MSK (0x1 << 12 )
+#define PWMCON0_PWM3INV (0x1 << 12 )
+#define PWMCON0_PWM3INV_DIS (0x0 << 12 ) /* DIS */
+#define PWMCON0_PWM3INV_EN (0x1 << 12 ) /* EN */
+
+/* PWMCON0[PWM1INV] - Inversion of PWM output */
+#define PWMCON0_PWM1INV_BBA (*(volatile unsigned long *) 0x4202002C)
+#define PWMCON0_PWM1INV_MSK (0x1 << 11 )
+#define PWMCON0_PWM1INV (0x1 << 11 )
+#define PWMCON0_PWM1INV_DIS (0x0 << 11 ) /* DIS */
+#define PWMCON0_PWM1INV_EN (0x1 << 11 ) /* EN */
+
+/* PWMCON0[PWMIEN] - Enables PWM interrupts */
+#define PWMCON0_PWMIEN_BBA (*(volatile unsigned long *) 0x42020028)
+#define PWMCON0_PWMIEN_MSK (0x1 << 10 )
+#define PWMCON0_PWMIEN (0x1 << 10 )
+#define PWMCON0_PWMIEN_DIS (0x0 << 10 ) /* DIS */
+#define PWMCON0_PWMIEN_EN (0x1 << 10 ) /* EN */
+
+/* PWMCON0[ENA] - enable PWM outputs */
+#define PWMCON0_ENA_BBA (*(volatile unsigned long *) 0x42020024)
+#define PWMCON0_ENA_MSK (0x1 << 9 )
+#define PWMCON0_ENA (0x1 << 9 )
+#define PWMCON0_ENA_DIS (0x0 << 9 ) /* DIS */
+#define PWMCON0_ENA_EN (0x1 << 9 ) /* EN */
+
+/* PWMCON0[PRE] - PWM Clock Prescaler */
+#define PWMCON0_PRE_MSK (0x7 << 6 )
+
+/* PWMCON0[POINV] - Invert all PWM outputs */
+#define PWMCON0_POINV_BBA (*(volatile unsigned long *) 0x42020014)
+#define PWMCON0_POINV_MSK (0x1 << 5 )
+#define PWMCON0_POINV (0x1 << 5 )
+#define PWMCON0_POINV_DIS (0x0 << 5 ) /* DIS */
+#define PWMCON0_POINV_EN (0x1 << 5 ) /* EN */
+
+/* PWMCON0[HOFF] - High Side Off */
+#define PWMCON0_HOFF_BBA (*(volatile unsigned long *) 0x42020010)
+#define PWMCON0_HOFF_MSK (0x1 << 4 )
+#define PWMCON0_HOFF (0x1 << 4 )
+#define PWMCON0_HOFF_DIS (0x0 << 4 ) /* DIS */
+#define PWMCON0_HOFF_EN (0x1 << 4 ) /* EN */
+
+/* PWMCON0[LCOMP] - Load Compare Registers */
+#define PWMCON0_LCOMP_BBA (*(volatile unsigned long *) 0x4202000C)
+#define PWMCON0_LCOMP_MSK (0x1 << 3 )
+#define PWMCON0_LCOMP (0x1 << 3 )
+#define PWMCON0_LCOMP_DIS (0x0 << 3 ) /* DIS */
+#define PWMCON0_LCOMP_EN (0x1 << 3 ) /* EN */
+
+/* PWMCON0[DIR] - Direction Control */
+#define PWMCON0_DIR_BBA (*(volatile unsigned long *) 0x42020008)
+#define PWMCON0_DIR_MSK (0x1 << 2 )
+#define PWMCON0_DIR (0x1 << 2 )
+#define PWMCON0_DIR_DIS (0x0 << 2 ) /* DIS */
+#define PWMCON0_DIR_EN (0x1 << 2 ) /* EN */
+
+/* PWMCON0[MOD] - Enables H-Bridge Mode */
+#define PWMCON0_MOD_BBA (*(volatile unsigned long *) 0x42020004)
+#define PWMCON0_MOD_MSK (0x1 << 1 )
+#define PWMCON0_MOD (0x1 << 1 )
+#define PWMCON0_MOD_DIS (0x0 << 1 ) /* DIS */
+#define PWMCON0_MOD_EN (0x1 << 1 ) /* EN */
+
+/* PWMCON0[ENABLE] - Enables all PWM outputs */
+#define PWMCON0_ENABLE_BBA (*(volatile unsigned long *) 0x42020000)
+#define PWMCON0_ENABLE_MSK (0x1 << 0 )
+#define PWMCON0_ENABLE (0x1 << 0 )
+#define PWMCON0_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define PWMCON0_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for PWMCON1*/
+#define PWMCON1_RVAL 0x0
+
+/* PWMCON1[CONVSTART] - Enable adc conversion start from pwm */
+#define PWMCON1_CONVSTART_BBA (*(volatile unsigned long *) 0x4202009C)
+#define PWMCON1_CONVSTART_MSK (0x1 << 7 )
+#define PWMCON1_CONVSTART (0x1 << 7 )
+#define PWMCON1_CONVSTART_DIS (0x0 << 7 ) /* DIS */
+#define PWMCON1_CONVSTART_EN (0x1 << 7 ) /* EN */
+
+/* PWMCON1[TRIPEN] - Enable PWM trip functionality */
+#define PWMCON1_TRIPEN_BBA (*(volatile unsigned long *) 0x42020098)
+#define PWMCON1_TRIPEN_MSK (0x1 << 6 )
+#define PWMCON1_TRIPEN (0x1 << 6 )
+#define PWMCON1_TRIPEN_DIS (0x0 << 6 ) /* DIS */
+#define PWMCON1_TRIPEN_EN (0x1 << 6 ) /* EN */
+
+/* PWMCON1[CONVSTARTDELAY] - ADC conversion start delay configuration */
+#define PWMCON1_CONVSTARTDELAY_MSK (0xF << 0 )
+
+/* Reset Value for PWMCLRI*/
+#define PWMCLRI_RVAL 0x0
+
+/* PWMCLRI[TRIP] - Clear the latched trip interrupt */
+#define PWMCLRI_TRIP_BBA (*(volatile unsigned long *) 0x42020110)
+#define PWMCLRI_TRIP_MSK (0x1 << 4 )
+#define PWMCLRI_TRIP (0x1 << 4 )
+#define PWMCLRI_TRIP_DIS (0x0 << 4 ) /* DIS */
+#define PWMCLRI_TRIP_EN (0x1 << 4 ) /* EN */
+
+/* PWMCLRI[PWM2] - Clear the latched PWM2 interrupt */
+#define PWMCLRI_PWM2_BBA (*(volatile unsigned long *) 0x42020108)
+#define PWMCLRI_PWM2_MSK (0x1 << 2 )
+#define PWMCLRI_PWM2 (0x1 << 2 )
+#define PWMCLRI_PWM2_DIS (0x0 << 2 ) /* DIS */
+#define PWMCLRI_PWM2_EN (0x1 << 2 ) /* EN */
+
+/* PWMCLRI[PWM1] - Clear the latched PWM1 interrupt */
+#define PWMCLRI_PWM1_BBA (*(volatile unsigned long *) 0x42020104)
+#define PWMCLRI_PWM1_MSK (0x1 << 1 )
+#define PWMCLRI_PWM1 (0x1 << 1 )
+#define PWMCLRI_PWM1_DIS (0x0 << 1 ) /* DIS */
+#define PWMCLRI_PWM1_EN (0x1 << 1 ) /* EN */
+
+/* PWMCLRI[PWM0] - Clear the latched PWM0 interrupt */
+#define PWMCLRI_PWM0_BBA (*(volatile unsigned long *) 0x42020100)
+#define PWMCLRI_PWM0_MSK (0x1 << 0 )
+#define PWMCLRI_PWM0 (0x1 << 0 )
+#define PWMCLRI_PWM0_DIS (0x0 << 0 ) /* DIS */
+#define PWMCLRI_PWM0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for PWM0COM0*/
+#define PWM0COM0_RVAL 0x0
+
+/* Reset Value for PWM0COM1*/
+#define PWM0COM1_RVAL 0x0
+
+/* Reset Value for PWM0COM2*/
+#define PWM0COM2_RVAL 0x0
+
+/* Reset Value for PWM0LEN*/
+#define PWM0LEN_RVAL 0x0
+
+/* Reset Value for PWM1COM0*/
+#define PWM1COM0_RVAL 0x0
+
+/* Reset Value for PWM1COM1*/
+#define PWM1COM1_RVAL 0x0
+
+/* Reset Value for PWM1COM2*/
+#define PWM1COM2_RVAL 0x0
+
+/* Reset Value for PWM1LEN*/
+#define PWM1LEN_RVAL 0x0
+
+/* Reset Value for PWM2COM0*/
+#define PWM2COM0_RVAL 0x0
+
+/* Reset Value for PWM2COM1*/
+#define PWM2COM1_RVAL 0x0
+
+/* Reset Value for PWM2COM2*/
+#define PWM2COM2_RVAL 0x0
+
+/* Reset Value for PWM2LEN*/
+#define PWM2LEN_RVAL 0x0
+// ------------------------------------------------------------------------------------------------
+// ----- PWRCTL -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Power Management Unit (pADI_PWRCTL)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_PWRCTL Structure */
+ __IO uint8_t
+ PWRMOD; /*!< Power modes register */
+ __I uint8_t RESERVED0[3];
+ __IO uint16_t
+ PWRKEY; /*!< Key protection for the PWRMOD register. */
+} ADI_PWRCTL_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define PWRMOD (*(volatile unsigned char *) 0x40002400)
+#define PWRKEY (*(volatile unsigned short int *) 0x40002404)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for PWRMOD*/
+#define PWRMOD_RVAL 0x40
+
+/* PWRMOD[WICENACK] - For Deepsleep mode only */
+#define PWRMOD_WICENACK_BBA (*(volatile unsigned long *) 0x4204800C)
+#define PWRMOD_WICENACK_MSK (0x1 << 3 )
+#define PWRMOD_WICENACK (0x1 << 3 )
+#define PWRMOD_WICENACK_DIS (0x0 << 3 ) /* DIS */
+#define PWRMOD_WICENACK_EN (0x1 << 3 ) /* EN */
+
+/* PWRMOD[MOD] - Power Mode */
+#define PWRMOD_MOD_MSK (0x7 << 0 )
+#define PWRMOD_MOD_FULLACTIVE (0x0 << 0 ) /* FULLACTIVE */
+#define PWRMOD_MOD_MCUHALT (0x1 << 0 ) /* MCUHALT */
+#define PWRMOD_MOD_PERHALT (0x2 << 0 ) /* PERHALT */
+#define PWRMOD_MOD_SYSHALT (0x3 << 0 ) /* SYSHALT */
+#define PWRMOD_MOD_TOTALHALT (0x4 << 0 ) /* TOTALHALT */
+#define PWRMOD_MOD_HIBERNATE (0x5 << 0 ) /* HIBERNATE */
+
+/* Reset Value for PWRKEY*/
+#define PWRKEY_RVAL 0x0
+
+/* PWRKEY[VALUE] - Key value */
+#define PWRKEY_VALUE_MSK (0xFFFF << 0 )
+#define PWRKEY_VALUE_KEY1 (0x4859 << 0 ) /* KEY1 */
+#define PWRKEY_VALUE_KEY2 (0xF27B << 0 ) /* KEY2 */
+// ------------------------------------------------------------------------------------------------
+// ----- RESET -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Reset (pADI_RESET)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_RESET Structure */
+
+ union {
+ __IO uint8_t
+ RSTSTA; /*!< Reset Status */
+ __IO uint8_t
+ RSTCLR; /*!< Reset Status Clear */
+ } ;
+} ADI_RESET_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define RSTSTA (*(volatile unsigned char *) 0x40002440)
+#define RSTCLR (*(volatile unsigned char *) 0x40002440)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for RSTSTA*/
+#define RSTSTA_RVAL 0x1
+
+/* RSTSTA[SWRST] - Software reset status bit */
+#define RSTSTA_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
+#define RSTSTA_SWRST_MSK (0x1 << 3 )
+#define RSTSTA_SWRST (0x1 << 3 )
+#define RSTSTA_SWRST_CLR (0x0 << 3 ) /* CLR */
+#define RSTSTA_SWRST_SET (0x1 << 3 ) /* SET */
+
+/* RSTSTA[WDRST] - Watchdog reset status bit */
+#define RSTSTA_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
+#define RSTSTA_WDRST_MSK (0x1 << 2 )
+#define RSTSTA_WDRST (0x1 << 2 )
+#define RSTSTA_WDRST_CLR (0x0 << 2 ) /* CLR */
+#define RSTSTA_WDRST_SET (0x1 << 2 ) /* SET */
+
+/* RSTSTA[EXTRST] - External reset status bit */
+#define RSTSTA_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
+#define RSTSTA_EXTRST_MSK (0x1 << 1 )
+#define RSTSTA_EXTRST (0x1 << 1 )
+#define RSTSTA_EXTRST_CLR (0x0 << 1 ) /* CLR */
+#define RSTSTA_EXTRST_SET (0x1 << 1 ) /* SET */
+
+/* RSTSTA[POR] - Power-on reset status bit */
+#define RSTSTA_POR_BBA (*(volatile unsigned long *) 0x42048800)
+#define RSTSTA_POR_MSK (0x1 << 0 )
+#define RSTSTA_POR (0x1 << 0 )
+#define RSTSTA_POR_CLR (0x0 << 0 ) /* CLR */
+#define RSTSTA_POR_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for RSTCLR*/
+#define RSTCLR_RVAL 0x1
+
+/* RSTCLR[SWRST] - Software reset status bit */
+#define RSTCLR_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
+#define RSTCLR_SWRST_MSK (0x1 << 3 )
+#define RSTCLR_SWRST (0x1 << 3 )
+#define RSTCLR_SWRST_DIS (0x0 << 3 ) /* DIS */
+#define RSTCLR_SWRST_EN (0x1 << 3 ) /* EN */
+
+/* RSTCLR[WDRST] - Watchdog reset status bit */
+#define RSTCLR_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
+#define RSTCLR_WDRST_MSK (0x1 << 2 )
+#define RSTCLR_WDRST (0x1 << 2 )
+#define RSTCLR_WDRST_DIS (0x0 << 2 ) /* DIS */
+#define RSTCLR_WDRST_EN (0x1 << 2 ) /* EN */
+
+/* RSTCLR[EXTRST] - External reset status bit */
+#define RSTCLR_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
+#define RSTCLR_EXTRST_MSK (0x1 << 1 )
+#define RSTCLR_EXTRST (0x1 << 1 )
+#define RSTCLR_EXTRST_DIS (0x0 << 1 ) /* DIS */
+#define RSTCLR_EXTRST_EN (0x1 << 1 ) /* EN */
+
+/* RSTCLR[POR] - Power-on reset status bit */
+#define RSTCLR_POR_BBA (*(volatile unsigned long *) 0x42048800)
+#define RSTCLR_POR_MSK (0x1 << 0 )
+#define RSTCLR_POR (0x1 << 0 )
+#define RSTCLR_POR_DIS (0x0 << 0 ) /* DIS */
+#define RSTCLR_POR_EN (0x1 << 0 ) /* EN */
+// ------------------------------------------------------------------------------------------------
+// ----- INTERRUPT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Interrupts (pADI_INTERRUPT)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_INTERRUPT Structure */
+ __IO uint16_t
+ EI0CFG; /*!< External Interrupt configuration register 0 */
+ __I uint16_t RESERVED0;
+ __IO uint16_t
+ EI1CFG; /*!< External Interrupt configuration register 1 */
+ __I uint16_t RESERVED1[5];
+ __IO uint16_t
+ EICLR; /*!< External Interrupts Clear register */
+} ADI_INTERRUPT_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define EI0CFG (*(volatile unsigned short int *) 0x40002420)
+#define EI1CFG (*(volatile unsigned short int *) 0x40002424)
+#define EICLR (*(volatile unsigned short int *) 0x40002430)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for EI0CFG*/
+#define EI0CFG_RVAL 0x0
+
+/* EI0CFG[IRQ3EN] - External Interrupt 3 Enable */
+#define EI0CFG_IRQ3EN_BBA (*(volatile unsigned long *) 0x4204843C)
+#define EI0CFG_IRQ3EN_MSK (0x1 << 15 )
+#define EI0CFG_IRQ3EN (0x1 << 15 )
+#define EI0CFG_IRQ3EN_DIS (0x0 << 15 ) /* DIS */
+#define EI0CFG_IRQ3EN_EN (0x1 << 15 ) /* EN */
+
+/* EI0CFG[IRQ3MDE] - External Interrupt 0 Mode */
+#define EI0CFG_IRQ3MDE_MSK (0x7 << 12 )
+#define EI0CFG_IRQ3MDE_RISE (0x0 << 12 ) /* RISE */
+#define EI0CFG_IRQ3MDE_FALL (0x1 << 12 ) /* FALL */
+#define EI0CFG_IRQ3MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
+#define EI0CFG_IRQ3MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
+#define EI0CFG_IRQ3MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
+
+/* EI0CFG[IRQ2EN] - External Interrupt 2 Enable */
+#define EI0CFG_IRQ2EN_BBA (*(volatile unsigned long *) 0x4204842C)
+#define EI0CFG_IRQ2EN_MSK (0x1 << 11 )
+#define EI0CFG_IRQ2EN (0x1 << 11 )
+#define EI0CFG_IRQ2EN_DIS (0x0 << 11 ) /* DIS */
+#define EI0CFG_IRQ2EN_EN (0x1 << 11 ) /* EN */
+
+/* EI0CFG[IRQ2MDE] - External Interrupt 2 Mode */
+#define EI0CFG_IRQ2MDE_MSK (0x7 << 8 )
+#define EI0CFG_IRQ2MDE_RISE (0x0 << 8 ) /* RISE */
+#define EI0CFG_IRQ2MDE_FALL (0x1 << 8 ) /* FALL */
+#define EI0CFG_IRQ2MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
+#define EI0CFG_IRQ2MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
+#define EI0CFG_IRQ2MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
+
+/* EI0CFG[IRQ1EN] - External Interrupt 1 Enable */
+#define EI0CFG_IRQ1EN_BBA (*(volatile unsigned long *) 0x4204841C)
+#define EI0CFG_IRQ1EN_MSK (0x1 << 7 )
+#define EI0CFG_IRQ1EN (0x1 << 7 )
+#define EI0CFG_IRQ1EN_DIS (0x0 << 7 ) /* DIS */
+#define EI0CFG_IRQ1EN_EN (0x1 << 7 ) /* EN */
+
+/* EI0CFG[IRQ1MDE] - External Interrupt 1 Mode */
+#define EI0CFG_IRQ1MDE_MSK (0x7 << 4 )
+#define EI0CFG_IRQ1MDE_RISE (0x0 << 4 ) /* RISE */
+#define EI0CFG_IRQ1MDE_FALL (0x1 << 4 ) /* FALL */
+#define EI0CFG_IRQ1MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
+#define EI0CFG_IRQ1MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
+#define EI0CFG_IRQ1MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
+
+/* EI0CFG[IRQ0EN] - External Interrupt 0 Enable */
+#define EI0CFG_IRQ0EN_BBA (*(volatile unsigned long *) 0x4204840C)
+#define EI0CFG_IRQ0EN_MSK (0x1 << 3 )
+#define EI0CFG_IRQ0EN (0x1 << 3 )
+#define EI0CFG_IRQ0EN_DIS (0x0 << 3 ) /* DIS */
+#define EI0CFG_IRQ0EN_EN (0x1 << 3 ) /* EN */
+
+/* EI0CFG[IRQ0MDE] - External Interrupt 0 Mode */
+#define EI0CFG_IRQ0MDE_MSK (0x7 << 0 )
+#define EI0CFG_IRQ0MDE_RISE (0x0 << 0 ) /* RISE */
+#define EI0CFG_IRQ0MDE_FALL (0x1 << 0 ) /* FALL */
+#define EI0CFG_IRQ0MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
+#define EI0CFG_IRQ0MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
+#define EI0CFG_IRQ0MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
+
+/* Reset Value for EI1CFG*/
+#define EI1CFG_RVAL 0x0
+
+/* EI1CFG[IRQ7EN] - External Interrupt 7 Enable */
+#define EI1CFG_IRQ7EN_BBA (*(volatile unsigned long *) 0x420484BC)
+#define EI1CFG_IRQ7EN_MSK (0x1 << 15 )
+#define EI1CFG_IRQ7EN (0x1 << 15 )
+#define EI1CFG_IRQ7EN_DIS (0x0 << 15 ) /* DIS */
+#define EI1CFG_IRQ7EN_EN (0x1 << 15 ) /* EN */
+
+/* EI1CFG[IRQ7MDE] - External Interrupt 7 Mode */
+#define EI1CFG_IRQ7MDE_MSK (0x7 << 12 )
+#define EI1CFG_IRQ7MDE_RISE (0x0 << 12 ) /* RISE */
+#define EI1CFG_IRQ7MDE_FALL (0x1 << 12 ) /* FALL */
+#define EI1CFG_IRQ7MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
+#define EI1CFG_IRQ7MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
+#define EI1CFG_IRQ7MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
+
+/* EI1CFG[IRQ6EN] - External Interrupt 6 Enable */
+#define EI1CFG_IRQ6EN_BBA (*(volatile unsigned long *) 0x420484AC)
+#define EI1CFG_IRQ6EN_MSK (0x1 << 11 )
+#define EI1CFG_IRQ6EN (0x1 << 11 )
+#define EI1CFG_IRQ6EN_DIS (0x0 << 11 ) /* DIS */
+#define EI1CFG_IRQ6EN_EN (0x1 << 11 ) /* EN */
+
+/* EI1CFG[IRQ6MDE] - External Interrupt 6 Mode */
+#define EI1CFG_IRQ6MDE_MSK (0x7 << 8 )
+#define EI1CFG_IRQ6MDE_RISE (0x0 << 8 ) /* RISE */
+#define EI1CFG_IRQ6MDE_FALL (0x1 << 8 ) /* FALL */
+#define EI1CFG_IRQ6MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
+#define EI1CFG_IRQ6MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
+#define EI1CFG_IRQ6MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
+
+/* EI1CFG[IRQ5EN] - External Interrupt 5 Enable */
+#define EI1CFG_IRQ5EN_BBA (*(volatile unsigned long *) 0x4204849C)
+#define EI1CFG_IRQ5EN_MSK (0x1 << 7 )
+#define EI1CFG_IRQ5EN (0x1 << 7 )
+#define EI1CFG_IRQ5EN_DIS (0x0 << 7 ) /* DIS */
+#define EI1CFG_IRQ5EN_EN (0x1 << 7 ) /* EN */
+
+/* EI1CFG[IRQ5MDE] - External Interrupt 5 Mode */
+#define EI1CFG_IRQ5MDE_MSK (0x7 << 4 )
+#define EI1CFG_IRQ5MDE_RISE (0x0 << 4 ) /* RISE */
+#define EI1CFG_IRQ5MDE_FALL (0x1 << 4 ) /* FALL */
+#define EI1CFG_IRQ5MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
+#define EI1CFG_IRQ5MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
+#define EI1CFG_IRQ5MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
+
+/* EI1CFG[IRQ4EN] - External Interrupt 4 Enable */
+#define EI1CFG_IRQ4EN_BBA (*(volatile unsigned long *) 0x4204848C)
+#define EI1CFG_IRQ4EN_MSK (0x1 << 3 )
+#define EI1CFG_IRQ4EN (0x1 << 3 )
+#define EI1CFG_IRQ4EN_DIS (0x0 << 3 ) /* DIS */
+#define EI1CFG_IRQ4EN_EN (0x1 << 3 ) /* EN */
+
+/* EI1CFG[IRQ4MDE] - External Interrupt 4 Mode */
+#define EI1CFG_IRQ4MDE_MSK (0x7 << 0 )
+#define EI1CFG_IRQ4MDE_RISE (0x0 << 0 ) /* RISE */
+#define EI1CFG_IRQ4MDE_FALL (0x1 << 0 ) /* FALL */
+#define EI1CFG_IRQ4MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
+#define EI1CFG_IRQ4MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
+#define EI1CFG_IRQ4MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
+
+/* Reset Value for EICLR*/
+#define EICLR_RVAL 0x0
+
+/* EICLR[IRQ7] - Clears External interrupt 7 internal flag */
+#define EICLR_IRQ7_BBA (*(volatile unsigned long *) 0x4204861C)
+#define EICLR_IRQ7_MSK (0x1 << 7 )
+#define EICLR_IRQ7 (0x1 << 7 )
+#define EICLR_IRQ7_CLR (0x1 << 7 ) /* CLR */
+
+/* EICLR[IRQ6] - Clears External interrupt 6 internal flag */
+#define EICLR_IRQ6_BBA (*(volatile unsigned long *) 0x42048618)
+#define EICLR_IRQ6_MSK (0x1 << 6 )
+#define EICLR_IRQ6 (0x1 << 6 )
+#define EICLR_IRQ6_CLR (0x1 << 6 ) /* CLR */
+
+/* EICLR[IRQ5] - Clears External interrupt 5 internal flag */
+#define EICLR_IRQ5_BBA (*(volatile unsigned long *) 0x42048614)
+#define EICLR_IRQ5_MSK (0x1 << 5 )
+#define EICLR_IRQ5 (0x1 << 5 )
+#define EICLR_IRQ5_CLR (0x1 << 5 ) /* CLR */
+
+/* EICLR[IRQ4] - Clears External interrupt 4 internal flag */
+#define EICLR_IRQ4_BBA (*(volatile unsigned long *) 0x42048610)
+#define EICLR_IRQ4_MSK (0x1 << 4 )
+#define EICLR_IRQ4 (0x1 << 4 )
+#define EICLR_IRQ4_CLR (0x1 << 4 ) /* CLR */
+
+/* EICLR[IRQ3] - Clears External interrupt 3 internal flag */
+#define EICLR_IRQ3_BBA (*(volatile unsigned long *) 0x4204860C)
+#define EICLR_IRQ3_MSK (0x1 << 3 )
+#define EICLR_IRQ3 (0x1 << 3 )
+#define EICLR_IRQ3_CLR (0x1 << 3 ) /* CLR */
+
+/* EICLR[IRQ2] - Clears External interrupt 2 internal flag */
+#define EICLR_IRQ2_BBA (*(volatile unsigned long *) 0x42048608)
+#define EICLR_IRQ2_MSK (0x1 << 2 )
+#define EICLR_IRQ2 (0x1 << 2 )
+#define EICLR_IRQ2_CLR (0x1 << 2 ) /* CLR */
+
+/* EICLR[IRQ1] - Clears External interrupt 1 internal flag */
+#define EICLR_IRQ1_BBA (*(volatile unsigned long *) 0x42048604)
+#define EICLR_IRQ1_MSK (0x1 << 1 )
+#define EICLR_IRQ1 (0x1 << 1 )
+#define EICLR_IRQ1_CLR (0x1 << 1 ) /* CLR */
+
+/* EICLR[IRQ0] - Clears External interrupt 0 internal flag */
+#define EICLR_IRQ0_BBA (*(volatile unsigned long *) 0x42048600)
+#define EICLR_IRQ0_MSK (0x1 << 0 )
+#define EICLR_IRQ0 (0x1 << 0 )
+#define EICLR_IRQ0_CLR (0x1 << 0 ) /* CLR */
+// ------------------------------------------------------------------------------------------------
+// ----- WDT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Watchdog Timer (pADI_WDT)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_WDT Structure */
+ __IO uint16_t
+ T3LD; /*!< Load value. */
+ __I uint16_t RESERVED0;
+ __IO uint16_t
+ T3VAL; /*!< "Current count value, read only." */
+ __I uint16_t RESERVED1;
+ __IO uint16_t
+ T3CON; /*!< Control Register */
+ __I uint16_t RESERVED2;
+ __IO uint16_t
+ T3CLRI; /*!< "Clear interrupt, write only." */
+ __I uint16_t RESERVED3[5];
+ __IO uint16_t
+ T3STA; /*!< "Status register, read only." */
+} ADI_WDT_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define T3LD (*(volatile unsigned short int *) 0x40002580)
+#define T3VAL (*(volatile unsigned short int *) 0x40002584)
+#define T3CON (*(volatile unsigned short int *) 0x40002588)
+#define T3CLRI (*(volatile unsigned short int *) 0x4000258C)
+#define T3STA (*(volatile unsigned short int *) 0x40002598)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for T3LD*/
+#define T3LD_RVAL 0x1000
+
+/* T3LD[VALUE] - Current Value */
+#define T3LD_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T3VAL*/
+#define T3VAL_RVAL 0x1000
+
+/* T3VAL[VALUE] - Current Value */
+#define T3VAL_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T3CON*/
+#define T3CON_RVAL 0xE9
+
+/* T3CON[MOD] - Mode */
+#define T3CON_MOD_BBA (*(volatile unsigned long *) 0x4204B118)
+#define T3CON_MOD_MSK (0x1 << 6 )
+#define T3CON_MOD (0x1 << 6 )
+#define T3CON_MOD_FREERUN (0x0 << 6 ) /* FREERUN */
+#define T3CON_MOD_PERIODIC (0x1 << 6 ) /* PERIODIC */
+
+/* T3CON[ENABLE] - Enable */
+#define T3CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204B114)
+#define T3CON_ENABLE_MSK (0x1 << 5 )
+#define T3CON_ENABLE (0x1 << 5 )
+#define T3CON_ENABLE_DIS (0x0 << 5 ) /* DIS */
+#define T3CON_ENABLE_EN (0x1 << 5 ) /* EN */
+
+/* T3CON[PRE] - Prescaler */
+#define T3CON_PRE_MSK (0x3 << 2 )
+#define T3CON_PRE_DIV1 (0x0 << 2 ) /* DIV1 */
+#define T3CON_PRE_DIV16 (0x1 << 2 ) /* DIV16 */
+#define T3CON_PRE_DIV256 (0x2 << 2 ) /* DIV256 */
+#define T3CON_PRE_DIV4096 (0x3 << 2 ) /* DIV4096 */
+
+/* T3CON[IRQ] - Timer Interrupt , */
+#define T3CON_IRQ_BBA (*(volatile unsigned long *) 0x4204B104)
+#define T3CON_IRQ_MSK (0x1 << 1 )
+#define T3CON_IRQ (0x1 << 1 )
+#define T3CON_IRQ_DIS (0x0 << 1 ) /* DIS */
+#define T3CON_IRQ_EN (0x1 << 1 ) /* EN */
+
+/* T3CON[PD] - Power down clear */
+#define T3CON_PD_BBA (*(volatile unsigned long *) 0x4204B100)
+#define T3CON_PD_MSK (0x1 << 0 )
+#define T3CON_PD (0x1 << 0 )
+#define T3CON_PD_DIS (0x0 << 0 ) /* DIS */
+#define T3CON_PD_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for T3CLRI*/
+#define T3CLRI_RVAL 0x0
+
+/* T3CLRI[VALUE] - Clear Watchdog */
+#define T3CLRI_VALUE_MSK (0xFFFF << 0 )
+#define T3CLRI_VALUE_CLR (0xCCCC << 0 ) /* CLR */
+
+/* Reset Value for T3STA*/
+#define T3STA_RVAL 0x20
+
+/* T3STA[LOCK] - Lock status bit */
+#define T3STA_LOCK_BBA (*(volatile unsigned long *) 0x4204B310)
+#define T3STA_LOCK_MSK (0x1 << 4 )
+#define T3STA_LOCK (0x1 << 4 )
+#define T3STA_LOCK_CLR (0x0 << 4 ) /* CLR */
+#define T3STA_LOCK_SET (0x1 << 4 ) /* SET */
+
+/* T3STA[CON] - T3CON write sync in progress */
+#define T3STA_CON_BBA (*(volatile unsigned long *) 0x4204B30C)
+#define T3STA_CON_MSK (0x1 << 3 )
+#define T3STA_CON (0x1 << 3 )
+#define T3STA_CON_CLR (0x0 << 3 ) /* CLR */
+#define T3STA_CON_SET (0x1 << 3 ) /* SET */
+
+/* T3STA[LD] - T3LD write sync in progress */
+#define T3STA_LD_BBA (*(volatile unsigned long *) 0x4204B308)
+#define T3STA_LD_MSK (0x1 << 2 )
+#define T3STA_LD (0x1 << 2 )
+#define T3STA_LD_CLR (0x0 << 2 ) /* CLR */
+#define T3STA_LD_SET (0x1 << 2 ) /* SET */
+
+/* T3STA[CLRI] - T3CLRI write sync in progress */
+#define T3STA_CLRI_BBA (*(volatile unsigned long *) 0x4204B304)
+#define T3STA_CLRI_MSK (0x1 << 1 )
+#define T3STA_CLRI (0x1 << 1 )
+#define T3STA_CLRI_CLR (0x0 << 1 ) /* CLR */
+#define T3STA_CLRI_SET (0x1 << 1 ) /* SET */
+
+/* T3STA[IRQ] - Interrupt Pending */
+#define T3STA_IRQ_BBA (*(volatile unsigned long *) 0x4204B300)
+#define T3STA_IRQ_MSK (0x1 << 0 )
+#define T3STA_IRQ (0x1 << 0 )
+#define T3STA_IRQ_CLR (0x0 << 0 ) /* CLR */
+#define T3STA_IRQ_SET (0x1 << 0 ) /* SET */
+// ------------------------------------------------------------------------------------------------
+// ----- WUT -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief WakeUp Timer (pADI_WUT)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_WUT Structure */
+ __IO uint16_t
+ T2VAL0; /*!< Current count value LSB */
+ __I uint16_t RESERVED0;
+ __IO uint16_t
+ T2VAL1; /*!< Current count value MSB */
+ __I uint16_t RESERVED1;
+ __IO uint16_t
+ T2CON; /*!< Control Register */
+ __I uint16_t RESERVED2;
+ __IO uint16_t
+ T2INC; /*!< 12-bit register. Wake up field A */
+ __I uint16_t RESERVED3;
+ __IO uint16_t
+ T2WUFB0; /*!< Wake up field B LSB */
+ __I uint16_t RESERVED4;
+ __IO uint16_t
+ T2WUFB1; /*!< Wake up field B MSB */
+ __I uint16_t RESERVED5;
+ __IO uint16_t
+ T2WUFC0; /*!< Wake up field C LSB */
+ __I uint16_t RESERVED6;
+ __IO uint16_t
+ T2WUFC1; /*!< Wake up field C MSB */
+ __I uint16_t RESERVED7;
+ __IO uint16_t
+ T2WUFD0; /*!< Wake up field D LSB */
+ __I uint16_t RESERVED8;
+ __IO uint16_t
+ T2WUFD1; /*!< Wake up field D MSB */
+ __I uint16_t RESERVED9;
+ __IO uint16_t
+ T2IEN; /*!< Interrupt enable */
+ __I uint16_t RESERVED10;
+ __IO uint16_t
+ T2STA; /*!< Status */
+ __I uint16_t RESERVED11;
+ __IO uint16_t
+ T2CLRI; /*!< Clear interrupts. Write only. */
+ __I uint16_t RESERVED12[5];
+ __IO uint16_t
+ T2WUFA0; /*!< Wake up field A LSB. */
+ __I uint16_t RESERVED13;
+ __IO uint16_t
+ T2WUFA1; /*!< Wake up field A MSB. */
+} ADI_WUT_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define T2VAL0 (*(volatile unsigned short int *) 0x40002500)
+#define T2VAL1 (*(volatile unsigned short int *) 0x40002504)
+#define T2CON (*(volatile unsigned short int *) 0x40002508)
+#define T2INC (*(volatile unsigned short int *) 0x4000250C)
+#define T2WUFB0 (*(volatile unsigned short int *) 0x40002510)
+#define T2WUFB1 (*(volatile unsigned short int *) 0x40002514)
+#define T2WUFC0 (*(volatile unsigned short int *) 0x40002518)
+#define T2WUFC1 (*(volatile unsigned short int *) 0x4000251C)
+#define T2WUFD0 (*(volatile unsigned short int *) 0x40002520)
+#define T2WUFD1 (*(volatile unsigned short int *) 0x40002524)
+#define T2IEN (*(volatile unsigned short int *) 0x40002528)
+#define T2STA (*(volatile unsigned short int *) 0x4000252C)
+#define T2CLRI (*(volatile unsigned short int *) 0x40002530)
+#define T2WUFA0 (*(volatile unsigned short int *) 0x4000253C)
+#define T2WUFA1 (*(volatile unsigned short int *) 0x40002540)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for T2VAL0*/
+#define T2VAL0_RVAL 0x0
+
+/* T2VAL0[VALUE] - Current Value */
+#define T2VAL0_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2VAL1*/
+#define T2VAL1_RVAL 0x0
+
+/* T2VAL1[VALUE] - Current Value */
+#define T2VAL1_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2CON*/
+#define T2CON_RVAL 0x40
+
+/* T2CON[STOPINC] - Stop wake up field A being updated */
+#define T2CON_STOPINC_BBA (*(volatile unsigned long *) 0x4204A12C)
+#define T2CON_STOPINC_MSK (0x1 << 11 )
+#define T2CON_STOPINC (0x1 << 11 )
+#define T2CON_STOPINC_DIS (0x0 << 11 ) /* DIS */
+#define T2CON_STOPINC_EN (0x1 << 11 ) /* EN */
+
+/* T2CON[CLK] - Clock */
+#define T2CON_CLK_MSK (0x3 << 9 )
+#define T2CON_CLK_PCLK (0x0 << 9 ) /* PCLK */
+#define T2CON_CLK_LFXTAL (0x1 << 9 ) /* LFXTAL */
+#define T2CON_CLK_LFOSC (0x2 << 9 ) /* LFOSC */
+#define T2CON_CLK_EXTCLK (0x3 << 9 ) /* EXTCLK */
+
+/* T2CON[WUEN] - WUEN */
+#define T2CON_WUEN_BBA (*(volatile unsigned long *) 0x4204A120)
+#define T2CON_WUEN_MSK (0x1 << 8 )
+#define T2CON_WUEN (0x1 << 8 )
+#define T2CON_WUEN_DIS (0x0 << 8 ) /* DIS */
+#define T2CON_WUEN_EN (0x1 << 8 ) /* EN */
+
+/* T2CON[ENABLE] - Enable */
+#define T2CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204A11C)
+#define T2CON_ENABLE_MSK (0x1 << 7 )
+#define T2CON_ENABLE (0x1 << 7 )
+#define T2CON_ENABLE_DIS (0x0 << 7 ) /* DIS */
+#define T2CON_ENABLE_EN (0x1 << 7 ) /* EN */
+
+/* T2CON[MOD] - Mode */
+#define T2CON_MOD_BBA (*(volatile unsigned long *) 0x4204A118)
+#define T2CON_MOD_MSK (0x1 << 6 )
+#define T2CON_MOD (0x1 << 6 )
+#define T2CON_MOD_PERIODIC (0x0 << 6 ) /* PERIODIC */
+#define T2CON_MOD_FREERUN (0x1 << 6 ) /* FREERUN */
+
+/* T2CON[FREEZE] - Freeze */
+#define T2CON_FREEZE_BBA (*(volatile unsigned long *) 0x4204A10C)
+#define T2CON_FREEZE_MSK (0x1 << 3 )
+#define T2CON_FREEZE (0x1 << 3 )
+#define T2CON_FREEZE_DIS (0x0 << 3 ) /* DIS */
+#define T2CON_FREEZE_EN (0x1 << 3 ) /* EN */
+
+/* T2CON[PRE] - Prescaler */
+#define T2CON_PRE_MSK (0x3 << 0 )
+#define T2CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
+#define T2CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
+#define T2CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
+#define T2CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 */
+
+/* Reset Value for T2INC*/
+#define T2INC_RVAL 0xC8
+
+/* T2INC[VALUE] - 12 bit value */
+#define T2INC_VALUE_MSK (0xFFF << 0 )
+
+/* Reset Value for T2WUFB0*/
+#define T2WUFB0_RVAL 0x1FFF
+
+/* T2WUFB0[VALUE] - Current Value */
+#define T2WUFB0_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2WUFB1*/
+#define T2WUFB1_RVAL 0x0
+
+/* T2WUFB1[VALUE] - Current Value */
+#define T2WUFB1_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2WUFC0*/
+#define T2WUFC0_RVAL 0x2FFF
+
+/* T2WUFC0[VALUE] - Current Value */
+#define T2WUFC0_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2WUFC1*/
+#define T2WUFC1_RVAL 0x0
+
+/* T2WUFC1[VALUE] - Current Value */
+#define T2WUFC1_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2WUFD0*/
+#define T2WUFD0_RVAL 0x3FFF
+
+/* T2WUFD0[VALUE] - Current Value */
+#define T2WUFD0_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2WUFD1*/
+#define T2WUFD1_RVAL 0x0
+
+/* T2WUFD1[VALUE] - Current Value */
+#define T2WUFD1_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2IEN*/
+#define T2IEN_RVAL 0x0
+
+/* T2IEN[ROLL] - Enable interrupt on Rollover */
+#define T2IEN_ROLL_BBA (*(volatile unsigned long *) 0x4204A510)
+#define T2IEN_ROLL_MSK (0x1 << 4 )
+#define T2IEN_ROLL (0x1 << 4 )
+#define T2IEN_ROLL_DIS (0x0 << 4 ) /* DIS */
+#define T2IEN_ROLL_EN (0x1 << 4 ) /* EN */
+
+/* T2IEN[WUFD] - Enable interrupt on WUFD */
+#define T2IEN_WUFD_BBA (*(volatile unsigned long *) 0x4204A50C)
+#define T2IEN_WUFD_MSK (0x1 << 3 )
+#define T2IEN_WUFD (0x1 << 3 )
+#define T2IEN_WUFD_DIS (0x0 << 3 ) /* DIS */
+#define T2IEN_WUFD_EN (0x1 << 3 ) /* EN */
+
+/* T2IEN[WUFC] - Enable interrupt on WUFC */
+#define T2IEN_WUFC_BBA (*(volatile unsigned long *) 0x4204A508)
+#define T2IEN_WUFC_MSK (0x1 << 2 )
+#define T2IEN_WUFC (0x1 << 2 )
+#define T2IEN_WUFC_DIS (0x0 << 2 ) /* DIS */
+#define T2IEN_WUFC_EN (0x1 << 2 ) /* EN */
+
+/* T2IEN[WUFB] - Enable interrupt on WUFB */
+#define T2IEN_WUFB_BBA (*(volatile unsigned long *) 0x4204A504)
+#define T2IEN_WUFB_MSK (0x1 << 1 )
+#define T2IEN_WUFB (0x1 << 1 )
+#define T2IEN_WUFB_DIS (0x0 << 1 ) /* DIS */
+#define T2IEN_WUFB_EN (0x1 << 1 ) /* EN */
+
+/* T2IEN[WUFA] - Enable interrupt on WUFA */
+#define T2IEN_WUFA_BBA (*(volatile unsigned long *) 0x4204A500)
+#define T2IEN_WUFA_MSK (0x1 << 0 )
+#define T2IEN_WUFA (0x1 << 0 )
+#define T2IEN_WUFA_DIS (0x0 << 0 ) /* DIS */
+#define T2IEN_WUFA_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for T2STA*/
+#define T2STA_RVAL 0x0
+
+/* T2STA[CON] - Sync */
+#define T2STA_CON_BBA (*(volatile unsigned long *) 0x4204A5A0)
+#define T2STA_CON_MSK (0x1 << 8 )
+#define T2STA_CON (0x1 << 8 )
+#define T2STA_CON_CLR (0x0 << 8 ) /* CLR */
+#define T2STA_CON_SET (0x1 << 8 ) /* SET */
+
+/* T2STA[FREEZE] - Timer Value Freeze */
+#define T2STA_FREEZE_BBA (*(volatile unsigned long *) 0x4204A59C)
+#define T2STA_FREEZE_MSK (0x1 << 7 )
+#define T2STA_FREEZE (0x1 << 7 )
+#define T2STA_FREEZE_CLR (0x0 << 7 ) /* CLR */
+#define T2STA_FREEZE_SET (0x1 << 7 ) /* SET */
+
+/* T2STA[ROLL] - Rollover Interrupt */
+#define T2STA_ROLL_BBA (*(volatile unsigned long *) 0x4204A590)
+#define T2STA_ROLL_MSK (0x1 << 4 )
+#define T2STA_ROLL (0x1 << 4 )
+#define T2STA_ROLL_CLR (0x0 << 4 ) /* CLR */
+#define T2STA_ROLL_SET (0x1 << 4 ) /* SET */
+
+/* T2STA[WUFD] - WUFD Interrupt */
+#define T2STA_WUFD_BBA (*(volatile unsigned long *) 0x4204A58C)
+#define T2STA_WUFD_MSK (0x1 << 3 )
+#define T2STA_WUFD (0x1 << 3 )
+#define T2STA_WUFD_CLR (0x0 << 3 ) /* CLR */
+#define T2STA_WUFD_SET (0x1 << 3 ) /* SET */
+
+/* T2STA[WUFC] - WUFC Interrupt */
+#define T2STA_WUFC_BBA (*(volatile unsigned long *) 0x4204A588)
+#define T2STA_WUFC_MSK (0x1 << 2 )
+#define T2STA_WUFC (0x1 << 2 )
+#define T2STA_WUFC_CLR (0x0 << 2 ) /* CLR */
+#define T2STA_WUFC_SET (0x1 << 2 ) /* SET */
+
+/* T2STA[WUFB] - WUFB Interrupt */
+#define T2STA_WUFB_BBA (*(volatile unsigned long *) 0x4204A584)
+#define T2STA_WUFB_MSK (0x1 << 1 )
+#define T2STA_WUFB (0x1 << 1 )
+#define T2STA_WUFB_CLR (0x0 << 1 ) /* CLR */
+#define T2STA_WUFB_SET (0x1 << 1 ) /* SET */
+
+/* T2STA[WUFA] - WUFA Interrupt */
+#define T2STA_WUFA_BBA (*(volatile unsigned long *) 0x4204A580)
+#define T2STA_WUFA_MSK (0x1 << 0 )
+#define T2STA_WUFA (0x1 << 0 )
+#define T2STA_WUFA_CLR (0x0 << 0 ) /* CLR */
+#define T2STA_WUFA_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for T2CLRI*/
+#define T2CLRI_RVAL 0x0
+
+/* T2CLRI[ROLL] - Clear interrupt on Rollover */
+#define T2CLRI_ROLL_BBA (*(volatile unsigned long *) 0x4204A610)
+#define T2CLRI_ROLL_MSK (0x1 << 4 )
+#define T2CLRI_ROLL (0x1 << 4 )
+#define T2CLRI_ROLL_CLR (0x1 << 4 ) /* CLR */
+
+/* T2CLRI[WUFD] - Clear interrupt on WUFD */
+#define T2CLRI_WUFD_BBA (*(volatile unsigned long *) 0x4204A60C)
+#define T2CLRI_WUFD_MSK (0x1 << 3 )
+#define T2CLRI_WUFD (0x1 << 3 )
+#define T2CLRI_WUFD_CLR (0x1 << 3 ) /* CLR */
+
+/* T2CLRI[WUFC] - Clear interrupt on WUFC */
+#define T2CLRI_WUFC_BBA (*(volatile unsigned long *) 0x4204A608)
+#define T2CLRI_WUFC_MSK (0x1 << 2 )
+#define T2CLRI_WUFC (0x1 << 2 )
+#define T2CLRI_WUFC_CLR (0x1 << 2 ) /* CLR */
+
+/* T2CLRI[WUFB] - Clear interrupt on WUFB */
+#define T2CLRI_WUFB_BBA (*(volatile unsigned long *) 0x4204A604)
+#define T2CLRI_WUFB_MSK (0x1 << 1 )
+#define T2CLRI_WUFB (0x1 << 1 )
+#define T2CLRI_WUFB_CLR (0x1 << 1 ) /* CLR */
+
+/* T2CLRI[WUFA] - Clear interrupt on WUFA */
+#define T2CLRI_WUFA_BBA (*(volatile unsigned long *) 0x4204A600)
+#define T2CLRI_WUFA_MSK (0x1 << 0 )
+#define T2CLRI_WUFA (0x1 << 0 )
+#define T2CLRI_WUFA_CLR (0x1 << 0 ) /* CLR */
+
+/* Reset Value for T2WUFA0*/
+#define T2WUFA0_RVAL 0x1900
+
+/* T2WUFA0[VALUE] - Current Value */
+#define T2WUFA0_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for T2WUFA1*/
+#define T2WUFA1_RVAL 0x0
+
+/* T2WUFA1[VALUE] - Current Value */
+#define T2WUFA1_VALUE_MSK (0xFFFF << 0 )
+// ------------------------------------------------------------------------------------------------
+// ----- CLKCTL -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Clock Control (pADI_CLKCTL)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_CLKCTL Structure */
+ __IO uint16_t
+ CLKCON0; /*!< System clocking architecture control register */
+ __I uint16_t RESERVED0;
+ __IO uint16_t
+ CLKCON1; /*!< System Clocks Control Register 1 */
+ __I uint16_t RESERVED1[19];
+ __IO uint16_t
+ CLKDIS; /*!< System Clocks Control Register 1 */
+ __I uint16_t RESERVED2[497];
+ __IO uint8_t
+ XOSCCON; /*!< Crystal Oscillator control */
+ __I uint8_t RESERVED3[51];
+ __IO uint16_t
+ CLKSYSDIV; /*!< Sys Clock div2 Register */
+} ADI_CLKCTL_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define CLKCON0 (*(volatile unsigned short int *) 0x40002000)
+#define CLKCON1 (*(volatile unsigned short int *) 0x40002004)
+#define CLKDIS (*(volatile unsigned short int *) 0x4000202C)
+#define XOSCCON (*(volatile unsigned char *) 0x40002410)
+#define CLKSYSDIV (*(volatile unsigned short int *) 0x40002444)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for CLKCON0*/
+#define CLKCON0_RVAL 0x0
+
+/* CLKCON0[CLKOUT] - GPIO output clock multiplexer select bits */
+#define CLKCON0_CLKOUT_MSK (0x7 << 5 )
+#define CLKCON0_CLKOUT_UCLKCG (0x0 << 5 ) /* UCLKCG */
+#define CLKCON0_CLKOUT_UCLK (0x1 << 5 ) /* UCLK */
+#define CLKCON0_CLKOUT_PCLK (0x2 << 5 ) /* PCLK */
+#define CLKCON0_CLKOUT_HFOSC (0x5 << 5 ) /* HFOSC */
+#define CLKCON0_CLKOUT_LFOSC (0x6 << 5 ) /* LFOSC */
+#define CLKCON0_CLKOUT_LFXTAL (0x7 << 5 ) /* LFXTAL */
+
+/* CLKCON0[CLKMUX] - Digital subsystem clock source select bits. */
+#define CLKCON0_CLKMUX_MSK (0x3 << 3 )
+#define CLKCON0_CLKMUX_HFOSC (0x0 << 3 ) /* HFOSC */
+#define CLKCON0_CLKMUX_LFXTAL (0x1 << 3 ) /* LFXTAL */
+#define CLKCON0_CLKMUX_LFOSC (0x2 << 3 ) /* LFOSC */
+#define CLKCON0_CLKMUX_EXTCLK (0x3 << 3 ) /* EXTCLK */
+
+/* CLKCON0[CD] - Clock divide bits */
+#define CLKCON0_CD_MSK (0x7 << 0 )
+#define CLKCON0_CD_DIV1 (0x0 << 0 ) /* DIV1 */
+#define CLKCON0_CD_DIV2 (0x1 << 0 ) /* DIV2 */
+#define CLKCON0_CD_DIV4 (0x2 << 0 ) /* DIV4 */
+#define CLKCON0_CD_DIV8 (0x3 << 0 ) /* DIV8 */
+#define CLKCON0_CD_DIV16 (0x4 << 0 ) /* DIV16 */
+#define CLKCON0_CD_DIV32 (0x5 << 0 ) /* DIV32 */
+#define CLKCON0_CD_DIV64 (0x6 << 0 ) /* DIV64 */
+#define CLKCON0_CD_DIV128 (0x7 << 0 ) /* DIV128 */
+
+/* Reset Value for CLKCON1*/
+#define CLKCON1_RVAL 0x0
+
+/* CLKCON1[PWMCD] - Clock divide bits for PWM system clock */
+#define CLKCON1_PWMCD_MSK (0x7 << 12 )
+#define CLKCON1_PWMCD_DIV1 (0x0 << 12 ) /* DIV1 */
+#define CLKCON1_PWMCD_DIV2 (0x1 << 12 ) /* DIV2 */
+#define CLKCON1_PWMCD_DIV4 (0x2 << 12 ) /* DIV4 */
+#define CLKCON1_PWMCD_DIV8 (0x3 << 12 ) /* DIV8 */
+#define CLKCON1_PWMCD_DIV16 (0x4 << 12 ) /* DIV16 */
+#define CLKCON1_PWMCD_DIV32 (0x5 << 12 ) /* DIV32 */
+#define CLKCON1_PWMCD_DIV64 (0x6 << 12 ) /* DIV64 */
+#define CLKCON1_PWMCD_DIV128 (0x7 << 12 ) /* DIV128 */
+
+/* CLKCON1[UARTCD] - Clock divide bits for UART system clock */
+#define CLKCON1_UARTCD_MSK (0x7 << 9 )
+#define CLKCON1_UARTCD_DIV1 (0x0 << 9 ) /* DIV1 */
+#define CLKCON1_UARTCD_DIV2 (0x1 << 9 ) /* DIV2 */
+#define CLKCON1_UARTCD_DIV4 (0x2 << 9 ) /* DIV4 */
+#define CLKCON1_UARTCD_DIV8 (0x3 << 9 ) /* DIV8 */
+#define CLKCON1_UARTCD_DIV16 (0x4 << 9 ) /* DIV16 */
+#define CLKCON1_UARTCD_DIV32 (0x5 << 9 ) /* DIV32 */
+#define CLKCON1_UARTCD_DIV64 (0x6 << 9 ) /* DIV64 */
+#define CLKCON1_UARTCD_DIV128 (0x7 << 9 ) /* DIV128 */
+
+/* CLKCON1[I2CCD] - Clock divide bits for I2C system clock */
+#define CLKCON1_I2CCD_MSK (0x7 << 6 )
+#define CLKCON1_I2CCD_DIV1 (0x0 << 6 ) /* DIV1 */
+#define CLKCON1_I2CCD_DIV2 (0x1 << 6 ) /* DIV2 */
+#define CLKCON1_I2CCD_DIV4 (0x2 << 6 ) /* DIV4 */
+#define CLKCON1_I2CCD_DIV8 (0x3 << 6 ) /* DIV8 */
+#define CLKCON1_I2CCD_DIV16 (0x4 << 6 ) /* DIV16 */
+#define CLKCON1_I2CCD_DIV32 (0x5 << 6 ) /* DIV32 */
+#define CLKCON1_I2CCD_DIV64 (0x6 << 6 ) /* DIV64 */
+#define CLKCON1_I2CCD_DIV128 (0x7 << 6 ) /* DIV128 */
+
+/* CLKCON1[SPI1CD] - Clock divide bits for SPI1 system clock */
+#define CLKCON1_SPI1CD_MSK (0x7 << 3 )
+#define CLKCON1_SPI1CD_DIV1 (0x0 << 3 ) /* DIV1 */
+#define CLKCON1_SPI1CD_DIV2 (0x1 << 3 ) /* DIV2 */
+#define CLKCON1_SPI1CD_DIV4 (0x2 << 3 ) /* DIV4 */
+#define CLKCON1_SPI1CD_DIV8 (0x3 << 3 ) /* DIV8 */
+#define CLKCON1_SPI1CD_DIV16 (0x4 << 3 ) /* DIV16 */
+#define CLKCON1_SPI1CD_DIV32 (0x5 << 3 ) /* DIV32 */
+#define CLKCON1_SPI1CD_DIV64 (0x6 << 3 ) /* DIV64 */
+#define CLKCON1_SPI1CD_DIV128 (0x7 << 3 ) /* DIV128 */
+
+/* CLKCON1[SPI0CD] - Clock divide bits for SPI0 system clock */
+#define CLKCON1_SPI0CD_MSK (0x7 << 0 )
+#define CLKCON1_SPI0CD_DIV1 (0x0 << 0 ) /* DIV1 */
+#define CLKCON1_SPI0CD_DIV2 (0x1 << 0 ) /* DIV2 */
+#define CLKCON1_SPI0CD_DIV4 (0x2 << 0 ) /* DIV4 */
+#define CLKCON1_SPI0CD_DIV8 (0x3 << 0 ) /* DIV8 */
+#define CLKCON1_SPI0CD_DIV16 (0x4 << 0 ) /* DIV16 */
+#define CLKCON1_SPI0CD_DIV32 (0x5 << 0 ) /* DIV32 */
+#define CLKCON1_SPI0CD_DIV64 (0x6 << 0 ) /* DIV64 */
+#define CLKCON1_SPI0CD_DIV128 (0x7 << 0 ) /* DIV128 */
+
+/* Reset Value for CLKDIS*/
+#define CLKDIS_RVAL 0xFFFF
+
+/* CLKDIS[DISADCCLK] - Disable ADC system clock */
+#define CLKDIS_DISADCCLK_BBA (*(volatile unsigned long *) 0x420405A4)
+#define CLKDIS_DISADCCLK_MSK (0x1 << 9 )
+#define CLKDIS_DISADCCLK (0x1 << 9 )
+#define CLKDIS_DISADCCLK_DIS (0x0 << 9 ) /* DIS */
+#define CLKDIS_DISADCCLK_EN (0x1 << 9 ) /* EN */
+
+/* CLKDIS[DISDMACLK] - Disable DMA system clock */
+#define CLKDIS_DISDMACLK_BBA (*(volatile unsigned long *) 0x420405A0)
+#define CLKDIS_DISDMACLK_MSK (0x1 << 8 )
+#define CLKDIS_DISDMACLK (0x1 << 8 )
+#define CLKDIS_DISDMACLK_DIS (0x0 << 8 ) /* DIS */
+#define CLKDIS_DISDMACLK_EN (0x1 << 8 ) /* EN */
+
+/* CLKDIS[DISDACCLK] - Disable DAC system clock */
+#define CLKDIS_DISDACCLK_BBA (*(volatile unsigned long *) 0x4204059C)
+#define CLKDIS_DISDACCLK_MSK (0x1 << 7 )
+#define CLKDIS_DISDACCLK (0x1 << 7 )
+#define CLKDIS_DISDACCLK_DIS (0x0 << 7 ) /* DIS */
+#define CLKDIS_DISDACCLK_EN (0x1 << 7 ) /* EN */
+
+/* CLKDIS[DIST1CLK] - Disable Timer 1 system clock */
+#define CLKDIS_DIST1CLK_BBA (*(volatile unsigned long *) 0x42040598)
+#define CLKDIS_DIST1CLK_MSK (0x1 << 6 )
+#define CLKDIS_DIST1CLK (0x1 << 6 )
+#define CLKDIS_DIST1CLK_DIS (0x0 << 6 ) /* DIS */
+#define CLKDIS_DIST1CLK_EN (0x1 << 6 ) /* EN */
+
+/* CLKDIS[DIST0CLK] - Disable Timer 0 system clock */
+#define CLKDIS_DIST0CLK_BBA (*(volatile unsigned long *) 0x42040594)
+#define CLKDIS_DIST0CLK_MSK (0x1 << 5 )
+#define CLKDIS_DIST0CLK (0x1 << 5 )
+#define CLKDIS_DIST0CLK_DIS (0x0 << 5 ) /* DIS */
+#define CLKDIS_DIST0CLK_EN (0x1 << 5 ) /* EN */
+
+/* CLKDIS[DISPWMCLK] - Disable PWM system clock */
+#define CLKDIS_DISPWMCLK_BBA (*(volatile unsigned long *) 0x42040590)
+#define CLKDIS_DISPWMCLK_MSK (0x1 << 4 )
+#define CLKDIS_DISPWMCLK (0x1 << 4 )
+#define CLKDIS_DISPWMCLK_DIS (0x0 << 4 ) /* DIS */
+#define CLKDIS_DISPWMCLK_EN (0x1 << 4 ) /* EN */
+
+/* CLKDIS[DISUARTCLK] - Disable UART system clock */
+#define CLKDIS_DISUARTCLK_BBA (*(volatile unsigned long *) 0x4204058C)
+#define CLKDIS_DISUARTCLK_MSK (0x1 << 3 )
+#define CLKDIS_DISUARTCLK (0x1 << 3 )
+#define CLKDIS_DISUARTCLK_DIS (0x0 << 3 ) /* DIS */
+#define CLKDIS_DISUARTCLK_EN (0x1 << 3 ) /* EN */
+
+/* CLKDIS[DISI2CCLK] - Disable I2C system clock */
+#define CLKDIS_DISI2CCLK_BBA (*(volatile unsigned long *) 0x42040588)
+#define CLKDIS_DISI2CCLK_MSK (0x1 << 2 )
+#define CLKDIS_DISI2CCLK (0x1 << 2 )
+#define CLKDIS_DISI2CCLK_DIS (0x0 << 2 ) /* DIS */
+#define CLKDIS_DISI2CCLK_EN (0x1 << 2 ) /* EN */
+
+/* CLKDIS[DISSPI1CLK] - Disable SPI1 system clock */
+#define CLKDIS_DISSPI1CLK_BBA (*(volatile unsigned long *) 0x42040584)
+#define CLKDIS_DISSPI1CLK_MSK (0x1 << 1 )
+#define CLKDIS_DISSPI1CLK (0x1 << 1 )
+#define CLKDIS_DISSPI1CLK_DIS (0x0 << 1 ) /* DIS */
+#define CLKDIS_DISSPI1CLK_EN (0x1 << 1 ) /* EN */
+
+/* CLKDIS[DISSPI0CLK] - Disable SPI0 system clock bits */
+#define CLKDIS_DISSPI0CLK_BBA (*(volatile unsigned long *) 0x42040580)
+#define CLKDIS_DISSPI0CLK_MSK (0x1 << 0 )
+#define CLKDIS_DISSPI0CLK (0x1 << 0 )
+#define CLKDIS_DISSPI0CLK_DIS (0x0 << 0 ) /* DIS */
+#define CLKDIS_DISSPI0CLK_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for XOSCCON*/
+#define XOSCCON_RVAL 0x0
+
+/* XOSCCON[DIV2] - Divide by two enable */
+#define XOSCCON_DIV2_BBA (*(volatile unsigned long *) 0x42048208)
+#define XOSCCON_DIV2_MSK (0x1 << 2 )
+#define XOSCCON_DIV2 (0x1 << 2 )
+#define XOSCCON_DIV2_DIS (0x0 << 2 ) /* DIS */
+#define XOSCCON_DIV2_EN (0x1 << 2 ) /* EN */
+
+/* XOSCCON[ENABLE] - Crystal oscillator circuit enable (Enable the oscillator circuitry.) */
+#define XOSCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42048200)
+#define XOSCCON_ENABLE_MSK (0x1 << 0 )
+#define XOSCCON_ENABLE (0x1 << 0 )
+#define XOSCCON_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define XOSCCON_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for CLKSYSDIV*/
+#define CLKSYSDIV_RVAL 0x0
+
+/* CLKSYSDIV[DIV2EN] - bits */
+#define CLKSYSDIV_DIV2EN_BBA (*(volatile unsigned long *) 0x42048880)
+#define CLKSYSDIV_DIV2EN_MSK (0x1 << 0 )
+#define CLKSYSDIV_DIV2EN (0x1 << 0 )
+#define CLKSYSDIV_DIV2EN_DIS (0x0 << 0 ) /* DIS */
+#define CLKSYSDIV_DIV2EN_EN (0x1 << 0 ) /* EN */
+// ------------------------------------------------------------------------------------------------
+// ----- FEE -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Flash Controller (pADI_FEE)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_FEE Structure */
+ __IO uint16_t
+ FEESTA; /*!< Status Register */
+ __I uint16_t RESERVED0;
+ __IO uint16_t
+ FEECON0; /*!< Command Control Register */
+ __I uint16_t RESERVED1;
+ __IO uint16_t
+ FEECMD; /*!< Command register */
+ __I uint16_t RESERVED2[3];
+ __IO uint16_t
+ FEEADR0L; /*!< Low Page (Lower 16 bits) */
+ __I uint16_t RESERVED3;
+ __IO uint16_t
+ FEEADR0H; /*!< Low Page (Upper 16 bits) */
+ __I uint16_t RESERVED4;
+ __IO uint16_t
+ FEEADR1L; /*!< Hi Page (Lower 16 bits) */
+ __I uint16_t RESERVED5;
+ __IO uint16_t
+ FEEADR1H; /*!< Hi Page (Upper 16 bits) */
+ __I uint16_t RESERVED6;
+ __IO uint16_t
+ FEEKEY; /*!< Key */
+ __I uint16_t RESERVED7[3];
+ __IO uint16_t
+ FEEPROL; /*!< Write Protection (Lower 16 bits) */
+ __I uint16_t RESERVED8;
+ __IO uint16_t
+ FEEPROH; /*!< Write Protection (Upper 16 bits) */
+ __I uint16_t RESERVED9;
+ __IO uint16_t
+ FEESIGL; /*!< Signature (Lower 16 bits) */
+ __I uint16_t RESERVED10;
+ __IO uint16_t
+ FEESIGH; /*!< Signature (Upper 16 bits) */
+ __I uint16_t RESERVED11;
+ __IO uint16_t
+ FEECON1; /*!< User Setup register */
+ __I uint16_t RESERVED12[7];
+ __IO uint16_t
+ FEEADRAL; /*!< Abort address (Lower 16 bits) */
+ __I uint16_t RESERVED13;
+ __IO uint16_t
+ FEEADRAH; /*!< Abort address (Upper 16 bits) */
+ __I uint16_t RESERVED14[21];
+ __IO uint16_t
+ FEEAEN0; /*!< Lower 16 bits of the sys irq abort enable register. */
+ __I uint16_t RESERVED15;
+ __IO uint16_t
+ FEEAEN1; /*!< Upper 16 bits of the sys irq abort enable register. */
+ __I uint16_t RESERVED16;
+ __IO uint16_t
+ FEEAEN2; /*!< Upper 32..47 bits of the sys irq abort enable register. */
+} ADI_FEE_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define FEESTA (*(volatile unsigned short int *) 0x40002800)
+#define FEECON0 (*(volatile unsigned short int *) 0x40002804)
+#define FEECMD (*(volatile unsigned short int *) 0x40002808)
+#define FEEADR0L (*(volatile unsigned short int *) 0x40002810)
+#define FEEADR0H (*(volatile unsigned short int *) 0x40002814)
+#define FEEADR1L (*(volatile unsigned short int *) 0x40002818)
+#define FEEADR1H (*(volatile unsigned short int *) 0x4000281C)
+#define FEEKEY (*(volatile unsigned short int *) 0x40002820)
+#define FEEPROL (*(volatile unsigned short int *) 0x40002828)
+#define FEEPROH (*(volatile unsigned short int *) 0x4000282C)
+#define FEESIGL (*(volatile unsigned short int *) 0x40002830)
+#define FEESIGH (*(volatile unsigned short int *) 0x40002834)
+#define FEECON1 (*(volatile unsigned short int *) 0x40002838)
+#define FEEADRAL (*(volatile unsigned short int *) 0x40002848)
+#define FEEADRAH (*(volatile unsigned short int *) 0x4000284C)
+#define FEEAEN0 (*(volatile unsigned short int *) 0x40002878)
+#define FEEAEN1 (*(volatile unsigned short int *) 0x4000287C)
+#define FEEAEN2 (*(volatile unsigned short int *) 0x40002880)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for FEESTA*/
+#define FEESTA_RVAL 0x0
+
+/* FEESTA[SIGNERR] - Info space signature check on reset error */
+#define FEESTA_SIGNERR_BBA (*(volatile unsigned long *) 0x42050018)
+#define FEESTA_SIGNERR_MSK (0x1 << 6 )
+#define FEESTA_SIGNERR (0x1 << 6 )
+#define FEESTA_SIGNERR_CLR (0x0 << 6 ) /* CLR */
+#define FEESTA_SIGNERR_SET (0x1 << 6 ) /* SET */
+
+/* FEESTA[CMDRES] - Command result */
+#define FEESTA_CMDRES_MSK (0x3 << 4 )
+#define FEESTA_CMDRES_SUCCESS (0x0 << 4 ) /* SUCCESS */
+#define FEESTA_CMDRES_PROTECTED (0x1 << 4 ) /* PROTECTED */
+#define FEESTA_CMDRES_VERIFYERR (0x2 << 4 ) /* VERIFYERR */
+#define FEESTA_CMDRES_ABORT (0x3 << 4 ) /* ABORT */
+
+/* FEESTA[WRDONE] - Write Complete */
+#define FEESTA_WRDONE_BBA (*(volatile unsigned long *) 0x4205000C)
+#define FEESTA_WRDONE_MSK (0x1 << 3 )
+#define FEESTA_WRDONE (0x1 << 3 )
+#define FEESTA_WRDONE_CLR (0x0 << 3 ) /* CLR */
+#define FEESTA_WRDONE_SET (0x1 << 3 ) /* SET */
+
+/* FEESTA[CMDDONE] - Command complete */
+#define FEESTA_CMDDONE_BBA (*(volatile unsigned long *) 0x42050008)
+#define FEESTA_CMDDONE_MSK (0x1 << 2 )
+#define FEESTA_CMDDONE (0x1 << 2 )
+#define FEESTA_CMDDONE_CLR (0x0 << 2 ) /* CLR */
+#define FEESTA_CMDDONE_SET (0x1 << 2 ) /* SET */
+
+/* FEESTA[WRBUSY] - Write busy */
+#define FEESTA_WRBUSY_BBA (*(volatile unsigned long *) 0x42050004)
+#define FEESTA_WRBUSY_MSK (0x1 << 1 )
+#define FEESTA_WRBUSY (0x1 << 1 )
+#define FEESTA_WRBUSY_CLR (0x0 << 1 ) /* CLR */
+#define FEESTA_WRBUSY_SET (0x1 << 1 ) /* SET */
+
+/* FEESTA[CMDBUSY] - Command busy */
+#define FEESTA_CMDBUSY_BBA (*(volatile unsigned long *) 0x42050000)
+#define FEESTA_CMDBUSY_MSK (0x1 << 0 )
+#define FEESTA_CMDBUSY (0x1 << 0 )
+#define FEESTA_CMDBUSY_CLR (0x0 << 0 ) /* CLR */
+#define FEESTA_CMDBUSY_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for FEECON0*/
+#define FEECON0_RVAL 0x0
+
+/* FEECON0[WREN] - Write enable. */
+#define FEECON0_WREN_BBA (*(volatile unsigned long *) 0x42050088)
+#define FEECON0_WREN_MSK (0x1 << 2 )
+#define FEECON0_WREN (0x1 << 2 )
+#define FEECON0_WREN_DIS (0x0 << 2 ) /* DIS */
+#define FEECON0_WREN_EN (0x1 << 2 ) /* EN */
+
+/* FEECON0[IENERR] - Error interrupt enable */
+#define FEECON0_IENERR_BBA (*(volatile unsigned long *) 0x42050084)
+#define FEECON0_IENERR_MSK (0x1 << 1 )
+#define FEECON0_IENERR (0x1 << 1 )
+#define FEECON0_IENERR_DIS (0x0 << 1 ) /* DIS */
+#define FEECON0_IENERR_EN (0x1 << 1 ) /* EN */
+
+/* FEECON0[IENCMD] - Command complete interrupt enable */
+#define FEECON0_IENCMD_BBA (*(volatile unsigned long *) 0x42050080)
+#define FEECON0_IENCMD_MSK (0x1 << 0 )
+#define FEECON0_IENCMD (0x1 << 0 )
+#define FEECON0_IENCMD_DIS (0x0 << 0 ) /* DIS */
+#define FEECON0_IENCMD_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for FEECMD*/
+#define FEECMD_RVAL 0x0
+
+/* FEECMD[CMD] - Command */
+#define FEECMD_CMD_MSK (0xF << 0 )
+#define FEECMD_CMD_IDLE (0x0 << 0 ) /* IDLE - No command executed */
+#define FEECMD_CMD_ERASEPAGE (0x1 << 0 ) /* ERASEPAGE - Erase Page */
+#define FEECMD_CMD_SIGN (0x2 << 0 ) /* SIGN - Sign Range */
+#define FEECMD_CMD_MASSERASE (0x3 << 0 ) /* MASSERASE - Mass Erase User Space */
+#define FEECMD_CMD_ABORT (0x4 << 0 ) /* ABORT - Abort a running command */
+
+/* Reset Value for FEEADR0L*/
+#define FEEADR0L_RVAL 0x0
+
+/* FEEADR0L[VALUE] - Value */
+#define FEEADR0L_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for FEEADR0H*/
+#define FEEADR0H_RVAL 0x0
+
+/* FEEADR0H[VALUE] - Value */
+#define FEEADR0H_VALUE_MSK (0x3 << 0 )
+
+/* Reset Value for FEEADR1L*/
+#define FEEADR1L_RVAL 0x0
+
+/* FEEADR1L[VALUE] - Value */
+#define FEEADR1L_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for FEEADR1H*/
+#define FEEADR1H_RVAL 0x0
+
+/* FEEADR1H[VALUE] - Value */
+#define FEEADR1H_VALUE_MSK (0x3 << 0 )
+
+/* Reset Value for FEEKEY*/
+#define FEEKEY_RVAL 0x0
+
+/* FEEKEY[VALUE] - Value */
+#define FEEKEY_VALUE_MSK (0xFFFF << 0 )
+#define FEEKEY_VALUE_USERKEY1 (0xF456 << 0 ) /* USERKEY1 */
+#define FEEKEY_VALUE_USERKEY2 (0xF123 << 0 ) /* USERKEY2 */
+
+/* Reset Value for FEEPROL*/
+#define FEEPROL_RVAL 0xFFFF
+
+/* FEEPROL[VALUE] - Value */
+#define FEEPROL_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for FEEPROH*/
+#define FEEPROH_RVAL 0xFFFF
+
+/* FEEPROH[VALUE] - Value */
+#define FEEPROH_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for FEESIGL*/
+#define FEESIGL_RVAL 0xFFFF
+
+/* FEESIGL[VALUE] - Value */
+#define FEESIGL_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for FEESIGH*/
+#define FEESIGH_RVAL 0xFFFF
+
+/* FEESIGH[VALUE] - Value */
+#define FEESIGH_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for FEECON1*/
+#define FEECON1_RVAL 0x1
+
+/* FEECON1[DBG] - Serial Wire debug enable , */
+#define FEECON1_DBG_BBA (*(volatile unsigned long *) 0x42050700)
+#define FEECON1_DBG_MSK (0x1 << 0 )
+#define FEECON1_DBG (0x1 << 0 )
+#define FEECON1_DBG_DIS (0x0 << 0 ) /* DIS */
+#define FEECON1_DBG_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for FEEADRAL*/
+#define FEEADRAL_RVAL 0x800
+
+/* FEEADRAL[VALUE] - Value */
+#define FEEADRAL_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for FEEADRAH*/
+#define FEEADRAH_RVAL 0x2
+
+/* FEEADRAH[VALUE] - Value */
+#define FEEADRAH_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for FEEAEN0*/
+#define FEEAEN0_RVAL 0x0
+
+/* FEEAEN0[SINC2] - */
+#define FEEAEN0_SINC2_BBA (*(volatile unsigned long *) 0x42050F3C)
+#define FEEAEN0_SINC2_MSK (0x1 << 15 )
+#define FEEAEN0_SINC2 (0x1 << 15 )
+#define FEEAEN0_SINC2_DIS (0x0 << 15 ) /* DIS */
+#define FEEAEN0_SINC2_EN (0x1 << 15 ) /* EN */
+
+/* FEEAEN0[ADC1] - */
+#define FEEAEN0_ADC1_BBA (*(volatile unsigned long *) 0x42050F38)
+#define FEEAEN0_ADC1_MSK (0x1 << 14 )
+#define FEEAEN0_ADC1 (0x1 << 14 )
+#define FEEAEN0_ADC1_DIS (0x0 << 14 ) /* DIS */
+#define FEEAEN0_ADC1_EN (0x1 << 14 ) /* EN */
+
+/* FEEAEN0[ADC0] - */
+#define FEEAEN0_ADC0_BBA (*(volatile unsigned long *) 0x42050F34)
+#define FEEAEN0_ADC0_MSK (0x1 << 13 )
+#define FEEAEN0_ADC0 (0x1 << 13 )
+#define FEEAEN0_ADC0_DIS (0x0 << 13 ) /* DIS */
+#define FEEAEN0_ADC0_EN (0x1 << 13 ) /* EN */
+
+/* FEEAEN0[T1] - */
+#define FEEAEN0_T1_BBA (*(volatile unsigned long *) 0x42050F30)
+#define FEEAEN0_T1_MSK (0x1 << 12 )
+#define FEEAEN0_T1 (0x1 << 12 )
+#define FEEAEN0_T1_DIS (0x0 << 12 ) /* DIS */
+#define FEEAEN0_T1_EN (0x1 << 12 ) /* EN */
+
+/* FEEAEN0[T0] - */
+#define FEEAEN0_T0_BBA (*(volatile unsigned long *) 0x42050F2C)
+#define FEEAEN0_T0_MSK (0x1 << 11 )
+#define FEEAEN0_T0 (0x1 << 11 )
+#define FEEAEN0_T0_DIS (0x0 << 11 ) /* DIS */
+#define FEEAEN0_T0_EN (0x1 << 11 ) /* EN */
+
+/* FEEAEN0[T3] - */
+#define FEEAEN0_T3_BBA (*(volatile unsigned long *) 0x42050F24)
+#define FEEAEN0_T3_MSK (0x1 << 9 )
+#define FEEAEN0_T3 (0x1 << 9 )
+#define FEEAEN0_T3_DIS (0x0 << 9 ) /* DIS */
+#define FEEAEN0_T3_EN (0x1 << 9 ) /* EN */
+
+/* FEEAEN0[EXTINT7] - */
+#define FEEAEN0_EXTINT7_BBA (*(volatile unsigned long *) 0x42050F20)
+#define FEEAEN0_EXTINT7_MSK (0x1 << 8 )
+#define FEEAEN0_EXTINT7 (0x1 << 8 )
+#define FEEAEN0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
+#define FEEAEN0_EXTINT7_EN (0x1 << 8 ) /* EN */
+
+/* FEEAEN0[EXTINT6] - */
+#define FEEAEN0_EXTINT6_BBA (*(volatile unsigned long *) 0x42050F1C)
+#define FEEAEN0_EXTINT6_MSK (0x1 << 7 )
+#define FEEAEN0_EXTINT6 (0x1 << 7 )
+#define FEEAEN0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
+#define FEEAEN0_EXTINT6_EN (0x1 << 7 ) /* EN */
+
+/* FEEAEN0[EXTINT5] - */
+#define FEEAEN0_EXTINT5_BBA (*(volatile unsigned long *) 0x42050F18)
+#define FEEAEN0_EXTINT5_MSK (0x1 << 6 )
+#define FEEAEN0_EXTINT5 (0x1 << 6 )
+#define FEEAEN0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
+#define FEEAEN0_EXTINT5_EN (0x1 << 6 ) /* EN */
+
+/* FEEAEN0[EXTINT4] - */
+#define FEEAEN0_EXTINT4_BBA (*(volatile unsigned long *) 0x42050F14)
+#define FEEAEN0_EXTINT4_MSK (0x1 << 5 )
+#define FEEAEN0_EXTINT4 (0x1 << 5 )
+#define FEEAEN0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
+#define FEEAEN0_EXTINT4_EN (0x1 << 5 ) /* EN */
+
+/* FEEAEN0[EXTINT3] - */
+#define FEEAEN0_EXTINT3_BBA (*(volatile unsigned long *) 0x42050F10)
+#define FEEAEN0_EXTINT3_MSK (0x1 << 4 )
+#define FEEAEN0_EXTINT3 (0x1 << 4 )
+#define FEEAEN0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
+#define FEEAEN0_EXTINT3_EN (0x1 << 4 ) /* EN */
+
+/* FEEAEN0[EXTINT2] - */
+#define FEEAEN0_EXTINT2_BBA (*(volatile unsigned long *) 0x42050F0C)
+#define FEEAEN0_EXTINT2_MSK (0x1 << 3 )
+#define FEEAEN0_EXTINT2 (0x1 << 3 )
+#define FEEAEN0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
+#define FEEAEN0_EXTINT2_EN (0x1 << 3 ) /* EN */
+
+/* FEEAEN0[EXTINT1] - */
+#define FEEAEN0_EXTINT1_BBA (*(volatile unsigned long *) 0x42050F08)
+#define FEEAEN0_EXTINT1_MSK (0x1 << 2 )
+#define FEEAEN0_EXTINT1 (0x1 << 2 )
+#define FEEAEN0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
+#define FEEAEN0_EXTINT1_EN (0x1 << 2 ) /* EN */
+
+/* FEEAEN0[EXTINT0] - */
+#define FEEAEN0_EXTINT0_BBA (*(volatile unsigned long *) 0x42050F04)
+#define FEEAEN0_EXTINT0_MSK (0x1 << 1 )
+#define FEEAEN0_EXTINT0 (0x1 << 1 )
+#define FEEAEN0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
+#define FEEAEN0_EXTINT0_EN (0x1 << 1 ) /* EN */
+
+/* FEEAEN0[T2] - */
+#define FEEAEN0_T2_BBA (*(volatile unsigned long *) 0x42050F00)
+#define FEEAEN0_T2_MSK (0x1 << 0 )
+#define FEEAEN0_T2 (0x1 << 0 )
+#define FEEAEN0_T2_DIS (0x0 << 0 ) /* DIS */
+#define FEEAEN0_T2_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for FEEAEN1*/
+#define FEEAEN1_RVAL 0x0
+
+/* FEEAEN1[DMADAC] - */
+#define FEEAEN1_DMADAC_BBA (*(volatile unsigned long *) 0x42050FBC)
+#define FEEAEN1_DMADAC_MSK (0x1 << 15 )
+#define FEEAEN1_DMADAC (0x1 << 15 )
+#define FEEAEN1_DMADAC_DIS (0x0 << 15 ) /* DIS */
+#define FEEAEN1_DMADAC_EN (0x1 << 15 ) /* EN */
+
+/* FEEAEN1[DMAI2CMRX] - */
+#define FEEAEN1_DMAI2CMRX_BBA (*(volatile unsigned long *) 0x42050FB8)
+#define FEEAEN1_DMAI2CMRX_MSK (0x1 << 14 )
+#define FEEAEN1_DMAI2CMRX (0x1 << 14 )
+#define FEEAEN1_DMAI2CMRX_DIS (0x0 << 14 ) /* DIS */
+#define FEEAEN1_DMAI2CMRX_EN (0x1 << 14 ) /* EN */
+
+/* FEEAEN1[DMAI2CMTX] - */
+#define FEEAEN1_DMAI2CMTX_BBA (*(volatile unsigned long *) 0x42050FB4)
+#define FEEAEN1_DMAI2CMTX_MSK (0x1 << 13 )
+#define FEEAEN1_DMAI2CMTX (0x1 << 13 )
+#define FEEAEN1_DMAI2CMTX_DIS (0x0 << 13 ) /* DIS */
+#define FEEAEN1_DMAI2CMTX_EN (0x1 << 13 ) /* EN */
+
+/* FEEAEN1[DMAI2CSRX] - */
+#define FEEAEN1_DMAI2CSRX_BBA (*(volatile unsigned long *) 0x42050FB0)
+#define FEEAEN1_DMAI2CSRX_MSK (0x1 << 12 )
+#define FEEAEN1_DMAI2CSRX (0x1 << 12 )
+#define FEEAEN1_DMAI2CSRX_DIS (0x0 << 12 ) /* DIS */
+#define FEEAEN1_DMAI2CSRX_EN (0x1 << 12 ) /* EN */
+
+/* FEEAEN1[DMAI2CSTX] - */
+#define FEEAEN1_DMAI2CSTX_BBA (*(volatile unsigned long *) 0x42050FAC)
+#define FEEAEN1_DMAI2CSTX_MSK (0x1 << 11 )
+#define FEEAEN1_DMAI2CSTX (0x1 << 11 )
+#define FEEAEN1_DMAI2CSTX_DIS (0x0 << 11 ) /* DIS */
+#define FEEAEN1_DMAI2CSTX_EN (0x1 << 11 ) /* EN */
+
+/* FEEAEN1[DMAUARTRX] - */
+#define FEEAEN1_DMAUARTRX_BBA (*(volatile unsigned long *) 0x42050FA8)
+#define FEEAEN1_DMAUARTRX_MSK (0x1 << 10 )
+#define FEEAEN1_DMAUARTRX (0x1 << 10 )
+#define FEEAEN1_DMAUARTRX_DIS (0x0 << 10 ) /* DIS */
+#define FEEAEN1_DMAUARTRX_EN (0x1 << 10 ) /* EN */
+
+/* FEEAEN1[DMAUARTTX] - */
+#define FEEAEN1_DMAUARTTX_BBA (*(volatile unsigned long *) 0x42050FA4)
+#define FEEAEN1_DMAUARTTX_MSK (0x1 << 9 )
+#define FEEAEN1_DMAUARTTX (0x1 << 9 )
+#define FEEAEN1_DMAUARTTX_DIS (0x0 << 9 ) /* DIS */
+#define FEEAEN1_DMAUARTTX_EN (0x1 << 9 ) /* EN */
+
+/* FEEAEN1[DMASPI1RX] - */
+#define FEEAEN1_DMASPI1RX_BBA (*(volatile unsigned long *) 0x42050FA0)
+#define FEEAEN1_DMASPI1RX_MSK (0x1 << 8 )
+#define FEEAEN1_DMASPI1RX (0x1 << 8 )
+#define FEEAEN1_DMASPI1RX_DIS (0x0 << 8 ) /* DIS */
+#define FEEAEN1_DMASPI1RX_EN (0x1 << 8 ) /* EN */
+
+/* FEEAEN1[DMASPI1TX] - */
+#define FEEAEN1_DMASPI1TX_BBA (*(volatile unsigned long *) 0x42050F9C)
+#define FEEAEN1_DMASPI1TX_MSK (0x1 << 7 )
+#define FEEAEN1_DMASPI1TX (0x1 << 7 )
+#define FEEAEN1_DMASPI1TX_DIS (0x0 << 7 ) /* DIS */
+#define FEEAEN1_DMASPI1TX_EN (0x1 << 7 ) /* EN */
+
+/* FEEAEN1[DMAERROR] - */
+#define FEEAEN1_DMAERROR_BBA (*(volatile unsigned long *) 0x42050F98)
+#define FEEAEN1_DMAERROR_MSK (0x1 << 6 )
+#define FEEAEN1_DMAERROR (0x1 << 6 )
+#define FEEAEN1_DMAERROR_DIS (0x0 << 6 ) /* DIS */
+#define FEEAEN1_DMAERROR_EN (0x1 << 6 ) /* EN */
+
+/* FEEAEN1[I2CM] - */
+#define FEEAEN1_I2CM_BBA (*(volatile unsigned long *) 0x42050F94)
+#define FEEAEN1_I2CM_MSK (0x1 << 5 )
+#define FEEAEN1_I2CM (0x1 << 5 )
+#define FEEAEN1_I2CM_DIS (0x0 << 5 ) /* DIS */
+#define FEEAEN1_I2CM_EN (0x1 << 5 ) /* EN */
+
+/* FEEAEN1[I2CS] - */
+#define FEEAEN1_I2CS_BBA (*(volatile unsigned long *) 0x42050F90)
+#define FEEAEN1_I2CS_MSK (0x1 << 4 )
+#define FEEAEN1_I2CS (0x1 << 4 )
+#define FEEAEN1_I2CS_DIS (0x0 << 4 ) /* DIS */
+#define FEEAEN1_I2CS_EN (0x1 << 4 ) /* EN */
+
+/* FEEAEN1[SPI1] - */
+#define FEEAEN1_SPI1_BBA (*(volatile unsigned long *) 0x42050F8C)
+#define FEEAEN1_SPI1_MSK (0x1 << 3 )
+#define FEEAEN1_SPI1 (0x1 << 3 )
+#define FEEAEN1_SPI1_DIS (0x0 << 3 ) /* DIS */
+#define FEEAEN1_SPI1_EN (0x1 << 3 ) /* EN */
+
+/* FEEAEN1[SPI0] - */
+#define FEEAEN1_SPI0_BBA (*(volatile unsigned long *) 0x42050F88)
+#define FEEAEN1_SPI0_MSK (0x1 << 2 )
+#define FEEAEN1_SPI0 (0x1 << 2 )
+#define FEEAEN1_SPI0_DIS (0x0 << 2 ) /* DIS */
+#define FEEAEN1_SPI0_EN (0x1 << 2 ) /* EN */
+
+/* FEEAEN1[UART] - */
+#define FEEAEN1_UART_BBA (*(volatile unsigned long *) 0x42050F84)
+#define FEEAEN1_UART_MSK (0x1 << 1 )
+#define FEEAEN1_UART (0x1 << 1 )
+#define FEEAEN1_UART_DIS (0x0 << 1 ) /* DIS */
+#define FEEAEN1_UART_EN (0x1 << 1 ) /* EN */
+
+/* FEEAEN1[FEE] - */
+#define FEEAEN1_FEE_BBA (*(volatile unsigned long *) 0x42050F80)
+#define FEEAEN1_FEE_MSK (0x1 << 0 )
+#define FEEAEN1_FEE (0x1 << 0 )
+#define FEEAEN1_FEE_DIS (0x0 << 0 ) /* DIS */
+#define FEEAEN1_FEE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for FEEAEN2*/
+#define FEEAEN2_RVAL 0x0
+
+/* FEEAEN2[PWM2] - */
+#define FEEAEN2_PWM2_BBA (*(volatile unsigned long *) 0x42051018)
+#define FEEAEN2_PWM2_MSK (0x1 << 6 )
+#define FEEAEN2_PWM2 (0x1 << 6 )
+#define FEEAEN2_PWM2_DIS (0x0 << 6 ) /* DIS */
+#define FEEAEN2_PWM2_EN (0x1 << 6 ) /* EN */
+
+/* FEEAEN2[PWM1] - */
+#define FEEAEN2_PWM1_BBA (*(volatile unsigned long *) 0x42051014)
+#define FEEAEN2_PWM1_MSK (0x1 << 5 )
+#define FEEAEN2_PWM1 (0x1 << 5 )
+#define FEEAEN2_PWM1_DIS (0x0 << 5 ) /* DIS */
+#define FEEAEN2_PWM1_EN (0x1 << 5 ) /* EN */
+
+/* FEEAEN2[PWM0] - */
+#define FEEAEN2_PWM0_BBA (*(volatile unsigned long *) 0x42051010)
+#define FEEAEN2_PWM0_MSK (0x1 << 4 )
+#define FEEAEN2_PWM0 (0x1 << 4 )
+#define FEEAEN2_PWM0_DIS (0x0 << 4 ) /* DIS */
+#define FEEAEN2_PWM0_EN (0x1 << 4 ) /* EN */
+
+/* FEEAEN2[PWMTRIP] - */
+#define FEEAEN2_PWMTRIP_BBA (*(volatile unsigned long *) 0x4205100C)
+#define FEEAEN2_PWMTRIP_MSK (0x1 << 3 )
+#define FEEAEN2_PWMTRIP (0x1 << 3 )
+#define FEEAEN2_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
+#define FEEAEN2_PWMTRIP_EN (0x1 << 3 ) /* EN */
+
+/* FEEAEN2[DMASINC2] - */
+#define FEEAEN2_DMASINC2_BBA (*(volatile unsigned long *) 0x42051008)
+#define FEEAEN2_DMASINC2_MSK (0x1 << 2 )
+#define FEEAEN2_DMASINC2 (0x1 << 2 )
+#define FEEAEN2_DMASINC2_DIS (0x0 << 2 ) /* DIS */
+#define FEEAEN2_DMASINC2_EN (0x1 << 2 ) /* EN */
+
+/* FEEAEN2[DMAADC1] - */
+#define FEEAEN2_DMAADC1_BBA (*(volatile unsigned long *) 0x42051004)
+#define FEEAEN2_DMAADC1_MSK (0x1 << 1 )
+#define FEEAEN2_DMAADC1 (0x1 << 1 )
+#define FEEAEN2_DMAADC1_DIS (0x0 << 1 ) /* DIS */
+#define FEEAEN2_DMAADC1_EN (0x1 << 1 ) /* EN */
+
+/* FEEAEN2[DMAADC0] - */
+#define FEEAEN2_DMAADC0_BBA (*(volatile unsigned long *) 0x42051000)
+#define FEEAEN2_DMAADC0_MSK (0x1 << 0 )
+#define FEEAEN2_DMAADC0 (0x1 << 0 )
+#define FEEAEN2_DMAADC0_DIS (0x0 << 0 ) /* DIS */
+#define FEEAEN2_DMAADC0_EN (0x1 << 0 ) /* EN */
+// ------------------------------------------------------------------------------------------------
+// ----- I2C -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief I2C (pADI_I2C)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_I2C Structure */
+ __IO uint16_t
+ I2CMCON; /*!< Master Control Register */
+ __I uint16_t RESERVED0;
+ __IO uint16_t
+ I2CMSTA; /*!< Master Status Register */
+ __I uint16_t RESERVED1;
+ __IO uint8_t
+ I2CMRX; /*!< Master Receive Data */
+ __I uint8_t RESERVED2[3];
+ __IO uint8_t
+ I2CMTX; /*!< Master Transmit Data */
+ __I uint8_t RESERVED3[3];
+ __IO uint16_t
+ I2CMRXCNT; /*!< Master Receive Data Count */
+ __I uint16_t RESERVED4;
+ __IO uint16_t
+ I2CMCRXCNT; /*!< Master Current Receive Data Count */
+ __I uint16_t RESERVED5;
+ __IO uint8_t
+ I2CADR0; /*!< 1st Master Address Byte */
+ __I uint8_t RESERVED6[3];
+ __IO uint8_t
+ I2CADR1; /*!< 2nd Master Address Byte */
+ __I uint8_t RESERVED7[7];
+ __IO uint16_t
+ I2CDIV; /*!< Serial clock period divisor register */
+ __I uint16_t RESERVED8;
+ __IO uint16_t
+ I2CSCON; /*!< Slave Control Register */
+ __I uint16_t RESERVED9;
+ __IO uint16_t
+ I2CSSTA; /*!< "Slave I2C Status, Error and IRQ Register" */
+ __I uint16_t RESERVED10;
+ __IO uint16_t
+ I2CSRX; /*!< Slave Receive Data Register */
+ __I uint16_t RESERVED11;
+ __IO uint16_t
+ I2CSTX; /*!< Slave Transmit Data Register */
+ __I uint16_t RESERVED12;
+ __IO uint16_t
+ I2CALT; /*!< Hardware General Call ID */
+ __I uint16_t RESERVED13;
+ __IO uint16_t
+ I2CID0; /*!< 1st Slave Address Device ID */
+ __I uint16_t RESERVED14;
+ __IO uint16_t
+ I2CID1; /*!< 2nd Slave Address Device ID */
+ __I uint16_t RESERVED15;
+ __IO uint16_t
+ I2CID2; /*!< 3rd Slave Address Device ID */
+ __I uint16_t RESERVED16;
+ __IO uint16_t
+ I2CID3; /*!< 4th Slave Address Device ID */
+ __I uint16_t RESERVED17;
+ __IO uint16_t
+ I2CFSTA; /*!< Master and Slave Rx/Tx FIFO Status Register */
+} ADI_I2C_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define I2CMCON (*(volatile unsigned short int *) 0x40003000)
+#define I2CMSTA (*(volatile unsigned short int *) 0x40003004)
+#define I2CMRX (*(volatile unsigned char *) 0x40003008)
+#define I2CMTX (*(volatile unsigned char *) 0x4000300C)
+#define I2CMRXCNT (*(volatile unsigned short int *) 0x40003010)
+#define I2CMCRXCNT (*(volatile unsigned short int *) 0x40003014)
+#define I2CADR0 (*(volatile unsigned char *) 0x40003018)
+#define I2CADR1 (*(volatile unsigned char *) 0x4000301C)
+#define I2CDIV (*(volatile unsigned short int *) 0x40003024)
+#define I2CSCON (*(volatile unsigned short int *) 0x40003028)
+#define I2CSSTA (*(volatile unsigned short int *) 0x4000302C)
+#define I2CSRX (*(volatile unsigned short int *) 0x40003030)
+#define I2CSTX (*(volatile unsigned short int *) 0x40003034)
+#define I2CALT (*(volatile unsigned short int *) 0x40003038)
+#define I2CID0 (*(volatile unsigned short int *) 0x4000303C)
+#define I2CID1 (*(volatile unsigned short int *) 0x40003040)
+#define I2CID2 (*(volatile unsigned short int *) 0x40003044)
+#define I2CID3 (*(volatile unsigned short int *) 0x40003048)
+#define I2CFSTA (*(volatile unsigned short int *) 0x4000304C)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for I2CMCON*/
+#define I2CMCON_RVAL 0x0
+
+/* I2CMCON[TXDMA] - Enable master Tx DMA request */
+#define I2CMCON_TXDMA_BBA (*(volatile unsigned long *) 0x4206002C)
+#define I2CMCON_TXDMA_MSK (0x1 << 11 )
+#define I2CMCON_TXDMA (0x1 << 11 )
+#define I2CMCON_TXDMA_DIS (0x0 << 11 ) /* DIS */
+#define I2CMCON_TXDMA_EN (0x1 << 11 ) /* EN */
+
+/* I2CMCON[RXDMA] - Enable master Rx DMA request */
+#define I2CMCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060028)
+#define I2CMCON_RXDMA_MSK (0x1 << 10 )
+#define I2CMCON_RXDMA (0x1 << 10 )
+#define I2CMCON_RXDMA_DIS (0x0 << 10 ) /* DIS */
+#define I2CMCON_RXDMA_EN (0x1 << 10 ) /* EN */
+
+/* I2CMCON[IENCMP] - Transaction completed interrupt enable */
+#define I2CMCON_IENCMP_BBA (*(volatile unsigned long *) 0x42060020)
+#define I2CMCON_IENCMP_MSK (0x1 << 8 )
+#define I2CMCON_IENCMP (0x1 << 8 )
+#define I2CMCON_IENCMP_DIS (0x0 << 8 ) /* DIS */
+#define I2CMCON_IENCMP_EN (0x1 << 8 ) /* EN */
+
+/* I2CMCON[IENNACK] - ACK not received interrupt enable */
+#define I2CMCON_IENNACK_BBA (*(volatile unsigned long *) 0x4206001C)
+#define I2CMCON_IENNACK_MSK (0x1 << 7 )
+#define I2CMCON_IENNACK (0x1 << 7 )
+#define I2CMCON_IENNACK_DIS (0x0 << 7 ) /* DIS */
+#define I2CMCON_IENNACK_EN (0x1 << 7 ) /* EN */
+
+/* I2CMCON[IENALOST] - Arbitration lost interrupt enable */
+#define I2CMCON_IENALOST_BBA (*(volatile unsigned long *) 0x42060018)
+#define I2CMCON_IENALOST_MSK (0x1 << 6 )
+#define I2CMCON_IENALOST (0x1 << 6 )
+#define I2CMCON_IENALOST_DIS (0x0 << 6 ) /* DIS */
+#define I2CMCON_IENALOST_EN (0x1 << 6 ) /* EN */
+
+/* I2CMCON[IENTX] - Transmit request interrupt enable */
+#define I2CMCON_IENTX_BBA (*(volatile unsigned long *) 0x42060014)
+#define I2CMCON_IENTX_MSK (0x1 << 5 )
+#define I2CMCON_IENTX (0x1 << 5 )
+#define I2CMCON_IENTX_DIS (0x0 << 5 ) /* DIS */
+#define I2CMCON_IENTX_EN (0x1 << 5 ) /* EN */
+
+/* I2CMCON[IENRX] - Receive request interrupt enable */
+#define I2CMCON_IENRX_BBA (*(volatile unsigned long *) 0x42060010)
+#define I2CMCON_IENRX_MSK (0x1 << 4 )
+#define I2CMCON_IENRX (0x1 << 4 )
+#define I2CMCON_IENRX_DIS (0x0 << 4 ) /* DIS */
+#define I2CMCON_IENRX_EN (0x1 << 4 ) /* EN */
+
+/* I2CMCON[STRETCH] - Stretch SCL */
+#define I2CMCON_STRETCH_BBA (*(volatile unsigned long *) 0x4206000C)
+#define I2CMCON_STRETCH_MSK (0x1 << 3 )
+#define I2CMCON_STRETCH (0x1 << 3 )
+#define I2CMCON_STRETCH_DIS (0x0 << 3 ) /* DIS */
+#define I2CMCON_STRETCH_EN (0x1 << 3 ) /* EN */
+
+/* I2CMCON[LOOPBACK] - Internal loop back */
+#define I2CMCON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42060008)
+#define I2CMCON_LOOPBACK_MSK (0x1 << 2 )
+#define I2CMCON_LOOPBACK (0x1 << 2 )
+#define I2CMCON_LOOPBACK_DIS (0x0 << 2 ) /* DIS */
+#define I2CMCON_LOOPBACK_EN (0x1 << 2 ) /* EN */
+
+/* I2CMCON[COMPETE] - Compete for ownership */
+#define I2CMCON_COMPETE_BBA (*(volatile unsigned long *) 0x42060004)
+#define I2CMCON_COMPETE_MSK (0x1 << 1 )
+#define I2CMCON_COMPETE (0x1 << 1 )
+#define I2CMCON_COMPETE_DIS (0x0 << 1 ) /* DIS */
+#define I2CMCON_COMPETE_EN (0x1 << 1 ) /* EN */
+
+/* I2CMCON[MAS] - Master Enable */
+#define I2CMCON_MAS_BBA (*(volatile unsigned long *) 0x42060000)
+#define I2CMCON_MAS_MSK (0x1 << 0 )
+#define I2CMCON_MAS (0x1 << 0 )
+#define I2CMCON_MAS_DIS (0x0 << 0 ) /* DIS */
+#define I2CMCON_MAS_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for I2CMSTA*/
+#define I2CMSTA_RVAL 0x0
+
+/* I2CMSTA[TXUR] - Master Transmit FIFO underflow */
+#define I2CMSTA_TXUR_BBA (*(volatile unsigned long *) 0x420600B0)
+#define I2CMSTA_TXUR_MSK (0x1 << 12 )
+#define I2CMSTA_TXUR (0x1 << 12 )
+#define I2CMSTA_TXUR_CLR (0x0 << 12 ) /* CLR */
+#define I2CMSTA_TXUR_SET (0x1 << 12 ) /* SET */
+
+/* I2CMSTA[MSTOP] - STOP driven by th eI2C master */
+#define I2CMSTA_MSTOP_BBA (*(volatile unsigned long *) 0x420600AC)
+#define I2CMSTA_MSTOP_MSK (0x1 << 11 )
+#define I2CMSTA_MSTOP (0x1 << 11 )
+#define I2CMSTA_MSTOP_CLR (0x0 << 11 ) /* CLR */
+#define I2CMSTA_MSTOP_SET (0x1 << 11 ) /* SET */
+
+/* I2CMSTA[LINEBUSY] - Line is busy */
+#define I2CMSTA_LINEBUSY_BBA (*(volatile unsigned long *) 0x420600A8)
+#define I2CMSTA_LINEBUSY_MSK (0x1 << 10 )
+#define I2CMSTA_LINEBUSY (0x1 << 10 )
+#define I2CMSTA_LINEBUSY_CLR (0x0 << 10 ) /* CLR */
+#define I2CMSTA_LINEBUSY_SET (0x1 << 10 ) /* SET */
+
+/* I2CMSTA[RXOF] - Receive FIFO overflow */
+#define I2CMSTA_RXOF_BBA (*(volatile unsigned long *) 0x420600A4)
+#define I2CMSTA_RXOF_MSK (0x1 << 9 )
+#define I2CMSTA_RXOF (0x1 << 9 )
+#define I2CMSTA_RXOF_CLR (0x0 << 9 ) /* CLR */
+#define I2CMSTA_RXOF_SET (0x1 << 9 ) /* SET */
+
+/* I2CMSTA[TCOMP] - Transaction completed */
+#define I2CMSTA_TCOMP_BBA (*(volatile unsigned long *) 0x420600A0)
+#define I2CMSTA_TCOMP_MSK (0x1 << 8 )
+#define I2CMSTA_TCOMP (0x1 << 8 )
+#define I2CMSTA_TCOMP_CLR (0x0 << 8 ) /* CLR */
+#define I2CMSTA_TCOMP_SET (0x1 << 8 ) /* SET */
+
+/* I2CMSTA[NACKDATA] - Ack not received in response to data write */
+#define I2CMSTA_NACKDATA_BBA (*(volatile unsigned long *) 0x4206009C)
+#define I2CMSTA_NACKDATA_MSK (0x1 << 7 )
+#define I2CMSTA_NACKDATA (0x1 << 7 )
+#define I2CMSTA_NACKDATA_CLR (0x0 << 7 ) /* CLR */
+#define I2CMSTA_NACKDATA_SET (0x1 << 7 ) /* SET */
+
+/* I2CMSTA[BUSY] - Master Busy */
+#define I2CMSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060098)
+#define I2CMSTA_BUSY_MSK (0x1 << 6 )
+#define I2CMSTA_BUSY (0x1 << 6 )
+#define I2CMSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
+#define I2CMSTA_BUSY_SET (0x1 << 6 ) /* SET */
+
+/* I2CMSTA[ALOST] - Arbitration lost */
+#define I2CMSTA_ALOST_BBA (*(volatile unsigned long *) 0x42060094)
+#define I2CMSTA_ALOST_MSK (0x1 << 5 )
+#define I2CMSTA_ALOST (0x1 << 5 )
+#define I2CMSTA_ALOST_CLR (0x0 << 5 ) /* CLR */
+#define I2CMSTA_ALOST_SET (0x1 << 5 ) /* SET */
+
+/* I2CMSTA[NACKADDR] - Ack not received in response to an address */
+#define I2CMSTA_NACKADDR_BBA (*(volatile unsigned long *) 0x42060090)
+#define I2CMSTA_NACKADDR_MSK (0x1 << 4 )
+#define I2CMSTA_NACKADDR (0x1 << 4 )
+#define I2CMSTA_NACKADDR_CLR (0x0 << 4 ) /* CLR */
+#define I2CMSTA_NACKADDR_SET (0x1 << 4 ) /* SET */
+
+/* I2CMSTA[RXREQ] - Receive request */
+#define I2CMSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206008C)
+#define I2CMSTA_RXREQ_MSK (0x1 << 3 )
+#define I2CMSTA_RXREQ (0x1 << 3 )
+#define I2CMSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
+#define I2CMSTA_RXREQ_SET (0x1 << 3 ) /* SET */
+
+/* I2CMSTA[TXREQ] - Transmit request */
+#define I2CMSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060088)
+#define I2CMSTA_TXREQ_MSK (0x1 << 2 )
+#define I2CMSTA_TXREQ (0x1 << 2 )
+#define I2CMSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
+#define I2CMSTA_TXREQ_SET (0x1 << 2 ) /* SET */
+
+/* I2CMSTA[TXFSTA] - Transmit FIFO Status */
+#define I2CMSTA_TXFSTA_MSK (0x3 << 0 )
+#define I2CMSTA_TXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
+#define I2CMSTA_TXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
+#define I2CMSTA_TXFSTA_FULL (0x3 << 0 ) /* FULL */
+
+/* Reset Value for I2CMRX*/
+#define I2CMRX_RVAL 0x0
+
+/* I2CMRX[VALUE] - Current Receive Value */
+#define I2CMRX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CMTX*/
+#define I2CMTX_RVAL 0x0
+
+/* I2CMTX[VALUE] - Current Transmit Value */
+#define I2CMTX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CMRXCNT*/
+#define I2CMRXCNT_RVAL 0x0
+
+/* I2CMRXCNT[EXTEND] - Extended Read */
+#define I2CMRXCNT_EXTEND_BBA (*(volatile unsigned long *) 0x42060220)
+#define I2CMRXCNT_EXTEND_MSK (0x1 << 8 )
+#define I2CMRXCNT_EXTEND (0x1 << 8 )
+#define I2CMRXCNT_EXTEND_DIS (0x0 << 8 ) /* DIS */
+#define I2CMRXCNT_EXTEND_EN (0x1 << 8 ) /* EN */
+
+/* I2CMRXCNT[COUNT] - Receive count */
+#define I2CMRXCNT_COUNT_MSK (0xFF << 0 )
+
+/* Reset Value for I2CMCRXCNT*/
+#define I2CMCRXCNT_RVAL 0x0
+
+/* I2CMCRXCNT[VALUE] - Current Receive count */
+#define I2CMCRXCNT_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CADR0*/
+#define I2CADR0_RVAL 0x0
+
+/* I2CADR0[VALUE] - Address byte */
+#define I2CADR0_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CADR1*/
+#define I2CADR1_RVAL 0x0
+
+/* I2CADR1[VALUE] - Address byte */
+#define I2CADR1_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CDIV*/
+#define I2CDIV_RVAL 0x1F1F
+
+/* I2CDIV[HIGH] - High Time */
+#define I2CDIV_HIGH_MSK (0xFF << 8 )
+
+/* I2CDIV[LOW] - Low Time */
+#define I2CDIV_LOW_MSK (0xFF << 0 )
+
+/* Reset Value for I2CSCON*/
+#define I2CSCON_RVAL 0x0
+
+/* I2CSCON[TXDMA] - Enable slave Tx DMA request */
+#define I2CSCON_TXDMA_BBA (*(volatile unsigned long *) 0x42060538)
+#define I2CSCON_TXDMA_MSK (0x1 << 14 )
+#define I2CSCON_TXDMA (0x1 << 14 )
+#define I2CSCON_TXDMA_DIS (0x0 << 14 ) /* DIS */
+#define I2CSCON_TXDMA_EN (0x1 << 14 ) /* EN */
+
+/* I2CSCON[RXDMA] - Enable slave Rx DMA request */
+#define I2CSCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060534)
+#define I2CSCON_RXDMA_MSK (0x1 << 13 )
+#define I2CSCON_RXDMA (0x1 << 13 )
+#define I2CSCON_RXDMA_DIS (0x0 << 13 ) /* DIS */
+#define I2CSCON_RXDMA_EN (0x1 << 13 ) /* EN */
+
+/* I2CSCON[IENREPST] - Repeated start interrupt enable */
+#define I2CSCON_IENREPST_BBA (*(volatile unsigned long *) 0x42060530)
+#define I2CSCON_IENREPST_MSK (0x1 << 12 )
+#define I2CSCON_IENREPST (0x1 << 12 )
+#define I2CSCON_IENREPST_DIS (0x0 << 12 ) /* DIS */
+#define I2CSCON_IENREPST_EN (0x1 << 12 ) /* EN */
+
+/* I2CSCON[IENTX] - Transmit request interrupt enable */
+#define I2CSCON_IENTX_BBA (*(volatile unsigned long *) 0x42060528)
+#define I2CSCON_IENTX_MSK (0x1 << 10 )
+#define I2CSCON_IENTX (0x1 << 10 )
+#define I2CSCON_IENTX_DIS (0x0 << 10 ) /* DIS */
+#define I2CSCON_IENTX_EN (0x1 << 10 ) /* EN */
+
+/* I2CSCON[IENRX] - Receive request interrupt enable */
+#define I2CSCON_IENRX_BBA (*(volatile unsigned long *) 0x42060524)
+#define I2CSCON_IENRX_MSK (0x1 << 9 )
+#define I2CSCON_IENRX (0x1 << 9 )
+#define I2CSCON_IENRX_DIS (0x0 << 9 ) /* DIS */
+#define I2CSCON_IENRX_EN (0x1 << 9 ) /* EN */
+
+/* I2CSCON[IENSTOP] - Stop condition detected interrupt enable */
+#define I2CSCON_IENSTOP_BBA (*(volatile unsigned long *) 0x42060520)
+#define I2CSCON_IENSTOP_MSK (0x1 << 8 )
+#define I2CSCON_IENSTOP (0x1 << 8 )
+#define I2CSCON_IENSTOP_DIS (0x0 << 8 ) /* DIS */
+#define I2CSCON_IENSTOP_EN (0x1 << 8 ) /* EN */
+
+/* I2CSCON[NACK] - NACK next communication */
+#define I2CSCON_NACK_BBA (*(volatile unsigned long *) 0x4206051C)
+#define I2CSCON_NACK_MSK (0x1 << 7 )
+#define I2CSCON_NACK (0x1 << 7 )
+#define I2CSCON_NACK_DIS (0x0 << 7 ) /* DIS */
+#define I2CSCON_NACK_EN (0x1 << 7 ) /* EN */
+
+/* I2CSCON[STRETCH] - Stretch SCL */
+#define I2CSCON_STRETCH_BBA (*(volatile unsigned long *) 0x42060518)
+#define I2CSCON_STRETCH_MSK (0x1 << 6 )
+#define I2CSCON_STRETCH (0x1 << 6 )
+#define I2CSCON_STRETCH_DIS (0x0 << 6 ) /* DIS */
+#define I2CSCON_STRETCH_EN (0x1 << 6 ) /* EN */
+
+/* I2CSCON[EARLYTXR] - Early transmit request mode */
+#define I2CSCON_EARLYTXR_BBA (*(volatile unsigned long *) 0x42060514)
+#define I2CSCON_EARLYTXR_MSK (0x1 << 5 )
+#define I2CSCON_EARLYTXR (0x1 << 5 )
+#define I2CSCON_EARLYTXR_DIS (0x0 << 5 ) /* DIS */
+#define I2CSCON_EARLYTXR_EN (0x1 << 5 ) /* EN */
+
+/* I2CSCON[GCSB] - General call status bit clear */
+#define I2CSCON_GCSB_BBA (*(volatile unsigned long *) 0x42060510)
+#define I2CSCON_GCSB_MSK (0x1 << 4 )
+#define I2CSCON_GCSB (0x1 << 4 )
+#define I2CSCON_GCSB_CLR (0x1 << 4 ) /* CLR */
+
+/* I2CSCON[HGC] - Hardware general Call enable */
+#define I2CSCON_HGC_BBA (*(volatile unsigned long *) 0x4206050C)
+#define I2CSCON_HGC_MSK (0x1 << 3 )
+#define I2CSCON_HGC (0x1 << 3 )
+#define I2CSCON_HGC_DIS (0x0 << 3 ) /* DIS */
+#define I2CSCON_HGC_EN (0x1 << 3 ) /* EN */
+
+/* I2CSCON[GC] - General Call enable */
+#define I2CSCON_GC_BBA (*(volatile unsigned long *) 0x42060508)
+#define I2CSCON_GC_MSK (0x1 << 2 )
+#define I2CSCON_GC (0x1 << 2 )
+#define I2CSCON_GC_DIS (0x0 << 2 ) /* DIS */
+#define I2CSCON_GC_EN (0x1 << 2 ) /* EN */
+
+/* I2CSCON[ADR10] - Enable 10 bit addressing */
+#define I2CSCON_ADR10_BBA (*(volatile unsigned long *) 0x42060504)
+#define I2CSCON_ADR10_MSK (0x1 << 1 )
+#define I2CSCON_ADR10 (0x1 << 1 )
+#define I2CSCON_ADR10_DIS (0x0 << 1 ) /* DIS */
+#define I2CSCON_ADR10_EN (0x1 << 1 ) /* EN */
+
+/* I2CSCON[SLV] - Slave Enable */
+#define I2CSCON_SLV_BBA (*(volatile unsigned long *) 0x42060500)
+#define I2CSCON_SLV_MSK (0x1 << 0 )
+#define I2CSCON_SLV (0x1 << 0 )
+#define I2CSCON_SLV_DIS (0x0 << 0 ) /* DIS */
+#define I2CSCON_SLV_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for I2CSSTA*/
+#define I2CSSTA_RVAL 0x1
+
+/* I2CSSTA[START] - Start and matching address */
+#define I2CSSTA_START_BBA (*(volatile unsigned long *) 0x420605B8)
+#define I2CSSTA_START_MSK (0x1 << 14 )
+#define I2CSSTA_START (0x1 << 14 )
+#define I2CSSTA_START_CLR (0x0 << 14 ) /* CLR */
+#define I2CSSTA_START_SET (0x1 << 14 ) /* SET */
+
+/* I2CSSTA[REPSTART] - Repeated start and matching address */
+#define I2CSSTA_REPSTART_BBA (*(volatile unsigned long *) 0x420605B4)
+#define I2CSSTA_REPSTART_MSK (0x1 << 13 )
+#define I2CSSTA_REPSTART (0x1 << 13 )
+#define I2CSSTA_REPSTART_CLR (0x0 << 13 ) /* CLR */
+#define I2CSSTA_REPSTART_SET (0x1 << 13 ) /* SET */
+
+/* I2CSSTA[IDMAT] - Device ID matched */
+#define I2CSSTA_IDMAT_MSK (0x3 << 11 )
+#define I2CSSTA_IDMAT_CLR (0x0 << 11 ) /* CLR */
+#define I2CSSTA_IDMAT_SET (0x1 << 11 ) /* SET */
+
+/* I2CSSTA[STOP] - Stop after start and matching address */
+#define I2CSSTA_STOP_BBA (*(volatile unsigned long *) 0x420605A8)
+#define I2CSSTA_STOP_MSK (0x1 << 10 )
+#define I2CSSTA_STOP (0x1 << 10 )
+#define I2CSSTA_STOP_CLR (0x0 << 10 ) /* CLR */
+#define I2CSSTA_STOP_SET (0x1 << 10 ) /* SET */
+
+/* I2CSSTA[GCID] - General ID */
+#define I2CSSTA_GCID_MSK (0x3 << 8 )
+#define I2CSSTA_GCID_CLR (0x0 << 8 ) /* CLR */
+#define I2CSSTA_GCID_SET (0x1 << 8 ) /* SET */
+
+/* I2CSSTA[GCINT] - General call */
+#define I2CSSTA_GCINT_BBA (*(volatile unsigned long *) 0x4206059C)
+#define I2CSSTA_GCINT_MSK (0x1 << 7 )
+#define I2CSSTA_GCINT (0x1 << 7 )
+#define I2CSSTA_GCINT_CLR (0x0 << 7 ) /* CLR */
+#define I2CSSTA_GCINT_SET (0x1 << 7 ) /* SET */
+
+/* I2CSSTA[BUSY] - Slave busy */
+#define I2CSSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060598)
+#define I2CSSTA_BUSY_MSK (0x1 << 6 )
+#define I2CSSTA_BUSY (0x1 << 6 )
+#define I2CSSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
+#define I2CSSTA_BUSY_SET (0x1 << 6 ) /* SET */
+
+/* I2CSSTA[NOACK] - Ack not generated by the slave */
+#define I2CSSTA_NOACK_BBA (*(volatile unsigned long *) 0x42060594)
+#define I2CSSTA_NOACK_MSK (0x1 << 5 )
+#define I2CSSTA_NOACK (0x1 << 5 )
+#define I2CSSTA_NOACK_CLR (0x0 << 5 ) /* CLR */
+#define I2CSSTA_NOACK_SET (0x1 << 5 ) /* SET */
+
+/* I2CSSTA[RXOF] - Receive FIFO */
+#define I2CSSTA_RXOF_BBA (*(volatile unsigned long *) 0x42060590)
+#define I2CSSTA_RXOF_MSK (0x1 << 4 )
+#define I2CSSTA_RXOF (0x1 << 4 )
+#define I2CSSTA_RXOF_CLR (0x0 << 4 ) /* CLR */
+#define I2CSSTA_RXOF_SET (0x1 << 4 ) /* SET */
+
+/* I2CSSTA[RXREQ] - Receive */
+#define I2CSSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206058C)
+#define I2CSSTA_RXREQ_MSK (0x1 << 3 )
+#define I2CSSTA_RXREQ (0x1 << 3 )
+#define I2CSSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
+#define I2CSSTA_RXREQ_SET (0x1 << 3 ) /* SET */
+
+/* I2CSSTA[TXREQ] - Transmit */
+#define I2CSSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060588)
+#define I2CSSTA_TXREQ_MSK (0x1 << 2 )
+#define I2CSSTA_TXREQ (0x1 << 2 )
+#define I2CSSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
+#define I2CSSTA_TXREQ_SET (0x1 << 2 ) /* SET */
+
+/* I2CSSTA[TXUR] - Transmit FIFO underflow */
+#define I2CSSTA_TXUR_BBA (*(volatile unsigned long *) 0x42060584)
+#define I2CSSTA_TXUR_MSK (0x1 << 1 )
+#define I2CSSTA_TXUR (0x1 << 1 )
+#define I2CSSTA_TXUR_CLR (0x0 << 1 ) /* CLR */
+#define I2CSSTA_TXUR_SET (0x1 << 1 ) /* SET */
+
+/* I2CSSTA[TXFSEREQ] - Tx FIFO status or early request */
+#define I2CSSTA_TXFSEREQ_BBA (*(volatile unsigned long *) 0x42060580)
+#define I2CSSTA_TXFSEREQ_MSK (0x1 << 0 )
+#define I2CSSTA_TXFSEREQ (0x1 << 0 )
+#define I2CSSTA_TXFSEREQ_CLR (0x0 << 0 ) /* CLR */
+#define I2CSSTA_TXFSEREQ_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for I2CSRX*/
+#define I2CSRX_RVAL 0x0
+
+/* I2CSRX[VALUE] - Receive register */
+#define I2CSRX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CSTX*/
+#define I2CSTX_RVAL 0x0
+
+/* I2CSTX[VALUE] - Transmit register */
+#define I2CSTX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CALT*/
+#define I2CALT_RVAL 0x0
+
+/* I2CALT[VALUE] - Alt register */
+#define I2CALT_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CID0*/
+#define I2CID0_RVAL 0x0
+
+/* I2CID0[VALUE] - Slave ID */
+#define I2CID0_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CID1*/
+#define I2CID1_RVAL 0x0
+
+/* I2CID1[VALUE] - Slave ID */
+#define I2CID1_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CID2*/
+#define I2CID2_RVAL 0x0
+
+/* I2CID2[VALUE] - Slave ID */
+#define I2CID2_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CID3*/
+#define I2CID3_RVAL 0x0
+
+/* I2CID3[VALUE] - Slave ID */
+#define I2CID3_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for I2CFSTA*/
+#define I2CFSTA_RVAL 0x0
+
+/* I2CFSTA[MFLUSH] - Flush the master transmit FIFO */
+#define I2CFSTA_MFLUSH_BBA (*(volatile unsigned long *) 0x420609A4)
+#define I2CFSTA_MFLUSH_MSK (0x1 << 9 )
+#define I2CFSTA_MFLUSH (0x1 << 9 )
+#define I2CFSTA_MFLUSH_DIS (0x0 << 9 ) /* DIS */
+#define I2CFSTA_MFLUSH_EN (0x1 << 9 ) /* EN */
+
+/* I2CFSTA[SFLUSH] - Flush the slave transmit FIFO */
+#define I2CFSTA_SFLUSH_BBA (*(volatile unsigned long *) 0x420609A0)
+#define I2CFSTA_SFLUSH_MSK (0x1 << 8 )
+#define I2CFSTA_SFLUSH (0x1 << 8 )
+#define I2CFSTA_SFLUSH_DIS (0x0 << 8 ) /* DIS */
+#define I2CFSTA_SFLUSH_EN (0x1 << 8 ) /* EN */
+
+/* I2CFSTA[MRXFSTA] - Master receive FIFO Status */
+#define I2CFSTA_MRXFSTA_MSK (0x3 << 6 )
+#define I2CFSTA_MRXFSTA_EMPTY (0x0 << 6 ) /* EMPTY */
+#define I2CFSTA_MRXFSTA_ONEBYTE (0x1 << 6 ) /* ONEBYTE */
+#define I2CFSTA_MRXFSTA_TWOBYTES (0x2 << 6 ) /* TWOBYTES */
+
+/* I2CFSTA[MTXFSTA] - Master Transmit FIFO Status */
+#define I2CFSTA_MTXFSTA_MSK (0x3 << 4 )
+#define I2CFSTA_MTXFSTA_EMPTY (0x0 << 4 ) /* EMPTY */
+#define I2CFSTA_MTXFSTA_ONEBYTE (0x1 << 4 ) /* ONEBYTE */
+#define I2CFSTA_MTXFSTA_TWOBYTES (0x2 << 4 ) /* TWOBYTES */
+
+/* I2CFSTA[SRXFSTA] - Slave receive FIFO Status */
+#define I2CFSTA_SRXFSTA_MSK (0x3 << 2 )
+#define I2CFSTA_SRXFSTA_EMPTY (0x0 << 2 ) /* EMPTY */
+#define I2CFSTA_SRXFSTA_ONEBYTE (0x1 << 2 ) /* ONEBYTE */
+#define I2CFSTA_SRXFSTA_TWOBYTES (0x2 << 2 ) /* TWOBYTES */
+
+/* I2CFSTA[STXFSTA] - Slave Transmit FIFO Status */
+#define I2CFSTA_STXFSTA_MSK (0x3 << 0 )
+#define I2CFSTA_STXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
+#define I2CFSTA_STXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
+#define I2CFSTA_STXFSTA_TWOBYTES (0x2 << 0 ) /* TWOBYTES */
+// ------------------------------------------------------------------------------------------------
+// ----- SPI0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Serial Peripheral Interface (pADI_SPI0)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_SPI0 Structure */
+ __IO uint16_t
+ SPISTA; /*!< Status Register */
+ __I uint16_t RESERVED0;
+ __IO uint8_t
+ SPIRX; /*!< 8-bit Receive register. */
+ __I uint8_t RESERVED1[3];
+ __IO uint8_t
+ SPITX; /*!< 8-bit Transmit register */
+ __I uint8_t RESERVED2[3];
+ __IO uint16_t
+ SPIDIV; /*!< SPI Clock Divider Registers */
+ __I uint16_t RESERVED3;
+ __IO uint16_t
+ SPICON; /*!< 16-bit configuration register */
+ __I uint16_t RESERVED4;
+ __IO uint16_t
+ SPIDMA; /*!< DMA enable register */
+ __I uint16_t RESERVED5;
+ __IO uint16_t
+ SPICNT; /*!< 8-bit received byte count register */
+} ADI_SPI_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define SPI0STA (*(volatile unsigned short int *) 0x40004000)
+#define SPI0RX (*(volatile unsigned char *) 0x40004004)
+#define SPI0TX (*(volatile unsigned char *) 0x40004008)
+#define SPI0DIV (*(volatile unsigned short int *) 0x4000400C)
+#define SPI0CON (*(volatile unsigned short int *) 0x40004010)
+#define SPI0DMA (*(volatile unsigned short int *) 0x40004014)
+#define SPI0CNT (*(volatile unsigned short int *) 0x40004018)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for SPI0STA*/
+#define SPI0STA_RVAL 0x0
+
+/* SPI0STA[CSERR] - Detected an abrupt CS deassertion */
+#define SPI0STA_CSERR_BBA (*(volatile unsigned long *) 0x42080030)
+#define SPI0STA_CSERR_MSK (0x1 << 12 )
+#define SPI0STA_CSERR (0x1 << 12 )
+#define SPI0STA_CSERR_CLR (0x0 << 12 ) /* CLR */
+#define SPI0STA_CSERR_SET (0x1 << 12 ) /* SET */
+
+/* SPI0STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
+#define SPI0STA_RXS_BBA (*(volatile unsigned long *) 0x4208002C)
+#define SPI0STA_RXS_MSK (0x1 << 11 )
+#define SPI0STA_RXS (0x1 << 11 )
+#define SPI0STA_RXS_CLR (0x0 << 11 ) /* CLR */
+#define SPI0STA_RXS_SET (0x1 << 11 ) /* SET */
+
+/* SPI0STA[RXFSTA] - Receive FIFO Status */
+#define SPI0STA_RXFSTA_MSK (0x7 << 8 )
+#define SPI0STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
+#define SPI0STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
+#define SPI0STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
+#define SPI0STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
+#define SPI0STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
+
+/* SPI0STA[RXOF] - Receive FIFO overflow */
+#define SPI0STA_RXOF_BBA (*(volatile unsigned long *) 0x4208001C)
+#define SPI0STA_RXOF_MSK (0x1 << 7 )
+#define SPI0STA_RXOF (0x1 << 7 )
+#define SPI0STA_RXOF_CLR (0x0 << 7 ) /* CLR */
+#define SPI0STA_RXOF_SET (0x1 << 7 ) /* SET */
+
+/* SPI0STA[RX] - Set when a receive interrupt occurs */
+#define SPI0STA_RX_BBA (*(volatile unsigned long *) 0x42080018)
+#define SPI0STA_RX_MSK (0x1 << 6 )
+#define SPI0STA_RX (0x1 << 6 )
+#define SPI0STA_RX_CLR (0x0 << 6 ) /* CLR */
+#define SPI0STA_RX_SET (0x1 << 6 ) /* SET */
+
+/* SPI0STA[TX] - Set when a transmit interrupt occurs */
+#define SPI0STA_TX_BBA (*(volatile unsigned long *) 0x42080014)
+#define SPI0STA_TX_MSK (0x1 << 5 )
+#define SPI0STA_TX (0x1 << 5 )
+#define SPI0STA_TX_CLR (0x0 << 5 ) /* CLR */
+#define SPI0STA_TX_SET (0x1 << 5 ) /* SET */
+
+/* SPI0STA[TXUR] - Transmit FIFO underflow */
+#define SPI0STA_TXUR_BBA (*(volatile unsigned long *) 0x42080010)
+#define SPI0STA_TXUR_MSK (0x1 << 4 )
+#define SPI0STA_TXUR (0x1 << 4 )
+#define SPI0STA_TXUR_CLR (0x0 << 4 ) /* CLR */
+#define SPI0STA_TXUR_SET (0x1 << 4 ) /* SET */
+
+/* SPI0STA[TXFSTA] - transmit FIFO Status */
+#define SPI0STA_TXFSTA_MSK (0x7 << 1 )
+#define SPI0STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
+#define SPI0STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
+#define SPI0STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
+#define SPI0STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
+#define SPI0STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
+
+/* SPI0STA[IRQ] - Interrupt status bit */
+#define SPI0STA_IRQ_BBA (*(volatile unsigned long *) 0x42080000)
+#define SPI0STA_IRQ_MSK (0x1 << 0 )
+#define SPI0STA_IRQ (0x1 << 0 )
+#define SPI0STA_IRQ_CLR (0x0 << 0 ) /* CLR */
+#define SPI0STA_IRQ_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for SPI0RX*/
+#define SPI0RX_RVAL 0x0
+
+/* SPI0RX[VALUE] - Received data */
+#define SPI0RX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for SPI0TX*/
+#define SPI0TX_RVAL 0x0
+
+/* SPI0TX[VALUE] - Data to transmit */
+#define SPI0TX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for SPI0DIV*/
+#define SPI0DIV_RVAL 0x0
+
+/* SPI0DIV[BCRST] - Bit counter reset */
+#define SPI0DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208019C)
+#define SPI0DIV_BCRST_MSK (0x1 << 7 )
+#define SPI0DIV_BCRST (0x1 << 7 )
+#define SPI0DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
+#define SPI0DIV_BCRST_EN (0x1 << 7 ) /* EN */
+
+/* SPI0DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
+#define SPI0DIV_DIV_MSK (0x3F << 0 )
+
+/* Reset Value for SPI0CON*/
+#define SPI0CON_RVAL 0x0
+
+/* SPI0CON[MOD] - SPI IRQ Mode bits */
+#define SPI0CON_MOD_MSK (0x3 << 14 )
+#define SPI0CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
+#define SPI0CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
+#define SPI0CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
+#define SPI0CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
+
+/* SPI0CON[TFLUSH] - TX FIFO Flush Enable bit */
+#define SPI0CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42080234)
+#define SPI0CON_TFLUSH_MSK (0x1 << 13 )
+#define SPI0CON_TFLUSH (0x1 << 13 )
+#define SPI0CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
+#define SPI0CON_TFLUSH_EN (0x1 << 13 ) /* EN */
+
+/* SPI0CON[RFLUSH] - RX FIFO Flush Enable bit */
+#define SPI0CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42080230)
+#define SPI0CON_RFLUSH_MSK (0x1 << 12 )
+#define SPI0CON_RFLUSH (0x1 << 12 )
+#define SPI0CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
+#define SPI0CON_RFLUSH_EN (0x1 << 12 ) /* EN */
+
+/* SPI0CON[CON] - Continuous transfer enable */
+#define SPI0CON_CON_BBA (*(volatile unsigned long *) 0x4208022C)
+#define SPI0CON_CON_MSK (0x1 << 11 )
+#define SPI0CON_CON (0x1 << 11 )
+#define SPI0CON_CON_DIS (0x0 << 11 ) /* DIS */
+#define SPI0CON_CON_EN (0x1 << 11 ) /* EN */
+
+/* SPI0CON[LOOPBACK] - Loopback enable bit */
+#define SPI0CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42080228)
+#define SPI0CON_LOOPBACK_MSK (0x1 << 10 )
+#define SPI0CON_LOOPBACK (0x1 << 10 )
+#define SPI0CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
+#define SPI0CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
+
+/* SPI0CON[SOEN] - Slave MISO output enable bit */
+#define SPI0CON_SOEN_BBA (*(volatile unsigned long *) 0x42080224)
+#define SPI0CON_SOEN_MSK (0x1 << 9 )
+#define SPI0CON_SOEN (0x1 << 9 )
+#define SPI0CON_SOEN_DIS (0x0 << 9 ) /* DIS */
+#define SPI0CON_SOEN_EN (0x1 << 9 ) /* EN */
+
+/* SPI0CON[RXOF] - RX Oveflow Overwrite enable */
+#define SPI0CON_RXOF_BBA (*(volatile unsigned long *) 0x42080220)
+#define SPI0CON_RXOF_MSK (0x1 << 8 )
+#define SPI0CON_RXOF (0x1 << 8 )
+#define SPI0CON_RXOF_DIS (0x0 << 8 ) /* DIS */
+#define SPI0CON_RXOF_EN (0x1 << 8 ) /* EN */
+
+/* SPI0CON[ZEN] - Transmit zeros when empty */
+#define SPI0CON_ZEN_BBA (*(volatile unsigned long *) 0x4208021C)
+#define SPI0CON_ZEN_MSK (0x1 << 7 )
+#define SPI0CON_ZEN (0x1 << 7 )
+#define SPI0CON_ZEN_DIS (0x0 << 7 ) /* DIS */
+#define SPI0CON_ZEN_EN (0x1 << 7 ) /* EN */
+
+/* SPI0CON[TIM] - Transfer and interrupt mode */
+#define SPI0CON_TIM_BBA (*(volatile unsigned long *) 0x42080218)
+#define SPI0CON_TIM_MSK (0x1 << 6 )
+#define SPI0CON_TIM (0x1 << 6 )
+#define SPI0CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
+#define SPI0CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
+
+/* SPI0CON[LSB] - LSB First Transfer enable */
+#define SPI0CON_LSB_BBA (*(volatile unsigned long *) 0x42080214)
+#define SPI0CON_LSB_MSK (0x1 << 5 )
+#define SPI0CON_LSB (0x1 << 5 )
+#define SPI0CON_LSB_DIS (0x0 << 5 ) /* DIS */
+#define SPI0CON_LSB_EN (0x1 << 5 ) /* EN */
+
+/* SPI0CON[WOM] - Wired OR enable */
+#define SPI0CON_WOM_BBA (*(volatile unsigned long *) 0x42080210)
+#define SPI0CON_WOM_MSK (0x1 << 4 )
+#define SPI0CON_WOM (0x1 << 4 )
+#define SPI0CON_WOM_DIS (0x0 << 4 ) /* DIS */
+#define SPI0CON_WOM_EN (0x1 << 4 ) /* EN */
+
+/* SPI0CON[CPOL] - Clock polarity mode */
+#define SPI0CON_CPOL_BBA (*(volatile unsigned long *) 0x4208020C)
+#define SPI0CON_CPOL_MSK (0x1 << 3 )
+#define SPI0CON_CPOL (0x1 << 3 )
+#define SPI0CON_CPOL_LOW (0x0 << 3 ) /* LOW */
+#define SPI0CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
+
+/* SPI0CON[CPHA] - Clock phase mode */
+#define SPI0CON_CPHA_BBA (*(volatile unsigned long *) 0x42080208)
+#define SPI0CON_CPHA_MSK (0x1 << 2 )
+#define SPI0CON_CPHA (0x1 << 2 )
+#define SPI0CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
+#define SPI0CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
+
+/* SPI0CON[MASEN] - Master enable */
+#define SPI0CON_MASEN_BBA (*(volatile unsigned long *) 0x42080204)
+#define SPI0CON_MASEN_MSK (0x1 << 1 )
+#define SPI0CON_MASEN (0x1 << 1 )
+#define SPI0CON_MASEN_DIS (0x0 << 1 ) /* DIS */
+#define SPI0CON_MASEN_EN (0x1 << 1 ) /* EN */
+
+/* SPI0CON[ENABLE] - SPI Enable bit */
+#define SPI0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42080200)
+#define SPI0CON_ENABLE_MSK (0x1 << 0 )
+#define SPI0CON_ENABLE (0x1 << 0 )
+#define SPI0CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define SPI0CON_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for SPI0DMA*/
+#define SPI0DMA_RVAL 0x0
+
+/* SPI0DMA[IENRXDMA] - Enable receive DMA request */
+#define SPI0DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42080288)
+#define SPI0DMA_IENRXDMA_MSK (0x1 << 2 )
+#define SPI0DMA_IENRXDMA (0x1 << 2 )
+#define SPI0DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
+#define SPI0DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
+
+/* SPI0DMA[IENTXDMA] - Enable transmit DMA request */
+#define SPI0DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42080284)
+#define SPI0DMA_IENTXDMA_MSK (0x1 << 1 )
+#define SPI0DMA_IENTXDMA (0x1 << 1 )
+#define SPI0DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
+#define SPI0DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
+
+/* SPI0DMA[ENABLE] - Enable DMA for data transfer */
+#define SPI0DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42080280)
+#define SPI0DMA_ENABLE_MSK (0x1 << 0 )
+#define SPI0DMA_ENABLE (0x1 << 0 )
+#define SPI0DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define SPI0DMA_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for SPI0CNT*/
+#define SPI0CNT_RVAL 0x0
+
+/* SPI0CNT[VALUE] - Count */
+#define SPI0CNT_VALUE_MSK (0xFF << 0 )
+#if (__NO_MMR_STRUCTS__==1)
+
+#define SPI1STA (*(volatile unsigned short int *) 0x40004400)
+#define SPI1RX (*(volatile unsigned char *) 0x40004404)
+#define SPI1TX (*(volatile unsigned char *) 0x40004408)
+#define SPI1DIV (*(volatile unsigned short int *) 0x4000440C)
+#define SPI1CON (*(volatile unsigned short int *) 0x40004410)
+#define SPI1DMA (*(volatile unsigned short int *) 0x40004414)
+#define SPI1CNT (*(volatile unsigned short int *) 0x40004418)
+#endif // (__NO_MMR_STRUCTS__==1)
+
+/* Reset Value for SPI1STA*/
+#define SPI1STA_RVAL 0x0
+
+/* SPI1STA[CSERR] - Detected an abrupt CS deassertion */
+#define SPI1STA_CSERR_BBA (*(volatile unsigned long *) 0x42088030)
+#define SPI1STA_CSERR_MSK (0x1 << 12 )
+#define SPI1STA_CSERR (0x1 << 12 )
+#define SPI1STA_CSERR_CLR (0x0 << 12 ) /* CLR */
+#define SPI1STA_CSERR_SET (0x1 << 12 ) /* SET */
+
+/* SPI1STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
+#define SPI1STA_RXS_BBA (*(volatile unsigned long *) 0x4208802C)
+#define SPI1STA_RXS_MSK (0x1 << 11 )
+#define SPI1STA_RXS (0x1 << 11 )
+#define SPI1STA_RXS_CLR (0x0 << 11 ) /* CLR */
+#define SPI1STA_RXS_SET (0x1 << 11 ) /* SET */
+
+/* SPI1STA[RXFSTA] - Receive FIFO Status */
+#define SPI1STA_RXFSTA_MSK (0x7 << 8 )
+#define SPI1STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
+#define SPI1STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
+#define SPI1STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
+#define SPI1STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
+#define SPI1STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
+
+/* SPI1STA[RXOF] - Receive FIFO overflow */
+#define SPI1STA_RXOF_BBA (*(volatile unsigned long *) 0x4208801C)
+#define SPI1STA_RXOF_MSK (0x1 << 7 )
+#define SPI1STA_RXOF (0x1 << 7 )
+#define SPI1STA_RXOF_CLR (0x0 << 7 ) /* CLR */
+#define SPI1STA_RXOF_SET (0x1 << 7 ) /* SET */
+
+/* SPI1STA[RX] - Set when a receive interrupt occurs */
+#define SPI1STA_RX_BBA (*(volatile unsigned long *) 0x42088018)
+#define SPI1STA_RX_MSK (0x1 << 6 )
+#define SPI1STA_RX (0x1 << 6 )
+#define SPI1STA_RX_CLR (0x0 << 6 ) /* CLR */
+#define SPI1STA_RX_SET (0x1 << 6 ) /* SET */
+
+/* SPI1STA[TX] - Set when a transmit interrupt occurs */
+#define SPI1STA_TX_BBA (*(volatile unsigned long *) 0x42088014)
+#define SPI1STA_TX_MSK (0x1 << 5 )
+#define SPI1STA_TX (0x1 << 5 )
+#define SPI1STA_TX_CLR (0x0 << 5 ) /* CLR */
+#define SPI1STA_TX_SET (0x1 << 5 ) /* SET */
+
+/* SPI1STA[TXUR] - Transmit FIFO underflow */
+#define SPI1STA_TXUR_BBA (*(volatile unsigned long *) 0x42088010)
+#define SPI1STA_TXUR_MSK (0x1 << 4 )
+#define SPI1STA_TXUR (0x1 << 4 )
+#define SPI1STA_TXUR_CLR (0x0 << 4 ) /* CLR */
+#define SPI1STA_TXUR_SET (0x1 << 4 ) /* SET */
+
+/* SPI1STA[TXFSTA] - transmit FIFO Status */
+#define SPI1STA_TXFSTA_MSK (0x7 << 1 )
+#define SPI1STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
+#define SPI1STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
+#define SPI1STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
+#define SPI1STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
+#define SPI1STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
+
+/* SPI1STA[IRQ] - Interrupt status bit */
+#define SPI1STA_IRQ_BBA (*(volatile unsigned long *) 0x42088000)
+#define SPI1STA_IRQ_MSK (0x1 << 0 )
+#define SPI1STA_IRQ (0x1 << 0 )
+#define SPI1STA_IRQ_CLR (0x0 << 0 ) /* CLR */
+#define SPI1STA_IRQ_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for SPI1RX*/
+#define SPI1RX_RVAL 0x0
+
+/* SPI1RX[VALUE] - Received data */
+#define SPI1RX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for SPI1TX*/
+#define SPI1TX_RVAL 0x0
+
+/* SPI1TX[VALUE] - Data to transmit */
+#define SPI1TX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for SPI1DIV*/
+#define SPI1DIV_RVAL 0x0
+
+/* SPI1DIV[BCRST] - Bit counter reset */
+#define SPI1DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208819C)
+#define SPI1DIV_BCRST_MSK (0x1 << 7 )
+#define SPI1DIV_BCRST (0x1 << 7 )
+#define SPI1DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
+#define SPI1DIV_BCRST_EN (0x1 << 7 ) /* EN */
+
+/* SPI1DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
+#define SPI1DIV_DIV_MSK (0x3F << 0 )
+
+/* Reset Value for SPI1CON*/
+#define SPI1CON_RVAL 0x0
+
+/* SPI1CON[MOD] - SPI IRQ Mode bits */
+#define SPI1CON_MOD_MSK (0x3 << 14 )
+#define SPI1CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
+#define SPI1CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
+#define SPI1CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
+#define SPI1CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
+
+/* SPI1CON[TFLUSH] - TX FIFO Flush Enable bit */
+#define SPI1CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42088234)
+#define SPI1CON_TFLUSH_MSK (0x1 << 13 )
+#define SPI1CON_TFLUSH (0x1 << 13 )
+#define SPI1CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
+#define SPI1CON_TFLUSH_EN (0x1 << 13 ) /* EN */
+
+/* SPI1CON[RFLUSH] - RX FIFO Flush Enable bit */
+#define SPI1CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42088230)
+#define SPI1CON_RFLUSH_MSK (0x1 << 12 )
+#define SPI1CON_RFLUSH (0x1 << 12 )
+#define SPI1CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
+#define SPI1CON_RFLUSH_EN (0x1 << 12 ) /* EN */
+
+/* SPI1CON[CON] - Continuous transfer enable */
+#define SPI1CON_CON_BBA (*(volatile unsigned long *) 0x4208822C)
+#define SPI1CON_CON_MSK (0x1 << 11 )
+#define SPI1CON_CON (0x1 << 11 )
+#define SPI1CON_CON_DIS (0x0 << 11 ) /* DIS */
+#define SPI1CON_CON_EN (0x1 << 11 ) /* EN */
+
+/* SPI1CON[LOOPBACK] - Loopback enable bit */
+#define SPI1CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42088228)
+#define SPI1CON_LOOPBACK_MSK (0x1 << 10 )
+#define SPI1CON_LOOPBACK (0x1 << 10 )
+#define SPI1CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
+#define SPI1CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
+
+/* SPI1CON[SOEN] - Slave MISO output enable bit */
+#define SPI1CON_SOEN_BBA (*(volatile unsigned long *) 0x42088224)
+#define SPI1CON_SOEN_MSK (0x1 << 9 )
+#define SPI1CON_SOEN (0x1 << 9 )
+#define SPI1CON_SOEN_DIS (0x0 << 9 ) /* DIS */
+#define SPI1CON_SOEN_EN (0x1 << 9 ) /* EN */
+
+/* SPI1CON[RXOF] - RX Oveflow Overwrite enable */
+#define SPI1CON_RXOF_BBA (*(volatile unsigned long *) 0x42088220)
+#define SPI1CON_RXOF_MSK (0x1 << 8 )
+#define SPI1CON_RXOF (0x1 << 8 )
+#define SPI1CON_RXOF_DIS (0x0 << 8 ) /* DIS */
+#define SPI1CON_RXOF_EN (0x1 << 8 ) /* EN */
+
+/* SPI1CON[ZEN] - Transmit zeros when empty */
+#define SPI1CON_ZEN_BBA (*(volatile unsigned long *) 0x4208821C)
+#define SPI1CON_ZEN_MSK (0x1 << 7 )
+#define SPI1CON_ZEN (0x1 << 7 )
+#define SPI1CON_ZEN_DIS (0x0 << 7 ) /* DIS */
+#define SPI1CON_ZEN_EN (0x1 << 7 ) /* EN */
+
+/* SPI1CON[TIM] - Transfer and interrupt mode */
+#define SPI1CON_TIM_BBA (*(volatile unsigned long *) 0x42088218)
+#define SPI1CON_TIM_MSK (0x1 << 6 )
+#define SPI1CON_TIM (0x1 << 6 )
+#define SPI1CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
+#define SPI1CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
+
+/* SPI1CON[LSB] - LSB First Transfer enable */
+#define SPI1CON_LSB_BBA (*(volatile unsigned long *) 0x42088214)
+#define SPI1CON_LSB_MSK (0x1 << 5 )
+#define SPI1CON_LSB (0x1 << 5 )
+#define SPI1CON_LSB_DIS (0x0 << 5 ) /* DIS */
+#define SPI1CON_LSB_EN (0x1 << 5 ) /* EN */
+
+/* SPI1CON[WOM] - Wired OR enable */
+#define SPI1CON_WOM_BBA (*(volatile unsigned long *) 0x42088210)
+#define SPI1CON_WOM_MSK (0x1 << 4 )
+#define SPI1CON_WOM (0x1 << 4 )
+#define SPI1CON_WOM_DIS (0x0 << 4 ) /* DIS */
+#define SPI1CON_WOM_EN (0x1 << 4 ) /* EN */
+
+/* SPI1CON[CPOL] - Clock polarity mode */
+#define SPI1CON_CPOL_BBA (*(volatile unsigned long *) 0x4208820C)
+#define SPI1CON_CPOL_MSK (0x1 << 3 )
+#define SPI1CON_CPOL (0x1 << 3 )
+#define SPI1CON_CPOL_LOW (0x0 << 3 ) /* LOW */
+#define SPI1CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
+
+/* SPI1CON[CPHA] - Clock phase mode */
+#define SPI1CON_CPHA_BBA (*(volatile unsigned long *) 0x42088208)
+#define SPI1CON_CPHA_MSK (0x1 << 2 )
+#define SPI1CON_CPHA (0x1 << 2 )
+#define SPI1CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
+#define SPI1CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
+
+/* SPI1CON[MASEN] - Master enable */
+#define SPI1CON_MASEN_BBA (*(volatile unsigned long *) 0x42088204)
+#define SPI1CON_MASEN_MSK (0x1 << 1 )
+#define SPI1CON_MASEN (0x1 << 1 )
+#define SPI1CON_MASEN_DIS (0x0 << 1 ) /* DIS */
+#define SPI1CON_MASEN_EN (0x1 << 1 ) /* EN */
+
+/* SPI1CON[ENABLE] - SPI Enable bit */
+#define SPI1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42088200)
+#define SPI1CON_ENABLE_MSK (0x1 << 0 )
+#define SPI1CON_ENABLE (0x1 << 0 )
+#define SPI1CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define SPI1CON_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for SPI1DMA*/
+#define SPI1DMA_RVAL 0x0
+
+/* SPI1DMA[IENRXDMA] - Enable receive DMA request */
+#define SPI1DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42088288)
+#define SPI1DMA_IENRXDMA_MSK (0x1 << 2 )
+#define SPI1DMA_IENRXDMA (0x1 << 2 )
+#define SPI1DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
+#define SPI1DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
+
+/* SPI1DMA[IENTXDMA] - Enable transmit DMA request */
+#define SPI1DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42088284)
+#define SPI1DMA_IENTXDMA_MSK (0x1 << 1 )
+#define SPI1DMA_IENTXDMA (0x1 << 1 )
+#define SPI1DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
+#define SPI1DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
+
+/* SPI1DMA[ENABLE] - Enable DMA for data transfer */
+#define SPI1DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42088280)
+#define SPI1DMA_ENABLE_MSK (0x1 << 0 )
+#define SPI1DMA_ENABLE (0x1 << 0 )
+#define SPI1DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define SPI1DMA_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for SPI1CNT*/
+#define SPI1CNT_RVAL 0x0
+
+/* SPI1CNT[VALUE] - Count */
+#define SPI1CNT_VALUE_MSK (0xFF << 0 )
+// ------------------------------------------------------------------------------------------------
+// ----- UART -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief UART (pADI_UART)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_UART Structure */
+
+ union {
+ __IO uint8_t
+ COMTX; /*!< Transmit Holding register */
+ __IO uint8_t
+ COMRX; /*!< Receive Buffer register */
+ } ;
+ __I uint8_t RESERVED0[3];
+ __IO uint8_t
+ COMIEN; /*!< Interrupt Enable register */
+ __I uint8_t RESERVED1[3];
+ __IO uint8_t
+ COMIIR; /*!< Interrupt Identification register */
+ __I uint8_t RESERVED2[3];
+ __IO uint8_t
+ COMLCR; /*!< Line Control register */
+ __I uint8_t RESERVED3[3];
+ __IO uint8_t
+ COMMCR; /*!< Module Control register */
+ __I uint8_t RESERVED4[3];
+ __IO uint8_t
+ COMLSR; /*!< Line Status register */
+ __I uint8_t RESERVED5[3];
+ __IO uint8_t
+ COMMSR; /*!< Modem Status register */
+ __I uint8_t RESERVED6[11];
+ __IO uint16_t
+ COMFBR; /*!< Fractional baud rate divider register. */
+ __I uint16_t RESERVED7;
+ __IO uint16_t
+ COMDIV; /*!< Baud rate Divisor register */
+ __I uint16_t RESERVED8[3];
+ __IO uint8_t
+ COMCON; /*!< UART control register */
+ __I uint8_t RESERVED9[3];
+} ADI_UART_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define COMTX (*(volatile unsigned char *) 0x40005000)
+#define COMRX (*(volatile unsigned char *) 0x40005000)
+#define COMIEN (*(volatile unsigned char *) 0x40005004)
+#define COMIIR (*(volatile unsigned char *) 0x40005008)
+#define COMLCR (*(volatile unsigned char *) 0x4000500C)
+#define COMMCR (*(volatile unsigned char *) 0x40005010)
+#define COMLSR (*(volatile unsigned char *) 0x40005014)
+#define COMMSR (*(volatile unsigned char *) 0x40005018)
+#define COMFBR (*(volatile unsigned short int *) 0x40005024)
+#define COMDIV (*(volatile unsigned short int *) 0x40005028)
+#define COMCON (*(volatile unsigned char *) 0x40005030)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for COMTX*/
+#define COMTX_RVAL 0x0
+
+/* COMTX[VALUE] - Value */
+#define COMTX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for COMRX*/
+#define COMRX_RVAL 0x0
+
+/* COMRX[VALUE] - Value */
+#define COMRX_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for COMIEN*/
+#define COMIEN_RVAL 0x0
+
+/* COMIEN[EDMAR] - Enable DMA requests in transmit mode */
+#define COMIEN_EDMAR_BBA (*(volatile unsigned long *) 0x420A0094)
+#define COMIEN_EDMAR_MSK (0x1 << 5 )
+#define COMIEN_EDMAR (0x1 << 5 )
+#define COMIEN_EDMAR_DIS (0x0 << 5 ) /* DIS */
+#define COMIEN_EDMAR_EN (0x1 << 5 ) /* EN */
+
+/* COMIEN[EDMAT] - Enable DMA requests in receive mode */
+#define COMIEN_EDMAT_BBA (*(volatile unsigned long *) 0x420A0090)
+#define COMIEN_EDMAT_MSK (0x1 << 4 )
+#define COMIEN_EDMAT (0x1 << 4 )
+#define COMIEN_EDMAT_DIS (0x0 << 4 ) /* DIS */
+#define COMIEN_EDMAT_EN (0x1 << 4 ) /* EN */
+
+/* COMIEN[EDSSI] - Enable Modem Status interrupt */
+#define COMIEN_EDSSI_BBA (*(volatile unsigned long *) 0x420A008C)
+#define COMIEN_EDSSI_MSK (0x1 << 3 )
+#define COMIEN_EDSSI (0x1 << 3 )
+#define COMIEN_EDSSI_DIS (0x0 << 3 ) /* DIS */
+#define COMIEN_EDSSI_EN (0x1 << 3 ) /* EN */
+
+/* COMIEN[ELSI] - Enable Rx status interrupt */
+#define COMIEN_ELSI_BBA (*(volatile unsigned long *) 0x420A0088)
+#define COMIEN_ELSI_MSK (0x1 << 2 )
+#define COMIEN_ELSI (0x1 << 2 )
+#define COMIEN_ELSI_DIS (0x0 << 2 ) /* DIS */
+#define COMIEN_ELSI_EN (0x1 << 2 ) /* EN */
+
+/* COMIEN[ETBEI] - Enable transmit buffer empty interrupt */
+#define COMIEN_ETBEI_BBA (*(volatile unsigned long *) 0x420A0084)
+#define COMIEN_ETBEI_MSK (0x1 << 1 )
+#define COMIEN_ETBEI (0x1 << 1 )
+#define COMIEN_ETBEI_DIS (0x0 << 1 ) /* DIS */
+#define COMIEN_ETBEI_EN (0x1 << 1 ) /* EN */
+
+/* COMIEN[ERBFI] - Enable receive buffer full interrupt */
+#define COMIEN_ERBFI_BBA (*(volatile unsigned long *) 0x420A0080)
+#define COMIEN_ERBFI_MSK (0x1 << 0 )
+#define COMIEN_ERBFI (0x1 << 0 )
+#define COMIEN_ERBFI_DIS (0x0 << 0 ) /* DIS */
+#define COMIEN_ERBFI_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for COMIIR*/
+#define COMIIR_RVAL 0x1
+
+/* COMIIR[STA] - Status bits. */
+#define COMIIR_STA_MSK (0x3 << 1 )
+#define COMIIR_STA_MODEMSTATUS (0x0 << 1 ) /* MODEMSTATUS - Modem status interrupt. */
+#define COMIIR_STA_TXBUFEMPTY (0x1 << 1 ) /* TXBUFEMPTY - Transmit buffer empty interrupt. */
+#define COMIIR_STA_RXBUFFULL (0x2 << 1 ) /* RXBUFFULL - Receive buffer full interrupt. Read RBR register to clear. */
+#define COMIIR_STA_RXLINESTATUS (0x3 << 1 ) /* RXLINESTATUS - Receive line status interrupt. Read LSR register to clear. */
+
+/* COMIIR[NINT] - Interrupt flag. */
+#define COMIIR_NINT_BBA (*(volatile unsigned long *) 0x420A0100)
+#define COMIIR_NINT_MSK (0x1 << 0 )
+#define COMIIR_NINT (0x1 << 0 )
+#define COMIIR_NINT_CLR (0x0 << 0 ) /* CLR */
+#define COMIIR_NINT_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for COMLCR*/
+#define COMLCR_RVAL 0x0
+
+/* COMLCR[BRK] - Set Break. */
+#define COMLCR_BRK_BBA (*(volatile unsigned long *) 0x420A0198)
+#define COMLCR_BRK_MSK (0x1 << 6 )
+#define COMLCR_BRK (0x1 << 6 )
+#define COMLCR_BRK_DIS (0x0 << 6 ) /* DIS */
+#define COMLCR_BRK_EN (0x1 << 6 ) /* EN */
+
+/* COMLCR[SP] - Stick Parity. */
+#define COMLCR_SP_BBA (*(volatile unsigned long *) 0x420A0194)
+#define COMLCR_SP_MSK (0x1 << 5 )
+#define COMLCR_SP (0x1 << 5 )
+#define COMLCR_SP_DIS (0x0 << 5 ) /* DIS */
+#define COMLCR_SP_EN (0x1 << 5 ) /* EN */
+
+/* COMLCR[EPS] - Even Parity Select Bit. */
+#define COMLCR_EPS_BBA (*(volatile unsigned long *) 0x420A0190)
+#define COMLCR_EPS_MSK (0x1 << 4 )
+#define COMLCR_EPS (0x1 << 4 )
+#define COMLCR_EPS_DIS (0x0 << 4 ) /* DIS */
+#define COMLCR_EPS_EN (0x1 << 4 ) /* EN */
+
+/* COMLCR[PEN] - Parity Enable Bit. */
+#define COMLCR_PEN_BBA (*(volatile unsigned long *) 0x420A018C)
+#define COMLCR_PEN_MSK (0x1 << 3 )
+#define COMLCR_PEN (0x1 << 3 )
+#define COMLCR_PEN_DIS (0x0 << 3 ) /* DIS */
+#define COMLCR_PEN_EN (0x1 << 3 ) /* EN */
+
+/* COMLCR[STOP] - Stop Bit. */
+#define COMLCR_STOP_BBA (*(volatile unsigned long *) 0x420A0188)
+#define COMLCR_STOP_MSK (0x1 << 2 )
+#define COMLCR_STOP (0x1 << 2 )
+#define COMLCR_STOP_DIS (0x0 << 2 ) /* DIS */
+#define COMLCR_STOP_EN (0x1 << 2 ) /* EN */
+
+/* COMLCR[WLS] - Word Length Select bits */
+#define COMLCR_WLS_MSK (0x3 << 0 )
+#define COMLCR_WLS_5BITS (0x0 << 0 ) /* 5BITS */
+#define COMLCR_WLS_6BITS (0x1 << 0 ) /* 6BITS */
+#define COMLCR_WLS_7BITS (0x2 << 0 ) /* 7BITS */
+#define COMLCR_WLS_8BITS (0x3 << 0 ) /* 8BITS */
+
+/* Reset Value for COMMCR*/
+#define COMMCR_RVAL 0x0
+
+/* COMMCR[LOOPBACK] - Loop Back. */
+#define COMMCR_LOOPBACK_BBA (*(volatile unsigned long *) 0x420A0210)
+#define COMMCR_LOOPBACK_MSK (0x1 << 4 )
+#define COMMCR_LOOPBACK (0x1 << 4 )
+#define COMMCR_LOOPBACK_DIS (0x0 << 4 ) /* DIS */
+#define COMMCR_LOOPBACK_EN (0x1 << 4 ) /* EN */
+
+/* COMMCR[OUT1] - Parity Enable Bit. */
+#define COMMCR_OUT1_BBA (*(volatile unsigned long *) 0x420A020C)
+#define COMMCR_OUT1_MSK (0x1 << 3 )
+#define COMMCR_OUT1 (0x1 << 3 )
+#define COMMCR_OUT1_DIS (0x0 << 3 ) /* DIS */
+#define COMMCR_OUT1_EN (0x1 << 3 ) /* EN */
+
+/* COMMCR[OUT2] - Stop Bit. */
+#define COMMCR_OUT2_BBA (*(volatile unsigned long *) 0x420A0208)
+#define COMMCR_OUT2_MSK (0x1 << 2 )
+#define COMMCR_OUT2 (0x1 << 2 )
+#define COMMCR_OUT2_DIS (0x0 << 2 ) /* DIS */
+#define COMMCR_OUT2_EN (0x1 << 2 ) /* EN */
+
+/* COMMCR[RTS] - Request To Send. */
+#define COMMCR_RTS_BBA (*(volatile unsigned long *) 0x420A0204)
+#define COMMCR_RTS_MSK (0x1 << 1 )
+#define COMMCR_RTS (0x1 << 1 )
+#define COMMCR_RTS_DIS (0x0 << 1 ) /* DIS */
+#define COMMCR_RTS_EN (0x1 << 1 ) /* EN */
+
+/* COMMCR[DTR] - Data Terminal Ready. */
+#define COMMCR_DTR_BBA (*(volatile unsigned long *) 0x420A0200)
+#define COMMCR_DTR_MSK (0x1 << 0 )
+#define COMMCR_DTR (0x1 << 0 )
+#define COMMCR_DTR_DIS (0x0 << 0 ) /* DIS */
+#define COMMCR_DTR_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for COMLSR*/
+#define COMLSR_RVAL 0x60
+
+/* COMLSR[TEMT] - COMTX and Shift Register Empty Status Bit. */
+#define COMLSR_TEMT_BBA (*(volatile unsigned long *) 0x420A0298)
+#define COMLSR_TEMT_MSK (0x1 << 6 )
+#define COMLSR_TEMT (0x1 << 6 )
+#define COMLSR_TEMT_CLR (0x0 << 6 ) /* CLR */
+#define COMLSR_TEMT_SET (0x1 << 6 ) /* SET */
+
+/* COMLSR[THRE] - COMTX Empty Status Bit. */
+#define COMLSR_THRE_BBA (*(volatile unsigned long *) 0x420A0294)
+#define COMLSR_THRE_MSK (0x1 << 5 )
+#define COMLSR_THRE (0x1 << 5 )
+#define COMLSR_THRE_CLR (0x0 << 5 ) /* CLR */
+#define COMLSR_THRE_SET (0x1 << 5 ) /* SET */
+
+/* COMLSR[BI] - Break Indicator. */
+#define COMLSR_BI_BBA (*(volatile unsigned long *) 0x420A0290)
+#define COMLSR_BI_MSK (0x1 << 4 )
+#define COMLSR_BI (0x1 << 4 )
+#define COMLSR_BI_CLR (0x0 << 4 ) /* CLR */
+#define COMLSR_BI_SET (0x1 << 4 ) /* SET */
+
+/* COMLSR[FE] - Framing Error. */
+#define COMLSR_FE_BBA (*(volatile unsigned long *) 0x420A028C)
+#define COMLSR_FE_MSK (0x1 << 3 )
+#define COMLSR_FE (0x1 << 3 )
+#define COMLSR_FE_CLR (0x0 << 3 ) /* CLR */
+#define COMLSR_FE_SET (0x1 << 3 ) /* SET */
+
+/* COMLSR[PE] - Parity Error. */
+#define COMLSR_PE_BBA (*(volatile unsigned long *) 0x420A0288)
+#define COMLSR_PE_MSK (0x1 << 2 )
+#define COMLSR_PE (0x1 << 2 )
+#define COMLSR_PE_CLR (0x0 << 2 ) /* CLR */
+#define COMLSR_PE_SET (0x1 << 2 ) /* SET */
+
+/* COMLSR[OE] - Overrun Error. */
+#define COMLSR_OE_BBA (*(volatile unsigned long *) 0x420A0284)
+#define COMLSR_OE_MSK (0x1 << 1 )
+#define COMLSR_OE (0x1 << 1 )
+#define COMLSR_OE_CLR (0x0 << 1 ) /* CLR */
+#define COMLSR_OE_SET (0x1 << 1 ) /* SET */
+
+/* COMLSR[DR] - Data Ready. */
+#define COMLSR_DR_BBA (*(volatile unsigned long *) 0x420A0280)
+#define COMLSR_DR_MSK (0x1 << 0 )
+#define COMLSR_DR (0x1 << 0 )
+#define COMLSR_DR_CLR (0x0 << 0 ) /* CLR */
+#define COMLSR_DR_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for COMMSR*/
+#define COMMSR_RVAL 0x0
+
+/* COMMSR[DCD] - Data Carrier Detect. */
+#define COMMSR_DCD_BBA (*(volatile unsigned long *) 0x420A031C)
+#define COMMSR_DCD_MSK (0x1 << 7 )
+#define COMMSR_DCD (0x1 << 7 )
+#define COMMSR_DCD_DIS (0x0 << 7 ) /* DIS */
+#define COMMSR_DCD_EN (0x1 << 7 ) /* EN */
+
+/* COMMSR[RI] - Ring Indicator. */
+#define COMMSR_RI_BBA (*(volatile unsigned long *) 0x420A0318)
+#define COMMSR_RI_MSK (0x1 << 6 )
+#define COMMSR_RI (0x1 << 6 )
+#define COMMSR_RI_DIS (0x0 << 6 ) /* DIS */
+#define COMMSR_RI_EN (0x1 << 6 ) /* EN */
+
+/* COMMSR[DSR] - Data Set Ready. */
+#define COMMSR_DSR_BBA (*(volatile unsigned long *) 0x420A0314)
+#define COMMSR_DSR_MSK (0x1 << 5 )
+#define COMMSR_DSR (0x1 << 5 )
+#define COMMSR_DSR_DIS (0x0 << 5 ) /* DIS */
+#define COMMSR_DSR_EN (0x1 << 5 ) /* EN */
+
+/* COMMSR[CTS] - Clear To Send. */
+#define COMMSR_CTS_BBA (*(volatile unsigned long *) 0x420A0310)
+#define COMMSR_CTS_MSK (0x1 << 4 )
+#define COMMSR_CTS (0x1 << 4 )
+#define COMMSR_CTS_DIS (0x0 << 4 ) /* DIS */
+#define COMMSR_CTS_EN (0x1 << 4 ) /* EN */
+
+/* COMMSR[DDCD] - Delta DCD. */
+#define COMMSR_DDCD_BBA (*(volatile unsigned long *) 0x420A030C)
+#define COMMSR_DDCD_MSK (0x1 << 3 )
+#define COMMSR_DDCD (0x1 << 3 )
+#define COMMSR_DDCD_DIS (0x0 << 3 ) /* DIS */
+#define COMMSR_DDCD_EN (0x1 << 3 ) /* EN */
+
+/* COMMSR[TERI] - Trailing Edge RI. */
+#define COMMSR_TERI_BBA (*(volatile unsigned long *) 0x420A0308)
+#define COMMSR_TERI_MSK (0x1 << 2 )
+#define COMMSR_TERI (0x1 << 2 )
+#define COMMSR_TERI_DIS (0x0 << 2 ) /* DIS */
+#define COMMSR_TERI_EN (0x1 << 2 ) /* EN */
+
+/* COMMSR[DDSR] - Delta DSR. */
+#define COMMSR_DDSR_BBA (*(volatile unsigned long *) 0x420A0304)
+#define COMMSR_DDSR_MSK (0x1 << 1 )
+#define COMMSR_DDSR (0x1 << 1 )
+#define COMMSR_DDSR_DIS (0x0 << 1 ) /* DIS */
+#define COMMSR_DDSR_EN (0x1 << 1 ) /* EN */
+
+/* COMMSR[DCTS] - Delta CTS. */
+#define COMMSR_DCTS_BBA (*(volatile unsigned long *) 0x420A0300)
+#define COMMSR_DCTS_MSK (0x1 << 0 )
+#define COMMSR_DCTS (0x1 << 0 )
+#define COMMSR_DCTS_DIS (0x0 << 0 ) /* DIS */
+#define COMMSR_DCTS_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for COMFBR*/
+#define COMFBR_RVAL 0x0
+
+/* COMFBR[ENABLE] - Enable */
+#define COMFBR_ENABLE_BBA (*(volatile unsigned long *) 0x420A04BC)
+#define COMFBR_ENABLE_MSK (0x1 << 15 )
+#define COMFBR_ENABLE (0x1 << 15 )
+#define COMFBR_ENABLE_DIS (0x0 << 15 ) /* DIS */
+#define COMFBR_ENABLE_EN (0x1 << 15 ) /* EN */
+
+/* COMFBR[DIVM] - Fractional M Divide bits */
+#define COMFBR_DIVM_MSK (0x3 << 11 )
+
+/* COMFBR[DIVN] - Fractional N Divide bits */
+#define COMFBR_DIVN_MSK (0x7FF << 0 )
+
+/* Reset Value for COMDIV*/
+#define COMDIV_RVAL 0x1
+
+/* COMDIV[VALUE] - Sets the baudrate */
+#define COMDIV_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for COMCON*/
+#define COMCON_RVAL 0x0
+
+/* COMCON[DISABLE] - Uart Disable */
+#define COMCON_DISABLE_BBA (*(volatile unsigned long *) 0x420A0600)
+#define COMCON_DISABLE_MSK (0x1 << 0 )
+#define COMCON_DISABLE (0x1 << 0 )
+#define COMCON_DISABLE_DIS (0x0 << 0 ) /* DIS */
+#define COMCON_DISABLE_EN (0x1 << 0 ) /* EN */
+// ------------------------------------------------------------------------------------------------
+// ----- GPIO0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief General Purpose Input Output (pADI_GP0)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_GP0 Structure */
+ __IO uint16_t
+ GPCON; /*!< GPIO Port 0 configuration */
+ __I uint16_t RESERVED0;
+ __IO uint8_t
+ GPOEN; /*!< GPIO Port 0 output enable */
+ __I uint8_t RESERVED1[3];
+ __IO uint8_t
+ GPPUL; /*!< GPIO Port 0 output pull up enable. */
+ __I uint8_t RESERVED2[3];
+ __IO uint8_t
+ GPOCE; /*!< GPIO Port 0 tri state */
+ __I uint8_t RESERVED3[7];
+ __IO uint8_t
+ GPIN; /*!< GPIO Port 0 data input. */
+ __I uint8_t RESERVED4[3];
+ __IO uint8_t
+ GPOUT; /*!< GPIO Port 0 data out. */
+ __I uint8_t RESERVED5[3];
+ __IO uint8_t
+ GPSET; /*!< GPIO Port 0 data out set */
+ __I uint8_t RESERVED6[3];
+ __IO uint8_t
+ GPCLR; /*!< GPIO Port 0 data out clear. */
+ __I uint8_t RESERVED7[3];
+ __IO uint8_t
+ GPTGL; /*!< GPIO Port 0 pin toggle. */
+ __I uint8_t RESERVED8[3];
+} ADI_GPIO_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define GP0CON (*(volatile unsigned short int *) 0x40006000)
+#define GP0OEN (*(volatile unsigned char *) 0x40006004)
+#define GP0PUL (*(volatile unsigned char *) 0x40006008)
+#define GP0OCE (*(volatile unsigned char *) 0x4000600C)
+#define GP0IN (*(volatile unsigned char *) 0x40006014)
+#define GP0OUT (*(volatile unsigned char *) 0x40006018)
+#define GP0SET (*(volatile unsigned char *) 0x4000601C)
+#define GP0CLR (*(volatile unsigned char *) 0x40006020)
+#define GP0TGL (*(volatile unsigned char *) 0x40006024)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for GP0CON*/
+#define GP0CON_RVAL 0x0
+
+/* GP0CON[CON7] - Configuration bits for P0.7 */
+#define GP0CON_CON7_MSK (0x3 << 14 )
+#define GP0CON_CON7_PORB (0x0 << 14 ) /* PORB */
+#define GP0CON_CON7_GPIO (0x1 << 14 ) /* GPIO */
+#define GP0CON_CON7_UARTTXD (0x2 << 14 ) /* UARTTXD */
+
+/* GP0CON[CON6] - Configuration bits for P0.6 */
+#define GP0CON_CON6_MSK (0x3 << 12 )
+#define GP0CON_CON6_GPIOIRQ2 (0x0 << 12 ) /* GPIOIRQ2 */
+#define GP0CON_CON6_UARTRXD (0x1 << 12 ) /* UARTRXD */
+
+/* GP0CON[CON5] - Configuration bits for P0.5 */
+#define GP0CON_CON5_MSK (0x3 << 10 )
+#define GP0CON_CON5_GPIOIRQ1 (0x0 << 10 ) /* GPIOIRQ1 */
+#define GP0CON_CON5_UARTCTS (0x1 << 10 ) /* UARTCTS */
+
+/* GP0CON[CON4] - Configuration bits for P0.4 */
+#define GP0CON_CON4_MSK (0x3 << 8 )
+#define GP0CON_CON4_GPIO (0x0 << 8 ) /* GPIO */
+#define GP0CON_CON4_UARTRTS (0x1 << 8 ) /* UARTRTS */
+#define GP0CON_CON4_ECLKOUT (0x2 << 8 ) /* ECLKOUT */
+
+/* GP0CON[CON3] - Configuration bits for P0.3 */
+#define GP0CON_CON3_MSK (0x3 << 6 )
+#define GP0CON_CON3_GPIOIRQ0 (0x0 << 6 ) /* GPIOIRQ0 */
+#define GP0CON_CON3_SPI1CS0 (0x1 << 6 ) /* SPI1CS0 */
+
+/* GP0CON[CON2] - Configuration bits for P0.2 */
+#define GP0CON_CON2_MSK (0x3 << 4 )
+#define GP0CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
+#define GP0CON_CON2_SPI1MOSI (0x1 << 4 ) /* SPI1MOSI */
+#define GP0CON_CON2_I2CSDA (0x2 << 4 ) /* I2CSDA */
+#define GP0CON_CON2_UARTTXD (0x3 << 4 ) /* UARTTXD */
+
+/* GP0CON[CON1] - Configuration bits for P0.1 */
+#define GP0CON_CON1_MSK (0x3 << 2 )
+#define GP0CON_CON1_GPIO (0x0 << 2 ) /* GPIO */
+#define GP0CON_CON1_SPI1SCLK (0x1 << 2 ) /* SPI1SCLK */
+#define GP0CON_CON1_I2CSCL (0x2 << 2 ) /* I2CSCL */
+#define GP0CON_CON1_UARTRXD (0x3 << 2 ) /* UARTRXD */
+
+/* GP0CON[CON0] - Configuration bits for P0.0 */
+#define GP0CON_CON0_MSK (0x3 << 0 )
+#define GP0CON_CON0_GPIO (0x0 << 0 ) /* GPIO */
+#define GP0CON_CON0_SPI1MISO (0x1 << 0 ) /* SPI1MISO */
+
+/* Reset Value for GP0OEN*/
+#define GP0OEN_RVAL 0x0
+
+/* GP0OEN[OEN7] - Direction for port pin */
+#define GP0OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C009C)
+#define GP0OEN_OEN7_MSK (0x1 << 7 )
+#define GP0OEN_OEN7 (0x1 << 7 )
+#define GP0OEN_OEN7_IN (0x0 << 7 ) /* IN */
+#define GP0OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
+
+/* GP0OEN[OEN6] - Direction for port pin */
+#define GP0OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0098)
+#define GP0OEN_OEN6_MSK (0x1 << 6 )
+#define GP0OEN_OEN6 (0x1 << 6 )
+#define GP0OEN_OEN6_IN (0x0 << 6 ) /* IN */
+#define GP0OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
+
+/* GP0OEN[OEN5] - Direction for port pin */
+#define GP0OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0094)
+#define GP0OEN_OEN5_MSK (0x1 << 5 )
+#define GP0OEN_OEN5 (0x1 << 5 )
+#define GP0OEN_OEN5_IN (0x0 << 5 ) /* IN */
+#define GP0OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
+
+/* GP0OEN[OEN4] - Direction for port pin */
+#define GP0OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0090)
+#define GP0OEN_OEN4_MSK (0x1 << 4 )
+#define GP0OEN_OEN4 (0x1 << 4 )
+#define GP0OEN_OEN4_IN (0x0 << 4 ) /* IN */
+#define GP0OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
+
+/* GP0OEN[OEN3] - Direction for port pin */
+#define GP0OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C008C)
+#define GP0OEN_OEN3_MSK (0x1 << 3 )
+#define GP0OEN_OEN3 (0x1 << 3 )
+#define GP0OEN_OEN3_IN (0x0 << 3 ) /* IN */
+#define GP0OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
+
+/* GP0OEN[OEN2] - Direction for port pin */
+#define GP0OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0088)
+#define GP0OEN_OEN2_MSK (0x1 << 2 )
+#define GP0OEN_OEN2 (0x1 << 2 )
+#define GP0OEN_OEN2_IN (0x0 << 2 ) /* IN */
+#define GP0OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
+
+/* GP0OEN[OEN1] - Direction for port pin */
+#define GP0OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0084)
+#define GP0OEN_OEN1_MSK (0x1 << 1 )
+#define GP0OEN_OEN1 (0x1 << 1 )
+#define GP0OEN_OEN1_IN (0x0 << 1 ) /* IN */
+#define GP0OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
+
+/* GP0OEN[OEN0] - Direction for port pin */
+#define GP0OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0080)
+#define GP0OEN_OEN0_MSK (0x1 << 0 )
+#define GP0OEN_OEN0 (0x1 << 0 )
+#define GP0OEN_OEN0_IN (0x0 << 0 ) /* IN */
+#define GP0OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
+
+/* Reset Value for GP0PUL*/
+#define GP0PUL_RVAL 0xFF
+
+/* GP0PUL[PUL7] - Pull Up Enable for port pin */
+#define GP0PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C011C)
+#define GP0PUL_PUL7_MSK (0x1 << 7 )
+#define GP0PUL_PUL7 (0x1 << 7 )
+#define GP0PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
+#define GP0PUL_PUL7_EN (0x1 << 7 ) /* EN */
+
+/* GP0PUL[PUL6] - Pull Up Enable for port pin */
+#define GP0PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0118)
+#define GP0PUL_PUL6_MSK (0x1 << 6 )
+#define GP0PUL_PUL6 (0x1 << 6 )
+#define GP0PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
+#define GP0PUL_PUL6_EN (0x1 << 6 ) /* EN */
+
+/* GP0PUL[PUL5] - Pull Up Enable for port pin */
+#define GP0PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0114)
+#define GP0PUL_PUL5_MSK (0x1 << 5 )
+#define GP0PUL_PUL5 (0x1 << 5 )
+#define GP0PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
+#define GP0PUL_PUL5_EN (0x1 << 5 ) /* EN */
+
+/* GP0PUL[PUL4] - Pull Up Enable for port pin */
+#define GP0PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0110)
+#define GP0PUL_PUL4_MSK (0x1 << 4 )
+#define GP0PUL_PUL4 (0x1 << 4 )
+#define GP0PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
+#define GP0PUL_PUL4_EN (0x1 << 4 ) /* EN */
+
+/* GP0PUL[PUL3] - Pull Up Enable for port pin */
+#define GP0PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C010C)
+#define GP0PUL_PUL3_MSK (0x1 << 3 )
+#define GP0PUL_PUL3 (0x1 << 3 )
+#define GP0PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
+#define GP0PUL_PUL3_EN (0x1 << 3 ) /* EN */
+
+/* GP0PUL[PUL2] - Pull Up Enable for port pin */
+#define GP0PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0108)
+#define GP0PUL_PUL2_MSK (0x1 << 2 )
+#define GP0PUL_PUL2 (0x1 << 2 )
+#define GP0PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
+#define GP0PUL_PUL2_EN (0x1 << 2 ) /* EN */
+
+/* GP0PUL[PUL1] - Pull Up Enable for port pin */
+#define GP0PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0104)
+#define GP0PUL_PUL1_MSK (0x1 << 1 )
+#define GP0PUL_PUL1 (0x1 << 1 )
+#define GP0PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
+#define GP0PUL_PUL1_EN (0x1 << 1 ) /* EN */
+
+/* GP0PUL[PUL0] - Pull Up Enable for port pin */
+#define GP0PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0100)
+#define GP0PUL_PUL0_MSK (0x1 << 0 )
+#define GP0PUL_PUL0 (0x1 << 0 )
+#define GP0PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
+#define GP0PUL_PUL0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for GP0OCE*/
+#define GP0OCE_RVAL 0x0
+
+/* GP0OCE[OCE7] - open circuit Enable for port pin */
+#define GP0OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C019C)
+#define GP0OCE_OCE7_MSK (0x1 << 7 )
+#define GP0OCE_OCE7 (0x1 << 7 )
+#define GP0OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
+#define GP0OCE_OCE7_EN (0x1 << 7 ) /* EN */
+
+/* GP0OCE[OCE6] - open circuit Enable for port pin */
+#define GP0OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0198)
+#define GP0OCE_OCE6_MSK (0x1 << 6 )
+#define GP0OCE_OCE6 (0x1 << 6 )
+#define GP0OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
+#define GP0OCE_OCE6_EN (0x1 << 6 ) /* EN */
+
+/* GP0OCE[OCE5] - open circuit Enable for port pin */
+#define GP0OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0194)
+#define GP0OCE_OCE5_MSK (0x1 << 5 )
+#define GP0OCE_OCE5 (0x1 << 5 )
+#define GP0OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
+#define GP0OCE_OCE5_EN (0x1 << 5 ) /* EN */
+
+/* GP0OCE[OCE4] - open circuit Enable for port pin */
+#define GP0OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0190)
+#define GP0OCE_OCE4_MSK (0x1 << 4 )
+#define GP0OCE_OCE4 (0x1 << 4 )
+#define GP0OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
+#define GP0OCE_OCE4_EN (0x1 << 4 ) /* EN */
+
+/* GP0OCE[OCE3] - open circuit Enable for port pin */
+#define GP0OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C018C)
+#define GP0OCE_OCE3_MSK (0x1 << 3 )
+#define GP0OCE_OCE3 (0x1 << 3 )
+#define GP0OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
+#define GP0OCE_OCE3_EN (0x1 << 3 ) /* EN */
+
+/* GP0OCE[OCE2] - open circuit Enable for port pin */
+#define GP0OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0188)
+#define GP0OCE_OCE2_MSK (0x1 << 2 )
+#define GP0OCE_OCE2 (0x1 << 2 )
+#define GP0OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
+#define GP0OCE_OCE2_EN (0x1 << 2 ) /* EN */
+
+/* GP0OCE[OCE1] - open circuit Enable for port pin */
+#define GP0OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0184)
+#define GP0OCE_OCE1_MSK (0x1 << 1 )
+#define GP0OCE_OCE1 (0x1 << 1 )
+#define GP0OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
+#define GP0OCE_OCE1_EN (0x1 << 1 ) /* EN */
+
+/* GP0OCE[OCE0] - open circuit Enable for port pin */
+#define GP0OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0180)
+#define GP0OCE_OCE0_MSK (0x1 << 0 )
+#define GP0OCE_OCE0 (0x1 << 0 )
+#define GP0OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
+#define GP0OCE_OCE0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for GP0IN*/
+#define GP0IN_RVAL 0xFF
+
+/* GP0IN[IN7] - Input for port pin */
+#define GP0IN_IN7_BBA (*(volatile unsigned long *) 0x420C029C)
+#define GP0IN_IN7_MSK (0x1 << 7 )
+#define GP0IN_IN7 (0x1 << 7 )
+#define GP0IN_IN7_LOW (0x0 << 7 ) /* LOW */
+#define GP0IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GP0IN[IN6] - Input for port pin */
+#define GP0IN_IN6_BBA (*(volatile unsigned long *) 0x420C0298)
+#define GP0IN_IN6_MSK (0x1 << 6 )
+#define GP0IN_IN6 (0x1 << 6 )
+#define GP0IN_IN6_LOW (0x0 << 6 ) /* LOW */
+#define GP0IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GP0IN[IN5] - Input for port pin */
+#define GP0IN_IN5_BBA (*(volatile unsigned long *) 0x420C0294)
+#define GP0IN_IN5_MSK (0x1 << 5 )
+#define GP0IN_IN5 (0x1 << 5 )
+#define GP0IN_IN5_LOW (0x0 << 5 ) /* LOW */
+#define GP0IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GP0IN[IN4] - Input for port pin */
+#define GP0IN_IN4_BBA (*(volatile unsigned long *) 0x420C0290)
+#define GP0IN_IN4_MSK (0x1 << 4 )
+#define GP0IN_IN4 (0x1 << 4 )
+#define GP0IN_IN4_LOW (0x0 << 4 ) /* LOW */
+#define GP0IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GP0IN[IN3] - Input for port pin */
+#define GP0IN_IN3_BBA (*(volatile unsigned long *) 0x420C028C)
+#define GP0IN_IN3_MSK (0x1 << 3 )
+#define GP0IN_IN3 (0x1 << 3 )
+#define GP0IN_IN3_LOW (0x0 << 3 ) /* LOW */
+#define GP0IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GP0IN[IN2] - Input for port pin */
+#define GP0IN_IN2_BBA (*(volatile unsigned long *) 0x420C0288)
+#define GP0IN_IN2_MSK (0x1 << 2 )
+#define GP0IN_IN2 (0x1 << 2 )
+#define GP0IN_IN2_LOW (0x0 << 2 ) /* LOW */
+#define GP0IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GP0IN[IN1] - Input for port pin */
+#define GP0IN_IN1_BBA (*(volatile unsigned long *) 0x420C0284)
+#define GP0IN_IN1_MSK (0x1 << 1 )
+#define GP0IN_IN1 (0x1 << 1 )
+#define GP0IN_IN1_LOW (0x0 << 1 ) /* LOW */
+#define GP0IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GP0IN[IN0] - Input for port pin */
+#define GP0IN_IN0_BBA (*(volatile unsigned long *) 0x420C0280)
+#define GP0IN_IN0_MSK (0x1 << 0 )
+#define GP0IN_IN0 (0x1 << 0 )
+#define GP0IN_IN0_LOW (0x0 << 0 ) /* LOW */
+#define GP0IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* Reset Value for GP0OUT*/
+#define GP0OUT_RVAL 0x0
+
+/* GP0OUT[OUT7] - Output for port pin */
+#define GP0OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C031C)
+#define GP0OUT_OUT7_MSK (0x1 << 7 )
+#define GP0OUT_OUT7 (0x1 << 7 )
+#define GP0OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
+#define GP0OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GP0OUT[OUT6] - Output for port pin */
+#define GP0OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0318)
+#define GP0OUT_OUT6_MSK (0x1 << 6 )
+#define GP0OUT_OUT6 (0x1 << 6 )
+#define GP0OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
+#define GP0OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GP0OUT[OUT5] - Output for port pin */
+#define GP0OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0314)
+#define GP0OUT_OUT5_MSK (0x1 << 5 )
+#define GP0OUT_OUT5 (0x1 << 5 )
+#define GP0OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
+#define GP0OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GP0OUT[OUT4] - Output for port pin */
+#define GP0OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0310)
+#define GP0OUT_OUT4_MSK (0x1 << 4 )
+#define GP0OUT_OUT4 (0x1 << 4 )
+#define GP0OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
+#define GP0OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GP0OUT[OUT3] - Output for port pin */
+#define GP0OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C030C)
+#define GP0OUT_OUT3_MSK (0x1 << 3 )
+#define GP0OUT_OUT3 (0x1 << 3 )
+#define GP0OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
+#define GP0OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GP0OUT[OUT2] - Output for port pin */
+#define GP0OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0308)
+#define GP0OUT_OUT2_MSK (0x1 << 2 )
+#define GP0OUT_OUT2 (0x1 << 2 )
+#define GP0OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
+#define GP0OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GP0OUT[OUT1] - Output for port pin */
+#define GP0OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0304)
+#define GP0OUT_OUT1_MSK (0x1 << 1 )
+#define GP0OUT_OUT1 (0x1 << 1 )
+#define GP0OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
+#define GP0OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GP0OUT[OUT0] - Output for port pin */
+#define GP0OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0300)
+#define GP0OUT_OUT0_MSK (0x1 << 0 )
+#define GP0OUT_OUT0 (0x1 << 0 )
+#define GP0OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
+#define GP0OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* Reset Value for GP0SET*/
+#define GP0SET_RVAL 0x0
+
+/* GP0SET[SET7] - Set Output High for port pin */
+#define GP0SET_SET7_BBA (*(volatile unsigned long *) 0x420C039C)
+#define GP0SET_SET7_MSK (0x1 << 7 )
+#define GP0SET_SET7 (0x1 << 7 )
+#define GP0SET_SET7_SET (0x1 << 7 ) /* SET */
+
+/* GP0SET[SET6] - Set Output High for port pin */
+#define GP0SET_SET6_BBA (*(volatile unsigned long *) 0x420C0398)
+#define GP0SET_SET6_MSK (0x1 << 6 )
+#define GP0SET_SET6 (0x1 << 6 )
+#define GP0SET_SET6_SET (0x1 << 6 ) /* SET */
+
+/* GP0SET[SET5] - Set Output High for port pin */
+#define GP0SET_SET5_BBA (*(volatile unsigned long *) 0x420C0394)
+#define GP0SET_SET5_MSK (0x1 << 5 )
+#define GP0SET_SET5 (0x1 << 5 )
+#define GP0SET_SET5_SET (0x1 << 5 ) /* SET */
+
+/* GP0SET[SET4] - Set Output High for port pin */
+#define GP0SET_SET4_BBA (*(volatile unsigned long *) 0x420C0390)
+#define GP0SET_SET4_MSK (0x1 << 4 )
+#define GP0SET_SET4 (0x1 << 4 )
+#define GP0SET_SET4_SET (0x1 << 4 ) /* SET */
+
+/* GP0SET[SET3] - Set Output High for port pin */
+#define GP0SET_SET3_BBA (*(volatile unsigned long *) 0x420C038C)
+#define GP0SET_SET3_MSK (0x1 << 3 )
+#define GP0SET_SET3 (0x1 << 3 )
+#define GP0SET_SET3_SET (0x1 << 3 ) /* SET */
+
+/* GP0SET[SET2] - Set Output High for port pin */
+#define GP0SET_SET2_BBA (*(volatile unsigned long *) 0x420C0388)
+#define GP0SET_SET2_MSK (0x1 << 2 )
+#define GP0SET_SET2 (0x1 << 2 )
+#define GP0SET_SET2_SET (0x1 << 2 ) /* SET */
+
+/* GP0SET[SET1] - Set Output High for port pin */
+#define GP0SET_SET1_BBA (*(volatile unsigned long *) 0x420C0384)
+#define GP0SET_SET1_MSK (0x1 << 1 )
+#define GP0SET_SET1 (0x1 << 1 )
+#define GP0SET_SET1_SET (0x1 << 1 ) /* SET */
+
+/* GP0SET[SET0] - Set Output High for port pin */
+#define GP0SET_SET0_BBA (*(volatile unsigned long *) 0x420C0380)
+#define GP0SET_SET0_MSK (0x1 << 0 )
+#define GP0SET_SET0 (0x1 << 0 )
+#define GP0SET_SET0_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for GP0CLR*/
+#define GP0CLR_RVAL 0x0
+
+/* GP0CLR[CLR7] - Set Output Low for port pin */
+#define GP0CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C041C)
+#define GP0CLR_CLR7_MSK (0x1 << 7 )
+#define GP0CLR_CLR7 (0x1 << 7 )
+#define GP0CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
+
+/* GP0CLR[CLR6] - Set Output Low for port pin */
+#define GP0CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0418)
+#define GP0CLR_CLR6_MSK (0x1 << 6 )
+#define GP0CLR_CLR6 (0x1 << 6 )
+#define GP0CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
+
+/* GP0CLR[CLR5] - Set Output Low for port pin */
+#define GP0CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0414)
+#define GP0CLR_CLR5_MSK (0x1 << 5 )
+#define GP0CLR_CLR5 (0x1 << 5 )
+#define GP0CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
+
+/* GP0CLR[CLR4] - Set Output Low for port pin */
+#define GP0CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0410)
+#define GP0CLR_CLR4_MSK (0x1 << 4 )
+#define GP0CLR_CLR4 (0x1 << 4 )
+#define GP0CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
+
+/* GP0CLR[CLR3] - Set Output Low for port pin */
+#define GP0CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C040C)
+#define GP0CLR_CLR3_MSK (0x1 << 3 )
+#define GP0CLR_CLR3 (0x1 << 3 )
+#define GP0CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
+
+/* GP0CLR[CLR2] - Set Output Low for port pin */
+#define GP0CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0408)
+#define GP0CLR_CLR2_MSK (0x1 << 2 )
+#define GP0CLR_CLR2 (0x1 << 2 )
+#define GP0CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
+
+/* GP0CLR[CLR1] - Set Output Low for port pin */
+#define GP0CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0404)
+#define GP0CLR_CLR1_MSK (0x1 << 1 )
+#define GP0CLR_CLR1 (0x1 << 1 )
+#define GP0CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
+
+/* GP0CLR[CLR0] - Set Output Low for port pin */
+#define GP0CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0400)
+#define GP0CLR_CLR0_MSK (0x1 << 0 )
+#define GP0CLR_CLR0 (0x1 << 0 )
+#define GP0CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
+
+/* Reset Value for GP0TGL*/
+#define GP0TGL_RVAL 0x0
+
+/* GP0TGL[TGL7] - Toggle Output for port pin */
+#define GP0TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C049C)
+#define GP0TGL_TGL7_MSK (0x1 << 7 )
+#define GP0TGL_TGL7 (0x1 << 7 )
+#define GP0TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
+
+/* GP0TGL[TGL6] - Toggle Output for port pin */
+#define GP0TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0498)
+#define GP0TGL_TGL6_MSK (0x1 << 6 )
+#define GP0TGL_TGL6 (0x1 << 6 )
+#define GP0TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
+
+/* GP0TGL[TGL5] - Toggle Output for port pin */
+#define GP0TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0494)
+#define GP0TGL_TGL5_MSK (0x1 << 5 )
+#define GP0TGL_TGL5 (0x1 << 5 )
+#define GP0TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
+
+/* GP0TGL[TGL4] - Toggle Output for port pin */
+#define GP0TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0490)
+#define GP0TGL_TGL4_MSK (0x1 << 4 )
+#define GP0TGL_TGL4 (0x1 << 4 )
+#define GP0TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
+
+/* GP0TGL[TGL3] - Toggle Output for port pin */
+#define GP0TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C048C)
+#define GP0TGL_TGL3_MSK (0x1 << 3 )
+#define GP0TGL_TGL3 (0x1 << 3 )
+#define GP0TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
+
+/* GP0TGL[TGL2] - Toggle Output for port pin */
+#define GP0TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0488)
+#define GP0TGL_TGL2_MSK (0x1 << 2 )
+#define GP0TGL_TGL2 (0x1 << 2 )
+#define GP0TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
+
+/* GP0TGL[TGL1] - Toggle Output for port pin */
+#define GP0TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0484)
+#define GP0TGL_TGL1_MSK (0x1 << 1 )
+#define GP0TGL_TGL1 (0x1 << 1 )
+#define GP0TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
+
+/* GP0TGL[TGL0] - Toggle Output for port pin */
+#define GP0TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0480)
+#define GP0TGL_TGL0_MSK (0x1 << 0 )
+#define GP0TGL_TGL0 (0x1 << 0 )
+#define GP0TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
+#if (__NO_MMR_STRUCTS__==1)
+
+#define GP1CON (*(volatile unsigned short int *) 0x40006030)
+#define GP1OEN (*(volatile unsigned char *) 0x40006034)
+#define GP1PUL (*(volatile unsigned char *) 0x40006038)
+#define GP1OCE (*(volatile unsigned char *) 0x4000603C)
+#define GP1IN (*(volatile unsigned char *) 0x40006044)
+#define GP1OUT (*(volatile unsigned char *) 0x40006048)
+#define GP1SET (*(volatile unsigned char *) 0x4000604C)
+#define GP1CLR (*(volatile unsigned char *) 0x40006050)
+#define GP1TGL (*(volatile unsigned char *) 0x40006054)
+#endif // (__NO_MMR_STRUCTS__==1)
+
+/* Reset Value for GP1CON*/
+#define GP1CON_RVAL 0x0
+
+/* GP1CON[CON7] - Configuration bits for P1.7 */
+#define GP1CON_CON7_MSK (0x3 << 14 )
+#define GP1CON_CON7_GPIOIRQ7 (0x0 << 14 ) /* GPIOIRQ7 */
+#define GP1CON_CON7_PWM5 (0x1 << 14 ) /* PWM5 */
+#define GP1CON_CON7_SPI0CS (0x2 << 14 ) /* SPI0CS */
+
+/* GP1CON[CON6] - Configuration bits for P1.6 */
+#define GP1CON_CON6_MSK (0x3 << 12 )
+#define GP1CON_CON6_GPIOIRQ6 (0x0 << 12 ) /* GPIOIRQ6 */
+#define GP1CON_CON6_PWM4 (0x1 << 12 ) /* PWM4 */
+#define GP1CON_CON6_SPI0MOSI (0x2 << 12 ) /* SPI0MOSI */
+
+/* GP1CON[CON5] - Configuration bits for P1.5 */
+#define GP1CON_CON5_MSK (0x3 << 10 )
+#define GP1CON_CON5_GPIOIRQ5 (0x0 << 10 ) /* GPIOIRQ5 */
+#define GP1CON_CON5_PWM3 (0x1 << 10 ) /* PWM3 */
+#define GP1CON_CON5_SPI0SCLK (0x2 << 10 ) /* SPI0SCLK */
+
+/* GP1CON[CON4] - Configuration bits for P1.4 */
+#define GP1CON_CON4_MSK (0x3 << 8 )
+#define GP1CON_CON4_GPIO (0x0 << 8 ) /* GPIO */
+#define GP1CON_CON4_PWM2 (0x1 << 8 ) /* PWM2 */
+#define GP1CON_CON4_SPI0MISO (0x2 << 8 ) /* SPI0MISO */
+
+/* GP1CON[CON3] - Configuration bits for P1.3 */
+#define GP1CON_CON3_MSK (0x3 << 6 )
+#define GP1CON_CON3_GPIO (0x0 << 6 ) /* GPIO */
+#define GP1CON_CON3_PWM1 (0x1 << 6 ) /* PWM1 */
+
+/* GP1CON[CON2] - Configuration bits for P1.2 */
+#define GP1CON_CON2_MSK (0x3 << 4 )
+#define GP1CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
+#define GP1CON_CON2_PWM0 (0x1 << 4 ) /* PWM0 */
+
+/* GP1CON[CON1] - Configuration bits for P1.1 */
+#define GP1CON_CON1_MSK (0x3 << 2 )
+#define GP1CON_CON1_GPIOIRQ4 (0x0 << 2 ) /* GPIOIRQ4 */
+#define GP1CON_CON1_PWMTRIP (0x1 << 2 ) /* PWMTRIP */
+
+/* GP1CON[CON0] - Configuration bits for P1.0 */
+#define GP1CON_CON0_MSK (0x3 << 0 )
+#define GP1CON_CON0_GPIOIRQ3 (0x0 << 0 ) /* GPIOIRQ3 */
+#define GP1CON_CON0_PWMSYNC (0x1 << 0 ) /* PWMSYNC */
+#define GP1CON_CON0_EXTCLKIN (0x2 << 0 ) /* EXTCLKIN */
+
+/* Reset Value for GP1OEN*/
+#define GP1OEN_RVAL 0x0
+
+/* GP1OEN[OEN7] - Direction for port pin */
+#define GP1OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C069C)
+#define GP1OEN_OEN7_MSK (0x1 << 7 )
+#define GP1OEN_OEN7 (0x1 << 7 )
+#define GP1OEN_OEN7_IN (0x0 << 7 ) /* IN */
+#define GP1OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
+
+/* GP1OEN[OEN6] - Direction for port pin */
+#define GP1OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0698)
+#define GP1OEN_OEN6_MSK (0x1 << 6 )
+#define GP1OEN_OEN6 (0x1 << 6 )
+#define GP1OEN_OEN6_IN (0x0 << 6 ) /* IN */
+#define GP1OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
+
+/* GP1OEN[OEN5] - Direction for port pin */
+#define GP1OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0694)
+#define GP1OEN_OEN5_MSK (0x1 << 5 )
+#define GP1OEN_OEN5 (0x1 << 5 )
+#define GP1OEN_OEN5_IN (0x0 << 5 ) /* IN */
+#define GP1OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
+
+/* GP1OEN[OEN4] - Direction for port pin */
+#define GP1OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0690)
+#define GP1OEN_OEN4_MSK (0x1 << 4 )
+#define GP1OEN_OEN4 (0x1 << 4 )
+#define GP1OEN_OEN4_IN (0x0 << 4 ) /* IN */
+#define GP1OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
+
+/* GP1OEN[OEN3] - Direction for port pin */
+#define GP1OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C068C)
+#define GP1OEN_OEN3_MSK (0x1 << 3 )
+#define GP1OEN_OEN3 (0x1 << 3 )
+#define GP1OEN_OEN3_IN (0x0 << 3 ) /* IN */
+#define GP1OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
+
+/* GP1OEN[OEN2] - Direction for port pin */
+#define GP1OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0688)
+#define GP1OEN_OEN2_MSK (0x1 << 2 )
+#define GP1OEN_OEN2 (0x1 << 2 )
+#define GP1OEN_OEN2_IN (0x0 << 2 ) /* IN */
+#define GP1OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
+
+/* GP1OEN[OEN1] - Direction for port pin */
+#define GP1OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0684)
+#define GP1OEN_OEN1_MSK (0x1 << 1 )
+#define GP1OEN_OEN1 (0x1 << 1 )
+#define GP1OEN_OEN1_IN (0x0 << 1 ) /* IN */
+#define GP1OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
+
+/* GP1OEN[OEN0] - Direction for port pin */
+#define GP1OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0680)
+#define GP1OEN_OEN0_MSK (0x1 << 0 )
+#define GP1OEN_OEN0 (0x1 << 0 )
+#define GP1OEN_OEN0_IN (0x0 << 0 ) /* IN */
+#define GP1OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
+
+/* Reset Value for GP1PUL*/
+#define GP1PUL_RVAL 0xFF
+
+/* GP1PUL[PUL7] - Pull Up Enable for port pin */
+#define GP1PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C071C)
+#define GP1PUL_PUL7_MSK (0x1 << 7 )
+#define GP1PUL_PUL7 (0x1 << 7 )
+#define GP1PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
+#define GP1PUL_PUL7_EN (0x1 << 7 ) /* EN */
+
+/* GP1PUL[PUL6] - Pull Up Enable for port pin */
+#define GP1PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0718)
+#define GP1PUL_PUL6_MSK (0x1 << 6 )
+#define GP1PUL_PUL6 (0x1 << 6 )
+#define GP1PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
+#define GP1PUL_PUL6_EN (0x1 << 6 ) /* EN */
+
+/* GP1PUL[PUL5] - Pull Up Enable for port pin */
+#define GP1PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0714)
+#define GP1PUL_PUL5_MSK (0x1 << 5 )
+#define GP1PUL_PUL5 (0x1 << 5 )
+#define GP1PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
+#define GP1PUL_PUL5_EN (0x1 << 5 ) /* EN */
+
+/* GP1PUL[PUL4] - Pull Up Enable for port pin */
+#define GP1PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0710)
+#define GP1PUL_PUL4_MSK (0x1 << 4 )
+#define GP1PUL_PUL4 (0x1 << 4 )
+#define GP1PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
+#define GP1PUL_PUL4_EN (0x1 << 4 ) /* EN */
+
+/* GP1PUL[PUL3] - Pull Up Enable for port pin */
+#define GP1PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C070C)
+#define GP1PUL_PUL3_MSK (0x1 << 3 )
+#define GP1PUL_PUL3 (0x1 << 3 )
+#define GP1PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
+#define GP1PUL_PUL3_EN (0x1 << 3 ) /* EN */
+
+/* GP1PUL[PUL2] - Pull Up Enable for port pin */
+#define GP1PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0708)
+#define GP1PUL_PUL2_MSK (0x1 << 2 )
+#define GP1PUL_PUL2 (0x1 << 2 )
+#define GP1PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
+#define GP1PUL_PUL2_EN (0x1 << 2 ) /* EN */
+
+/* GP1PUL[PUL1] - Pull Up Enable for port pin */
+#define GP1PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0704)
+#define GP1PUL_PUL1_MSK (0x1 << 1 )
+#define GP1PUL_PUL1 (0x1 << 1 )
+#define GP1PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
+#define GP1PUL_PUL1_EN (0x1 << 1 ) /* EN */
+
+/* GP1PUL[PUL0] - Pull Up Enable for port pin */
+#define GP1PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0700)
+#define GP1PUL_PUL0_MSK (0x1 << 0 )
+#define GP1PUL_PUL0 (0x1 << 0 )
+#define GP1PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
+#define GP1PUL_PUL0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for GP1OCE*/
+#define GP1OCE_RVAL 0x0
+
+/* GP1OCE[OCE7] - open circuit Enable for port pin */
+#define GP1OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C079C)
+#define GP1OCE_OCE7_MSK (0x1 << 7 )
+#define GP1OCE_OCE7 (0x1 << 7 )
+#define GP1OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
+#define GP1OCE_OCE7_EN (0x1 << 7 ) /* EN */
+
+/* GP1OCE[OCE6] - open circuit Enable for port pin */
+#define GP1OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0798)
+#define GP1OCE_OCE6_MSK (0x1 << 6 )
+#define GP1OCE_OCE6 (0x1 << 6 )
+#define GP1OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
+#define GP1OCE_OCE6_EN (0x1 << 6 ) /* EN */
+
+/* GP1OCE[OCE5] - open circuit Enable for port pin */
+#define GP1OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0794)
+#define GP1OCE_OCE5_MSK (0x1 << 5 )
+#define GP1OCE_OCE5 (0x1 << 5 )
+#define GP1OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
+#define GP1OCE_OCE5_EN (0x1 << 5 ) /* EN */
+
+/* GP1OCE[OCE4] - open circuit Enable for port pin */
+#define GP1OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0790)
+#define GP1OCE_OCE4_MSK (0x1 << 4 )
+#define GP1OCE_OCE4 (0x1 << 4 )
+#define GP1OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
+#define GP1OCE_OCE4_EN (0x1 << 4 ) /* EN */
+
+/* GP1OCE[OCE3] - open circuit Enable for port pin */
+#define GP1OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C078C)
+#define GP1OCE_OCE3_MSK (0x1 << 3 )
+#define GP1OCE_OCE3 (0x1 << 3 )
+#define GP1OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
+#define GP1OCE_OCE3_EN (0x1 << 3 ) /* EN */
+
+/* GP1OCE[OCE2] - open circuit Enable for port pin */
+#define GP1OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0788)
+#define GP1OCE_OCE2_MSK (0x1 << 2 )
+#define GP1OCE_OCE2 (0x1 << 2 )
+#define GP1OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
+#define GP1OCE_OCE2_EN (0x1 << 2 ) /* EN */
+
+/* GP1OCE[OCE1] - open circuit Enable for port pin */
+#define GP1OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0784)
+#define GP1OCE_OCE1_MSK (0x1 << 1 )
+#define GP1OCE_OCE1 (0x1 << 1 )
+#define GP1OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
+#define GP1OCE_OCE1_EN (0x1 << 1 ) /* EN */
+
+/* GP1OCE[OCE0] - open circuit Enable for port pin */
+#define GP1OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0780)
+#define GP1OCE_OCE0_MSK (0x1 << 0 )
+#define GP1OCE_OCE0 (0x1 << 0 )
+#define GP1OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
+#define GP1OCE_OCE0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for GP1IN*/
+#define GP1IN_RVAL 0xFF
+
+/* GP1IN[IN7] - Input for port pin */
+#define GP1IN_IN7_BBA (*(volatile unsigned long *) 0x420C089C)
+#define GP1IN_IN7_MSK (0x1 << 7 )
+#define GP1IN_IN7 (0x1 << 7 )
+#define GP1IN_IN7_LOW (0x0 << 7 ) /* LOW */
+#define GP1IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GP1IN[IN6] - Input for port pin */
+#define GP1IN_IN6_BBA (*(volatile unsigned long *) 0x420C0898)
+#define GP1IN_IN6_MSK (0x1 << 6 )
+#define GP1IN_IN6 (0x1 << 6 )
+#define GP1IN_IN6_LOW (0x0 << 6 ) /* LOW */
+#define GP1IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GP1IN[IN5] - Input for port pin */
+#define GP1IN_IN5_BBA (*(volatile unsigned long *) 0x420C0894)
+#define GP1IN_IN5_MSK (0x1 << 5 )
+#define GP1IN_IN5 (0x1 << 5 )
+#define GP1IN_IN5_LOW (0x0 << 5 ) /* LOW */
+#define GP1IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GP1IN[IN4] - Input for port pin */
+#define GP1IN_IN4_BBA (*(volatile unsigned long *) 0x420C0890)
+#define GP1IN_IN4_MSK (0x1 << 4 )
+#define GP1IN_IN4 (0x1 << 4 )
+#define GP1IN_IN4_LOW (0x0 << 4 ) /* LOW */
+#define GP1IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GP1IN[IN3] - Input for port pin */
+#define GP1IN_IN3_BBA (*(volatile unsigned long *) 0x420C088C)
+#define GP1IN_IN3_MSK (0x1 << 3 )
+#define GP1IN_IN3 (0x1 << 3 )
+#define GP1IN_IN3_LOW (0x0 << 3 ) /* LOW */
+#define GP1IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GP1IN[IN2] - Input for port pin */
+#define GP1IN_IN2_BBA (*(volatile unsigned long *) 0x420C0888)
+#define GP1IN_IN2_MSK (0x1 << 2 )
+#define GP1IN_IN2 (0x1 << 2 )
+#define GP1IN_IN2_LOW (0x0 << 2 ) /* LOW */
+#define GP1IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GP1IN[IN1] - Input for port pin */
+#define GP1IN_IN1_BBA (*(volatile unsigned long *) 0x420C0884)
+#define GP1IN_IN1_MSK (0x1 << 1 )
+#define GP1IN_IN1 (0x1 << 1 )
+#define GP1IN_IN1_LOW (0x0 << 1 ) /* LOW */
+#define GP1IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GP1IN[IN0] - Input for port pin */
+#define GP1IN_IN0_BBA (*(volatile unsigned long *) 0x420C0880)
+#define GP1IN_IN0_MSK (0x1 << 0 )
+#define GP1IN_IN0 (0x1 << 0 )
+#define GP1IN_IN0_LOW (0x0 << 0 ) /* LOW */
+#define GP1IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* Reset Value for GP1OUT*/
+#define GP1OUT_RVAL 0x0
+
+/* GP1OUT[OUT7] - Output for port pin */
+#define GP1OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C091C)
+#define GP1OUT_OUT7_MSK (0x1 << 7 )
+#define GP1OUT_OUT7 (0x1 << 7 )
+#define GP1OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
+#define GP1OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GP1OUT[OUT6] - Output for port pin */
+#define GP1OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0918)
+#define GP1OUT_OUT6_MSK (0x1 << 6 )
+#define GP1OUT_OUT6 (0x1 << 6 )
+#define GP1OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
+#define GP1OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GP1OUT[OUT5] - Output for port pin */
+#define GP1OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0914)
+#define GP1OUT_OUT5_MSK (0x1 << 5 )
+#define GP1OUT_OUT5 (0x1 << 5 )
+#define GP1OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
+#define GP1OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GP1OUT[OUT4] - Output for port pin */
+#define GP1OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0910)
+#define GP1OUT_OUT4_MSK (0x1 << 4 )
+#define GP1OUT_OUT4 (0x1 << 4 )
+#define GP1OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
+#define GP1OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GP1OUT[OUT3] - Output for port pin */
+#define GP1OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C090C)
+#define GP1OUT_OUT3_MSK (0x1 << 3 )
+#define GP1OUT_OUT3 (0x1 << 3 )
+#define GP1OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
+#define GP1OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GP1OUT[OUT2] - Output for port pin */
+#define GP1OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0908)
+#define GP1OUT_OUT2_MSK (0x1 << 2 )
+#define GP1OUT_OUT2 (0x1 << 2 )
+#define GP1OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
+#define GP1OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GP1OUT[OUT1] - Output for port pin */
+#define GP1OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0904)
+#define GP1OUT_OUT1_MSK (0x1 << 1 )
+#define GP1OUT_OUT1 (0x1 << 1 )
+#define GP1OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
+#define GP1OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GP1OUT[OUT0] - Output for port pin */
+#define GP1OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0900)
+#define GP1OUT_OUT0_MSK (0x1 << 0 )
+#define GP1OUT_OUT0 (0x1 << 0 )
+#define GP1OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
+#define GP1OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* Reset Value for GP1SET*/
+#define GP1SET_RVAL 0x0
+
+/* GP1SET[SET7] - Set Output High for port pin */
+#define GP1SET_SET7_BBA (*(volatile unsigned long *) 0x420C099C)
+#define GP1SET_SET7_MSK (0x1 << 7 )
+#define GP1SET_SET7 (0x1 << 7 )
+#define GP1SET_SET7_SET (0x1 << 7 ) /* SET */
+
+/* GP1SET[SET6] - Set Output High for port pin */
+#define GP1SET_SET6_BBA (*(volatile unsigned long *) 0x420C0998)
+#define GP1SET_SET6_MSK (0x1 << 6 )
+#define GP1SET_SET6 (0x1 << 6 )
+#define GP1SET_SET6_SET (0x1 << 6 ) /* SET */
+
+/* GP1SET[SET5] - Set Output High for port pin */
+#define GP1SET_SET5_BBA (*(volatile unsigned long *) 0x420C0994)
+#define GP1SET_SET5_MSK (0x1 << 5 )
+#define GP1SET_SET5 (0x1 << 5 )
+#define GP1SET_SET5_SET (0x1 << 5 ) /* SET */
+
+/* GP1SET[SET4] - Set Output High for port pin */
+#define GP1SET_SET4_BBA (*(volatile unsigned long *) 0x420C0990)
+#define GP1SET_SET4_MSK (0x1 << 4 )
+#define GP1SET_SET4 (0x1 << 4 )
+#define GP1SET_SET4_SET (0x1 << 4 ) /* SET */
+
+/* GP1SET[SET3] - Set Output High for port pin */
+#define GP1SET_SET3_BBA (*(volatile unsigned long *) 0x420C098C)
+#define GP1SET_SET3_MSK (0x1 << 3 )
+#define GP1SET_SET3 (0x1 << 3 )
+#define GP1SET_SET3_SET (0x1 << 3 ) /* SET */
+
+/* GP1SET[SET2] - Set Output High for port pin */
+#define GP1SET_SET2_BBA (*(volatile unsigned long *) 0x420C0988)
+#define GP1SET_SET2_MSK (0x1 << 2 )
+#define GP1SET_SET2 (0x1 << 2 )
+#define GP1SET_SET2_SET (0x1 << 2 ) /* SET */
+
+/* GP1SET[SET1] - Set Output High for port pin */
+#define GP1SET_SET1_BBA (*(volatile unsigned long *) 0x420C0984)
+#define GP1SET_SET1_MSK (0x1 << 1 )
+#define GP1SET_SET1 (0x1 << 1 )
+#define GP1SET_SET1_SET (0x1 << 1 ) /* SET */
+
+/* GP1SET[SET0] - Set Output High for port pin */
+#define GP1SET_SET0_BBA (*(volatile unsigned long *) 0x420C0980)
+#define GP1SET_SET0_MSK (0x1 << 0 )
+#define GP1SET_SET0 (0x1 << 0 )
+#define GP1SET_SET0_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for GP1CLR*/
+#define GP1CLR_RVAL 0x0
+
+/* GP1CLR[CLR7] - Set Output Low for port pin */
+#define GP1CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C0A1C)
+#define GP1CLR_CLR7_MSK (0x1 << 7 )
+#define GP1CLR_CLR7 (0x1 << 7 )
+#define GP1CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
+
+/* GP1CLR[CLR6] - Set Output Low for port pin */
+#define GP1CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0A18)
+#define GP1CLR_CLR6_MSK (0x1 << 6 )
+#define GP1CLR_CLR6 (0x1 << 6 )
+#define GP1CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
+
+/* GP1CLR[CLR5] - Set Output Low for port pin */
+#define GP1CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0A14)
+#define GP1CLR_CLR5_MSK (0x1 << 5 )
+#define GP1CLR_CLR5 (0x1 << 5 )
+#define GP1CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
+
+/* GP1CLR[CLR4] - Set Output Low for port pin */
+#define GP1CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0A10)
+#define GP1CLR_CLR4_MSK (0x1 << 4 )
+#define GP1CLR_CLR4 (0x1 << 4 )
+#define GP1CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
+
+/* GP1CLR[CLR3] - Set Output Low for port pin */
+#define GP1CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C0A0C)
+#define GP1CLR_CLR3_MSK (0x1 << 3 )
+#define GP1CLR_CLR3 (0x1 << 3 )
+#define GP1CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
+
+/* GP1CLR[CLR2] - Set Output Low for port pin */
+#define GP1CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0A08)
+#define GP1CLR_CLR2_MSK (0x1 << 2 )
+#define GP1CLR_CLR2 (0x1 << 2 )
+#define GP1CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
+
+/* GP1CLR[CLR1] - Set Output Low for port pin */
+#define GP1CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0A04)
+#define GP1CLR_CLR1_MSK (0x1 << 1 )
+#define GP1CLR_CLR1 (0x1 << 1 )
+#define GP1CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
+
+/* GP1CLR[CLR0] - Set Output Low for port pin */
+#define GP1CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0A00)
+#define GP1CLR_CLR0_MSK (0x1 << 0 )
+#define GP1CLR_CLR0 (0x1 << 0 )
+#define GP1CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
+
+/* Reset Value for GP1TGL*/
+#define GP1TGL_RVAL 0x0
+
+/* GP1TGL[TGL7] - Toggle Output for port pin */
+#define GP1TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C0A9C)
+#define GP1TGL_TGL7_MSK (0x1 << 7 )
+#define GP1TGL_TGL7 (0x1 << 7 )
+#define GP1TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
+
+/* GP1TGL[TGL6] - Toggle Output for port pin */
+#define GP1TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0A98)
+#define GP1TGL_TGL6_MSK (0x1 << 6 )
+#define GP1TGL_TGL6 (0x1 << 6 )
+#define GP1TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
+
+/* GP1TGL[TGL5] - Toggle Output for port pin */
+#define GP1TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0A94)
+#define GP1TGL_TGL5_MSK (0x1 << 5 )
+#define GP1TGL_TGL5 (0x1 << 5 )
+#define GP1TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
+
+/* GP1TGL[TGL4] - Toggle Output for port pin */
+#define GP1TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0A90)
+#define GP1TGL_TGL4_MSK (0x1 << 4 )
+#define GP1TGL_TGL4 (0x1 << 4 )
+#define GP1TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
+
+/* GP1TGL[TGL3] - Toggle Output for port pin */
+#define GP1TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C0A8C)
+#define GP1TGL_TGL3_MSK (0x1 << 3 )
+#define GP1TGL_TGL3 (0x1 << 3 )
+#define GP1TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
+
+/* GP1TGL[TGL2] - Toggle Output for port pin */
+#define GP1TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0A88)
+#define GP1TGL_TGL2_MSK (0x1 << 2 )
+#define GP1TGL_TGL2 (0x1 << 2 )
+#define GP1TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
+
+/* GP1TGL[TGL1] - Toggle Output for port pin */
+#define GP1TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0A84)
+#define GP1TGL_TGL1_MSK (0x1 << 1 )
+#define GP1TGL_TGL1 (0x1 << 1 )
+#define GP1TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
+
+/* GP1TGL[TGL0] - Toggle Output for port pin */
+#define GP1TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0A80)
+#define GP1TGL_TGL0_MSK (0x1 << 0 )
+#define GP1TGL_TGL0 (0x1 << 0 )
+#define GP1TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
+#if (__NO_MMR_STRUCTS__==1)
+
+#define GP2CON (*(volatile unsigned short int *) 0x40006060)
+#define GP2OEN (*(volatile unsigned char *) 0x40006064)
+#define GP2PUL (*(volatile unsigned char *) 0x40006068)
+#define GP2OCE (*(volatile unsigned char *) 0x4000606C)
+#define GP2IN (*(volatile unsigned char *) 0x40006074)
+#define GP2OUT (*(volatile unsigned char *) 0x40006078)
+#define GP2SET (*(volatile unsigned char *) 0x4000607C)
+#define GP2CLR (*(volatile unsigned char *) 0x40006080)
+#define GP2TGL (*(volatile unsigned char *) 0x40006084)
+#endif // (__NO_MMR_STRUCTS__==1)
+
+/* Reset Value for GP2CON*/
+#define GP2CON_RVAL 0x0
+
+/* GP2CON[CON4] - Configuration bits for P2.4 */
+#define GP2CON_CON4_MSK (0x3 << 8 )
+#define GP2CON_CON4_SWDATA (0x1 << 8 ) /* SWDATA */
+
+/* GP2CON[CON3] - Configuration bits for P2.3 */
+#define GP2CON_CON3_MSK (0x3 << 6 )
+#define GP2CON_CON3_SWCLK (0x1 << 6 ) /* SWCLK */
+
+/* GP2CON[CON2] - Configuration bits for P2.2 */
+#define GP2CON_CON2_MSK (0x3 << 4 )
+#define GP2CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
+
+/* GP2CON[CON1] - Configuration bits for P2.1 */
+#define GP2CON_CON1_MSK (0x3 << 2 )
+#define GP2CON_CON1_GPIO (0x0 << 2 ) /* GPIO */
+#define GP2CON_CON1_I2CSDA (0x1 << 2 ) /* I2CSDA */
+
+/* GP2CON[CON0] - Configuration bits for P2.0 */
+#define GP2CON_CON0_MSK (0x3 << 0 )
+#define GP2CON_CON0_GPIO (0x0 << 0 ) /* GPIO */
+#define GP2CON_CON0_I2CSCL (0x1 << 0 ) /* I2CSCL */
+
+/* Reset Value for GP2OEN*/
+#define GP2OEN_RVAL 0x0
+
+/* GP2OEN[OEN7] - Direction for port pin */
+#define GP2OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C0C9C)
+#define GP2OEN_OEN7_MSK (0x1 << 7 )
+#define GP2OEN_OEN7 (0x1 << 7 )
+#define GP2OEN_OEN7_IN (0x0 << 7 ) /* IN */
+#define GP2OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
+
+/* GP2OEN[OEN6] - Direction for port pin */
+#define GP2OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0C98)
+#define GP2OEN_OEN6_MSK (0x1 << 6 )
+#define GP2OEN_OEN6 (0x1 << 6 )
+#define GP2OEN_OEN6_IN (0x0 << 6 ) /* IN */
+#define GP2OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
+
+/* GP2OEN[OEN5] - Direction for port pin */
+#define GP2OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0C94)
+#define GP2OEN_OEN5_MSK (0x1 << 5 )
+#define GP2OEN_OEN5 (0x1 << 5 )
+#define GP2OEN_OEN5_IN (0x0 << 5 ) /* IN */
+#define GP2OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
+
+/* GP2OEN[OEN4] - Direction for port pin */
+#define GP2OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0C90)
+#define GP2OEN_OEN4_MSK (0x1 << 4 )
+#define GP2OEN_OEN4 (0x1 << 4 )
+#define GP2OEN_OEN4_IN (0x0 << 4 ) /* IN */
+#define GP2OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
+
+/* GP2OEN[OEN3] - Direction for port pin */
+#define GP2OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C0C8C)
+#define GP2OEN_OEN3_MSK (0x1 << 3 )
+#define GP2OEN_OEN3 (0x1 << 3 )
+#define GP2OEN_OEN3_IN (0x0 << 3 ) /* IN */
+#define GP2OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
+
+/* GP2OEN[OEN2] - Direction for port pin */
+#define GP2OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0C88)
+#define GP2OEN_OEN2_MSK (0x1 << 2 )
+#define GP2OEN_OEN2 (0x1 << 2 )
+#define GP2OEN_OEN2_IN (0x0 << 2 ) /* IN */
+#define GP2OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
+
+/* GP2OEN[OEN1] - Direction for port pin */
+#define GP2OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0C84)
+#define GP2OEN_OEN1_MSK (0x1 << 1 )
+#define GP2OEN_OEN1 (0x1 << 1 )
+#define GP2OEN_OEN1_IN (0x0 << 1 ) /* IN */
+#define GP2OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
+
+/* GP2OEN[OEN0] - Direction for port pin */
+#define GP2OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0C80)
+#define GP2OEN_OEN0_MSK (0x1 << 0 )
+#define GP2OEN_OEN0 (0x1 << 0 )
+#define GP2OEN_OEN0_IN (0x0 << 0 ) /* IN */
+#define GP2OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
+
+/* Reset Value for GP2PUL*/
+#define GP2PUL_RVAL 0xFF
+
+/* GP2PUL[PUL7] - Pull Up Enable for port pin */
+#define GP2PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C0D1C)
+#define GP2PUL_PUL7_MSK (0x1 << 7 )
+#define GP2PUL_PUL7 (0x1 << 7 )
+#define GP2PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
+#define GP2PUL_PUL7_EN (0x1 << 7 ) /* EN */
+
+/* GP2PUL[PUL6] - Pull Up Enable for port pin */
+#define GP2PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0D18)
+#define GP2PUL_PUL6_MSK (0x1 << 6 )
+#define GP2PUL_PUL6 (0x1 << 6 )
+#define GP2PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
+#define GP2PUL_PUL6_EN (0x1 << 6 ) /* EN */
+
+/* GP2PUL[PUL5] - Pull Up Enable for port pin */
+#define GP2PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0D14)
+#define GP2PUL_PUL5_MSK (0x1 << 5 )
+#define GP2PUL_PUL5 (0x1 << 5 )
+#define GP2PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
+#define GP2PUL_PUL5_EN (0x1 << 5 ) /* EN */
+
+/* GP2PUL[PUL4] - Pull Up Enable for port pin */
+#define GP2PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0D10)
+#define GP2PUL_PUL4_MSK (0x1 << 4 )
+#define GP2PUL_PUL4 (0x1 << 4 )
+#define GP2PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
+#define GP2PUL_PUL4_EN (0x1 << 4 ) /* EN */
+
+/* GP2PUL[PUL3] - Pull Up Enable for port pin */
+#define GP2PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C0D0C)
+#define GP2PUL_PUL3_MSK (0x1 << 3 )
+#define GP2PUL_PUL3 (0x1 << 3 )
+#define GP2PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
+#define GP2PUL_PUL3_EN (0x1 << 3 ) /* EN */
+
+/* GP2PUL[PUL2] - Pull Up Enable for port pin */
+#define GP2PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0D08)
+#define GP2PUL_PUL2_MSK (0x1 << 2 )
+#define GP2PUL_PUL2 (0x1 << 2 )
+#define GP2PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
+#define GP2PUL_PUL2_EN (0x1 << 2 ) /* EN */
+
+/* GP2PUL[PUL1] - Pull Up Enable for port pin */
+#define GP2PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0D04)
+#define GP2PUL_PUL1_MSK (0x1 << 1 )
+#define GP2PUL_PUL1 (0x1 << 1 )
+#define GP2PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
+#define GP2PUL_PUL1_EN (0x1 << 1 ) /* EN */
+
+/* GP2PUL[PUL0] - Pull Up Enable for port pin */
+#define GP2PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0D00)
+#define GP2PUL_PUL0_MSK (0x1 << 0 )
+#define GP2PUL_PUL0 (0x1 << 0 )
+#define GP2PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
+#define GP2PUL_PUL0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for GP2OCE*/
+#define GP2OCE_RVAL 0x0
+
+/* GP2OCE[OCE7] - open circuit Enable for port pin */
+#define GP2OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C0D9C)
+#define GP2OCE_OCE7_MSK (0x1 << 7 )
+#define GP2OCE_OCE7 (0x1 << 7 )
+#define GP2OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
+#define GP2OCE_OCE7_EN (0x1 << 7 ) /* EN */
+
+/* GP2OCE[OCE6] - open circuit Enable for port pin */
+#define GP2OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0D98)
+#define GP2OCE_OCE6_MSK (0x1 << 6 )
+#define GP2OCE_OCE6 (0x1 << 6 )
+#define GP2OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
+#define GP2OCE_OCE6_EN (0x1 << 6 ) /* EN */
+
+/* GP2OCE[OCE5] - open circuit Enable for port pin */
+#define GP2OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0D94)
+#define GP2OCE_OCE5_MSK (0x1 << 5 )
+#define GP2OCE_OCE5 (0x1 << 5 )
+#define GP2OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
+#define GP2OCE_OCE5_EN (0x1 << 5 ) /* EN */
+
+/* GP2OCE[OCE4] - open circuit Enable for port pin */
+#define GP2OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0D90)
+#define GP2OCE_OCE4_MSK (0x1 << 4 )
+#define GP2OCE_OCE4 (0x1 << 4 )
+#define GP2OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
+#define GP2OCE_OCE4_EN (0x1 << 4 ) /* EN */
+
+/* GP2OCE[OCE3] - open circuit Enable for port pin */
+#define GP2OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C0D8C)
+#define GP2OCE_OCE3_MSK (0x1 << 3 )
+#define GP2OCE_OCE3 (0x1 << 3 )
+#define GP2OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
+#define GP2OCE_OCE3_EN (0x1 << 3 ) /* EN */
+
+/* GP2OCE[OCE2] - open circuit Enable for port pin */
+#define GP2OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0D88)
+#define GP2OCE_OCE2_MSK (0x1 << 2 )
+#define GP2OCE_OCE2 (0x1 << 2 )
+#define GP2OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
+#define GP2OCE_OCE2_EN (0x1 << 2 ) /* EN */
+
+/* GP2OCE[OCE1] - open circuit Enable for port pin */
+#define GP2OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0D84)
+#define GP2OCE_OCE1_MSK (0x1 << 1 )
+#define GP2OCE_OCE1 (0x1 << 1 )
+#define GP2OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
+#define GP2OCE_OCE1_EN (0x1 << 1 ) /* EN */
+
+/* GP2OCE[OCE0] - open circuit Enable for port pin */
+#define GP2OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0D80)
+#define GP2OCE_OCE0_MSK (0x1 << 0 )
+#define GP2OCE_OCE0 (0x1 << 0 )
+#define GP2OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
+#define GP2OCE_OCE0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for GP2IN*/
+#define GP2IN_RVAL 0x0
+
+/* GP2IN[IN7] - Input for port pin */
+#define GP2IN_IN7_BBA (*(volatile unsigned long *) 0x420C0E9C)
+#define GP2IN_IN7_MSK (0x1 << 7 )
+#define GP2IN_IN7 (0x1 << 7 )
+#define GP2IN_IN7_LOW (0x0 << 7 ) /* LOW */
+#define GP2IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GP2IN[IN6] - Input for port pin */
+#define GP2IN_IN6_BBA (*(volatile unsigned long *) 0x420C0E98)
+#define GP2IN_IN6_MSK (0x1 << 6 )
+#define GP2IN_IN6 (0x1 << 6 )
+#define GP2IN_IN6_LOW (0x0 << 6 ) /* LOW */
+#define GP2IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GP2IN[IN5] - Input for port pin */
+#define GP2IN_IN5_BBA (*(volatile unsigned long *) 0x420C0E94)
+#define GP2IN_IN5_MSK (0x1 << 5 )
+#define GP2IN_IN5 (0x1 << 5 )
+#define GP2IN_IN5_LOW (0x0 << 5 ) /* LOW */
+#define GP2IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GP2IN[IN4] - Input for port pin */
+#define GP2IN_IN4_BBA (*(volatile unsigned long *) 0x420C0E90)
+#define GP2IN_IN4_MSK (0x1 << 4 )
+#define GP2IN_IN4 (0x1 << 4 )
+#define GP2IN_IN4_LOW (0x0 << 4 ) /* LOW */
+#define GP2IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GP2IN[IN3] - Input for port pin */
+#define GP2IN_IN3_BBA (*(volatile unsigned long *) 0x420C0E8C)
+#define GP2IN_IN3_MSK (0x1 << 3 )
+#define GP2IN_IN3 (0x1 << 3 )
+#define GP2IN_IN3_LOW (0x0 << 3 ) /* LOW */
+#define GP2IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GP2IN[IN2] - Input for port pin */
+#define GP2IN_IN2_BBA (*(volatile unsigned long *) 0x420C0E88)
+#define GP2IN_IN2_MSK (0x1 << 2 )
+#define GP2IN_IN2 (0x1 << 2 )
+#define GP2IN_IN2_LOW (0x0 << 2 ) /* LOW */
+#define GP2IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GP2IN[IN1] - Input for port pin */
+#define GP2IN_IN1_BBA (*(volatile unsigned long *) 0x420C0E84)
+#define GP2IN_IN1_MSK (0x1 << 1 )
+#define GP2IN_IN1 (0x1 << 1 )
+#define GP2IN_IN1_LOW (0x0 << 1 ) /* LOW */
+#define GP2IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GP2IN[IN0] - Input for port pin */
+#define GP2IN_IN0_BBA (*(volatile unsigned long *) 0x420C0E80)
+#define GP2IN_IN0_MSK (0x1 << 0 )
+#define GP2IN_IN0 (0x1 << 0 )
+#define GP2IN_IN0_LOW (0x0 << 0 ) /* LOW */
+#define GP2IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* Reset Value for GP2OUT*/
+#define GP2OUT_RVAL 0x0
+
+/* GP2OUT[OUT7] - Output for port pin */
+#define GP2OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C0F1C)
+#define GP2OUT_OUT7_MSK (0x1 << 7 )
+#define GP2OUT_OUT7 (0x1 << 7 )
+#define GP2OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
+#define GP2OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
+
+/* GP2OUT[OUT6] - Output for port pin */
+#define GP2OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0F18)
+#define GP2OUT_OUT6_MSK (0x1 << 6 )
+#define GP2OUT_OUT6 (0x1 << 6 )
+#define GP2OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
+#define GP2OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
+
+/* GP2OUT[OUT5] - Output for port pin */
+#define GP2OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0F14)
+#define GP2OUT_OUT5_MSK (0x1 << 5 )
+#define GP2OUT_OUT5 (0x1 << 5 )
+#define GP2OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
+#define GP2OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
+
+/* GP2OUT[OUT4] - Output for port pin */
+#define GP2OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0F10)
+#define GP2OUT_OUT4_MSK (0x1 << 4 )
+#define GP2OUT_OUT4 (0x1 << 4 )
+#define GP2OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
+#define GP2OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
+
+/* GP2OUT[OUT3] - Output for port pin */
+#define GP2OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C0F0C)
+#define GP2OUT_OUT3_MSK (0x1 << 3 )
+#define GP2OUT_OUT3 (0x1 << 3 )
+#define GP2OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
+#define GP2OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
+
+/* GP2OUT[OUT2] - Output for port pin */
+#define GP2OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0F08)
+#define GP2OUT_OUT2_MSK (0x1 << 2 )
+#define GP2OUT_OUT2 (0x1 << 2 )
+#define GP2OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
+#define GP2OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
+
+/* GP2OUT[OUT1] - Output for port pin */
+#define GP2OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0F04)
+#define GP2OUT_OUT1_MSK (0x1 << 1 )
+#define GP2OUT_OUT1 (0x1 << 1 )
+#define GP2OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
+#define GP2OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
+
+/* GP2OUT[OUT0] - Output for port pin */
+#define GP2OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0F00)
+#define GP2OUT_OUT0_MSK (0x1 << 0 )
+#define GP2OUT_OUT0 (0x1 << 0 )
+#define GP2OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
+#define GP2OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
+
+/* Reset Value for GP2SET*/
+#define GP2SET_RVAL 0x0
+
+/* GP2SET[SET7] - Set Output High for port pin */
+#define GP2SET_SET7_BBA (*(volatile unsigned long *) 0x420C0F9C)
+#define GP2SET_SET7_MSK (0x1 << 7 )
+#define GP2SET_SET7 (0x1 << 7 )
+#define GP2SET_SET7_SET (0x1 << 7 ) /* SET */
+
+/* GP2SET[SET6] - Set Output High for port pin */
+#define GP2SET_SET6_BBA (*(volatile unsigned long *) 0x420C0F98)
+#define GP2SET_SET6_MSK (0x1 << 6 )
+#define GP2SET_SET6 (0x1 << 6 )
+#define GP2SET_SET6_SET (0x1 << 6 ) /* SET */
+
+/* GP2SET[SET5] - Set Output High for port pin */
+#define GP2SET_SET5_BBA (*(volatile unsigned long *) 0x420C0F94)
+#define GP2SET_SET5_MSK (0x1 << 5 )
+#define GP2SET_SET5 (0x1 << 5 )
+#define GP2SET_SET5_SET (0x1 << 5 ) /* SET */
+
+/* GP2SET[SET4] - Set Output High for port pin */
+#define GP2SET_SET4_BBA (*(volatile unsigned long *) 0x420C0F90)
+#define GP2SET_SET4_MSK (0x1 << 4 )
+#define GP2SET_SET4 (0x1 << 4 )
+#define GP2SET_SET4_SET (0x1 << 4 ) /* SET */
+
+/* GP2SET[SET3] - Set Output High for port pin */
+#define GP2SET_SET3_BBA (*(volatile unsigned long *) 0x420C0F8C)
+#define GP2SET_SET3_MSK (0x1 << 3 )
+#define GP2SET_SET3 (0x1 << 3 )
+#define GP2SET_SET3_SET (0x1 << 3 ) /* SET */
+
+/* GP2SET[SET2] - Set Output High for port pin */
+#define GP2SET_SET2_BBA (*(volatile unsigned long *) 0x420C0F88)
+#define GP2SET_SET2_MSK (0x1 << 2 )
+#define GP2SET_SET2 (0x1 << 2 )
+#define GP2SET_SET2_SET (0x1 << 2 ) /* SET */
+
+/* GP2SET[SET1] - Set Output High for port pin */
+#define GP2SET_SET1_BBA (*(volatile unsigned long *) 0x420C0F84)
+#define GP2SET_SET1_MSK (0x1 << 1 )
+#define GP2SET_SET1 (0x1 << 1 )
+#define GP2SET_SET1_SET (0x1 << 1 ) /* SET */
+
+/* GP2SET[SET0] - Set Output High for port pin */
+#define GP2SET_SET0_BBA (*(volatile unsigned long *) 0x420C0F80)
+#define GP2SET_SET0_MSK (0x1 << 0 )
+#define GP2SET_SET0 (0x1 << 0 )
+#define GP2SET_SET0_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for GP2CLR*/
+#define GP2CLR_RVAL 0x0
+
+/* GP2CLR[CLR7] - Set Output Low for port pin */
+#define GP2CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C101C)
+#define GP2CLR_CLR7_MSK (0x1 << 7 )
+#define GP2CLR_CLR7 (0x1 << 7 )
+#define GP2CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
+
+/* GP2CLR[CLR6] - Set Output Low for port pin */
+#define GP2CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1018)
+#define GP2CLR_CLR6_MSK (0x1 << 6 )
+#define GP2CLR_CLR6 (0x1 << 6 )
+#define GP2CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
+
+/* GP2CLR[CLR5] - Set Output Low for port pin */
+#define GP2CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1014)
+#define GP2CLR_CLR5_MSK (0x1 << 5 )
+#define GP2CLR_CLR5 (0x1 << 5 )
+#define GP2CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
+
+/* GP2CLR[CLR4] - Set Output Low for port pin */
+#define GP2CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1010)
+#define GP2CLR_CLR4_MSK (0x1 << 4 )
+#define GP2CLR_CLR4 (0x1 << 4 )
+#define GP2CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
+
+/* GP2CLR[CLR3] - Set Output Low for port pin */
+#define GP2CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C100C)
+#define GP2CLR_CLR3_MSK (0x1 << 3 )
+#define GP2CLR_CLR3 (0x1 << 3 )
+#define GP2CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
+
+/* GP2CLR[CLR2] - Set Output Low for port pin */
+#define GP2CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1008)
+#define GP2CLR_CLR2_MSK (0x1 << 2 )
+#define GP2CLR_CLR2 (0x1 << 2 )
+#define GP2CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
+
+/* GP2CLR[CLR1] - Set Output Low for port pin */
+#define GP2CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1004)
+#define GP2CLR_CLR1_MSK (0x1 << 1 )
+#define GP2CLR_CLR1 (0x1 << 1 )
+#define GP2CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
+
+/* GP2CLR[CLR0] - Set Output Low for port pin */
+#define GP2CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1000)
+#define GP2CLR_CLR0_MSK (0x1 << 0 )
+#define GP2CLR_CLR0 (0x1 << 0 )
+#define GP2CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
+
+/* Reset Value for GP2TGL*/
+#define GP2TGL_RVAL 0x0
+
+/* GP2TGL[TGL7] - Toggle Output for port pin */
+#define GP2TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C109C)
+#define GP2TGL_TGL7_MSK (0x1 << 7 )
+#define GP2TGL_TGL7 (0x1 << 7 )
+#define GP2TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
+
+/* GP2TGL[TGL6] - Toggle Output for port pin */
+#define GP2TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1098)
+#define GP2TGL_TGL6_MSK (0x1 << 6 )
+#define GP2TGL_TGL6 (0x1 << 6 )
+#define GP2TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
+
+/* GP2TGL[TGL5] - Toggle Output for port pin */
+#define GP2TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1094)
+#define GP2TGL_TGL5_MSK (0x1 << 5 )
+#define GP2TGL_TGL5 (0x1 << 5 )
+#define GP2TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
+
+/* GP2TGL[TGL4] - Toggle Output for port pin */
+#define GP2TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1090)
+#define GP2TGL_TGL4_MSK (0x1 << 4 )
+#define GP2TGL_TGL4 (0x1 << 4 )
+#define GP2TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
+
+/* GP2TGL[TGL3] - Toggle Output for port pin */
+#define GP2TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C108C)
+#define GP2TGL_TGL3_MSK (0x1 << 3 )
+#define GP2TGL_TGL3 (0x1 << 3 )
+#define GP2TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
+
+/* GP2TGL[TGL2] - Toggle Output for port pin */
+#define GP2TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1088)
+#define GP2TGL_TGL2_MSK (0x1 << 2 )
+#define GP2TGL_TGL2 (0x1 << 2 )
+#define GP2TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
+
+/* GP2TGL[TGL1] - Toggle Output for port pin */
+#define GP2TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1084)
+#define GP2TGL_TGL1_MSK (0x1 << 1 )
+#define GP2TGL_TGL1 (0x1 << 1 )
+#define GP2TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
+
+/* GP2TGL[TGL0] - Toggle Output for port pin */
+#define GP2TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1080)
+#define GP2TGL_TGL0_MSK (0x1 << 0 )
+#define GP2TGL_TGL0 (0x1 << 0 )
+#define GP2TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
+// ------------------------------------------------------------------------------------------------
+// ----- ANA -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Analog Control (pADI_ANA)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_ANA Structure */
+ __I uint32_t RESERVED0[12];
+ __IO uint16_t
+ REFCTRL; /*!< Internal Reference Control register */
+ __I uint16_t RESERVED1[7];
+ __IO uint8_t
+ IEXCCON; /*!< Controls the on-chip Excitation Current Sources */
+ __I uint8_t RESERVED2[3];
+ __IO uint8_t
+ IEXCDAT; /*!< Sets the output current setting for both Excitation Current sources */
+ __I uint8_t RESERVED3[3];
+} ADI_ANA_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define REFCTRL (*(volatile unsigned short int *) 0x40008840)
+#define IEXCCON (*(volatile unsigned char *) 0x40008850)
+#define IEXCDAT (*(volatile unsigned char *) 0x40008854)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for REFCTRL*/
+#define REFCTRL_RVAL 0x0
+
+/* REFCTRL[REFPD] - Power down reference */
+#define REFCTRL_REFPD_BBA (*(volatile unsigned long *) 0x42110800)
+#define REFCTRL_REFPD_MSK (0x1 << 0 )
+#define REFCTRL_REFPD (0x1 << 0 )
+#define REFCTRL_REFPD_DIS (0x0 << 0 ) /* DIS */
+#define REFCTRL_REFPD_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for IEXCCON*/
+#define IEXCCON_RVAL 0xC0
+
+/* IEXCCON[PD] - IEXC Power down- bits */
+#define IEXCCON_PD_BBA (*(volatile unsigned long *) 0x42110A1C)
+#define IEXCCON_PD_MSK (0x1 << 7 )
+#define IEXCCON_PD (0x1 << 7 )
+#define IEXCCON_PD_En (0x1 << 7 ) /* En */
+#define IEXCCON_PD_off (0x0 << 7 ) /* off */
+
+/* IEXCCON[REFSEL] - IREF Source- bits */
+#define IEXCCON_REFSEL_BBA (*(volatile unsigned long *) 0x42110A18)
+#define IEXCCON_REFSEL_MSK (0x1 << 6 )
+#define IEXCCON_REFSEL (0x1 << 6 )
+#define IEXCCON_REFSEL_Ext (0x0 << 6 ) /* Ext */
+#define IEXCCON_REFSEL_Int (0x1 << 6 ) /* Int */
+
+/* IEXCCON[IPSEL1] - Select IEXC1 pin AIN- bits */
+#define IEXCCON_IPSEL1_MSK (0x7 << 3 )
+#define IEXCCON_IPSEL1_Off (0x0 << 3 ) /* Off */
+#define IEXCCON_IPSEL1_AIN4 (0x4 << 3 ) /* AIN4 */
+#define IEXCCON_IPSEL1_AIN5 (0x5 << 3 ) /* AIN5 */
+#define IEXCCON_IPSEL1_AIN6 (0x6 << 3 ) /* AIN6 */
+#define IEXCCON_IPSEL1_AIN7 (0x7 << 3 ) /* AIN7 */
+
+/* IEXCCON[IPSEL0] - Select IEXC0 pin AIN- bits */
+#define IEXCCON_IPSEL0_MSK (0x7 << 0 )
+#define IEXCCON_IPSEL0_Off (0x0 << 0 ) /* Off */
+#define IEXCCON_IPSEL0_AIN4 (0x4 << 0 ) /* AIN4 */
+#define IEXCCON_IPSEL0_AIN5 (0x5 << 0 ) /* AIN5 */
+#define IEXCCON_IPSEL0_AIN6 (0x6 << 0 ) /* AIN6 */
+#define IEXCCON_IPSEL0_AIN7 (0x7 << 0 ) /* AIN7 */
+
+/* Reset Value for IEXCDAT*/
+#define IEXCDAT_RVAL 0x6
+
+/* IEXCDAT[IDAT] - Output Current- bits */
+#define IEXCDAT_IDAT_MSK (0x1F << 1 )
+#define IEXCDAT_IDAT_0uA (0x0 << 1 ) /* 0uA */
+#define IEXCDAT_IDAT_50uA (0x4 << 1 ) /* 50uA */
+#define IEXCDAT_IDAT_100uA (0x5 << 1 ) /* 100uA */
+#define IEXCDAT_IDAT_150uA (0x6 << 1 ) /* 150uA */
+#define IEXCDAT_IDAT_200uA (0x7 << 1 ) /* 200uA */
+#define IEXCDAT_IDAT_250uA (0x14 << 1 ) /* 250uA */
+#define IEXCDAT_IDAT_300uA (0xA << 1 ) /* 300uA */
+#define IEXCDAT_IDAT_400uA (0xB << 1 ) /* 400uA */
+#define IEXCDAT_IDAT_450uA (0xE << 1 ) /* 450uA */
+#define IEXCDAT_IDAT_500uA (0x15 << 1 ) /* 500uA */
+#define IEXCDAT_IDAT_600uA (0xF << 1 ) /* 600uA */
+#define IEXCDAT_IDAT_750uA (0x16 << 1 ) /* 750uA */
+#define IEXCDAT_IDAT_800uA (0x13 << 1 ) /* 800uA */
+#define IEXCDAT_IDAT_1mA (0x1F << 1 ) /* 1mA */
+
+/* IEXCDAT[IDAT0] - 10uA Enable */
+#define IEXCDAT_IDAT0_BBA (*(volatile unsigned long *) 0x42110A80)
+#define IEXCDAT_IDAT0_MSK (0x1 << 0 )
+#define IEXCDAT_IDAT0 (0x1 << 0 )
+#define IEXCDAT_IDAT0_DIS (0x0 << 0 ) /* DIS */
+#define IEXCDAT_IDAT0_EN (0x1 << 0 ) /* EN */
+// ------------------------------------------------------------------------------------------------
+// ----- DMA -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Direct Memory Access (pADI_DMA)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_DMA Structure */
+ __IO uint32_t
+ DMASTA; /*!< Returns the status of the controller when not in the reset state. */
+ __IO uint32_t
+ DMACFG; /*!< Configuraton */
+ __IO uint32_t
+ DMAPDBPTR; /*!< Channel primary control database pointer */
+ __IO uint32_t
+ DMAADBPTR; /*!< Channel alt control database pointer */
+ __I uint32_t RESERVED0;
+ __IO uint32_t
+ DMASWREQ; /*!< Channel Software Request */
+ __I uint32_t RESERVED1[2];
+ __IO uint32_t
+ DMARMSKSET; /*!< Channel Request Mask Set */
+ __IO uint32_t
+ DMARMSKCLR; /*!< Channel Request Mask Clear */
+ __IO uint32_t
+ DMAENSET; /*!< Channel Enable Set */
+ __IO uint32_t
+ DMAENCLR; /*!< Channel Enable Clear */
+ __IO uint32_t
+ DMAALTSET; /*!< Channel Primary-Alternate Set */
+ __IO uint32_t
+ DMAALTCLR; /*!< Channel Primary-Alternate Clear */
+ __IO uint32_t
+ DMAPRISET; /*!< Channel Priority Set */
+ __IO uint32_t
+ DMAPRICLR; /*!< Channel Priority Clear */
+ __I uint32_t RESERVED2[3];
+ __IO uint32_t
+ DMAERRCLR; /*!< Bus Error Clear */
+ __I uint32_t RESERVED3[992];
+ __IO uint8_t
+ DMAPERID4; /*!< Peripheral identification 4 */
+ __I uint8_t RESERVED4[15];
+ __IO uint8_t
+ DMAPERID0; /*!< Peripheral identification 0 */
+ __I uint8_t RESERVED5[3];
+ __IO uint8_t
+ DMAPERID1; /*!< Peripheral identification 1 */
+ __I uint8_t RESERVED6[3];
+ __IO uint8_t
+ DMAPERID2; /*!< Peripheral identification 2 */
+ __I uint8_t RESERVED7[3];
+ __IO uint8_t
+ DMAPERID3; /*!< Peripheral identification 3 */
+ __I uint8_t RESERVED8[3];
+ __IO uint8_t
+ DMAPCELLID0; /*!< PrimeCell identification 0 */
+ __I uint8_t RESERVED9[3];
+ __IO uint8_t
+ DMAPCELLID1; /*!< PrimeCell identification 1 */
+ __I uint8_t RESERVED10[3];
+ __IO uint8_t
+ DMAPCELLID2; /*!< PrimeCell identification 2 */
+ __I uint8_t RESERVED11[3];
+ __IO uint8_t
+ DMAPCELLID3; /*!< PrimeCell identification 3 */
+ __I uint8_t RESERVED12[3];
+} ADI_DMA_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define DMASTA (*(volatile unsigned long *) 0x40010000)
+#define DMACFG (*(volatile unsigned long *) 0x40010004)
+#define DMAPDBPTR (*(volatile unsigned long *) 0x40010008)
+#define DMAADBPTR (*(volatile unsigned long *) 0x4001000C)
+#define DMASWREQ (*(volatile unsigned long *) 0x40010014)
+#define DMARMSKSET (*(volatile unsigned long *) 0x40010020)
+#define DMARMSKCLR (*(volatile unsigned long *) 0x40010024)
+#define DMAENSET (*(volatile unsigned long *) 0x40010028)
+#define DMAENCLR (*(volatile unsigned long *) 0x4001002C)
+#define DMAALTSET (*(volatile unsigned long *) 0x40010030)
+#define DMAALTCLR (*(volatile unsigned long *) 0x40010034)
+#define DMAPRISET (*(volatile unsigned long *) 0x40010038)
+#define DMAPRICLR (*(volatile unsigned long *) 0x4001003C)
+#define DMAERRCLR (*(volatile unsigned long *) 0x4001004C)
+#define DMAPERID4 (*(volatile unsigned char *) 0x40010FD0)
+#define DMAPERID0 (*(volatile unsigned char *) 0x40010FE0)
+#define DMAPERID1 (*(volatile unsigned char *) 0x40010FE4)
+#define DMAPERID2 (*(volatile unsigned char *) 0x40010FE8)
+#define DMAPERID3 (*(volatile unsigned char *) 0x40010FEC)
+#define DMAPCELLID0 (*(volatile unsigned char *) 0x40010FF0)
+#define DMAPCELLID1 (*(volatile unsigned char *) 0x40010FF4)
+#define DMAPCELLID2 (*(volatile unsigned char *) 0x40010FF8)
+#define DMAPCELLID3 (*(volatile unsigned char *) 0x40010FFC)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for DMASTA*/
+#define DMASTA_RVAL 0xB0000
+
+/* DMASTA[CHNLSMINUS1] - Number of available DMA channels minus one. */
+#define DMASTA_CHNLSMINUS1_MSK (0x1F << 16 )
+#define DMASTA_CHNLSMINUS1_FOURTEENCHNLS (0xD << 16 ) /* FOURTEENCHNLS - Controller configured to use 14 DMA channels */
+#define DMASTA_CHNLSMINUS1_TWELVECHNLS (0xB << 16 ) /* TWELVECHNLS - Controller configured to use 12 DMA channels */
+
+/* DMASTA[STATE] - Current state of the control state machine. */
+#define DMASTA_STATE_MSK (0xF << 4 )
+#define DMASTA_STATE_IDLE (0x0 << 4 ) /* IDLE - Idle */
+#define DMASTA_STATE_RDCHNLDATA (0x1 << 4 ) /* RDCHNLDATA - Reading channel controller data */
+#define DMASTA_STATE_RDSRCENDPTR (0x2 << 4 ) /* RDSRCENDPTR - Reading source data end pointer */
+#define DMASTA_STATE_RDDSTENDPTR (0x3 << 4 ) /* RDDSTENDPTR - Reading destination data end pointer */
+#define DMASTA_STATE_RDSRCDATA (0x4 << 4 ) /* RDSRCDATA - Reading source data */
+#define DMASTA_STATE_WRDSTDATA (0x5 << 4 ) /* WRDSTDATA - Writing destination data */
+#define DMASTA_STATE_WAITDMAREQCLR (0x6 << 4 ) /* WAITDMAREQCLR - Waiting for DMA request to clear */
+#define DMASTA_STATE_WRCHNLDATA (0x7 << 4 ) /* WRCHNLDATA - Writing channel controller data */
+#define DMASTA_STATE_STALLED (0x8 << 4 ) /* STALLED - Stalled */
+#define DMASTA_STATE_DONE (0x9 << 4 ) /* DONE - Done */
+#define DMASTA_STATE_SCATRGATHR (0xA << 4 ) /* SCATRGATHR - Peripheral scatter-gather transition */
+
+/* DMASTA[ENABLE] - Master DMA controller enable status. */
+#define DMASTA_ENABLE_BBA (*(volatile unsigned long *) 0x42200000)
+#define DMASTA_ENABLE_MSK (0x1 << 0 )
+#define DMASTA_ENABLE (0x1 << 0 )
+#define DMASTA_ENABLE_CLR (0x0 << 0 ) /* CLR */
+#define DMASTA_ENABLE_SET (0x1 << 0 ) /* SET */
+
+/* Reset Value for DMACFG*/
+#define DMACFG_RVAL 0x0
+
+/* DMACFG[ENABLE] - Master DMA controller enable */
+#define DMACFG_ENABLE_BBA (*(volatile unsigned long *) 0x42200080)
+#define DMACFG_ENABLE_MSK (0x1 << 0 )
+#define DMACFG_ENABLE (0x1 << 0 )
+#define DMACFG_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define DMACFG_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAPDBPTR*/
+#define DMAPDBPTR_RVAL 0x0
+
+/* DMAPDBPTR[CTRLBASEPTR] - Pointer to the base address of the primary data structure */
+#define DMAPDBPTR_CTRLBASEPTR_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for DMAADBPTR*/
+#define DMAADBPTR_RVAL 0x100
+
+/* DMAADBPTR[ALTCBPTR] - Pointer to the base address of the alternate data structure */
+#define DMAADBPTR_ALTCBPTR_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for DMASWREQ*/
+#define DMASWREQ_RVAL 0x0
+
+/* DMASWREQ[SINC2] - SINC2 Output Step detection */
+#define DMASWREQ_SINC2_BBA (*(volatile unsigned long *) 0x422002AC)
+#define DMASWREQ_SINC2_MSK (0x1 << 11 )
+#define DMASWREQ_SINC2 (0x1 << 11 )
+#define DMASWREQ_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMASWREQ_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMASWREQ[ADC1] - ADC1 */
+#define DMASWREQ_ADC1_BBA (*(volatile unsigned long *) 0x422002A8)
+#define DMASWREQ_ADC1_MSK (0x1 << 10 )
+#define DMASWREQ_ADC1 (0x1 << 10 )
+#define DMASWREQ_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMASWREQ_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMASWREQ[ADC0] - ADC0 */
+#define DMASWREQ_ADC0_BBA (*(volatile unsigned long *) 0x422002A4)
+#define DMASWREQ_ADC0_MSK (0x1 << 9 )
+#define DMASWREQ_ADC0 (0x1 << 9 )
+#define DMASWREQ_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMASWREQ_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMASWREQ[DAC] - DAC DMA Output */
+#define DMASWREQ_DAC_BBA (*(volatile unsigned long *) 0x422002A0)
+#define DMASWREQ_DAC_MSK (0x1 << 8 )
+#define DMASWREQ_DAC (0x1 << 8 )
+#define DMASWREQ_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMASWREQ_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMASWREQ[I2CMRX] - DMA I2C Master RX */
+#define DMASWREQ_I2CMRX_BBA (*(volatile unsigned long *) 0x4220029C)
+#define DMASWREQ_I2CMRX_MSK (0x1 << 7 )
+#define DMASWREQ_I2CMRX (0x1 << 7 )
+#define DMASWREQ_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMASWREQ_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMASWREQ[I2CMTX] - DMA I2C Master TX */
+#define DMASWREQ_I2CMTX_BBA (*(volatile unsigned long *) 0x42200298)
+#define DMASWREQ_I2CMTX_MSK (0x1 << 6 )
+#define DMASWREQ_I2CMTX (0x1 << 6 )
+#define DMASWREQ_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMASWREQ_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMASWREQ[I2CSRX] - DMA I2C Slave RX */
+#define DMASWREQ_I2CSRX_BBA (*(volatile unsigned long *) 0x42200294)
+#define DMASWREQ_I2CSRX_MSK (0x1 << 5 )
+#define DMASWREQ_I2CSRX (0x1 << 5 )
+#define DMASWREQ_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMASWREQ_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMASWREQ[I2CSTX] - DMA I2C Slave TX */
+#define DMASWREQ_I2CSTX_BBA (*(volatile unsigned long *) 0x42200290)
+#define DMASWREQ_I2CSTX_MSK (0x1 << 4 )
+#define DMASWREQ_I2CSTX (0x1 << 4 )
+#define DMASWREQ_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMASWREQ_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMASWREQ[UARTRX] - DMA UART RX */
+#define DMASWREQ_UARTRX_BBA (*(volatile unsigned long *) 0x4220028C)
+#define DMASWREQ_UARTRX_MSK (0x1 << 3 )
+#define DMASWREQ_UARTRX (0x1 << 3 )
+#define DMASWREQ_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMASWREQ_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMASWREQ[UARTTX] - DMA UART TX */
+#define DMASWREQ_UARTTX_BBA (*(volatile unsigned long *) 0x42200288)
+#define DMASWREQ_UARTTX_MSK (0x1 << 2 )
+#define DMASWREQ_UARTTX (0x1 << 2 )
+#define DMASWREQ_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMASWREQ_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMASWREQ[SPI1RX] - DMA SPI 1 RX */
+#define DMASWREQ_SPI1RX_BBA (*(volatile unsigned long *) 0x42200284)
+#define DMASWREQ_SPI1RX_MSK (0x1 << 1 )
+#define DMASWREQ_SPI1RX (0x1 << 1 )
+#define DMASWREQ_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMASWREQ_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMASWREQ[SPI1TX] - DMA SPI 1 TX */
+#define DMASWREQ_SPI1TX_BBA (*(volatile unsigned long *) 0x42200280)
+#define DMASWREQ_SPI1TX_MSK (0x1 << 0 )
+#define DMASWREQ_SPI1TX (0x1 << 0 )
+#define DMASWREQ_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMASWREQ_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMARMSKSET*/
+#define DMARMSKSET_RVAL 0x0
+
+/* DMARMSKSET[SINC2] - SINC2 Output Step detection */
+#define DMARMSKSET_SINC2_BBA (*(volatile unsigned long *) 0x4220042C)
+#define DMARMSKSET_SINC2_MSK (0x1 << 11 )
+#define DMARMSKSET_SINC2 (0x1 << 11 )
+#define DMARMSKSET_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMARMSKSET_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMARMSKSET[ADC1] - ADC1 */
+#define DMARMSKSET_ADC1_BBA (*(volatile unsigned long *) 0x42200428)
+#define DMARMSKSET_ADC1_MSK (0x1 << 10 )
+#define DMARMSKSET_ADC1 (0x1 << 10 )
+#define DMARMSKSET_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMARMSKSET_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMARMSKSET[ADC0] - ADC0 */
+#define DMARMSKSET_ADC0_BBA (*(volatile unsigned long *) 0x42200424)
+#define DMARMSKSET_ADC0_MSK (0x1 << 9 )
+#define DMARMSKSET_ADC0 (0x1 << 9 )
+#define DMARMSKSET_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMARMSKSET_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMARMSKSET[DAC] - DAC DMA Output */
+#define DMARMSKSET_DAC_BBA (*(volatile unsigned long *) 0x42200420)
+#define DMARMSKSET_DAC_MSK (0x1 << 8 )
+#define DMARMSKSET_DAC (0x1 << 8 )
+#define DMARMSKSET_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMARMSKSET_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMARMSKSET[I2CMRX] - DMA I2C Master RX */
+#define DMARMSKSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220041C)
+#define DMARMSKSET_I2CMRX_MSK (0x1 << 7 )
+#define DMARMSKSET_I2CMRX (0x1 << 7 )
+#define DMARMSKSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMARMSKSET_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMARMSKSET[I2CMTX] - DMA I2C Master TX */
+#define DMARMSKSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200418)
+#define DMARMSKSET_I2CMTX_MSK (0x1 << 6 )
+#define DMARMSKSET_I2CMTX (0x1 << 6 )
+#define DMARMSKSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMARMSKSET_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMARMSKSET[I2CSRX] - DMA I2C Slave RX */
+#define DMARMSKSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200414)
+#define DMARMSKSET_I2CSRX_MSK (0x1 << 5 )
+#define DMARMSKSET_I2CSRX (0x1 << 5 )
+#define DMARMSKSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMARMSKSET_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMARMSKSET[I2CSTX] - DMA I2C Slave TX */
+#define DMARMSKSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200410)
+#define DMARMSKSET_I2CSTX_MSK (0x1 << 4 )
+#define DMARMSKSET_I2CSTX (0x1 << 4 )
+#define DMARMSKSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMARMSKSET_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMARMSKSET[UARTRX] - DMA UART RX */
+#define DMARMSKSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220040C)
+#define DMARMSKSET_UARTRX_MSK (0x1 << 3 )
+#define DMARMSKSET_UARTRX (0x1 << 3 )
+#define DMARMSKSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMARMSKSET_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMARMSKSET[UARTTX] - DMA UART TX */
+#define DMARMSKSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200408)
+#define DMARMSKSET_UARTTX_MSK (0x1 << 2 )
+#define DMARMSKSET_UARTTX (0x1 << 2 )
+#define DMARMSKSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMARMSKSET_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMARMSKSET[SPI1RX] - DMA SPI 1 RX */
+#define DMARMSKSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200404)
+#define DMARMSKSET_SPI1RX_MSK (0x1 << 1 )
+#define DMARMSKSET_SPI1RX (0x1 << 1 )
+#define DMARMSKSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMARMSKSET_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMARMSKSET[SPI1TX] - DMA SPI 1 TX */
+#define DMARMSKSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200400)
+#define DMARMSKSET_SPI1TX_MSK (0x1 << 0 )
+#define DMARMSKSET_SPI1TX (0x1 << 0 )
+#define DMARMSKSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMARMSKSET_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMARMSKCLR*/
+#define DMARMSKCLR_RVAL 0x0
+
+/* DMARMSKCLR[SINC2] - SINC2 Output Step detection */
+#define DMARMSKCLR_SINC2_BBA (*(volatile unsigned long *) 0x422004AC)
+#define DMARMSKCLR_SINC2_MSK (0x1 << 11 )
+#define DMARMSKCLR_SINC2 (0x1 << 11 )
+#define DMARMSKCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMARMSKCLR_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMARMSKCLR[ADC1] - ADC1 */
+#define DMARMSKCLR_ADC1_BBA (*(volatile unsigned long *) 0x422004A8)
+#define DMARMSKCLR_ADC1_MSK (0x1 << 10 )
+#define DMARMSKCLR_ADC1 (0x1 << 10 )
+#define DMARMSKCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMARMSKCLR_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMARMSKCLR[ADC0] - ADC0 */
+#define DMARMSKCLR_ADC0_BBA (*(volatile unsigned long *) 0x422004A4)
+#define DMARMSKCLR_ADC0_MSK (0x1 << 9 )
+#define DMARMSKCLR_ADC0 (0x1 << 9 )
+#define DMARMSKCLR_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMARMSKCLR_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMARMSKCLR[DAC] - DAC DMA Output */
+#define DMARMSKCLR_DAC_BBA (*(volatile unsigned long *) 0x422004A0)
+#define DMARMSKCLR_DAC_MSK (0x1 << 8 )
+#define DMARMSKCLR_DAC (0x1 << 8 )
+#define DMARMSKCLR_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMARMSKCLR_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMARMSKCLR[I2CMRX] - DMA I2C Master RX */
+#define DMARMSKCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220049C)
+#define DMARMSKCLR_I2CMRX_MSK (0x1 << 7 )
+#define DMARMSKCLR_I2CMRX (0x1 << 7 )
+#define DMARMSKCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMARMSKCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMARMSKCLR[I2CMTX] - DMA I2C Master TX */
+#define DMARMSKCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200498)
+#define DMARMSKCLR_I2CMTX_MSK (0x1 << 6 )
+#define DMARMSKCLR_I2CMTX (0x1 << 6 )
+#define DMARMSKCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMARMSKCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMARMSKCLR[I2CSRX] - DMA I2C Slave RX */
+#define DMARMSKCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200494)
+#define DMARMSKCLR_I2CSRX_MSK (0x1 << 5 )
+#define DMARMSKCLR_I2CSRX (0x1 << 5 )
+#define DMARMSKCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMARMSKCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMARMSKCLR[I2CSTX] - DMA I2C Slave TX */
+#define DMARMSKCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200490)
+#define DMARMSKCLR_I2CSTX_MSK (0x1 << 4 )
+#define DMARMSKCLR_I2CSTX (0x1 << 4 )
+#define DMARMSKCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMARMSKCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMARMSKCLR[UARTRX] - DMA UART RX */
+#define DMARMSKCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220048C)
+#define DMARMSKCLR_UARTRX_MSK (0x1 << 3 )
+#define DMARMSKCLR_UARTRX (0x1 << 3 )
+#define DMARMSKCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMARMSKCLR_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMARMSKCLR[UARTTX] - DMA UART TX */
+#define DMARMSKCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200488)
+#define DMARMSKCLR_UARTTX_MSK (0x1 << 2 )
+#define DMARMSKCLR_UARTTX (0x1 << 2 )
+#define DMARMSKCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMARMSKCLR_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMARMSKCLR[SPI1RX] - DMA SPI 1 RX */
+#define DMARMSKCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200484)
+#define DMARMSKCLR_SPI1RX_MSK (0x1 << 1 )
+#define DMARMSKCLR_SPI1RX (0x1 << 1 )
+#define DMARMSKCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMARMSKCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMARMSKCLR[SPI1TX] - DMA SPI 1 TX */
+#define DMARMSKCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200480)
+#define DMARMSKCLR_SPI1TX_MSK (0x1 << 0 )
+#define DMARMSKCLR_SPI1TX (0x1 << 0 )
+#define DMARMSKCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMARMSKCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAENSET*/
+#define DMAENSET_RVAL 0x0
+
+/* DMAENSET[SINC2] - SINC2 Output Step detection */
+#define DMAENSET_SINC2_BBA (*(volatile unsigned long *) 0x4220052C)
+#define DMAENSET_SINC2_MSK (0x1 << 11 )
+#define DMAENSET_SINC2 (0x1 << 11 )
+#define DMAENSET_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMAENSET_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMAENSET[ADC1] - ADC1 */
+#define DMAENSET_ADC1_BBA (*(volatile unsigned long *) 0x42200528)
+#define DMAENSET_ADC1_MSK (0x1 << 10 )
+#define DMAENSET_ADC1 (0x1 << 10 )
+#define DMAENSET_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMAENSET_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMAENSET[ADC0] - ADC0 */
+#define DMAENSET_ADC0_BBA (*(volatile unsigned long *) 0x42200524)
+#define DMAENSET_ADC0_MSK (0x1 << 9 )
+#define DMAENSET_ADC0 (0x1 << 9 )
+#define DMAENSET_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMAENSET_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMAENSET[DAC] - DAC DMA Output */
+#define DMAENSET_DAC_BBA (*(volatile unsigned long *) 0x42200520)
+#define DMAENSET_DAC_MSK (0x1 << 8 )
+#define DMAENSET_DAC (0x1 << 8 )
+#define DMAENSET_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMAENSET_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMAENSET[I2CMRX] - DMA I2C Master RX */
+#define DMAENSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220051C)
+#define DMAENSET_I2CMRX_MSK (0x1 << 7 )
+#define DMAENSET_I2CMRX (0x1 << 7 )
+#define DMAENSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMAENSET_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMAENSET[I2CMTX] - DMA I2C Master TX */
+#define DMAENSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200518)
+#define DMAENSET_I2CMTX_MSK (0x1 << 6 )
+#define DMAENSET_I2CMTX (0x1 << 6 )
+#define DMAENSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMAENSET_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMAENSET[I2CSRX] - DMA I2C Slave RX */
+#define DMAENSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200514)
+#define DMAENSET_I2CSRX_MSK (0x1 << 5 )
+#define DMAENSET_I2CSRX (0x1 << 5 )
+#define DMAENSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMAENSET_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMAENSET[I2CSTX] - DMA I2C Slave TX */
+#define DMAENSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200510)
+#define DMAENSET_I2CSTX_MSK (0x1 << 4 )
+#define DMAENSET_I2CSTX (0x1 << 4 )
+#define DMAENSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMAENSET_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMAENSET[UARTRX] - DMA UART RX */
+#define DMAENSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220050C)
+#define DMAENSET_UARTRX_MSK (0x1 << 3 )
+#define DMAENSET_UARTRX (0x1 << 3 )
+#define DMAENSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMAENSET_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMAENSET[UARTTX] - DMA UART TX */
+#define DMAENSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200508)
+#define DMAENSET_UARTTX_MSK (0x1 << 2 )
+#define DMAENSET_UARTTX (0x1 << 2 )
+#define DMAENSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMAENSET_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMAENSET[SPI1RX] - DMA SPI 1 RX */
+#define DMAENSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200504)
+#define DMAENSET_SPI1RX_MSK (0x1 << 1 )
+#define DMAENSET_SPI1RX (0x1 << 1 )
+#define DMAENSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMAENSET_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMAENSET[SPI1TX] - DMA SPI 1 TX */
+#define DMAENSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200500)
+#define DMAENSET_SPI1TX_MSK (0x1 << 0 )
+#define DMAENSET_SPI1TX (0x1 << 0 )
+#define DMAENSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMAENSET_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAENCLR*/
+#define DMAENCLR_RVAL 0x0
+
+/* DMAENCLR[SINC2] - SINC2 Output Step detection */
+#define DMAENCLR_SINC2_BBA (*(volatile unsigned long *) 0x422005AC)
+#define DMAENCLR_SINC2_MSK (0x1 << 11 )
+#define DMAENCLR_SINC2 (0x1 << 11 )
+#define DMAENCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMAENCLR_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMAENCLR[ADC1] - ADC1 */
+#define DMAENCLR_ADC1_BBA (*(volatile unsigned long *) 0x422005A8)
+#define DMAENCLR_ADC1_MSK (0x1 << 10 )
+#define DMAENCLR_ADC1 (0x1 << 10 )
+#define DMAENCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMAENCLR_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMAENCLR[ADC0] - ADC0 */
+#define DMAENCLR_ADC0_BBA (*(volatile unsigned long *) 0x422005A4)
+#define DMAENCLR_ADC0_MSK (0x1 << 9 )
+#define DMAENCLR_ADC0 (0x1 << 9 )
+#define DMAENCLR_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMAENCLR_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMAENCLR[DAC] - DAC DMA Output */
+#define DMAENCLR_DAC_BBA (*(volatile unsigned long *) 0x422005A0)
+#define DMAENCLR_DAC_MSK (0x1 << 8 )
+#define DMAENCLR_DAC (0x1 << 8 )
+#define DMAENCLR_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMAENCLR_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMAENCLR[I2CMRX] - DMA I2C Master RX */
+#define DMAENCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220059C)
+#define DMAENCLR_I2CMRX_MSK (0x1 << 7 )
+#define DMAENCLR_I2CMRX (0x1 << 7 )
+#define DMAENCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMAENCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMAENCLR[I2CMTX] - DMA I2C Master TX */
+#define DMAENCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200598)
+#define DMAENCLR_I2CMTX_MSK (0x1 << 6 )
+#define DMAENCLR_I2CMTX (0x1 << 6 )
+#define DMAENCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMAENCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMAENCLR[I2CSRX] - DMA I2C Slave RX */
+#define DMAENCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200594)
+#define DMAENCLR_I2CSRX_MSK (0x1 << 5 )
+#define DMAENCLR_I2CSRX (0x1 << 5 )
+#define DMAENCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMAENCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMAENCLR[I2CSTX] - DMA I2C Slave TX */
+#define DMAENCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200590)
+#define DMAENCLR_I2CSTX_MSK (0x1 << 4 )
+#define DMAENCLR_I2CSTX (0x1 << 4 )
+#define DMAENCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMAENCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMAENCLR[UARTRX] - DMA UART RX */
+#define DMAENCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220058C)
+#define DMAENCLR_UARTRX_MSK (0x1 << 3 )
+#define DMAENCLR_UARTRX (0x1 << 3 )
+#define DMAENCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMAENCLR_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMAENCLR[UARTTX] - DMA UART TX */
+#define DMAENCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200588)
+#define DMAENCLR_UARTTX_MSK (0x1 << 2 )
+#define DMAENCLR_UARTTX (0x1 << 2 )
+#define DMAENCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMAENCLR_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMAENCLR[SPI1RX] - DMA SPI 1 RX */
+#define DMAENCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200584)
+#define DMAENCLR_SPI1RX_MSK (0x1 << 1 )
+#define DMAENCLR_SPI1RX (0x1 << 1 )
+#define DMAENCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMAENCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMAENCLR[SPI1TX] - DMA SPI 1 TX */
+#define DMAENCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200580)
+#define DMAENCLR_SPI1TX_MSK (0x1 << 0 )
+#define DMAENCLR_SPI1TX (0x1 << 0 )
+#define DMAENCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMAENCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAALTSET*/
+#define DMAALTSET_RVAL 0x0
+
+/* DMAALTSET[SINC2] - SINC2 Output Step detection */
+#define DMAALTSET_SINC2_BBA (*(volatile unsigned long *) 0x4220062C)
+#define DMAALTSET_SINC2_MSK (0x1 << 11 )
+#define DMAALTSET_SINC2 (0x1 << 11 )
+#define DMAALTSET_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMAALTSET_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMAALTSET[ADC1] - ADC1 */
+#define DMAALTSET_ADC1_BBA (*(volatile unsigned long *) 0x42200628)
+#define DMAALTSET_ADC1_MSK (0x1 << 10 )
+#define DMAALTSET_ADC1 (0x1 << 10 )
+#define DMAALTSET_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMAALTSET_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMAALTSET[ADC0] - ADC0 */
+#define DMAALTSET_ADC0_BBA (*(volatile unsigned long *) 0x42200624)
+#define DMAALTSET_ADC0_MSK (0x1 << 9 )
+#define DMAALTSET_ADC0 (0x1 << 9 )
+#define DMAALTSET_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMAALTSET_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMAALTSET[DAC] - DAC DMA Output */
+#define DMAALTSET_DAC_BBA (*(volatile unsigned long *) 0x42200620)
+#define DMAALTSET_DAC_MSK (0x1 << 8 )
+#define DMAALTSET_DAC (0x1 << 8 )
+#define DMAALTSET_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMAALTSET_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMAALTSET[I2CMRX] - DMA I2C Master RX */
+#define DMAALTSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220061C)
+#define DMAALTSET_I2CMRX_MSK (0x1 << 7 )
+#define DMAALTSET_I2CMRX (0x1 << 7 )
+#define DMAALTSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMAALTSET_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMAALTSET[I2CMTX] - DMA I2C Master TX */
+#define DMAALTSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200618)
+#define DMAALTSET_I2CMTX_MSK (0x1 << 6 )
+#define DMAALTSET_I2CMTX (0x1 << 6 )
+#define DMAALTSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMAALTSET_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMAALTSET[I2CSRX] - DMA I2C Slave RX */
+#define DMAALTSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200614)
+#define DMAALTSET_I2CSRX_MSK (0x1 << 5 )
+#define DMAALTSET_I2CSRX (0x1 << 5 )
+#define DMAALTSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMAALTSET_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMAALTSET[I2CSTX] - DMA I2C Slave TX */
+#define DMAALTSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200610)
+#define DMAALTSET_I2CSTX_MSK (0x1 << 4 )
+#define DMAALTSET_I2CSTX (0x1 << 4 )
+#define DMAALTSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMAALTSET_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMAALTSET[UARTRX] - DMA UART RX */
+#define DMAALTSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220060C)
+#define DMAALTSET_UARTRX_MSK (0x1 << 3 )
+#define DMAALTSET_UARTRX (0x1 << 3 )
+#define DMAALTSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMAALTSET_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMAALTSET[UARTTX] - DMA UART TX */
+#define DMAALTSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200608)
+#define DMAALTSET_UARTTX_MSK (0x1 << 2 )
+#define DMAALTSET_UARTTX (0x1 << 2 )
+#define DMAALTSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMAALTSET_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMAALTSET[SPI1RX] - DMA SPI 1 RX */
+#define DMAALTSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200604)
+#define DMAALTSET_SPI1RX_MSK (0x1 << 1 )
+#define DMAALTSET_SPI1RX (0x1 << 1 )
+#define DMAALTSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMAALTSET_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMAALTSET[SPI1TX] - DMA SPI 1 TX */
+#define DMAALTSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200600)
+#define DMAALTSET_SPI1TX_MSK (0x1 << 0 )
+#define DMAALTSET_SPI1TX (0x1 << 0 )
+#define DMAALTSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMAALTSET_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAALTCLR*/
+#define DMAALTCLR_RVAL 0x0
+
+/* DMAALTCLR[SINC2] - SINC2 Output Step detection */
+#define DMAALTCLR_SINC2_BBA (*(volatile unsigned long *) 0x422006AC)
+#define DMAALTCLR_SINC2_MSK (0x1 << 11 )
+#define DMAALTCLR_SINC2 (0x1 << 11 )
+#define DMAALTCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMAALTCLR_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMAALTCLR[ADC1] - ADC1 */
+#define DMAALTCLR_ADC1_BBA (*(volatile unsigned long *) 0x422006A8)
+#define DMAALTCLR_ADC1_MSK (0x1 << 10 )
+#define DMAALTCLR_ADC1 (0x1 << 10 )
+#define DMAALTCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMAALTCLR_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMAALTCLR[ADC0] - ADC0 */
+#define DMAALTCLR_ADC0_BBA (*(volatile unsigned long *) 0x422006A4)
+#define DMAALTCLR_ADC0_MSK (0x1 << 9 )
+#define DMAALTCLR_ADC0 (0x1 << 9 )
+#define DMAALTCLR_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMAALTCLR_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMAALTCLR[DAC] - DAC DMA Output */
+#define DMAALTCLR_DAC_BBA (*(volatile unsigned long *) 0x422006A0)
+#define DMAALTCLR_DAC_MSK (0x1 << 8 )
+#define DMAALTCLR_DAC (0x1 << 8 )
+#define DMAALTCLR_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMAALTCLR_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMAALTCLR[I2CMRX] - DMA I2C Master RX */
+#define DMAALTCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220069C)
+#define DMAALTCLR_I2CMRX_MSK (0x1 << 7 )
+#define DMAALTCLR_I2CMRX (0x1 << 7 )
+#define DMAALTCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMAALTCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMAALTCLR[I2CMTX] - DMA I2C Master TX */
+#define DMAALTCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200698)
+#define DMAALTCLR_I2CMTX_MSK (0x1 << 6 )
+#define DMAALTCLR_I2CMTX (0x1 << 6 )
+#define DMAALTCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMAALTCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMAALTCLR[I2CSRX] - DMA I2C Slave RX */
+#define DMAALTCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200694)
+#define DMAALTCLR_I2CSRX_MSK (0x1 << 5 )
+#define DMAALTCLR_I2CSRX (0x1 << 5 )
+#define DMAALTCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMAALTCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMAALTCLR[I2CSTX] - DMA I2C Slave TX */
+#define DMAALTCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200690)
+#define DMAALTCLR_I2CSTX_MSK (0x1 << 4 )
+#define DMAALTCLR_I2CSTX (0x1 << 4 )
+#define DMAALTCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMAALTCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMAALTCLR[UARTRX] - DMA UART RX */
+#define DMAALTCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220068C)
+#define DMAALTCLR_UARTRX_MSK (0x1 << 3 )
+#define DMAALTCLR_UARTRX (0x1 << 3 )
+#define DMAALTCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMAALTCLR_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMAALTCLR[UARTTX] - DMA UART TX */
+#define DMAALTCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200688)
+#define DMAALTCLR_UARTTX_MSK (0x1 << 2 )
+#define DMAALTCLR_UARTTX (0x1 << 2 )
+#define DMAALTCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMAALTCLR_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMAALTCLR[SPI1RX] - DMA SPI 1 RX */
+#define DMAALTCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200684)
+#define DMAALTCLR_SPI1RX_MSK (0x1 << 1 )
+#define DMAALTCLR_SPI1RX (0x1 << 1 )
+#define DMAALTCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMAALTCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMAALTCLR[SPI1TX] - DMA SPI 1 TX */
+#define DMAALTCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200680)
+#define DMAALTCLR_SPI1TX_MSK (0x1 << 0 )
+#define DMAALTCLR_SPI1TX (0x1 << 0 )
+#define DMAALTCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMAALTCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAPRISET*/
+#define DMAPRISET_RVAL 0x0
+
+/* DMAPRISET[SINC2] - SINC2 Output Step detection */
+#define DMAPRISET_SINC2_BBA (*(volatile unsigned long *) 0x4220072C)
+#define DMAPRISET_SINC2_MSK (0x1 << 11 )
+#define DMAPRISET_SINC2 (0x1 << 11 )
+#define DMAPRISET_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMAPRISET_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMAPRISET[ADC1] - ADC1 */
+#define DMAPRISET_ADC1_BBA (*(volatile unsigned long *) 0x42200728)
+#define DMAPRISET_ADC1_MSK (0x1 << 10 )
+#define DMAPRISET_ADC1 (0x1 << 10 )
+#define DMAPRISET_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMAPRISET_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMAPRISET[ADC0] - ADC0 */
+#define DMAPRISET_ADC0_BBA (*(volatile unsigned long *) 0x42200724)
+#define DMAPRISET_ADC0_MSK (0x1 << 9 )
+#define DMAPRISET_ADC0 (0x1 << 9 )
+#define DMAPRISET_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMAPRISET_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMAPRISET[DAC] - DAC DMA Output */
+#define DMAPRISET_DAC_BBA (*(volatile unsigned long *) 0x42200720)
+#define DMAPRISET_DAC_MSK (0x1 << 8 )
+#define DMAPRISET_DAC (0x1 << 8 )
+#define DMAPRISET_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMAPRISET_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMAPRISET[I2CMRX] - DMA I2C Master RX */
+#define DMAPRISET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220071C)
+#define DMAPRISET_I2CMRX_MSK (0x1 << 7 )
+#define DMAPRISET_I2CMRX (0x1 << 7 )
+#define DMAPRISET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMAPRISET_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMAPRISET[I2CMTX] - DMA I2C Master TX */
+#define DMAPRISET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200718)
+#define DMAPRISET_I2CMTX_MSK (0x1 << 6 )
+#define DMAPRISET_I2CMTX (0x1 << 6 )
+#define DMAPRISET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMAPRISET_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMAPRISET[I2CSRX] - DMA I2C Slave RX */
+#define DMAPRISET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200714)
+#define DMAPRISET_I2CSRX_MSK (0x1 << 5 )
+#define DMAPRISET_I2CSRX (0x1 << 5 )
+#define DMAPRISET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMAPRISET_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMAPRISET[I2CSTX] - DMA I2C Slave TX */
+#define DMAPRISET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200710)
+#define DMAPRISET_I2CSTX_MSK (0x1 << 4 )
+#define DMAPRISET_I2CSTX (0x1 << 4 )
+#define DMAPRISET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMAPRISET_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMAPRISET[UARTRX] - DMA UART RX */
+#define DMAPRISET_UARTRX_BBA (*(volatile unsigned long *) 0x4220070C)
+#define DMAPRISET_UARTRX_MSK (0x1 << 3 )
+#define DMAPRISET_UARTRX (0x1 << 3 )
+#define DMAPRISET_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMAPRISET_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMAPRISET[UARTTX] - DMA UART TX */
+#define DMAPRISET_UARTTX_BBA (*(volatile unsigned long *) 0x42200708)
+#define DMAPRISET_UARTTX_MSK (0x1 << 2 )
+#define DMAPRISET_UARTTX (0x1 << 2 )
+#define DMAPRISET_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMAPRISET_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMAPRISET[SPI1RX] - DMA SPI 1 RX */
+#define DMAPRISET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200704)
+#define DMAPRISET_SPI1RX_MSK (0x1 << 1 )
+#define DMAPRISET_SPI1RX (0x1 << 1 )
+#define DMAPRISET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMAPRISET_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMAPRISET[SPI1TX] - DMA SPI 1 TX */
+#define DMAPRISET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200700)
+#define DMAPRISET_SPI1TX_MSK (0x1 << 0 )
+#define DMAPRISET_SPI1TX (0x1 << 0 )
+#define DMAPRISET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMAPRISET_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAPRICLR*/
+#define DMAPRICLR_RVAL 0x0
+
+/* DMAPRICLR[SINC2] - SINC2 Output Step detection */
+#define DMAPRICLR_SINC2_BBA (*(volatile unsigned long *) 0x422007AC)
+#define DMAPRICLR_SINC2_MSK (0x1 << 11 )
+#define DMAPRICLR_SINC2 (0x1 << 11 )
+#define DMAPRICLR_SINC2_DIS (0x0 << 11 ) /* DIS */
+#define DMAPRICLR_SINC2_EN (0x1 << 11 ) /* EN */
+
+/* DMAPRICLR[ADC1] - ADC1 */
+#define DMAPRICLR_ADC1_BBA (*(volatile unsigned long *) 0x422007A8)
+#define DMAPRICLR_ADC1_MSK (0x1 << 10 )
+#define DMAPRICLR_ADC1 (0x1 << 10 )
+#define DMAPRICLR_ADC1_DIS (0x0 << 10 ) /* DIS */
+#define DMAPRICLR_ADC1_EN (0x1 << 10 ) /* EN */
+
+/* DMAPRICLR[ADC0] - ADC0 */
+#define DMAPRICLR_ADC0_BBA (*(volatile unsigned long *) 0x422007A4)
+#define DMAPRICLR_ADC0_MSK (0x1 << 9 )
+#define DMAPRICLR_ADC0 (0x1 << 9 )
+#define DMAPRICLR_ADC0_DIS (0x0 << 9 ) /* DIS */
+#define DMAPRICLR_ADC0_EN (0x1 << 9 ) /* EN */
+
+/* DMAPRICLR[DAC] - DAC DMA Output */
+#define DMAPRICLR_DAC_BBA (*(volatile unsigned long *) 0x422007A0)
+#define DMAPRICLR_DAC_MSK (0x1 << 8 )
+#define DMAPRICLR_DAC (0x1 << 8 )
+#define DMAPRICLR_DAC_DIS (0x0 << 8 ) /* DIS */
+#define DMAPRICLR_DAC_EN (0x1 << 8 ) /* EN */
+
+/* DMAPRICLR[I2CMRX] - DMA I2C Master RX */
+#define DMAPRICLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220079C)
+#define DMAPRICLR_I2CMRX_MSK (0x1 << 7 )
+#define DMAPRICLR_I2CMRX (0x1 << 7 )
+#define DMAPRICLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
+#define DMAPRICLR_I2CMRX_EN (0x1 << 7 ) /* EN */
+
+/* DMAPRICLR[I2CMTX] - DMA I2C Master TX */
+#define DMAPRICLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200798)
+#define DMAPRICLR_I2CMTX_MSK (0x1 << 6 )
+#define DMAPRICLR_I2CMTX (0x1 << 6 )
+#define DMAPRICLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
+#define DMAPRICLR_I2CMTX_EN (0x1 << 6 ) /* EN */
+
+/* DMAPRICLR[I2CSRX] - DMA I2C Slave RX */
+#define DMAPRICLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200794)
+#define DMAPRICLR_I2CSRX_MSK (0x1 << 5 )
+#define DMAPRICLR_I2CSRX (0x1 << 5 )
+#define DMAPRICLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
+#define DMAPRICLR_I2CSRX_EN (0x1 << 5 ) /* EN */
+
+/* DMAPRICLR[I2CSTX] - DMA I2C Slave TX */
+#define DMAPRICLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200790)
+#define DMAPRICLR_I2CSTX_MSK (0x1 << 4 )
+#define DMAPRICLR_I2CSTX (0x1 << 4 )
+#define DMAPRICLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
+#define DMAPRICLR_I2CSTX_EN (0x1 << 4 ) /* EN */
+
+/* DMAPRICLR[UARTRX] - DMA UART RX */
+#define DMAPRICLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220078C)
+#define DMAPRICLR_UARTRX_MSK (0x1 << 3 )
+#define DMAPRICLR_UARTRX (0x1 << 3 )
+#define DMAPRICLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
+#define DMAPRICLR_UARTRX_EN (0x1 << 3 ) /* EN */
+
+/* DMAPRICLR[UARTTX] - DMA UART TX */
+#define DMAPRICLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200788)
+#define DMAPRICLR_UARTTX_MSK (0x1 << 2 )
+#define DMAPRICLR_UARTTX (0x1 << 2 )
+#define DMAPRICLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
+#define DMAPRICLR_UARTTX_EN (0x1 << 2 ) /* EN */
+
+/* DMAPRICLR[SPI1RX] - DMA SPI 1 RX */
+#define DMAPRICLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200784)
+#define DMAPRICLR_SPI1RX_MSK (0x1 << 1 )
+#define DMAPRICLR_SPI1RX (0x1 << 1 )
+#define DMAPRICLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
+#define DMAPRICLR_SPI1RX_EN (0x1 << 1 ) /* EN */
+
+/* DMAPRICLR[SPI1TX] - DMA SPI 1 TX */
+#define DMAPRICLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200780)
+#define DMAPRICLR_SPI1TX_MSK (0x1 << 0 )
+#define DMAPRICLR_SPI1TX (0x1 << 0 )
+#define DMAPRICLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
+#define DMAPRICLR_SPI1TX_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAERRCLR*/
+#define DMAERRCLR_RVAL 0x0
+
+/* DMAERRCLR[ERROR] - DMA Error status */
+#define DMAERRCLR_ERROR_BBA (*(volatile unsigned long *) 0x42200980)
+#define DMAERRCLR_ERROR_MSK (0x1 << 0 )
+#define DMAERRCLR_ERROR (0x1 << 0 )
+#define DMAERRCLR_ERROR_DIS (0x0 << 0 ) /* DIS */
+#define DMAERRCLR_ERROR_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for DMAPERID4*/
+#define DMAPERID4_RVAL 0x4
+
+/* DMAPERID4[BLOCKCOUNT] - The number of 4KB address blocks you require, to access the registers, expressed in powers of 2. */
+#define DMAPERID4_BLOCKCOUNT_MSK (0xF << 4 )
+
+/* DMAPERID4[JEP106CCODE] - The JEP106 continuation code value represents how many 0x7F continuation characters occur in the manufacturer?s identity code. */
+#define DMAPERID4_JEP106CCODE_MSK (0xF << 0 )
+
+/* Reset Value for DMAPERID0*/
+#define DMAPERID0_RVAL 0x30
+
+/* DMAPERID0[PARTNO0] - Identifies the peripheral (part_number_0) */
+#define DMAPERID0_PARTNO0_MSK (0xFF << 0 )
+
+/* Reset Value for DMAPERID1*/
+#define DMAPERID1_RVAL 0xB2
+
+/* DMAPERID1[JEP106ID0] - JEP106 identity code [3:0] */
+#define DMAPERID1_JEP106ID0_MSK (0xF << 4 )
+
+/* DMAPERID1[PARTNO1] - Identifies the peripheral (part_number_1) */
+#define DMAPERID1_PARTNO1_MSK (0xF << 0 )
+
+/* Reset Value for DMAPERID2*/
+#define DMAPERID2_RVAL 0xB
+
+/* DMAPERID2[REVISION] - The revision status of the controller. */
+#define DMAPERID2_REVISION_MSK (0xF << 4 )
+
+/* DMAPERID2[JEDECUSED] - This indicates that the controller uses a manufacturer?s identity code that was allocated by JEDEC according to JEP106. */
+#define DMAPERID2_JEDECUSED_BBA (*(volatile unsigned long *) 0x4221FD0C)
+#define DMAPERID2_JEDECUSED_MSK (0x1 << 3 )
+#define DMAPERID2_JEDECUSED (0x1 << 3 )
+#define DMAPERID2_JEDECUSED_DIS (0x0 << 3 ) /* DIS */
+#define DMAPERID2_JEDECUSED_EN (0x1 << 3 ) /* EN */
+
+/* DMAPERID2[JEP106ID1] - JEP106 identity code [6:4]. */
+#define DMAPERID2_JEP106ID1_MSK (0x7 << 0 )
+
+/* Reset Value for DMAPERID3*/
+#define DMAPERID3_RVAL 0x0
+
+/* DMAPERID3[MODNUM] - The customer must update this field if they modify the RTL of the controller. */
+#define DMAPERID3_MODNUM_MSK (0xF << 0 )
+
+/* Reset Value for DMAPCELLID0*/
+#define DMAPCELLID0_RVAL 0xD
+
+/* DMAPCELLID0[PCELLID0] - Primecell Identification */
+#define DMAPCELLID0_PCELLID0_MSK (0xFF << 0 )
+
+/* Reset Value for DMAPCELLID1*/
+#define DMAPCELLID1_RVAL 0xF0
+
+/* DMAPCELLID1[PCELLID1] - Primecell Identification */
+#define DMAPCELLID1_PCELLID1_MSK (0xFF << 0 )
+
+/* Reset Value for DMAPCELLID2*/
+#define DMAPCELLID2_RVAL 0x5
+
+/* DMAPCELLID2[PCELLID2] - Primecell Identification */
+#define DMAPCELLID2_PCELLID2_MSK (0xFF << 0 )
+
+/* Reset Value for DMAPCELLID3*/
+#define DMAPCELLID3_RVAL 0xB1
+
+/* DMAPCELLID3[PCELLID3] - Primecell Identification */
+#define DMAPCELLID3_PCELLID3_MSK (0xFF << 0 )
+// ------------------------------------------------------------------------------------------------
+// ----- NVIC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Nested Vectored Interrupt Controller (pADI_NVIC)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+#else // (__NO_MMR_STRUCTS__==0)
+#define ICTR (*(volatile unsigned long *) 0xE000E004)
+#define STCSR (*(volatile unsigned long *) 0xE000E010)
+#define STRVR (*(volatile unsigned long *) 0xE000E014)
+#define STCVR (*(volatile unsigned long *) 0xE000E018)
+#define STCR (*(volatile unsigned long *) 0xE000E01C)
+#define ISER0 (*(volatile unsigned long *) 0xE000E100)
+#define ISER1 (*(volatile unsigned long *) 0xE000E104)
+#define ICER0 (*(volatile unsigned long *) 0xE000E180)
+#define ICER1 (*(volatile unsigned long *) 0xE000E184)
+#define ISPR0 (*(volatile unsigned long *) 0xE000E200)
+#define ISPR1 (*(volatile unsigned long *) 0xE000E204)
+#define ICPR0 (*(volatile unsigned long *) 0xE000E280)
+#define ICPR1 (*(volatile unsigned long *) 0xE000E284)
+#define IABR0 (*(volatile unsigned long *) 0xE000E300)
+#define IABR1 (*(volatile unsigned long *) 0xE000E304)
+#define IPR0 (*(volatile unsigned long *) 0xE000E400)
+#define IPR1 (*(volatile unsigned long *) 0xE000E404)
+#define IPR2 (*(volatile unsigned long *) 0xE000E408)
+#define IPR3 (*(volatile unsigned long *) 0xE000E40C)
+#define IPR4 (*(volatile unsigned long *) 0xE000E410)
+#define IPR5 (*(volatile unsigned long *) 0xE000E414)
+#define IPR6 (*(volatile unsigned long *) 0xE000E418)
+#define IPR7 (*(volatile unsigned long *) 0xE000E41C)
+#define IPR8 (*(volatile unsigned long *) 0xE000E420)
+#define IPR9 (*(volatile unsigned long *) 0xE000E424)
+#define CPUID (*(volatile unsigned long *) 0xE000ED00)
+#define ICSR (*(volatile unsigned long *) 0xE000ED04)
+#define VTOR (*(volatile unsigned long *) 0xE000ED08)
+#define AIRCR (*(volatile unsigned long *) 0xE000ED0C)
+#define SCR (*(volatile unsigned long *) 0xE000ED10)
+#define CCR (*(volatile unsigned long *) 0xE000ED14)
+#define SHPR1 (*(volatile unsigned long *) 0xE000ED18)
+#define SHPR2 (*(volatile unsigned long *) 0xE000ED1C)
+#define SHPR3 (*(volatile unsigned long *) 0xE000ED20)
+#define SHCSR (*(volatile unsigned long *) 0xE000ED24)
+#define CFSR (*(volatile unsigned long *) 0xE000ED28)
+#define HFSR (*(volatile unsigned long *) 0xE000ED2C)
+#define MMFAR (*(volatile unsigned long *) 0xE000ED34)
+#define BFAR (*(volatile unsigned long *) 0xE000ED38)
+#define STIR (*(volatile unsigned long *) 0xE000EF00)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for ICTR*/
+#define ICTR_RVAL 0x1
+
+/* ICTR[INTLINESNUM] - Total number of interrupt lines in groups of 32 */
+#define ICTR_INTLINESNUM_MSK (0xF << 0 )
+
+/* Reset Value for STCSR*/
+#define STCSR_RVAL 0x0
+
+/* STCSR[COUNTFLAG] - Returns 1 if timer counted to 0 since last time this register was read */
+#define STCSR_COUNTFLAG_MSK (0x1 << 16 )
+#define STCSR_COUNTFLAG (0x1 << 16 )
+#define STCSR_COUNTFLAG_DIS (0x0 << 16 ) /* DIS */
+#define STCSR_COUNTFLAG_EN (0x1 << 16 ) /* EN */
+
+/* STCSR[CLKSOURCE] - clock source used for SysTick */
+#define STCSR_CLKSOURCE_MSK (0x1 << 2 )
+#define STCSR_CLKSOURCE (0x1 << 2 )
+#define STCSR_CLKSOURCE_DIS (0x0 << 2 ) /* DIS */
+#define STCSR_CLKSOURCE_EN (0x1 << 2 ) /* EN */
+
+/* STCSR[TICKINT] - If 1, counting down to 0 will cause the SysTick exception to pended. */
+#define STCSR_TICKINT_MSK (0x1 << 1 )
+#define STCSR_TICKINT (0x1 << 1 )
+#define STCSR_TICKINT_DIS (0x0 << 1 ) /* DIS */
+#define STCSR_TICKINT_EN (0x1 << 1 ) /* EN */
+
+/* STCSR[ENABLE] - Enable bit */
+#define STCSR_ENABLE_MSK (0x1 << 0 )
+#define STCSR_ENABLE (0x1 << 0 )
+#define STCSR_ENABLE_DIS (0x0 << 0 ) /* DIS */
+#define STCSR_ENABLE_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for STRVR*/
+#define STRVR_RVAL 0x0
+
+/* STRVR[RELOAD] - Value to load into the Current Value register when the counter reaches 0 */
+#define STRVR_RELOAD_MSK (0xFFFFFF << 0 )
+
+/* Reset Value for STCVR*/
+#define STCVR_RVAL 0x0
+
+/* STCVR[CURRENT] - Current counter value */
+#define STCVR_CURRENT_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for STCR*/
+#define STCR_RVAL 0x0
+
+/* STCR[NOREF] - If reads as 1, the Reference clock is not provided */
+#define STCR_NOREF_MSK (0x1 << 31 )
+#define STCR_NOREF (0x1 << 31 )
+#define STCR_NOREF_DIS (0x0 << 31 ) /* DIS */
+#define STCR_NOREF_EN (0x1 << 31 ) /* EN */
+
+/* STCR[SKEW] - If reads as 1, the calibration value for 10ms is inexact */
+#define STCR_SKEW_MSK (0x1 << 30 )
+#define STCR_SKEW (0x1 << 30 )
+#define STCR_SKEW_DIS (0x0 << 30 ) /* DIS */
+#define STCR_SKEW_EN (0x1 << 30 ) /* EN */
+
+/* STCR[TENMS] - An optional Reload value to be used for 10ms (100Hz) timing */
+#define STCR_TENMS_MSK (0xFFFFFF << 0 )
+
+/* Reset Value for ISER0*/
+#define ISER0_RVAL 0x0
+
+/* ISER0[DMADAC] - */
+#define ISER0_DMADAC_MSK (0x1 << 31 )
+#define ISER0_DMADAC (0x1 << 31 )
+#define ISER0_DMADAC_DIS (0x0 << 31 ) /* DIS */
+#define ISER0_DMADAC_EN (0x1 << 31 ) /* EN */
+
+/* ISER0[DMAI2CMRX] - */
+#define ISER0_DMAI2CMRX_MSK (0x1 << 30 )
+#define ISER0_DMAI2CMRX (0x1 << 30 )
+#define ISER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
+#define ISER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
+
+/* ISER0[DMAI2CMTX] - */
+#define ISER0_DMAI2CMTX_MSK (0x1 << 29 )
+#define ISER0_DMAI2CMTX (0x1 << 29 )
+#define ISER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
+#define ISER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
+
+/* ISER0[DMAI2CSRX] - */
+#define ISER0_DMAI2CSRX_MSK (0x1 << 28 )
+#define ISER0_DMAI2CSRX (0x1 << 28 )
+#define ISER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
+#define ISER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
+
+/* ISER0[DMAI2CSTX] - */
+#define ISER0_DMAI2CSTX_MSK (0x1 << 27 )
+#define ISER0_DMAI2CSTX (0x1 << 27 )
+#define ISER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
+#define ISER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
+
+/* ISER0[DMAUARTRX] - */
+#define ISER0_DMAUARTRX_MSK (0x1 << 26 )
+#define ISER0_DMAUARTRX (0x1 << 26 )
+#define ISER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
+#define ISER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
+
+/* ISER0[DMAUARTTX] - */
+#define ISER0_DMAUARTTX_MSK (0x1 << 25 )
+#define ISER0_DMAUARTTX (0x1 << 25 )
+#define ISER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
+#define ISER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
+
+/* ISER0[DMASPI1RX] - */
+#define ISER0_DMASPI1RX_MSK (0x1 << 24 )
+#define ISER0_DMASPI1RX (0x1 << 24 )
+#define ISER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
+#define ISER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
+
+/* ISER0[DMASPI1TX] - */
+#define ISER0_DMASPI1TX_MSK (0x1 << 23 )
+#define ISER0_DMASPI1TX (0x1 << 23 )
+#define ISER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
+#define ISER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
+
+/* ISER0[DMAERROR] - */
+#define ISER0_DMAERROR_MSK (0x1 << 22 )
+#define ISER0_DMAERROR (0x1 << 22 )
+#define ISER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
+#define ISER0_DMAERROR_EN (0x1 << 22 ) /* EN */
+
+/* ISER0[I2CM] - */
+#define ISER0_I2CM_MSK (0x1 << 21 )
+#define ISER0_I2CM (0x1 << 21 )
+#define ISER0_I2CM_DIS (0x0 << 21 ) /* DIS */
+#define ISER0_I2CM_EN (0x1 << 21 ) /* EN */
+
+/* ISER0[I2CS] - */
+#define ISER0_I2CS_MSK (0x1 << 20 )
+#define ISER0_I2CS (0x1 << 20 )
+#define ISER0_I2CS_DIS (0x0 << 20 ) /* DIS */
+#define ISER0_I2CS_EN (0x1 << 20 ) /* EN */
+
+/* ISER0[SPI1] - */
+#define ISER0_SPI1_MSK (0x1 << 19 )
+#define ISER0_SPI1 (0x1 << 19 )
+#define ISER0_SPI1_DIS (0x0 << 19 ) /* DIS */
+#define ISER0_SPI1_EN (0x1 << 19 ) /* EN */
+
+/* ISER0[SPI0] - */
+#define ISER0_SPI0_MSK (0x1 << 18 )
+#define ISER0_SPI0 (0x1 << 18 )
+#define ISER0_SPI0_DIS (0x0 << 18 ) /* DIS */
+#define ISER0_SPI0_EN (0x1 << 18 ) /* EN */
+
+/* ISER0[UART] - */
+#define ISER0_UART_MSK (0x1 << 17 )
+#define ISER0_UART (0x1 << 17 )
+#define ISER0_UART_DIS (0x0 << 17 ) /* DIS */
+#define ISER0_UART_EN (0x1 << 17 ) /* EN */
+
+/* ISER0[FEE] - */
+#define ISER0_FEE_MSK (0x1 << 16 )
+#define ISER0_FEE (0x1 << 16 )
+#define ISER0_FEE_DIS (0x0 << 16 ) /* DIS */
+#define ISER0_FEE_EN (0x1 << 16 ) /* EN */
+
+/* ISER0[SINC2] - */
+#define ISER0_SINC2_MSK (0x1 << 15 )
+#define ISER0_SINC2 (0x1 << 15 )
+#define ISER0_SINC2_DIS (0x0 << 15 ) /* DIS */
+#define ISER0_SINC2_EN (0x1 << 15 ) /* EN */
+
+/* ISER0[ADC1] - */
+#define ISER0_ADC1_MSK (0x1 << 14 )
+#define ISER0_ADC1 (0x1 << 14 )
+#define ISER0_ADC1_DIS (0x0 << 14 ) /* DIS */
+#define ISER0_ADC1_EN (0x1 << 14 ) /* EN */
+
+/* ISER0[ADC0] - */
+#define ISER0_ADC0_MSK (0x1 << 13 )
+#define ISER0_ADC0 (0x1 << 13 )
+#define ISER0_ADC0_DIS (0x0 << 13 ) /* DIS */
+#define ISER0_ADC0_EN (0x1 << 13 ) /* EN */
+
+/* ISER0[T1] - */
+#define ISER0_T1_MSK (0x1 << 12 )
+#define ISER0_T1 (0x1 << 12 )
+#define ISER0_T1_DIS (0x0 << 12 ) /* DIS */
+#define ISER0_T1_EN (0x1 << 12 ) /* EN */
+
+/* ISER0[T0] - */
+#define ISER0_T0_MSK (0x1 << 11 )
+#define ISER0_T0 (0x1 << 11 )
+#define ISER0_T0_DIS (0x0 << 11 ) /* DIS */
+#define ISER0_T0_EN (0x1 << 11 ) /* EN */
+
+/* ISER0[T3] - */
+#define ISER0_T3_MSK (0x1 << 9 )
+#define ISER0_T3 (0x1 << 9 )
+#define ISER0_T3_DIS (0x0 << 9 ) /* DIS */
+#define ISER0_T3_EN (0x1 << 9 ) /* EN */
+
+/* ISER0[EXTINT7] - */
+#define ISER0_EXTINT7_MSK (0x1 << 8 )
+#define ISER0_EXTINT7 (0x1 << 8 )
+#define ISER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
+#define ISER0_EXTINT7_EN (0x1 << 8 ) /* EN */
+
+/* ISER0[EXTINT6] - */
+#define ISER0_EXTINT6_MSK (0x1 << 7 )
+#define ISER0_EXTINT6 (0x1 << 7 )
+#define ISER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
+#define ISER0_EXTINT6_EN (0x1 << 7 ) /* EN */
+
+/* ISER0[EXTINT5] - */
+#define ISER0_EXTINT5_MSK (0x1 << 6 )
+#define ISER0_EXTINT5 (0x1 << 6 )
+#define ISER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
+#define ISER0_EXTINT5_EN (0x1 << 6 ) /* EN */
+
+/* ISER0[EXTINT4] - */
+#define ISER0_EXTINT4_MSK (0x1 << 5 )
+#define ISER0_EXTINT4 (0x1 << 5 )
+#define ISER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
+#define ISER0_EXTINT4_EN (0x1 << 5 ) /* EN */
+
+/* ISER0[EXTINT3] - */
+#define ISER0_EXTINT3_MSK (0x1 << 4 )
+#define ISER0_EXTINT3 (0x1 << 4 )
+#define ISER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
+#define ISER0_EXTINT3_EN (0x1 << 4 ) /* EN */
+
+/* ISER0[EXTINT2] - */
+#define ISER0_EXTINT2_MSK (0x1 << 3 )
+#define ISER0_EXTINT2 (0x1 << 3 )
+#define ISER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
+#define ISER0_EXTINT2_EN (0x1 << 3 ) /* EN */
+
+/* ISER0[EXTINT1] - */
+#define ISER0_EXTINT1_MSK (0x1 << 2 )
+#define ISER0_EXTINT1 (0x1 << 2 )
+#define ISER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
+#define ISER0_EXTINT1_EN (0x1 << 2 ) /* EN */
+
+/* ISER0[EXTINT0] - */
+#define ISER0_EXTINT0_MSK (0x1 << 1 )
+#define ISER0_EXTINT0 (0x1 << 1 )
+#define ISER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
+#define ISER0_EXTINT0_EN (0x1 << 1 ) /* EN */
+
+/* ISER0[T2] - */
+#define ISER0_T2_MSK (0x1 << 0 )
+#define ISER0_T2 (0x1 << 0 )
+#define ISER0_T2_DIS (0x0 << 0 ) /* DIS */
+#define ISER0_T2_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ISER1*/
+#define ISER1_RVAL 0x0
+
+/* ISER1[PWM2] - */
+#define ISER1_PWM2_MSK (0x1 << 6 )
+#define ISER1_PWM2 (0x1 << 6 )
+#define ISER1_PWM2_DIS (0x0 << 6 ) /* DIS */
+#define ISER1_PWM2_EN (0x1 << 6 ) /* EN */
+
+/* ISER1[PWM1] - */
+#define ISER1_PWM1_MSK (0x1 << 5 )
+#define ISER1_PWM1 (0x1 << 5 )
+#define ISER1_PWM1_DIS (0x0 << 5 ) /* DIS */
+#define ISER1_PWM1_EN (0x1 << 5 ) /* EN */
+
+/* ISER1[PWM0] - */
+#define ISER1_PWM0_MSK (0x1 << 4 )
+#define ISER1_PWM0 (0x1 << 4 )
+#define ISER1_PWM0_DIS (0x0 << 4 ) /* DIS */
+#define ISER1_PWM0_EN (0x1 << 4 ) /* EN */
+
+/* ISER1[PWMTRIP] - */
+#define ISER1_PWMTRIP_MSK (0x1 << 3 )
+#define ISER1_PWMTRIP (0x1 << 3 )
+#define ISER1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
+#define ISER1_PWMTRIP_EN (0x1 << 3 ) /* EN */
+
+/* ISER1[DMASINC2] - */
+#define ISER1_DMASINC2_MSK (0x1 << 2 )
+#define ISER1_DMASINC2 (0x1 << 2 )
+#define ISER1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
+#define ISER1_DMASINC2_EN (0x1 << 2 ) /* EN */
+
+/* ISER1[DMAADC1] - */
+#define ISER1_DMAADC1_MSK (0x1 << 1 )
+#define ISER1_DMAADC1 (0x1 << 1 )
+#define ISER1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
+#define ISER1_DMAADC1_EN (0x1 << 1 ) /* EN */
+
+/* ISER1[DMAADC0] - */
+#define ISER1_DMAADC0_MSK (0x1 << 0 )
+#define ISER1_DMAADC0 (0x1 << 0 )
+#define ISER1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
+#define ISER1_DMAADC0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ICER0*/
+#define ICER0_RVAL 0x0
+
+/* ICER0[DMADAC] - */
+#define ICER0_DMADAC_MSK (0x1 << 31 )
+#define ICER0_DMADAC (0x1 << 31 )
+#define ICER0_DMADAC_DIS (0x0 << 31 ) /* DIS */
+#define ICER0_DMADAC_EN (0x1 << 31 ) /* EN */
+
+/* ICER0[DMAI2CMRX] - */
+#define ICER0_DMAI2CMRX_MSK (0x1 << 30 )
+#define ICER0_DMAI2CMRX (0x1 << 30 )
+#define ICER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
+#define ICER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
+
+/* ICER0[DMAI2CMTX] - */
+#define ICER0_DMAI2CMTX_MSK (0x1 << 29 )
+#define ICER0_DMAI2CMTX (0x1 << 29 )
+#define ICER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
+#define ICER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
+
+/* ICER0[DMAI2CSRX] - */
+#define ICER0_DMAI2CSRX_MSK (0x1 << 28 )
+#define ICER0_DMAI2CSRX (0x1 << 28 )
+#define ICER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
+#define ICER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
+
+/* ICER0[DMAI2CSTX] - */
+#define ICER0_DMAI2CSTX_MSK (0x1 << 27 )
+#define ICER0_DMAI2CSTX (0x1 << 27 )
+#define ICER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
+#define ICER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
+
+/* ICER0[DMAUARTRX] - */
+#define ICER0_DMAUARTRX_MSK (0x1 << 26 )
+#define ICER0_DMAUARTRX (0x1 << 26 )
+#define ICER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
+#define ICER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
+
+/* ICER0[DMAUARTTX] - */
+#define ICER0_DMAUARTTX_MSK (0x1 << 25 )
+#define ICER0_DMAUARTTX (0x1 << 25 )
+#define ICER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
+#define ICER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
+
+/* ICER0[DMASPI1RX] - */
+#define ICER0_DMASPI1RX_MSK (0x1 << 24 )
+#define ICER0_DMASPI1RX (0x1 << 24 )
+#define ICER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
+#define ICER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
+
+/* ICER0[DMASPI1TX] - */
+#define ICER0_DMASPI1TX_MSK (0x1 << 23 )
+#define ICER0_DMASPI1TX (0x1 << 23 )
+#define ICER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
+#define ICER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
+
+/* ICER0[DMAERROR] - */
+#define ICER0_DMAERROR_MSK (0x1 << 22 )
+#define ICER0_DMAERROR (0x1 << 22 )
+#define ICER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
+#define ICER0_DMAERROR_EN (0x1 << 22 ) /* EN */
+
+/* ICER0[I2CM] - */
+#define ICER0_I2CM_MSK (0x1 << 21 )
+#define ICER0_I2CM (0x1 << 21 )
+#define ICER0_I2CM_DIS (0x0 << 21 ) /* DIS */
+#define ICER0_I2CM_EN (0x1 << 21 ) /* EN */
+
+/* ICER0[I2CS] - */
+#define ICER0_I2CS_MSK (0x1 << 20 )
+#define ICER0_I2CS (0x1 << 20 )
+#define ICER0_I2CS_DIS (0x0 << 20 ) /* DIS */
+#define ICER0_I2CS_EN (0x1 << 20 ) /* EN */
+
+/* ICER0[SPI1] - */
+#define ICER0_SPI1_MSK (0x1 << 19 )
+#define ICER0_SPI1 (0x1 << 19 )
+#define ICER0_SPI1_DIS (0x0 << 19 ) /* DIS */
+#define ICER0_SPI1_EN (0x1 << 19 ) /* EN */
+
+/* ICER0[SPI0] - */
+#define ICER0_SPI0_MSK (0x1 << 18 )
+#define ICER0_SPI0 (0x1 << 18 )
+#define ICER0_SPI0_DIS (0x0 << 18 ) /* DIS */
+#define ICER0_SPI0_EN (0x1 << 18 ) /* EN */
+
+/* ICER0[UART] - */
+#define ICER0_UART_MSK (0x1 << 17 )
+#define ICER0_UART (0x1 << 17 )
+#define ICER0_UART_DIS (0x0 << 17 ) /* DIS */
+#define ICER0_UART_EN (0x1 << 17 ) /* EN */
+
+/* ICER0[FEE] - */
+#define ICER0_FEE_MSK (0x1 << 16 )
+#define ICER0_FEE (0x1 << 16 )
+#define ICER0_FEE_DIS (0x0 << 16 ) /* DIS */
+#define ICER0_FEE_EN (0x1 << 16 ) /* EN */
+
+/* ICER0[SINC2] - */
+#define ICER0_SINC2_MSK (0x1 << 15 )
+#define ICER0_SINC2 (0x1 << 15 )
+#define ICER0_SINC2_DIS (0x0 << 15 ) /* DIS */
+#define ICER0_SINC2_EN (0x1 << 15 ) /* EN */
+
+/* ICER0[ADC1] - */
+#define ICER0_ADC1_MSK (0x1 << 14 )
+#define ICER0_ADC1 (0x1 << 14 )
+#define ICER0_ADC1_DIS (0x0 << 14 ) /* DIS */
+#define ICER0_ADC1_EN (0x1 << 14 ) /* EN */
+
+/* ICER0[ADC0] - */
+#define ICER0_ADC0_MSK (0x1 << 13 )
+#define ICER0_ADC0 (0x1 << 13 )
+#define ICER0_ADC0_DIS (0x0 << 13 ) /* DIS */
+#define ICER0_ADC0_EN (0x1 << 13 ) /* EN */
+
+/* ICER0[T1] - */
+#define ICER0_T1_MSK (0x1 << 12 )
+#define ICER0_T1 (0x1 << 12 )
+#define ICER0_T1_DIS (0x0 << 12 ) /* DIS */
+#define ICER0_T1_EN (0x1 << 12 ) /* EN */
+
+/* ICER0[T0] - */
+#define ICER0_T0_MSK (0x1 << 11 )
+#define ICER0_T0 (0x1 << 11 )
+#define ICER0_T0_DIS (0x0 << 11 ) /* DIS */
+#define ICER0_T0_EN (0x1 << 11 ) /* EN */
+
+/* ICER0[T3] - */
+#define ICER0_T3_MSK (0x1 << 9 )
+#define ICER0_T3 (0x1 << 9 )
+#define ICER0_T3_DIS (0x0 << 9 ) /* DIS */
+#define ICER0_T3_EN (0x1 << 9 ) /* EN */
+
+/* ICER0[EXTINT7] - */
+#define ICER0_EXTINT7_MSK (0x1 << 8 )
+#define ICER0_EXTINT7 (0x1 << 8 )
+#define ICER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
+#define ICER0_EXTINT7_EN (0x1 << 8 ) /* EN */
+
+/* ICER0[EXTINT6] - */
+#define ICER0_EXTINT6_MSK (0x1 << 7 )
+#define ICER0_EXTINT6 (0x1 << 7 )
+#define ICER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
+#define ICER0_EXTINT6_EN (0x1 << 7 ) /* EN */
+
+/* ICER0[EXTINT5] - */
+#define ICER0_EXTINT5_MSK (0x1 << 6 )
+#define ICER0_EXTINT5 (0x1 << 6 )
+#define ICER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
+#define ICER0_EXTINT5_EN (0x1 << 6 ) /* EN */
+
+/* ICER0[EXTINT4] - */
+#define ICER0_EXTINT4_MSK (0x1 << 5 )
+#define ICER0_EXTINT4 (0x1 << 5 )
+#define ICER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
+#define ICER0_EXTINT4_EN (0x1 << 5 ) /* EN */
+
+/* ICER0[EXTINT3] - */
+#define ICER0_EXTINT3_MSK (0x1 << 4 )
+#define ICER0_EXTINT3 (0x1 << 4 )
+#define ICER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
+#define ICER0_EXTINT3_EN (0x1 << 4 ) /* EN */
+
+/* ICER0[EXTINT2] - */
+#define ICER0_EXTINT2_MSK (0x1 << 3 )
+#define ICER0_EXTINT2 (0x1 << 3 )
+#define ICER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
+#define ICER0_EXTINT2_EN (0x1 << 3 ) /* EN */
+
+/* ICER0[EXTINT1] - */
+#define ICER0_EXTINT1_MSK (0x1 << 2 )
+#define ICER0_EXTINT1 (0x1 << 2 )
+#define ICER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
+#define ICER0_EXTINT1_EN (0x1 << 2 ) /* EN */
+
+/* ICER0[EXTINT0] - */
+#define ICER0_EXTINT0_MSK (0x1 << 1 )
+#define ICER0_EXTINT0 (0x1 << 1 )
+#define ICER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
+#define ICER0_EXTINT0_EN (0x1 << 1 ) /* EN */
+
+/* ICER0[T2] - */
+#define ICER0_T2_MSK (0x1 << 0 )
+#define ICER0_T2 (0x1 << 0 )
+#define ICER0_T2_DIS (0x0 << 0 ) /* DIS */
+#define ICER0_T2_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ICER1*/
+#define ICER1_RVAL 0x0
+
+/* ICER1[PWM2] - */
+#define ICER1_PWM2_MSK (0x1 << 6 )
+#define ICER1_PWM2 (0x1 << 6 )
+#define ICER1_PWM2_DIS (0x0 << 6 ) /* DIS */
+#define ICER1_PWM2_EN (0x1 << 6 ) /* EN */
+
+/* ICER1[PWM1] - */
+#define ICER1_PWM1_MSK (0x1 << 5 )
+#define ICER1_PWM1 (0x1 << 5 )
+#define ICER1_PWM1_DIS (0x0 << 5 ) /* DIS */
+#define ICER1_PWM1_EN (0x1 << 5 ) /* EN */
+
+/* ICER1[PWM0] - */
+#define ICER1_PWM0_MSK (0x1 << 4 )
+#define ICER1_PWM0 (0x1 << 4 )
+#define ICER1_PWM0_DIS (0x0 << 4 ) /* DIS */
+#define ICER1_PWM0_EN (0x1 << 4 ) /* EN */
+
+/* ICER1[PWMTRIP] - */
+#define ICER1_PWMTRIP_MSK (0x1 << 3 )
+#define ICER1_PWMTRIP (0x1 << 3 )
+#define ICER1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
+#define ICER1_PWMTRIP_EN (0x1 << 3 ) /* EN */
+
+/* ICER1[DMASINC2] - */
+#define ICER1_DMASINC2_MSK (0x1 << 2 )
+#define ICER1_DMASINC2 (0x1 << 2 )
+#define ICER1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
+#define ICER1_DMASINC2_EN (0x1 << 2 ) /* EN */
+
+/* ICER1[DMAADC1] - */
+#define ICER1_DMAADC1_MSK (0x1 << 1 )
+#define ICER1_DMAADC1 (0x1 << 1 )
+#define ICER1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
+#define ICER1_DMAADC1_EN (0x1 << 1 ) /* EN */
+
+/* ICER1[DMAADC0] - */
+#define ICER1_DMAADC0_MSK (0x1 << 0 )
+#define ICER1_DMAADC0 (0x1 << 0 )
+#define ICER1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
+#define ICER1_DMAADC0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ISPR0*/
+#define ISPR0_RVAL 0x0
+
+/* ISPR0[DMADAC] - */
+#define ISPR0_DMADAC_MSK (0x1 << 31 )
+#define ISPR0_DMADAC (0x1 << 31 )
+#define ISPR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
+#define ISPR0_DMADAC_EN (0x1 << 31 ) /* EN */
+
+/* ISPR0[DMAI2CMRX] - */
+#define ISPR0_DMAI2CMRX_MSK (0x1 << 30 )
+#define ISPR0_DMAI2CMRX (0x1 << 30 )
+#define ISPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
+#define ISPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
+
+/* ISPR0[DMAI2CMTX] - */
+#define ISPR0_DMAI2CMTX_MSK (0x1 << 29 )
+#define ISPR0_DMAI2CMTX (0x1 << 29 )
+#define ISPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
+#define ISPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
+
+/* ISPR0[DMAI2CSRX] - */
+#define ISPR0_DMAI2CSRX_MSK (0x1 << 28 )
+#define ISPR0_DMAI2CSRX (0x1 << 28 )
+#define ISPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
+#define ISPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
+
+/* ISPR0[DMAI2CSTX] - */
+#define ISPR0_DMAI2CSTX_MSK (0x1 << 27 )
+#define ISPR0_DMAI2CSTX (0x1 << 27 )
+#define ISPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
+#define ISPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
+
+/* ISPR0[DMAUARTRX] - */
+#define ISPR0_DMAUARTRX_MSK (0x1 << 26 )
+#define ISPR0_DMAUARTRX (0x1 << 26 )
+#define ISPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
+#define ISPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
+
+/* ISPR0[DMAUARTTX] - */
+#define ISPR0_DMAUARTTX_MSK (0x1 << 25 )
+#define ISPR0_DMAUARTTX (0x1 << 25 )
+#define ISPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
+#define ISPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
+
+/* ISPR0[DMASPI1RX] - */
+#define ISPR0_DMASPI1RX_MSK (0x1 << 24 )
+#define ISPR0_DMASPI1RX (0x1 << 24 )
+#define ISPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
+#define ISPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
+
+/* ISPR0[DMASPI1TX] - */
+#define ISPR0_DMASPI1TX_MSK (0x1 << 23 )
+#define ISPR0_DMASPI1TX (0x1 << 23 )
+#define ISPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
+#define ISPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
+
+/* ISPR0[DMAERROR] - */
+#define ISPR0_DMAERROR_MSK (0x1 << 22 )
+#define ISPR0_DMAERROR (0x1 << 22 )
+#define ISPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
+#define ISPR0_DMAERROR_EN (0x1 << 22 ) /* EN */
+
+/* ISPR0[I2CM] - */
+#define ISPR0_I2CM_MSK (0x1 << 21 )
+#define ISPR0_I2CM (0x1 << 21 )
+#define ISPR0_I2CM_DIS (0x0 << 21 ) /* DIS */
+#define ISPR0_I2CM_EN (0x1 << 21 ) /* EN */
+
+/* ISPR0[I2CS] - */
+#define ISPR0_I2CS_MSK (0x1 << 20 )
+#define ISPR0_I2CS (0x1 << 20 )
+#define ISPR0_I2CS_DIS (0x0 << 20 ) /* DIS */
+#define ISPR0_I2CS_EN (0x1 << 20 ) /* EN */
+
+/* ISPR0[SPI1] - */
+#define ISPR0_SPI1_MSK (0x1 << 19 )
+#define ISPR0_SPI1 (0x1 << 19 )
+#define ISPR0_SPI1_DIS (0x0 << 19 ) /* DIS */
+#define ISPR0_SPI1_EN (0x1 << 19 ) /* EN */
+
+/* ISPR0[SPI0] - */
+#define ISPR0_SPI0_MSK (0x1 << 18 )
+#define ISPR0_SPI0 (0x1 << 18 )
+#define ISPR0_SPI0_DIS (0x0 << 18 ) /* DIS */
+#define ISPR0_SPI0_EN (0x1 << 18 ) /* EN */
+
+/* ISPR0[UART] - */
+#define ISPR0_UART_MSK (0x1 << 17 )
+#define ISPR0_UART (0x1 << 17 )
+#define ISPR0_UART_DIS (0x0 << 17 ) /* DIS */
+#define ISPR0_UART_EN (0x1 << 17 ) /* EN */
+
+/* ISPR0[FEE] - */
+#define ISPR0_FEE_MSK (0x1 << 16 )
+#define ISPR0_FEE (0x1 << 16 )
+#define ISPR0_FEE_DIS (0x0 << 16 ) /* DIS */
+#define ISPR0_FEE_EN (0x1 << 16 ) /* EN */
+
+/* ISPR0[SINC2] - */
+#define ISPR0_SINC2_MSK (0x1 << 15 )
+#define ISPR0_SINC2 (0x1 << 15 )
+#define ISPR0_SINC2_DIS (0x0 << 15 ) /* DIS */
+#define ISPR0_SINC2_EN (0x1 << 15 ) /* EN */
+
+/* ISPR0[ADC1] - */
+#define ISPR0_ADC1_MSK (0x1 << 14 )
+#define ISPR0_ADC1 (0x1 << 14 )
+#define ISPR0_ADC1_DIS (0x0 << 14 ) /* DIS */
+#define ISPR0_ADC1_EN (0x1 << 14 ) /* EN */
+
+/* ISPR0[ADC0] - */
+#define ISPR0_ADC0_MSK (0x1 << 13 )
+#define ISPR0_ADC0 (0x1 << 13 )
+#define ISPR0_ADC0_DIS (0x0 << 13 ) /* DIS */
+#define ISPR0_ADC0_EN (0x1 << 13 ) /* EN */
+
+/* ISPR0[T1] - */
+#define ISPR0_T1_MSK (0x1 << 12 )
+#define ISPR0_T1 (0x1 << 12 )
+#define ISPR0_T1_DIS (0x0 << 12 ) /* DIS */
+#define ISPR0_T1_EN (0x1 << 12 ) /* EN */
+
+/* ISPR0[T0] - */
+#define ISPR0_T0_MSK (0x1 << 11 )
+#define ISPR0_T0 (0x1 << 11 )
+#define ISPR0_T0_DIS (0x0 << 11 ) /* DIS */
+#define ISPR0_T0_EN (0x1 << 11 ) /* EN */
+
+/* ISPR0[T3] - */
+#define ISPR0_T3_MSK (0x1 << 9 )
+#define ISPR0_T3 (0x1 << 9 )
+#define ISPR0_T3_DIS (0x0 << 9 ) /* DIS */
+#define ISPR0_T3_EN (0x1 << 9 ) /* EN */
+
+/* ISPR0[EXTINT7] - */
+#define ISPR0_EXTINT7_MSK (0x1 << 8 )
+#define ISPR0_EXTINT7 (0x1 << 8 )
+#define ISPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
+#define ISPR0_EXTINT7_EN (0x1 << 8 ) /* EN */
+
+/* ISPR0[EXTINT6] - */
+#define ISPR0_EXTINT6_MSK (0x1 << 7 )
+#define ISPR0_EXTINT6 (0x1 << 7 )
+#define ISPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
+#define ISPR0_EXTINT6_EN (0x1 << 7 ) /* EN */
+
+/* ISPR0[EXTINT5] - */
+#define ISPR0_EXTINT5_MSK (0x1 << 6 )
+#define ISPR0_EXTINT5 (0x1 << 6 )
+#define ISPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
+#define ISPR0_EXTINT5_EN (0x1 << 6 ) /* EN */
+
+/* ISPR0[EXTINT4] - */
+#define ISPR0_EXTINT4_MSK (0x1 << 5 )
+#define ISPR0_EXTINT4 (0x1 << 5 )
+#define ISPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
+#define ISPR0_EXTINT4_EN (0x1 << 5 ) /* EN */
+
+/* ISPR0[EXTINT3] - */
+#define ISPR0_EXTINT3_MSK (0x1 << 4 )
+#define ISPR0_EXTINT3 (0x1 << 4 )
+#define ISPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
+#define ISPR0_EXTINT3_EN (0x1 << 4 ) /* EN */
+
+/* ISPR0[EXTINT2] - */
+#define ISPR0_EXTINT2_MSK (0x1 << 3 )
+#define ISPR0_EXTINT2 (0x1 << 3 )
+#define ISPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
+#define ISPR0_EXTINT2_EN (0x1 << 3 ) /* EN */
+
+/* ISPR0[EXTINT1] - */
+#define ISPR0_EXTINT1_MSK (0x1 << 2 )
+#define ISPR0_EXTINT1 (0x1 << 2 )
+#define ISPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
+#define ISPR0_EXTINT1_EN (0x1 << 2 ) /* EN */
+
+/* ISPR0[EXTINT0] - */
+#define ISPR0_EXTINT0_MSK (0x1 << 1 )
+#define ISPR0_EXTINT0 (0x1 << 1 )
+#define ISPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
+#define ISPR0_EXTINT0_EN (0x1 << 1 ) /* EN */
+
+/* ISPR0[T2] - */
+#define ISPR0_T2_MSK (0x1 << 0 )
+#define ISPR0_T2 (0x1 << 0 )
+#define ISPR0_T2_DIS (0x0 << 0 ) /* DIS */
+#define ISPR0_T2_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ISPR1*/
+#define ISPR1_RVAL 0x0
+
+/* ISPR1[PWM2] - */
+#define ISPR1_PWM2_MSK (0x1 << 6 )
+#define ISPR1_PWM2 (0x1 << 6 )
+#define ISPR1_PWM2_DIS (0x0 << 6 ) /* DIS */
+#define ISPR1_PWM2_EN (0x1 << 6 ) /* EN */
+
+/* ISPR1[PWM1] - */
+#define ISPR1_PWM1_MSK (0x1 << 5 )
+#define ISPR1_PWM1 (0x1 << 5 )
+#define ISPR1_PWM1_DIS (0x0 << 5 ) /* DIS */
+#define ISPR1_PWM1_EN (0x1 << 5 ) /* EN */
+
+/* ISPR1[PWM0] - */
+#define ISPR1_PWM0_MSK (0x1 << 4 )
+#define ISPR1_PWM0 (0x1 << 4 )
+#define ISPR1_PWM0_DIS (0x0 << 4 ) /* DIS */
+#define ISPR1_PWM0_EN (0x1 << 4 ) /* EN */
+
+/* ISPR1[PWMTRIP] - */
+#define ISPR1_PWMTRIP_MSK (0x1 << 3 )
+#define ISPR1_PWMTRIP (0x1 << 3 )
+#define ISPR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
+#define ISPR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
+
+/* ISPR1[DMASINC2] - */
+#define ISPR1_DMASINC2_MSK (0x1 << 2 )
+#define ISPR1_DMASINC2 (0x1 << 2 )
+#define ISPR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
+#define ISPR1_DMASINC2_EN (0x1 << 2 ) /* EN */
+
+/* ISPR1[DMAADC1] - */
+#define ISPR1_DMAADC1_MSK (0x1 << 1 )
+#define ISPR1_DMAADC1 (0x1 << 1 )
+#define ISPR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
+#define ISPR1_DMAADC1_EN (0x1 << 1 ) /* EN */
+
+/* ISPR1[DMAADC0] - */
+#define ISPR1_DMAADC0_MSK (0x1 << 0 )
+#define ISPR1_DMAADC0 (0x1 << 0 )
+#define ISPR1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
+#define ISPR1_DMAADC0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ICPR0*/
+#define ICPR0_RVAL 0x0
+
+/* ICPR0[DMADAC] - */
+#define ICPR0_DMADAC_MSK (0x1 << 31 )
+#define ICPR0_DMADAC (0x1 << 31 )
+#define ICPR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
+#define ICPR0_DMADAC_EN (0x1 << 31 ) /* EN */
+
+/* ICPR0[DMAI2CMRX] - */
+#define ICPR0_DMAI2CMRX_MSK (0x1 << 30 )
+#define ICPR0_DMAI2CMRX (0x1 << 30 )
+#define ICPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
+#define ICPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
+
+/* ICPR0[DMAI2CMTX] - */
+#define ICPR0_DMAI2CMTX_MSK (0x1 << 29 )
+#define ICPR0_DMAI2CMTX (0x1 << 29 )
+#define ICPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
+#define ICPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
+
+/* ICPR0[DMAI2CSRX] - */
+#define ICPR0_DMAI2CSRX_MSK (0x1 << 28 )
+#define ICPR0_DMAI2CSRX (0x1 << 28 )
+#define ICPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
+#define ICPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
+
+/* ICPR0[DMAI2CSTX] - */
+#define ICPR0_DMAI2CSTX_MSK (0x1 << 27 )
+#define ICPR0_DMAI2CSTX (0x1 << 27 )
+#define ICPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
+#define ICPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
+
+/* ICPR0[DMAUARTRX] - */
+#define ICPR0_DMAUARTRX_MSK (0x1 << 26 )
+#define ICPR0_DMAUARTRX (0x1 << 26 )
+#define ICPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
+#define ICPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
+
+/* ICPR0[DMAUARTTX] - */
+#define ICPR0_DMAUARTTX_MSK (0x1 << 25 )
+#define ICPR0_DMAUARTTX (0x1 << 25 )
+#define ICPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
+#define ICPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
+
+/* ICPR0[DMASPI1RX] - */
+#define ICPR0_DMASPI1RX_MSK (0x1 << 24 )
+#define ICPR0_DMASPI1RX (0x1 << 24 )
+#define ICPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
+#define ICPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
+
+/* ICPR0[DMASPI1TX] - */
+#define ICPR0_DMASPI1TX_MSK (0x1 << 23 )
+#define ICPR0_DMASPI1TX (0x1 << 23 )
+#define ICPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
+#define ICPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
+
+/* ICPR0[DMAERROR] - */
+#define ICPR0_DMAERROR_MSK (0x1 << 22 )
+#define ICPR0_DMAERROR (0x1 << 22 )
+#define ICPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
+#define ICPR0_DMAERROR_EN (0x1 << 22 ) /* EN */
+
+/* ICPR0[I2CM] - */
+#define ICPR0_I2CM_MSK (0x1 << 21 )
+#define ICPR0_I2CM (0x1 << 21 )
+#define ICPR0_I2CM_DIS (0x0 << 21 ) /* DIS */
+#define ICPR0_I2CM_EN (0x1 << 21 ) /* EN */
+
+/* ICPR0[I2CS] - */
+#define ICPR0_I2CS_MSK (0x1 << 20 )
+#define ICPR0_I2CS (0x1 << 20 )
+#define ICPR0_I2CS_DIS (0x0 << 20 ) /* DIS */
+#define ICPR0_I2CS_EN (0x1 << 20 ) /* EN */
+
+/* ICPR0[SPI1] - */
+#define ICPR0_SPI1_MSK (0x1 << 19 )
+#define ICPR0_SPI1 (0x1 << 19 )
+#define ICPR0_SPI1_DIS (0x0 << 19 ) /* DIS */
+#define ICPR0_SPI1_EN (0x1 << 19 ) /* EN */
+
+/* ICPR0[SPI0] - */
+#define ICPR0_SPI0_MSK (0x1 << 18 )
+#define ICPR0_SPI0 (0x1 << 18 )
+#define ICPR0_SPI0_DIS (0x0 << 18 ) /* DIS */
+#define ICPR0_SPI0_EN (0x1 << 18 ) /* EN */
+
+/* ICPR0[UART] - */
+#define ICPR0_UART_MSK (0x1 << 17 )
+#define ICPR0_UART (0x1 << 17 )
+#define ICPR0_UART_DIS (0x0 << 17 ) /* DIS */
+#define ICPR0_UART_EN (0x1 << 17 ) /* EN */
+
+/* ICPR0[FEE] - */
+#define ICPR0_FEE_MSK (0x1 << 16 )
+#define ICPR0_FEE (0x1 << 16 )
+#define ICPR0_FEE_DIS (0x0 << 16 ) /* DIS */
+#define ICPR0_FEE_EN (0x1 << 16 ) /* EN */
+
+/* ICPR0[SINC2] - */
+#define ICPR0_SINC2_MSK (0x1 << 15 )
+#define ICPR0_SINC2 (0x1 << 15 )
+#define ICPR0_SINC2_DIS (0x0 << 15 ) /* DIS */
+#define ICPR0_SINC2_EN (0x1 << 15 ) /* EN */
+
+/* ICPR0[ADC1] - */
+#define ICPR0_ADC1_MSK (0x1 << 14 )
+#define ICPR0_ADC1 (0x1 << 14 )
+#define ICPR0_ADC1_DIS (0x0 << 14 ) /* DIS */
+#define ICPR0_ADC1_EN (0x1 << 14 ) /* EN */
+
+/* ICPR0[ADC0] - */
+#define ICPR0_ADC0_MSK (0x1 << 13 )
+#define ICPR0_ADC0 (0x1 << 13 )
+#define ICPR0_ADC0_DIS (0x0 << 13 ) /* DIS */
+#define ICPR0_ADC0_EN (0x1 << 13 ) /* EN */
+
+/* ICPR0[T1] - */
+#define ICPR0_T1_MSK (0x1 << 12 )
+#define ICPR0_T1 (0x1 << 12 )
+#define ICPR0_T1_DIS (0x0 << 12 ) /* DIS */
+#define ICPR0_T1_EN (0x1 << 12 ) /* EN */
+
+/* ICPR0[T0] - */
+#define ICPR0_T0_MSK (0x1 << 11 )
+#define ICPR0_T0 (0x1 << 11 )
+#define ICPR0_T0_DIS (0x0 << 11 ) /* DIS */
+#define ICPR0_T0_EN (0x1 << 11 ) /* EN */
+
+/* ICPR0[T3] - */
+#define ICPR0_T3_MSK (0x1 << 9 )
+#define ICPR0_T3 (0x1 << 9 )
+#define ICPR0_T3_DIS (0x0 << 9 ) /* DIS */
+#define ICPR0_T3_EN (0x1 << 9 ) /* EN */
+
+/* ICPR0[EXTINT7] - */
+#define ICPR0_EXTINT7_MSK (0x1 << 8 )
+#define ICPR0_EXTINT7 (0x1 << 8 )
+#define ICPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
+#define ICPR0_EXTINT7_EN (0x1 << 8 ) /* EN */
+
+/* ICPR0[EXTINT6] - */
+#define ICPR0_EXTINT6_MSK (0x1 << 7 )
+#define ICPR0_EXTINT6 (0x1 << 7 )
+#define ICPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
+#define ICPR0_EXTINT6_EN (0x1 << 7 ) /* EN */
+
+/* ICPR0[EXTINT5] - */
+#define ICPR0_EXTINT5_MSK (0x1 << 6 )
+#define ICPR0_EXTINT5 (0x1 << 6 )
+#define ICPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
+#define ICPR0_EXTINT5_EN (0x1 << 6 ) /* EN */
+
+/* ICPR0[EXTINT4] - */
+#define ICPR0_EXTINT4_MSK (0x1 << 5 )
+#define ICPR0_EXTINT4 (0x1 << 5 )
+#define ICPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
+#define ICPR0_EXTINT4_EN (0x1 << 5 ) /* EN */
+
+/* ICPR0[EXTINT3] - */
+#define ICPR0_EXTINT3_MSK (0x1 << 4 )
+#define ICPR0_EXTINT3 (0x1 << 4 )
+#define ICPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
+#define ICPR0_EXTINT3_EN (0x1 << 4 ) /* EN */
+
+/* ICPR0[EXTINT2] - */
+#define ICPR0_EXTINT2_MSK (0x1 << 3 )
+#define ICPR0_EXTINT2 (0x1 << 3 )
+#define ICPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
+#define ICPR0_EXTINT2_EN (0x1 << 3 ) /* EN */
+
+/* ICPR0[EXTINT1] - */
+#define ICPR0_EXTINT1_MSK (0x1 << 2 )
+#define ICPR0_EXTINT1 (0x1 << 2 )
+#define ICPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
+#define ICPR0_EXTINT1_EN (0x1 << 2 ) /* EN */
+
+/* ICPR0[EXTINT0] - */
+#define ICPR0_EXTINT0_MSK (0x1 << 1 )
+#define ICPR0_EXTINT0 (0x1 << 1 )
+#define ICPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
+#define ICPR0_EXTINT0_EN (0x1 << 1 ) /* EN */
+
+/* ICPR0[T2] - */
+#define ICPR0_T2_MSK (0x1 << 0 )
+#define ICPR0_T2 (0x1 << 0 )
+#define ICPR0_T2_DIS (0x0 << 0 ) /* DIS */
+#define ICPR0_T2_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ICPR1*/
+#define ICPR1_RVAL 0x0
+
+/* ICPR1[PWM2] - */
+#define ICPR1_PWM2_MSK (0x1 << 6 )
+#define ICPR1_PWM2 (0x1 << 6 )
+#define ICPR1_PWM2_DIS (0x0 << 6 ) /* DIS */
+#define ICPR1_PWM2_EN (0x1 << 6 ) /* EN */
+
+/* ICPR1[PWM1] - */
+#define ICPR1_PWM1_MSK (0x1 << 5 )
+#define ICPR1_PWM1 (0x1 << 5 )
+#define ICPR1_PWM1_DIS (0x0 << 5 ) /* DIS */
+#define ICPR1_PWM1_EN (0x1 << 5 ) /* EN */
+
+/* ICPR1[PWM0] - */
+#define ICPR1_PWM0_MSK (0x1 << 4 )
+#define ICPR1_PWM0 (0x1 << 4 )
+#define ICPR1_PWM0_DIS (0x0 << 4 ) /* DIS */
+#define ICPR1_PWM0_EN (0x1 << 4 ) /* EN */
+
+/* ICPR1[PWMTRIP] - */
+#define ICPR1_PWMTRIP_MSK (0x1 << 3 )
+#define ICPR1_PWMTRIP (0x1 << 3 )
+#define ICPR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
+#define ICPR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
+
+/* ICPR1[DMASINC2] - */
+#define ICPR1_DMASINC2_MSK (0x1 << 2 )
+#define ICPR1_DMASINC2 (0x1 << 2 )
+#define ICPR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
+#define ICPR1_DMASINC2_EN (0x1 << 2 ) /* EN */
+
+/* ICPR1[DMAADC1] - */
+#define ICPR1_DMAADC1_MSK (0x1 << 1 )
+#define ICPR1_DMAADC1 (0x1 << 1 )
+#define ICPR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
+#define ICPR1_DMAADC1_EN (0x1 << 1 ) /* EN */
+
+/* ICPR1[DMAADC0] - */
+#define ICPR1_DMAADC0_MSK (0x1 << 0 )
+#define ICPR1_DMAADC0 (0x1 << 0 )
+#define ICPR1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
+#define ICPR1_DMAADC0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for IABR0*/
+#define IABR0_RVAL 0x0
+
+/* IABR0[DMADAC] - */
+#define IABR0_DMADAC_MSK (0x1 << 31 )
+#define IABR0_DMADAC (0x1 << 31 )
+#define IABR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
+#define IABR0_DMADAC_EN (0x1 << 31 ) /* EN */
+
+/* IABR0[DMAI2CMRX] - */
+#define IABR0_DMAI2CMRX_MSK (0x1 << 30 )
+#define IABR0_DMAI2CMRX (0x1 << 30 )
+#define IABR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
+#define IABR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
+
+/* IABR0[DMAI2CMTX] - */
+#define IABR0_DMAI2CMTX_MSK (0x1 << 29 )
+#define IABR0_DMAI2CMTX (0x1 << 29 )
+#define IABR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
+#define IABR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
+
+/* IABR0[DMAI2CSRX] - */
+#define IABR0_DMAI2CSRX_MSK (0x1 << 28 )
+#define IABR0_DMAI2CSRX (0x1 << 28 )
+#define IABR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
+#define IABR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
+
+/* IABR0[DMAI2CSTX] - */
+#define IABR0_DMAI2CSTX_MSK (0x1 << 27 )
+#define IABR0_DMAI2CSTX (0x1 << 27 )
+#define IABR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
+#define IABR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
+
+/* IABR0[DMAUARTRX] - */
+#define IABR0_DMAUARTRX_MSK (0x1 << 26 )
+#define IABR0_DMAUARTRX (0x1 << 26 )
+#define IABR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
+#define IABR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
+
+/* IABR0[DMAUARTTX] - */
+#define IABR0_DMAUARTTX_MSK (0x1 << 25 )
+#define IABR0_DMAUARTTX (0x1 << 25 )
+#define IABR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
+#define IABR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
+
+/* IABR0[DMASPI1RX] - */
+#define IABR0_DMASPI1RX_MSK (0x1 << 24 )
+#define IABR0_DMASPI1RX (0x1 << 24 )
+#define IABR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
+#define IABR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
+
+/* IABR0[DMASPI1TX] - */
+#define IABR0_DMASPI1TX_MSK (0x1 << 23 )
+#define IABR0_DMASPI1TX (0x1 << 23 )
+#define IABR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
+#define IABR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
+
+/* IABR0[DMAERROR] - */
+#define IABR0_DMAERROR_MSK (0x1 << 22 )
+#define IABR0_DMAERROR (0x1 << 22 )
+#define IABR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
+#define IABR0_DMAERROR_EN (0x1 << 22 ) /* EN */
+
+/* IABR0[I2CM] - */
+#define IABR0_I2CM_MSK (0x1 << 21 )
+#define IABR0_I2CM (0x1 << 21 )
+#define IABR0_I2CM_DIS (0x0 << 21 ) /* DIS */
+#define IABR0_I2CM_EN (0x1 << 21 ) /* EN */
+
+/* IABR0[I2CS] - */
+#define IABR0_I2CS_MSK (0x1 << 20 )
+#define IABR0_I2CS (0x1 << 20 )
+#define IABR0_I2CS_DIS (0x0 << 20 ) /* DIS */
+#define IABR0_I2CS_EN (0x1 << 20 ) /* EN */
+
+/* IABR0[SPI1] - */
+#define IABR0_SPI1_MSK (0x1 << 19 )
+#define IABR0_SPI1 (0x1 << 19 )
+#define IABR0_SPI1_DIS (0x0 << 19 ) /* DIS */
+#define IABR0_SPI1_EN (0x1 << 19 ) /* EN */
+
+/* IABR0[SPI0] - */
+#define IABR0_SPI0_MSK (0x1 << 18 )
+#define IABR0_SPI0 (0x1 << 18 )
+#define IABR0_SPI0_DIS (0x0 << 18 ) /* DIS */
+#define IABR0_SPI0_EN (0x1 << 18 ) /* EN */
+
+/* IABR0[UART] - */
+#define IABR0_UART_MSK (0x1 << 17 )
+#define IABR0_UART (0x1 << 17 )
+#define IABR0_UART_DIS (0x0 << 17 ) /* DIS */
+#define IABR0_UART_EN (0x1 << 17 ) /* EN */
+
+/* IABR0[FEE] - */
+#define IABR0_FEE_MSK (0x1 << 16 )
+#define IABR0_FEE (0x1 << 16 )
+#define IABR0_FEE_DIS (0x0 << 16 ) /* DIS */
+#define IABR0_FEE_EN (0x1 << 16 ) /* EN */
+
+/* IABR0[SINC2] - */
+#define IABR0_SINC2_MSK (0x1 << 15 )
+#define IABR0_SINC2 (0x1 << 15 )
+#define IABR0_SINC2_DIS (0x0 << 15 ) /* DIS */
+#define IABR0_SINC2_EN (0x1 << 15 ) /* EN */
+
+/* IABR0[ADC1] - */
+#define IABR0_ADC1_MSK (0x1 << 14 )
+#define IABR0_ADC1 (0x1 << 14 )
+#define IABR0_ADC1_DIS (0x0 << 14 ) /* DIS */
+#define IABR0_ADC1_EN (0x1 << 14 ) /* EN */
+
+/* IABR0[ADC0] - */
+#define IABR0_ADC0_MSK (0x1 << 13 )
+#define IABR0_ADC0 (0x1 << 13 )
+#define IABR0_ADC0_DIS (0x0 << 13 ) /* DIS */
+#define IABR0_ADC0_EN (0x1 << 13 ) /* EN */
+
+/* IABR0[T1] - */
+#define IABR0_T1_MSK (0x1 << 12 )
+#define IABR0_T1 (0x1 << 12 )
+#define IABR0_T1_DIS (0x0 << 12 ) /* DIS */
+#define IABR0_T1_EN (0x1 << 12 ) /* EN */
+
+/* IABR0[T0] - */
+#define IABR0_T0_MSK (0x1 << 11 )
+#define IABR0_T0 (0x1 << 11 )
+#define IABR0_T0_DIS (0x0 << 11 ) /* DIS */
+#define IABR0_T0_EN (0x1 << 11 ) /* EN */
+
+/* IABR0[T3] - */
+#define IABR0_T3_MSK (0x1 << 9 )
+#define IABR0_T3 (0x1 << 9 )
+#define IABR0_T3_DIS (0x0 << 9 ) /* DIS */
+#define IABR0_T3_EN (0x1 << 9 ) /* EN */
+
+/* IABR0[EXTINT7] - */
+#define IABR0_EXTINT7_MSK (0x1 << 8 )
+#define IABR0_EXTINT7 (0x1 << 8 )
+#define IABR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
+#define IABR0_EXTINT7_EN (0x1 << 8 ) /* EN */
+
+/* IABR0[EXTINT6] - */
+#define IABR0_EXTINT6_MSK (0x1 << 7 )
+#define IABR0_EXTINT6 (0x1 << 7 )
+#define IABR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
+#define IABR0_EXTINT6_EN (0x1 << 7 ) /* EN */
+
+/* IABR0[EXTINT5] - */
+#define IABR0_EXTINT5_MSK (0x1 << 6 )
+#define IABR0_EXTINT5 (0x1 << 6 )
+#define IABR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
+#define IABR0_EXTINT5_EN (0x1 << 6 ) /* EN */
+
+/* IABR0[EXTINT4] - */
+#define IABR0_EXTINT4_MSK (0x1 << 5 )
+#define IABR0_EXTINT4 (0x1 << 5 )
+#define IABR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
+#define IABR0_EXTINT4_EN (0x1 << 5 ) /* EN */
+
+/* IABR0[EXTINT3] - */
+#define IABR0_EXTINT3_MSK (0x1 << 4 )
+#define IABR0_EXTINT3 (0x1 << 4 )
+#define IABR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
+#define IABR0_EXTINT3_EN (0x1 << 4 ) /* EN */
+
+/* IABR0[EXTINT2] - */
+#define IABR0_EXTINT2_MSK (0x1 << 3 )
+#define IABR0_EXTINT2 (0x1 << 3 )
+#define IABR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
+#define IABR0_EXTINT2_EN (0x1 << 3 ) /* EN */
+
+/* IABR0[EXTINT1] - */
+#define IABR0_EXTINT1_MSK (0x1 << 2 )
+#define IABR0_EXTINT1 (0x1 << 2 )
+#define IABR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
+#define IABR0_EXTINT1_EN (0x1 << 2 ) /* EN */
+
+/* IABR0[EXTINT0] - */
+#define IABR0_EXTINT0_MSK (0x1 << 1 )
+#define IABR0_EXTINT0 (0x1 << 1 )
+#define IABR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
+#define IABR0_EXTINT0_EN (0x1 << 1 ) /* EN */
+
+/* IABR0[T2] - */
+#define IABR0_T2_MSK (0x1 << 0 )
+#define IABR0_T2 (0x1 << 0 )
+#define IABR0_T2_DIS (0x0 << 0 ) /* DIS */
+#define IABR0_T2_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for IABR1*/
+#define IABR1_RVAL 0x0
+
+/* IABR1[PWM2] - */
+#define IABR1_PWM2_MSK (0x1 << 6 )
+#define IABR1_PWM2 (0x1 << 6 )
+#define IABR1_PWM2_DIS (0x0 << 6 ) /* DIS */
+#define IABR1_PWM2_EN (0x1 << 6 ) /* EN */
+
+/* IABR1[PWM1] - */
+#define IABR1_PWM1_MSK (0x1 << 5 )
+#define IABR1_PWM1 (0x1 << 5 )
+#define IABR1_PWM1_DIS (0x0 << 5 ) /* DIS */
+#define IABR1_PWM1_EN (0x1 << 5 ) /* EN */
+
+/* IABR1[PWM0] - */
+#define IABR1_PWM0_MSK (0x1 << 4 )
+#define IABR1_PWM0 (0x1 << 4 )
+#define IABR1_PWM0_DIS (0x0 << 4 ) /* DIS */
+#define IABR1_PWM0_EN (0x1 << 4 ) /* EN */
+
+/* IABR1[PWMTRIP] - */
+#define IABR1_PWMTRIP_MSK (0x1 << 3 )
+#define IABR1_PWMTRIP (0x1 << 3 )
+#define IABR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
+#define IABR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
+
+/* IABR1[DMASINC2] - */
+#define IABR1_DMASINC2_MSK (0x1 << 2 )
+#define IABR1_DMASINC2 (0x1 << 2 )
+#define IABR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
+#define IABR1_DMASINC2_EN (0x1 << 2 ) /* EN */
+
+/* IABR1[DMAADC1] - */
+#define IABR1_DMAADC1_MSK (0x1 << 1 )
+#define IABR1_DMAADC1 (0x1 << 1 )
+#define IABR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
+#define IABR1_DMAADC1_EN (0x1 << 1 ) /* EN */
+
+/* IABR1[DMAADC0] - */
+#define IABR1_DMAADC0_MSK (0x1 << 0 )
+#define IABR1_DMAADC0 (0x1 << 0 )
+#define IABR1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
+#define IABR1_DMAADC0_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for IPR0*/
+#define IPR0_RVAL 0x0
+
+/* IPR0[EXTINT2] - */
+#define IPR0_EXTINT2_MSK (0xFF << 24 )
+
+/* IPR0[EXTINT1] - */
+#define IPR0_EXTINT1_MSK (0xFF << 16 )
+
+/* IPR0[EXTINT0] - Priority of interrupt number 1 */
+#define IPR0_EXTINT0_MSK (0xFF << 8 )
+
+/* IPR0[T2] - Priority of interrupt number 0 */
+#define IPR0_T2_MSK (0xFF << 0 )
+
+/* Reset Value for IPR1*/
+#define IPR1_RVAL 0x0
+
+/* IPR1[EXTINT6] - */
+#define IPR1_EXTINT6_MSK (0xFF << 24 )
+
+/* IPR1[EXTINT5] - */
+#define IPR1_EXTINT5_MSK (0xFF << 16 )
+
+/* IPR1[EXTINT4] - */
+#define IPR1_EXTINT4_MSK (0xFF << 8 )
+
+/* IPR1[EXTINT3] - */
+#define IPR1_EXTINT3_MSK (0xFF << 0 )
+
+/* Reset Value for IPR2*/
+#define IPR2_RVAL 0x0
+
+/* IPR2[T0] - */
+#define IPR2_T0_MSK (0xFF << 24 )
+
+/* IPR2[T3] - */
+#define IPR2_T3_MSK (0xFF << 8 )
+
+/* IPR2[EXTINT7] - */
+#define IPR2_EXTINT7_MSK (0xFF << 0 )
+
+/* Reset Value for IPR3*/
+#define IPR3_RVAL 0x0
+
+/* IPR3[SINC2] - */
+#define IPR3_SINC2_MSK (0xFF << 24 )
+
+/* IPR3[ADC1] - */
+#define IPR3_ADC1_MSK (0xFF << 16 )
+
+/* IPR3[ADC0] - */
+#define IPR3_ADC0_MSK (0xFF << 8 )
+
+/* IPR3[T1] - */
+#define IPR3_T1_MSK (0xFF << 0 )
+
+/* Reset Value for IPR4*/
+#define IPR4_RVAL 0x0
+
+/* IPR4[SPI1] - */
+#define IPR4_SPI1_MSK (0xFF << 24 )
+
+/* IPR4[SPI0] - */
+#define IPR4_SPI0_MSK (0xFF << 16 )
+
+/* IPR4[UART] - */
+#define IPR4_UART_MSK (0xFF << 8 )
+
+/* IPR4[FEE] - */
+#define IPR4_FEE_MSK (0xFF << 0 )
+
+/* Reset Value for IPR5*/
+#define IPR5_RVAL 0x0
+
+/* IPR5[DMASPI1TX] - */
+#define IPR5_DMASPI1TX_MSK (0xFF << 24 )
+
+/* IPR5[DMAERROR] - */
+#define IPR5_DMAERROR_MSK (0xFF << 16 )
+
+/* IPR5[I2CM] - */
+#define IPR5_I2CM_MSK (0xFF << 8 )
+
+/* IPR5[I2CS] - */
+#define IPR5_I2CS_MSK (0xFF << 0 )
+
+/* Reset Value for IPR6*/
+#define IPR6_RVAL 0x0
+
+/* IPR6[DMAI2CSTX] - */
+#define IPR6_DMAI2CSTX_MSK (0xFF << 24 )
+
+/* IPR6[DMAUARTRX] - */
+#define IPR6_DMAUARTRX_MSK (0xFF << 16 )
+
+/* IPR6[DMAUARTTX] - */
+#define IPR6_DMAUARTTX_MSK (0xFF << 8 )
+
+/* IPR6[DMASPI1RX] - */
+#define IPR6_DMASPI1RX_MSK (0xFF << 0 )
+
+/* Reset Value for IPR7*/
+#define IPR7_RVAL 0x0
+
+/* IPR7[DMADAC] - */
+#define IPR7_DMADAC_MSK (0xFF << 24 )
+
+/* IPR7[DMAI2CMRX] - */
+#define IPR7_DMAI2CMRX_MSK (0xFF << 16 )
+
+/* IPR7[DMAI2CMTX] - */
+#define IPR7_DMAI2CMTX_MSK (0xFF << 8 )
+
+/* IPR7[DMAI2CSRX] - */
+#define IPR7_DMAI2CSRX_MSK (0xFF << 0 )
+
+/* Reset Value for IPR8*/
+#define IPR8_RVAL 0x0
+
+/* IPR8[PWMTRIP] - */
+#define IPR8_PWMTRIP_MSK (0xFF << 24 )
+
+/* IPR8[DMASINC2] - */
+#define IPR8_DMASINC2_MSK (0xFF << 16 )
+
+/* IPR8[DMAADC1] - */
+#define IPR8_DMAADC1_MSK (0xFF << 8 )
+
+/* IPR8[DMAADC0] - */
+#define IPR8_DMAADC0_MSK (0xFF << 0 )
+
+/* Reset Value for IPR9*/
+#define IPR9_RVAL 0x0
+
+/* IPR9[PWM2] - */
+#define IPR9_PWM2_MSK (0xFF << 16 )
+
+/* IPR9[PWM1] - */
+#define IPR9_PWM1_MSK (0xFF << 8 )
+
+/* IPR9[PWM0] - */
+#define IPR9_PWM0_MSK (0xFF << 0 )
+
+/* Reset Value for CPUID*/
+#define CPUID_RVAL 0x412FC230
+
+/* CPUID[IMPLEMENTER] - Indicates implementor */
+#define CPUID_IMPLEMENTER_MSK (0xFF << 24 )
+
+/* CPUID[VARIANT] - Indicates processor revision */
+#define CPUID_VARIANT_MSK (0xF << 20 )
+
+/* CPUID[PARTNO] - Indicates part number */
+#define CPUID_PARTNO_MSK (0xFFF << 4 )
+
+/* CPUID[REVISION] - Indicates patch release */
+#define CPUID_REVISION_MSK (0xF << 0 )
+
+/* Reset Value for ICSR*/
+#define ICSR_RVAL 0x0
+
+/* ICSR[NMIPENDSET] - Setting this bit will activate an NMI */
+#define ICSR_NMIPENDSET_MSK (0x1 << 31 )
+#define ICSR_NMIPENDSET (0x1 << 31 )
+#define ICSR_NMIPENDSET_DIS (0x0 << 31 ) /* DIS */
+#define ICSR_NMIPENDSET_EN (0x1 << 31 ) /* EN */
+
+/* ICSR[PENDSVSET] - Set a pending PendSV interrupt */
+#define ICSR_PENDSVSET_MSK (0x1 << 28 )
+#define ICSR_PENDSVSET (0x1 << 28 )
+#define ICSR_PENDSVSET_DIS (0x0 << 28 ) /* DIS */
+#define ICSR_PENDSVSET_EN (0x1 << 28 ) /* EN */
+
+/* ICSR[PENDSVCLR] - Clear a pending PendSV interrupt */
+#define ICSR_PENDSVCLR_MSK (0x1 << 27 )
+#define ICSR_PENDSVCLR (0x1 << 27 )
+#define ICSR_PENDSVCLR_DIS (0x0 << 27 ) /* DIS */
+#define ICSR_PENDSVCLR_EN (0x1 << 27 ) /* EN */
+
+/* ICSR[PENDSTSET] - Set a pending SysTick. Reads back with current state */
+#define ICSR_PENDSTSET_MSK (0x1 << 26 )
+#define ICSR_PENDSTSET (0x1 << 26 )
+#define ICSR_PENDSTSET_DIS (0x0 << 26 ) /* DIS */
+#define ICSR_PENDSTSET_EN (0x1 << 26 ) /* EN */
+
+/* ICSR[PENDSTCLR] - Clear a pending SysTick */
+#define ICSR_PENDSTCLR_MSK (0x1 << 25 )
+#define ICSR_PENDSTCLR (0x1 << 25 )
+#define ICSR_PENDSTCLR_DIS (0x0 << 25 ) /* DIS */
+#define ICSR_PENDSTCLR_EN (0x1 << 25 ) /* EN */
+
+/* ICSR[ISRPREEMPT] - If set, a pending exception will be serviced on exit from the debug halt state */
+#define ICSR_ISRPREEMPT_MSK (0x1 << 23 )
+#define ICSR_ISRPREEMPT (0x1 << 23 )
+#define ICSR_ISRPREEMPT_DIS (0x0 << 23 ) /* DIS */
+#define ICSR_ISRPREEMPT_EN (0x1 << 23 ) /* EN */
+
+/* ICSR[ISRPENDING] - Indicates if an external configurable is pending */
+#define ICSR_ISRPENDING_MSK (0x1 << 22 )
+#define ICSR_ISRPENDING (0x1 << 22 )
+#define ICSR_ISRPENDING_DIS (0x0 << 22 ) /* DIS */
+#define ICSR_ISRPENDING_EN (0x1 << 22 ) /* EN */
+
+/* ICSR[VECTPENDING] - Indicates the exception number for the highest priority pending exception */
+#define ICSR_VECTPENDING_MSK (0x1FF << 12 )
+
+/* ICSR[RETTOBASE] - */
+#define ICSR_RETTOBASE_MSK (0x1 << 11 )
+#define ICSR_RETTOBASE (0x1 << 11 )
+#define ICSR_RETTOBASE_DIS (0x0 << 11 ) /* DIS */
+#define ICSR_RETTOBASE_EN (0x1 << 11 ) /* EN */
+
+/* ICSR[VECTACTIVE] - Thread mode, or exception number */
+#define ICSR_VECTACTIVE_MSK (0x1FF << 0 )
+
+/* Reset Value for VTOR*/
+#define VTOR_RVAL 0x0
+
+/* VTOR[TBLBASE] - */
+#define VTOR_TBLBASE_MSK (0x1 << 29 )
+#define VTOR_TBLBASE (0x1 << 29 )
+#define VTOR_TBLBASE_DIS (0x0 << 29 ) /* DIS */
+#define VTOR_TBLBASE_EN (0x1 << 29 ) /* EN */
+
+/* VTOR[TBLOFF] - */
+#define VTOR_TBLOFF_MSK (0x3FFFFF << 7 )
+
+/* Reset Value for AIRCR*/
+#define AIRCR_RVAL 0xFA050000
+
+/* AIRCR[VECTKEYSTAT] - Reads as 0xFA05 */
+#define AIRCR_VECTKEYSTAT_MSK (0xFFFF << 16 )
+
+/* AIRCR[ENDIANESS] - This bit is static or configured by a hardware input on reset */
+#define AIRCR_ENDIANESS_MSK (0x1 << 15 )
+#define AIRCR_ENDIANESS (0x1 << 15 )
+#define AIRCR_ENDIANESS_DIS (0x0 << 15 ) /* DIS */
+#define AIRCR_ENDIANESS_EN (0x1 << 15 ) /* EN */
+
+/* AIRCR[PRIGROUP] - Priority grouping position */
+#define AIRCR_PRIGROUP_MSK (0x7 << 8 )
+
+/* AIRCR[SYSRESETREQ] - System Reset Request */
+#define AIRCR_SYSRESETREQ_MSK (0x1 << 2 )
+#define AIRCR_SYSRESETREQ (0x1 << 2 )
+#define AIRCR_SYSRESETREQ_DIS (0x0 << 2 ) /* DIS */
+#define AIRCR_SYSRESETREQ_EN (0x1 << 2 ) /* EN */
+
+/* AIRCR[VECTCLRACTIVE] - Clears all active state information for fixed and configurable exceptions */
+#define AIRCR_VECTCLRACTIVE_MSK (0x1 << 1 )
+#define AIRCR_VECTCLRACTIVE (0x1 << 1 )
+#define AIRCR_VECTCLRACTIVE_DIS (0x0 << 1 ) /* DIS */
+#define AIRCR_VECTCLRACTIVE_EN (0x1 << 1 ) /* EN */
+
+/* AIRCR[VECTRESET] - Local system reset */
+#define AIRCR_VECTRESET_MSK (0x1 << 0 )
+#define AIRCR_VECTRESET (0x1 << 0 )
+#define AIRCR_VECTRESET_DIS (0x0 << 0 ) /* DIS */
+#define AIRCR_VECTRESET_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for SCR*/
+#define SCR_RVAL 0x0
+
+/* SCR[SEVONPEND] - */
+#define SCR_SEVONPEND_MSK (0x1 << 4 )
+#define SCR_SEVONPEND (0x1 << 4 )
+#define SCR_SEVONPEND_DIS (0x0 << 4 ) /* DIS */
+#define SCR_SEVONPEND_EN (0x1 << 4 ) /* EN */
+
+/* SCR[SLEEPDEEP] - Sleep deep bit */
+#define SCR_SLEEPDEEP_MSK (0x1 << 2 )
+#define SCR_SLEEPDEEP (0x1 << 2 )
+#define SCR_SLEEPDEEP_DIS (0x0 << 2 ) /* DIS */
+#define SCR_SLEEPDEEP_EN (0x1 << 2 ) /* EN */
+
+/* SCR[SLEEPONEXIT] - Sleep on exit when returning from handler mode to thread mode */
+#define SCR_SLEEPONEXIT_MSK (0x1 << 1 )
+#define SCR_SLEEPONEXIT (0x1 << 1 )
+#define SCR_SLEEPONEXIT_DIS (0x0 << 1 ) /* DIS */
+#define SCR_SLEEPONEXIT_EN (0x1 << 1 ) /* EN */
+
+/* Reset Value for CCR*/
+#define CCR_RVAL 0x200
+
+/* CCR[STKALIGN] - */
+#define CCR_STKALIGN_MSK (0x1 << 9 )
+#define CCR_STKALIGN (0x1 << 9 )
+#define CCR_STKALIGN_DIS (0x0 << 9 ) /* DIS */
+#define CCR_STKALIGN_EN (0x1 << 9 ) /* EN */
+
+/* CCR[BFHFNMIGN] - */
+#define CCR_BFHFNMIGN_MSK (0x1 << 8 )
+#define CCR_BFHFNMIGN (0x1 << 8 )
+#define CCR_BFHFNMIGN_DIS (0x0 << 8 ) /* DIS */
+#define CCR_BFHFNMIGN_EN (0x1 << 8 ) /* EN */
+
+/* CCR[DIV0TRP] - */
+#define CCR_DIV0TRP_MSK (0x1 << 4 )
+#define CCR_DIV0TRP (0x1 << 4 )
+#define CCR_DIV0TRP_DIS (0x0 << 4 ) /* DIS */
+#define CCR_DIV0TRP_EN (0x1 << 4 ) /* EN */
+
+/* CCR[UNALIGNTRP] - */
+#define CCR_UNALIGNTRP_MSK (0x1 << 3 )
+#define CCR_UNALIGNTRP (0x1 << 3 )
+#define CCR_UNALIGNTRP_DIS (0x0 << 3 ) /* DIS */
+#define CCR_UNALIGNTRP_EN (0x1 << 3 ) /* EN */
+
+/* CCR[USERSETMPEND] - */
+#define CCR_USERSETMPEND_MSK (0x1 << 1 )
+#define CCR_USERSETMPEND (0x1 << 1 )
+#define CCR_USERSETMPEND_DIS (0x0 << 1 ) /* DIS */
+#define CCR_USERSETMPEND_EN (0x1 << 1 ) /* EN */
+
+/* CCR[NONBASETHRDENA] - */
+#define CCR_NONBASETHRDENA_MSK (0x1 << 0 )
+#define CCR_NONBASETHRDENA (0x1 << 0 )
+#define CCR_NONBASETHRDENA_DIS (0x0 << 0 ) /* DIS */
+#define CCR_NONBASETHRDENA_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for SHPR1*/
+#define SHPR1_RVAL 0x0
+
+/* SHPR1[PRI7] - Priority of system handler 7 - reserved */
+#define SHPR1_PRI7_MSK (0xFF << 24 )
+
+/* SHPR1[PRI6] - Priority of system handler 6 - UsageFault */
+#define SHPR1_PRI6_MSK (0xFF << 16 )
+
+/* SHPR1[PRI5] - Priority of system handler 5 - BusFault */
+#define SHPR1_PRI5_MSK (0xFF << 8 )
+
+/* SHPR1[PRI4] - Priority of system handler 4 - MemManage */
+#define SHPR1_PRI4_MSK (0xFF << 0 )
+
+/* Reset Value for SHPR2*/
+#define SHPR2_RVAL 0x0
+
+/* SHPR2[PRI11] - Priority of system handler 11 - SVCall */
+#define SHPR2_PRI11_MSK (0xFF << 24 )
+
+/* SHPR2[PRI10] - Priority of system handler 10 - reserved */
+#define SHPR2_PRI10_MSK (0xFF << 16 )
+
+/* SHPR2[PRI9] - Priority of system handler 9 - reserved */
+#define SHPR2_PRI9_MSK (0xFF << 8 )
+
+/* SHPR2[PRI8] - Priority of system handler 8 - reserved */
+#define SHPR2_PRI8_MSK (0xFF << 0 )
+
+/* Reset Value for SHPR3*/
+#define SHPR3_RVAL 0x0
+
+/* SHPR3[PRI15] - Priority of system handler 15 - SysTick */
+#define SHPR3_PRI15_MSK (0xFF << 24 )
+
+/* SHPR3[PRI14] - Priority of system handler 14 - PendSV */
+#define SHPR3_PRI14_MSK (0xFF << 16 )
+
+/* SHPR3[PRI13] - Priority of system handler 13 - reserved */
+#define SHPR3_PRI13_MSK (0xFF << 8 )
+
+/* SHPR3[PRI12] - Priority of system handler 12 - DebugMonitor */
+#define SHPR3_PRI12_MSK (0xFF << 0 )
+
+/* Reset Value for SHCSR*/
+#define SHCSR_RVAL 0x0
+
+/* SHCSR[USGFAULTENA] - Enable for UsageFault */
+#define SHCSR_USGFAULTENA_MSK (0x1 << 18 )
+#define SHCSR_USGFAULTENA (0x1 << 18 )
+#define SHCSR_USGFAULTENA_DIS (0x0 << 18 ) /* DIS */
+#define SHCSR_USGFAULTENA_EN (0x1 << 18 ) /* EN */
+
+/* SHCSR[BUSFAULTENA] - Enable for BusFault. */
+#define SHCSR_BUSFAULTENA_MSK (0x1 << 17 )
+#define SHCSR_BUSFAULTENA (0x1 << 17 )
+#define SHCSR_BUSFAULTENA_DIS (0x0 << 17 ) /* DIS */
+#define SHCSR_BUSFAULTENA_EN (0x1 << 17 ) /* EN */
+
+/* SHCSR[MEMFAULTENA] - Enable for MemManage fault. */
+#define SHCSR_MEMFAULTENA_MSK (0x1 << 16 )
+#define SHCSR_MEMFAULTENA (0x1 << 16 )
+#define SHCSR_MEMFAULTENA_DIS (0x0 << 16 ) /* DIS */
+#define SHCSR_MEMFAULTENA_EN (0x1 << 16 ) /* EN */
+
+/* SHCSR[SVCALLPENDED] - Reads as 1 if SVCall is Pending */
+#define SHCSR_SVCALLPENDED_MSK (0x1 << 15 )
+#define SHCSR_SVCALLPENDED (0x1 << 15 )
+#define SHCSR_SVCALLPENDED_DIS (0x0 << 15 ) /* DIS */
+#define SHCSR_SVCALLPENDED_EN (0x1 << 15 ) /* EN */
+
+/* SHCSR[BUSFAULTPENDED] - Reads as 1 if BusFault is Pending */
+#define SHCSR_BUSFAULTPENDED_MSK (0x1 << 14 )
+#define SHCSR_BUSFAULTPENDED (0x1 << 14 )
+#define SHCSR_BUSFAULTPENDED_DIS (0x0 << 14 ) /* DIS */
+#define SHCSR_BUSFAULTPENDED_EN (0x1 << 14 ) /* EN */
+
+/* SHCSR[MEMFAULTPENDED] - Reads as 1 if MemManage is Pending */
+#define SHCSR_MEMFAULTPENDED_MSK (0x1 << 13 )
+#define SHCSR_MEMFAULTPENDED (0x1 << 13 )
+#define SHCSR_MEMFAULTPENDED_DIS (0x0 << 13 ) /* DIS */
+#define SHCSR_MEMFAULTPENDED_EN (0x1 << 13 ) /* EN */
+
+/* SHCSR[USGFAULTPENDED] - Reads as 1 if UsageFault is Pending */
+#define SHCSR_USGFAULTPENDED_MSK (0x1 << 12 )
+#define SHCSR_USGFAULTPENDED (0x1 << 12 )
+#define SHCSR_USGFAULTPENDED_DIS (0x0 << 12 ) /* DIS */
+#define SHCSR_USGFAULTPENDED_EN (0x1 << 12 ) /* EN */
+
+/* SHCSR[SYSTICKACT] - Reads as 1 if SysTick is Active */
+#define SHCSR_SYSTICKACT_MSK (0x1 << 11 )
+#define SHCSR_SYSTICKACT (0x1 << 11 )
+#define SHCSR_SYSTICKACT_DIS (0x0 << 11 ) /* DIS */
+#define SHCSR_SYSTICKACT_EN (0x1 << 11 ) /* EN */
+
+/* SHCSR[PENDSVACT] - Reads as 1 if PendSV is Active */
+#define SHCSR_PENDSVACT_MSK (0x1 << 10 )
+#define SHCSR_PENDSVACT (0x1 << 10 )
+#define SHCSR_PENDSVACT_DIS (0x0 << 10 ) /* DIS */
+#define SHCSR_PENDSVACT_EN (0x1 << 10 ) /* EN */
+
+/* SHCSR[MONITORACT] - Reads as 1 if the Monitor is Active */
+#define SHCSR_MONITORACT_MSK (0x1 << 8 )
+#define SHCSR_MONITORACT (0x1 << 8 )
+#define SHCSR_MONITORACT_DIS (0x0 << 8 ) /* DIS */
+#define SHCSR_MONITORACT_EN (0x1 << 8 ) /* EN */
+
+/* SHCSR[SVCALLACT] - Reads as 1 if SVCall is Active */
+#define SHCSR_SVCALLACT_MSK (0x1 << 7 )
+#define SHCSR_SVCALLACT (0x1 << 7 )
+#define SHCSR_SVCALLACT_DIS (0x0 << 7 ) /* DIS */
+#define SHCSR_SVCALLACT_EN (0x1 << 7 ) /* EN */
+
+/* SHCSR[USGFAULTACT] - Reads as 1 if UsageFault is Active. */
+#define SHCSR_USGFAULTACT_MSK (0x1 << 3 )
+#define SHCSR_USGFAULTACT (0x1 << 3 )
+#define SHCSR_USGFAULTACT_DIS (0x0 << 3 ) /* DIS */
+#define SHCSR_USGFAULTACT_EN (0x1 << 3 ) /* EN */
+
+/* SHCSR[BUSFAULTACT] - Reads as 1 if BusFault is Active. */
+#define SHCSR_BUSFAULTACT_MSK (0x1 << 1 )
+#define SHCSR_BUSFAULTACT (0x1 << 1 )
+#define SHCSR_BUSFAULTACT_DIS (0x0 << 1 ) /* DIS */
+#define SHCSR_BUSFAULTACT_EN (0x1 << 1 ) /* EN */
+
+/* SHCSR[MEMFAULTACT] - Reads as 1 if MemManage is Active */
+#define SHCSR_MEMFAULTACT_MSK (0x1 << 0 )
+#define SHCSR_MEMFAULTACT (0x1 << 0 )
+#define SHCSR_MEMFAULTACT_DIS (0x0 << 0 ) /* DIS */
+#define SHCSR_MEMFAULTACT_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for CFSR*/
+#define CFSR_RVAL 0x0
+
+/* CFSR[DIVBYZERO] - Divide by zero error */
+#define CFSR_DIVBYZERO_MSK (0x1 << 25 )
+#define CFSR_DIVBYZERO (0x1 << 25 )
+#define CFSR_DIVBYZERO_DIS (0x0 << 25 ) /* DIS */
+#define CFSR_DIVBYZERO_EN (0x1 << 25 ) /* EN */
+
+/* CFSR[UNALIGNED] - Unaligned access error */
+#define CFSR_UNALIGNED_MSK (0x1 << 24 )
+#define CFSR_UNALIGNED (0x1 << 24 )
+#define CFSR_UNALIGNED_DIS (0x0 << 24 ) /* DIS */
+#define CFSR_UNALIGNED_EN (0x1 << 24 ) /* EN */
+
+/* CFSR[NOCP] - Coprocessor access error */
+#define CFSR_NOCP_MSK (0x1 << 19 )
+#define CFSR_NOCP (0x1 << 19 )
+#define CFSR_NOCP_DIS (0x0 << 19 ) /* DIS */
+#define CFSR_NOCP_EN (0x1 << 19 ) /* EN */
+
+/* CFSR[INVPC] - Integrity check error on EXC_RETURN */
+#define CFSR_INVPC_MSK (0x1 << 18 )
+#define CFSR_INVPC (0x1 << 18 )
+#define CFSR_INVPC_DIS (0x0 << 18 ) /* DIS */
+#define CFSR_INVPC_EN (0x1 << 18 ) /* EN */
+
+/* CFSR[INVSTATE] - Invalid EPSR.T bit or illegal EPSR.IT bits for executing */
+#define CFSR_INVSTATE_MSK (0x1 << 17 )
+#define CFSR_INVSTATE (0x1 << 17 )
+#define CFSR_INVSTATE_DIS (0x0 << 17 ) /* DIS */
+#define CFSR_INVSTATE_EN (0x1 << 17 ) /* EN */
+
+/* CFSR[UNDEFINSTR] - Undefined instruction executed */
+#define CFSR_UNDEFINSTR_MSK (0x1 << 16 )
+#define CFSR_UNDEFINSTR (0x1 << 16 )
+#define CFSR_UNDEFINSTR_DIS (0x0 << 16 ) /* DIS */
+#define CFSR_UNDEFINSTR_EN (0x1 << 16 ) /* EN */
+
+/* CFSR[BFARVALID] - This bit is set if the BFAR register has valid contents */
+#define CFSR_BFARVALID_MSK (0x1 << 15 )
+#define CFSR_BFARVALID (0x1 << 15 )
+#define CFSR_BFARVALID_DIS (0x0 << 15 ) /* DIS */
+#define CFSR_BFARVALID_EN (0x1 << 15 ) /* EN */
+
+/* CFSR[STKERR] - This bit indicates a derived bus fault has occurred on exception entry */
+#define CFSR_STKERR_MSK (0x1 << 12 )
+#define CFSR_STKERR (0x1 << 12 )
+#define CFSR_STKERR_DIS (0x0 << 12 ) /* DIS */
+#define CFSR_STKERR_EN (0x1 << 12 ) /* EN */
+
+/* CFSR[UNSTKERR] - This bit indicates a derived bus fault has occurred on exception return */
+#define CFSR_UNSTKERR_MSK (0x1 << 11 )
+#define CFSR_UNSTKERR (0x1 << 11 )
+#define CFSR_UNSTKERR_DIS (0x0 << 11 ) /* DIS */
+#define CFSR_UNSTKERR_EN (0x1 << 11 ) /* EN */
+
+/* CFSR[IMPRECISERR] - Imprecise data access error */
+#define CFSR_IMPRECISERR_MSK (0x1 << 10 )
+#define CFSR_IMPRECISERR (0x1 << 10 )
+#define CFSR_IMPRECISERR_DIS (0x0 << 10 ) /* DIS */
+#define CFSR_IMPRECISERR_EN (0x1 << 10 ) /* EN */
+
+/* CFSR[PRECISERR] - Precise data access error. The BFAR is written with the faulting address */
+#define CFSR_PRECISERR_MSK (0x1 << 9 )
+#define CFSR_PRECISERR (0x1 << 9 )
+#define CFSR_PRECISERR_DIS (0x0 << 9 ) /* DIS */
+#define CFSR_PRECISERR_EN (0x1 << 9 ) /* EN */
+
+/* CFSR[IBUSERR] - This bit indicates a bus fault on an instruction prefetch */
+#define CFSR_IBUSERR_MSK (0x1 << 8 )
+#define CFSR_IBUSERR (0x1 << 8 )
+#define CFSR_IBUSERR_DIS (0x0 << 8 ) /* DIS */
+#define CFSR_IBUSERR_EN (0x1 << 8 ) /* EN */
+
+/* CFSR[MMARVALID] - This bit is set if the MMAR register has valid contents. */
+#define CFSR_MMARVALID_MSK (0x1 << 7 )
+#define CFSR_MMARVALID (0x1 << 7 )
+#define CFSR_MMARVALID_DIS (0x0 << 7 ) /* DIS */
+#define CFSR_MMARVALID_EN (0x1 << 7 ) /* EN */
+
+/* CFSR[MSTKERR] - A derived MemManage fault has occurred on exception entry */
+#define CFSR_MSTKERR_MSK (0x1 << 4 )
+#define CFSR_MSTKERR (0x1 << 4 )
+#define CFSR_MSTKERR_DIS (0x0 << 4 ) /* DIS */
+#define CFSR_MSTKERR_EN (0x1 << 4 ) /* EN */
+
+/* CFSR[MUNSTKERR] - A derived MemManage fault has occurred on exception return */
+#define CFSR_MUNSTKERR_MSK (0x1 << 3 )
+#define CFSR_MUNSTKERR (0x1 << 3 )
+#define CFSR_MUNSTKERR_DIS (0x0 << 3 ) /* DIS */
+#define CFSR_MUNSTKERR_EN (0x1 << 3 ) /* EN */
+
+/* CFSR[DACCVIOL] - Data access violation. The MMAR is set to the data address which the load store tried to access. */
+#define CFSR_DACCVIOL_MSK (0x1 << 1 )
+#define CFSR_DACCVIOL (0x1 << 1 )
+#define CFSR_DACCVIOL_DIS (0x0 << 1 ) /* DIS */
+#define CFSR_DACCVIOL_EN (0x1 << 1 ) /* EN */
+
+/* CFSR[IACCVIOL] - violation on an instruction fetch. */
+#define CFSR_IACCVIOL_MSK (0x1 << 0 )
+#define CFSR_IACCVIOL (0x1 << 0 )
+#define CFSR_IACCVIOL_DIS (0x0 << 0 ) /* DIS */
+#define CFSR_IACCVIOL_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for HFSR*/
+#define HFSR_RVAL 0x0
+
+/* HFSR[DEBUGEVT] - Debug event, and the Debug Fault Status Register has been updated. */
+#define HFSR_DEBUGEVT_MSK (0x1 << 31 )
+#define HFSR_DEBUGEVT (0x1 << 31 )
+#define HFSR_DEBUGEVT_DIS (0x0 << 31 ) /* DIS */
+#define HFSR_DEBUGEVT_EN (0x1 << 31 ) /* EN */
+
+/* HFSR[FORCED] - Configurable fault cannot be activated due to priority or it was disabled. Priority escalated to a HardFault. */
+#define HFSR_FORCED_MSK (0x1 << 30 )
+#define HFSR_FORCED (0x1 << 30 )
+#define HFSR_FORCED_DIS (0x0 << 30 ) /* DIS */
+#define HFSR_FORCED_EN (0x1 << 30 ) /* EN */
+
+/* HFSR[VECTTBL] - Fault was due to vector table read on exception processing */
+#define HFSR_VECTTBL_MSK (0x1 << 1 )
+#define HFSR_VECTTBL (0x1 << 1 )
+#define HFSR_VECTTBL_DIS (0x0 << 1 ) /* DIS */
+#define HFSR_VECTTBL_EN (0x1 << 1 ) /* EN */
+
+/* Reset Value for MMFAR*/
+#define MMFAR_RVAL 0x0
+
+/* MMFAR[ADDRESS] - Data address MPU faulted. */
+#define MMFAR_ADDRESS_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for BFAR*/
+#define BFAR_RVAL 0x0
+
+/* BFAR[ADDRESS] - Updated on precise data access faults */
+#define BFAR_ADDRESS_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for STIR*/
+#define STIR_RVAL 0x0
+
+/* STIR[INTID] - The value written in this field is the interrupt to be triggered. */
+#define STIR_INTID_MSK (0x3FF << 0 )
+// ------------------------------------------------------------------------------------------------
+// ----- ADC0 -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Analog to Digital Converter (pADI_ADC0)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_ADC0 Structure */
+ __IO uint8_t
+ STA; /*!< ADC Status register */
+ __I uint8_t RESERVED0[3];
+ __IO uint8_t
+ MSKI; /*!< Interrupt control register */
+ __I uint8_t RESERVED1[3];
+ __IO uint32_t
+ CON; /*!< Main control register */
+ __IO uint16_t
+ OF; /*!< Offset calibration register */
+ __I uint16_t RESERVED2;
+ __IO uint16_t
+ INTGN; /*!< Gain calibration register when using internal reference */
+ __I uint16_t RESERVED3;
+ __IO uint16_t
+ EXTGN; /*!< Gain calibration register when using external reference */
+ __I uint16_t RESERVED4;
+ __IO uint16_t
+ VDDGN; /*!< Gain calibration register when using AVDD as the ADC reference */
+ __I uint16_t RESERVED5;
+ __IO uint16_t
+ ADCCFG; /*!< "Control register for the VBIAS voltage generator, ground switch and external reference buffer" */
+ __I uint16_t RESERVED6;
+ __IO uint16_t
+ FLT; /*!< Filter configuration register */
+ __I uint16_t RESERVED7;
+ __IO uint16_t
+ MDE; /*!< mode control register */
+ __I uint16_t RESERVED8;
+ __IO uint16_t
+ RCR; /*!< Number of ADC0 conversions before an ADC interrupt is generated. */
+ __I uint16_t RESERVED9;
+ __IO uint16_t
+ RCV; /*!< "This 16-bit, read-only MMR holds the current number of ADC0 conversion results" */
+ __I uint16_t RESERVED10;
+ __IO uint16_t
+ TH; /*!< Sets the threshold */
+ __I uint16_t RESERVED11;
+ __IO uint8_t
+ THC; /*!< Determines how many cumulative ADC0 conversion result readings above ADC0TH must occur */
+ __I uint8_t RESERVED12[3];
+ __IO uint8_t
+ THV; /*!< 8-bit threshold exceeded counter register */
+ __I uint8_t RESERVED13[3];
+ __IO uint32_t
+ ACC; /*!< 32-bit accumulator register */
+ __IO uint32_t
+ ATH; /*!< Holds the threshold value for the accumulator comparator */
+ __IO uint8_t
+ PRO; /*!< Configuration register for Post processing of ADC0 results */
+ __I uint8_t RESERVED14[3];
+ __IO uint32_t
+ DAT; /*!< conversion result register */
+} ADI_ADC_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define ADC0STA (*(volatile unsigned char *) 0x40030000)
+#define ADC0MSKI (*(volatile unsigned char *) 0x40030004)
+#define ADC0CON (*(volatile unsigned long *) 0x40030008)
+#define ADC0OF (*(volatile unsigned short int *) 0x4003000C)
+#define ADC0INTGN (*(volatile unsigned short int *) 0x40030010)
+#define ADC0EXTGN (*(volatile unsigned short int *) 0x40030014)
+#define ADC0VDDGN (*(volatile unsigned short int *) 0x40030018)
+#define ADCCFG (*(volatile unsigned short int *) 0x4003001C)
+#define ADC0FLT (*(volatile unsigned short int *) 0x40030020)
+#define ADC0MDE (*(volatile unsigned short int *) 0x40030024)
+#define ADC0RCR (*(volatile unsigned short int *) 0x40030028)
+#define ADC0RCV (*(volatile unsigned short int *) 0x4003002C)
+#define ADC0TH (*(volatile unsigned short int *) 0x40030030)
+#define ADC0THC (*(volatile unsigned char *) 0x40030034)
+#define ADC0THV (*(volatile unsigned char *) 0x40030038)
+#define ADC0ACC (*(volatile unsigned long *) 0x4003003C)
+#define ADC0ATH (*(volatile unsigned long *) 0x40030040)
+#define ADC0PRO (*(volatile unsigned char *) 0x40030044)
+#define ADC0DAT (*(volatile unsigned long *) 0x40030048)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for ADC0STA*/
+#define ADC0STA_RVAL 0x0
+
+/* ADC0STA[CAL] - ADC Calibration status register */
+#define ADC0STA_CAL_BBA (*(volatile unsigned long *) 0x42600014)
+#define ADC0STA_CAL_MSK (0x1 << 5 )
+#define ADC0STA_CAL (0x1 << 5 )
+#define ADC0STA_CAL_DIS (0x0 << 5 ) /* DIS */
+#define ADC0STA_CAL_EN (0x1 << 5 ) /* EN */
+
+/* ADC0STA[ERR] - ADC conversion error status bit. */
+#define ADC0STA_ERR_BBA (*(volatile unsigned long *) 0x42600010)
+#define ADC0STA_ERR_MSK (0x1 << 4 )
+#define ADC0STA_ERR (0x1 << 4 )
+#define ADC0STA_ERR_DIS (0x0 << 4 ) /* DIS */
+#define ADC0STA_ERR_EN (0x1 << 4 ) /* EN */
+
+/* ADC0STA[ATHEX] - ADC Accumulator Comparator Threshold status bit. */
+#define ADC0STA_ATHEX_BBA (*(volatile unsigned long *) 0x4260000C)
+#define ADC0STA_ATHEX_MSK (0x1 << 3 )
+#define ADC0STA_ATHEX (0x1 << 3 )
+#define ADC0STA_ATHEX_DIS (0x0 << 3 ) /* DIS */
+#define ADC0STA_ATHEX_EN (0x1 << 3 ) /* EN */
+
+/* ADC0STA[THEX] - ADC comparator threshold. */
+#define ADC0STA_THEX_BBA (*(volatile unsigned long *) 0x42600008)
+#define ADC0STA_THEX_MSK (0x1 << 2 )
+#define ADC0STA_THEX (0x1 << 2 )
+#define ADC0STA_THEX_DIS (0x0 << 2 ) /* DIS */
+#define ADC0STA_THEX_EN (0x1 << 2 ) /* EN */
+
+/* ADC0STA[OVR] - ADC overrange bit. */
+#define ADC0STA_OVR_BBA (*(volatile unsigned long *) 0x42600004)
+#define ADC0STA_OVR_MSK (0x1 << 1 )
+#define ADC0STA_OVR (0x1 << 1 )
+#define ADC0STA_OVR_DIS (0x0 << 1 ) /* DIS */
+#define ADC0STA_OVR_EN (0x1 << 1 ) /* EN */
+
+/* ADC0STA[RDY] - valid conversion result */
+#define ADC0STA_RDY_BBA (*(volatile unsigned long *) 0x42600000)
+#define ADC0STA_RDY_MSK (0x1 << 0 )
+#define ADC0STA_RDY (0x1 << 0 )
+#define ADC0STA_RDY_DIS (0x0 << 0 ) /* DIS */
+#define ADC0STA_RDY_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ADC0MSKI*/
+#define ADC0MSKI_RVAL 0x0
+
+/* ADC0MSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
+#define ADC0MSKI_ATHEX_BBA (*(volatile unsigned long *) 0x4260008C)
+#define ADC0MSKI_ATHEX_MSK (0x1 << 3 )
+#define ADC0MSKI_ATHEX (0x1 << 3 )
+#define ADC0MSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
+#define ADC0MSKI_ATHEX_EN (0x1 << 3 ) /* EN */
+
+/* ADC0MSKI[THEX] - ADC comparator threshold mask */
+#define ADC0MSKI_THEX_BBA (*(volatile unsigned long *) 0x42600088)
+#define ADC0MSKI_THEX_MSK (0x1 << 2 )
+#define ADC0MSKI_THEX (0x1 << 2 )
+#define ADC0MSKI_THEX_DIS (0x0 << 2 ) /* DIS */
+#define ADC0MSKI_THEX_EN (0x1 << 2 ) /* EN */
+
+/* ADC0MSKI[OVR] - ADC overrange bit mask. */
+#define ADC0MSKI_OVR_BBA (*(volatile unsigned long *) 0x42600084)
+#define ADC0MSKI_OVR_MSK (0x1 << 1 )
+#define ADC0MSKI_OVR (0x1 << 1 )
+#define ADC0MSKI_OVR_DIS (0x0 << 1 ) /* DIS */
+#define ADC0MSKI_OVR_EN (0x1 << 1 ) /* EN */
+
+/* ADC0MSKI[RDY] - valid conversion result mask */
+#define ADC0MSKI_RDY_BBA (*(volatile unsigned long *) 0x42600080)
+#define ADC0MSKI_RDY_MSK (0x1 << 0 )
+#define ADC0MSKI_RDY (0x1 << 0 )
+#define ADC0MSKI_RDY_DIS (0x0 << 0 ) /* DIS */
+#define ADC0MSKI_RDY_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ADC0CON*/
+#define ADC0CON_RVAL 0x3038C
+
+/* ADC0CON[ADCEN] - Enable Bit */
+#define ADC0CON_ADCEN_BBA (*(volatile unsigned long *) 0x4260014C)
+#define ADC0CON_ADCEN_MSK (0x1 << 19 )
+#define ADC0CON_ADCEN (0x1 << 19 )
+#define ADC0CON_ADCEN_DIS (0x0 << 19 ) /* DIS */
+#define ADC0CON_ADCEN_EN (0x1 << 19 ) /* EN */
+
+/* ADC0CON[ADCCODE] - ADC Output Coding bits */
+#define ADC0CON_ADCCODE_BBA (*(volatile unsigned long *) 0x42600148)
+#define ADC0CON_ADCCODE_MSK (0x1 << 18 )
+#define ADC0CON_ADCCODE (0x1 << 18 )
+#define ADC0CON_ADCCODE_INT (0x0 << 18 ) /* INT */
+#define ADC0CON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
+
+/* ADC0CON[BUFPOWN] - Negative buffer power down */
+#define ADC0CON_BUFPOWN_BBA (*(volatile unsigned long *) 0x42600144)
+#define ADC0CON_BUFPOWN_MSK (0x1 << 17 )
+#define ADC0CON_BUFPOWN (0x1 << 17 )
+#define ADC0CON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
+#define ADC0CON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
+
+/* ADC0CON[BUFPOWP] - Positive buffer power down */
+#define ADC0CON_BUFPOWP_BBA (*(volatile unsigned long *) 0x42600140)
+#define ADC0CON_BUFPOWP_MSK (0x1 << 16 )
+#define ADC0CON_BUFPOWP (0x1 << 16 )
+#define ADC0CON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
+#define ADC0CON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
+
+/* ADC0CON[BUFBYPP] - Positive buffer bypass */
+#define ADC0CON_BUFBYPP_BBA (*(volatile unsigned long *) 0x4260013C)
+#define ADC0CON_BUFBYPP_MSK (0x1 << 15 )
+#define ADC0CON_BUFBYPP (0x1 << 15 )
+#define ADC0CON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
+#define ADC0CON_BUFBYPP_EN (0x1 << 15 ) /* EN */
+
+/* ADC0CON[BUFBYPN] - Negative buffer bypass */
+#define ADC0CON_BUFBYPN_BBA (*(volatile unsigned long *) 0x42600138)
+#define ADC0CON_BUFBYPN_MSK (0x1 << 14 )
+#define ADC0CON_BUFBYPN (0x1 << 14 )
+#define ADC0CON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
+#define ADC0CON_BUFBYPN_EN (0x1 << 14 ) /* EN */
+
+/* ADC0CON[ADCREF] - Reference selection */
+#define ADC0CON_ADCREF_MSK (0x3 << 12 )
+#define ADC0CON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
+#define ADC0CON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
+#define ADC0CON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
+#define ADC0CON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
+
+/* ADC0CON[ADCDIAG] - Diagnostic Current bits bits */
+#define ADC0CON_ADCDIAG_MSK (0x3 << 10 )
+#define ADC0CON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
+#define ADC0CON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
+#define ADC0CON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
+#define ADC0CON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
+
+/* ADC0CON[ADCCP] - AIN+ bits */
+#define ADC0CON_ADCCP_MSK (0x1F << 5 )
+#define ADC0CON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
+#define ADC0CON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
+#define ADC0CON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
+#define ADC0CON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
+#define ADC0CON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
+#define ADC0CON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
+#define ADC0CON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
+#define ADC0CON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
+#define ADC0CON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
+#define ADC0CON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
+#define ADC0CON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
+#define ADC0CON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
+#define ADC0CON_ADCCP_DAC (0xC << 5 ) /* DAC */
+#define ADC0CON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
+#define ADC0CON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
+#define ADC0CON_ADCCP_AGND (0xF << 5 ) /* AGND */
+#define ADC0CON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
+
+/* ADC0CON[ADCCN] - AIN- bits */
+#define ADC0CON_ADCCN_MSK (0x1F << 0 )
+#define ADC0CON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
+#define ADC0CON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
+#define ADC0CON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
+#define ADC0CON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
+#define ADC0CON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
+#define ADC0CON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
+#define ADC0CON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
+#define ADC0CON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
+#define ADC0CON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
+#define ADC0CON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
+#define ADC0CON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
+#define ADC0CON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
+#define ADC0CON_ADCCN_DAC (0xC << 0 ) /* DAC */
+#define ADC0CON_ADCCN_AGND (0xF << 0 ) /* AGND */
+#define ADC0CON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
+
+/* Reset Value for ADC0OF*/
+#define ADC0OF_RVAL 0x0
+
+/* ADC0OF[VALUE] - Offset */
+#define ADC0OF_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC0INTGN*/
+#define ADC0INTGN_RVAL 0x5555
+
+/* ADC0INTGN[VALUE] - Gain with Int Ref */
+#define ADC0INTGN_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC0EXTGN*/
+#define ADC0EXTGN_RVAL 0x5555
+
+/* ADC0EXTGN[VALUE] - Gain with Ext Ref */
+#define ADC0EXTGN_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC0VDDGN*/
+#define ADC0VDDGN_RVAL 0x5555
+
+/* ADC0VDDGN[VALUE] - Gain with Avdd Ref */
+#define ADC0VDDGN_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADCCFG*/
+#define ADCCFG_RVAL 0xF
+
+/* ADCCFG[SIMU] - Enable both ADCs */
+#define ADCCFG_SIMU_BBA (*(volatile unsigned long *) 0x426003BC)
+#define ADCCFG_SIMU_MSK (0x1 << 15 )
+#define ADCCFG_SIMU (0x1 << 15 )
+#define ADCCFG_SIMU_DIS (0x0 << 15 ) /* DIS */
+#define ADCCFG_SIMU_EN (0x1 << 15 ) /* EN */
+
+/* ADCCFG[BOOST30] - Boost the Vbias current source ability by 30 times */
+#define ADCCFG_BOOST30_BBA (*(volatile unsigned long *) 0x426003B4)
+#define ADCCFG_BOOST30_MSK (0x1 << 13 )
+#define ADCCFG_BOOST30 (0x1 << 13 )
+#define ADCCFG_BOOST30_DIS (0x0 << 13 ) /* DIS */
+#define ADCCFG_BOOST30_EN (0x1 << 13 ) /* EN */
+
+/* ADCCFG[PINSEL] - Enable vbias generator, send vbias to selected ain pin bits */
+#define ADCCFG_PINSEL_MSK (0x7 << 8 )
+#define ADCCFG_PINSEL_DIS (0x0 << 8 ) /* Disable VBIAS generator */
+#define ADCCFG_PINSEL_AIN7 (0x4 << 8 ) /* AIN7 */
+#define ADCCFG_PINSEL_AIN11 (0x6 << 8 ) /* AIN11 */
+
+/* ADCCFG[GNDSWON] - GND_SW */
+#define ADCCFG_GNDSWON_BBA (*(volatile unsigned long *) 0x4260039C)
+#define ADCCFG_GNDSWON_MSK (0x1 << 7 )
+#define ADCCFG_GNDSWON (0x1 << 7 )
+#define ADCCFG_GNDSWON_DIS (0x0 << 7 ) /* DIS */
+#define ADCCFG_GNDSWON_EN (0x1 << 7 ) /* EN */
+
+/* ADCCFG[GNDSWRESEN] - 20k resistor in series with GND_SW */
+#define ADCCFG_GNDSWRESEN_BBA (*(volatile unsigned long *) 0x42600398)
+#define ADCCFG_GNDSWRESEN_MSK (0x1 << 6 )
+#define ADCCFG_GNDSWRESEN (0x1 << 6 )
+#define ADCCFG_GNDSWRESEN_DIS (0x0 << 6 ) /* DIS */
+#define ADCCFG_GNDSWRESEN_EN (0x1 << 6 ) /* EN */
+
+/* ADCCFG[EXTBUF] - Control signals for ext_ref buffers bits */
+#define ADCCFG_EXTBUF_MSK (0x3 << 0 )
+#define ADCCFG_EXTBUF_OFF (0x0 << 0 ) /* OFF */
+#define ADCCFG_EXTBUF_VREFPN (0x1 << 0 ) /* VREFPN */
+#define ADCCFG_EXTBUF_VREFP_VREF2P (0x2 << 0 ) /* VREFP_VREF2P */
+
+/* Reset Value for ADC0FLT*/
+#define ADC0FLT_RVAL 0x7D
+
+/* ADC0FLT[CHOP] - Enables System-Chopping bits */
+#define ADC0FLT_CHOP_BBA (*(volatile unsigned long *) 0x4260043C)
+#define ADC0FLT_CHOP_MSK (0x1 << 15 )
+#define ADC0FLT_CHOP (0x1 << 15 )
+#define ADC0FLT_CHOP_OFF (0x0 << 15 ) /* OFF */
+#define ADC0FLT_CHOP_ON (0x1 << 15 ) /* ON */
+
+/* ADC0FLT[RAVG2] - Enables a running Average-By-2 bits */
+#define ADC0FLT_RAVG2_BBA (*(volatile unsigned long *) 0x42600438)
+#define ADC0FLT_RAVG2_MSK (0x1 << 14 )
+#define ADC0FLT_RAVG2 (0x1 << 14 )
+#define ADC0FLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
+#define ADC0FLT_RAVG2_ON (0x1 << 14 ) /* ON */
+
+/* ADC0FLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
+#define ADC0FLT_SINC4EN_BBA (*(volatile unsigned long *) 0x42600430)
+#define ADC0FLT_SINC4EN_MSK (0x1 << 12 )
+#define ADC0FLT_SINC4EN (0x1 << 12 )
+#define ADC0FLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
+#define ADC0FLT_SINC4EN_EN (0x1 << 12 ) /* EN */
+
+/* ADC0FLT[AF] - Averaging filter */
+#define ADC0FLT_AF_MSK (0xF << 8 )
+
+/* ADC0FLT[NOTCH2] - Inserts a notch at FNOTCH2 */
+#define ADC0FLT_NOTCH2_BBA (*(volatile unsigned long *) 0x4260041C)
+#define ADC0FLT_NOTCH2_MSK (0x1 << 7 )
+#define ADC0FLT_NOTCH2 (0x1 << 7 )
+#define ADC0FLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
+#define ADC0FLT_NOTCH2_EN (0x1 << 7 ) /* EN */
+
+/* ADC0FLT[SF] - SINC Filter value */
+#define ADC0FLT_SF_MSK (0x7F << 0 )
+
+/* Reset Value for ADC0MDE*/
+#define ADC0MDE_RVAL 0x0
+
+/* ADC0MDE[PGA] - PGA Gain Select bit */
+#define ADC0MDE_PGA_MSK (0xF << 4 )
+#define ADC0MDE_PGA_G1 (0x0 << 4 ) /* G1 */
+#define ADC0MDE_PGA_G2 (0x1 << 4 ) /* G2 */
+#define ADC0MDE_PGA_G4 (0x2 << 4 ) /* G4 */
+#define ADC0MDE_PGA_G8 (0x3 << 4 ) /* G8 */
+#define ADC0MDE_PGA_G16 (0x4 << 4 ) /* G16 */
+#define ADC0MDE_PGA_G32 (0x5 << 4 ) /* G32 */
+#define ADC0MDE_PGA_G64 (0x6 << 4 ) /* G64 */
+#define ADC0MDE_PGA_G128 (0x7 << 4 ) /* G128 */
+
+/* ADC0MDE[ADCMOD2] - ADC modulator gain of 2 control bits */
+#define ADC0MDE_ADCMOD2_BBA (*(volatile unsigned long *) 0x4260048C)
+#define ADC0MDE_ADCMOD2_MSK (0x1 << 3 )
+#define ADC0MDE_ADCMOD2 (0x1 << 3 )
+#define ADC0MDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
+#define ADC0MDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
+
+/* ADC0MDE[ADCMD] - ADC Mode bits */
+#define ADC0MDE_ADCMD_MSK (0x7 << 0 )
+#define ADC0MDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
+#define ADC0MDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
+#define ADC0MDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
+#define ADC0MDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
+#define ADC0MDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
+#define ADC0MDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
+#define ADC0MDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
+#define ADC0MDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
+
+/* Reset Value for ADC0RCR*/
+#define ADC0RCR_RVAL 0x1
+
+/* ADC0RCR[VALUE] - */
+#define ADC0RCR_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC0RCV*/
+#define ADC0RCV_RVAL 0x0
+
+/* ADC0RCV[VALUE] - */
+#define ADC0RCV_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC0TH*/
+#define ADC0TH_RVAL 0x0
+
+/* ADC0TH[VALUE] - */
+#define ADC0TH_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC0THC*/
+#define ADC0THC_RVAL 0x1
+
+/* ADC0THC[VALUE] - */
+#define ADC0THC_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for ADC0THV*/
+#define ADC0THV_RVAL 0x0
+
+/* ADC0THV[VALUE] - */
+#define ADC0THV_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for ADC0ACC*/
+#define ADC0ACC_RVAL 0x0
+
+/* ADC0ACC[VALUE] - */
+#define ADC0ACC_VALUE_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for ADC0ATH*/
+#define ADC0ATH_RVAL 0x0
+
+/* ADC0ATH[VALUE] - */
+#define ADC0ATH_VALUE_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for ADC0PRO*/
+#define ADC0PRO_RVAL 0x0
+
+/* ADC0PRO[ACCEN] - ADC Accumulator Enable bits */
+#define ADC0PRO_ACCEN_MSK (0x3 << 4 )
+#define ADC0PRO_ACCEN_Off (0x0 << 4 ) /* Off */
+#define ADC0PRO_ACCEN_En (0x1 << 4 ) /* En */
+#define ADC0PRO_ACCEN_EnNDec (0x2 << 4 ) /* EnNDec */
+#define ADC0PRO_ACCEN_EnAccCnt (0x3 << 4 ) /* EnAccCnt */
+
+/* ADC0PRO[CMPEN] - ADC Comparator Enable bits */
+#define ADC0PRO_CMPEN_MSK (0x3 << 2 )
+#define ADC0PRO_CMPEN_Off (0x0 << 2 ) /* Off */
+#define ADC0PRO_CMPEN_En (0x1 << 2 ) /* En */
+#define ADC0PRO_CMPEN_EnCnt (0x2 << 2 ) /* EnCnt */
+#define ADC0PRO_CMPEN_EnCntDec (0x3 << 2 ) /* EnCntDec */
+
+/* ADC0PRO[OREN] - ADC OverRange Enable */
+#define ADC0PRO_OREN_BBA (*(volatile unsigned long *) 0x42600884)
+#define ADC0PRO_OREN_MSK (0x1 << 1 )
+#define ADC0PRO_OREN (0x1 << 1 )
+#define ADC0PRO_OREN_DIS (0x0 << 1 ) /* DIS */
+#define ADC0PRO_OREN_EN (0x1 << 1 ) /* EN */
+
+/* ADC0PRO[RCEN] - ADC Result Counter Enable */
+#define ADC0PRO_RCEN_BBA (*(volatile unsigned long *) 0x42600880)
+#define ADC0PRO_RCEN_MSK (0x1 << 0 )
+#define ADC0PRO_RCEN (0x1 << 0 )
+#define ADC0PRO_RCEN_DIS (0x0 << 0 ) /* DIS */
+#define ADC0PRO_RCEN_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ADC0DAT*/
+#define ADC0DAT_RVAL 0x0
+
+/* ADC0DAT[VALUE] - */
+#define ADC0DAT_VALUE_MSK (0xFFFFFFFF << 0 )
+#if (__NO_MMR_STRUCTS__==1)
+
+#define ADC1STA (*(volatile unsigned char *) 0x40030080)
+#define ADC1MSKI (*(volatile unsigned char *) 0x40030084)
+#define ADC1CON (*(volatile unsigned long *) 0x40030088)
+#define ADC1OF (*(volatile unsigned short int *) 0x4003008C)
+#define ADC1INTGN (*(volatile unsigned short int *) 0x40030090)
+#define ADC1EXTGN (*(volatile unsigned short int *) 0x40030094)
+#define ADC1VDDGN (*(volatile unsigned short int *) 0x40030098)
+#define ADCSCFG1 (*(volatile unsigned short int *) 0x4003009C)
+#define ADC1FLT (*(volatile unsigned short int *) 0x400300A0)
+#define ADC1MDE (*(volatile unsigned short int *) 0x400300A4)
+#define ADC1RCR (*(volatile unsigned short int *) 0x400300A8)
+#define ADC1RCV (*(volatile unsigned short int *) 0x400300AC)
+#define ADC1TH (*(volatile unsigned short int *) 0x400300B0)
+#define ADC1THC (*(volatile unsigned char *) 0x400300B4)
+#define ADC1THV (*(volatile unsigned char *) 0x400300B8)
+#define ADC1ACC (*(volatile unsigned long *) 0x400300BC)
+#define ADC1ATH (*(volatile unsigned long *) 0x400300C0)
+#define ADC1PRO (*(volatile unsigned char *) 0x400300C4)
+#define ADC1DAT (*(volatile unsigned long *) 0x400300C8)
+#endif // (__NO_MMR_STRUCTS__==1)
+
+/* Reset Value for ADC1STA*/
+#define ADC1STA_RVAL 0x0
+
+/* ADC1STA[CAL] - ADC Calibration status register */
+#define ADC1STA_CAL_BBA (*(volatile unsigned long *) 0x42601014)
+#define ADC1STA_CAL_MSK (0x1 << 5 )
+#define ADC1STA_CAL (0x1 << 5 )
+#define ADC1STA_CAL_DIS (0x0 << 5 ) /* DIS */
+#define ADC1STA_CAL_EN (0x1 << 5 ) /* EN */
+
+/* ADC1STA[ERR] - ADC conversion error status bit. */
+#define ADC1STA_ERR_BBA (*(volatile unsigned long *) 0x42601010)
+#define ADC1STA_ERR_MSK (0x1 << 4 )
+#define ADC1STA_ERR (0x1 << 4 )
+#define ADC1STA_ERR_DIS (0x0 << 4 ) /* DIS */
+#define ADC1STA_ERR_EN (0x1 << 4 ) /* EN */
+
+/* ADC1STA[ATHEX] - ADC Accumulator Comparator Threshold status bit. */
+#define ADC1STA_ATHEX_BBA (*(volatile unsigned long *) 0x4260100C)
+#define ADC1STA_ATHEX_MSK (0x1 << 3 )
+#define ADC1STA_ATHEX (0x1 << 3 )
+#define ADC1STA_ATHEX_DIS (0x0 << 3 ) /* DIS */
+#define ADC1STA_ATHEX_EN (0x1 << 3 ) /* EN */
+
+/* ADC1STA[THEX] - ADC comparator threshold. */
+#define ADC1STA_THEX_BBA (*(volatile unsigned long *) 0x42601008)
+#define ADC1STA_THEX_MSK (0x1 << 2 )
+#define ADC1STA_THEX (0x1 << 2 )
+#define ADC1STA_THEX_DIS (0x0 << 2 ) /* DIS */
+#define ADC1STA_THEX_EN (0x1 << 2 ) /* EN */
+
+/* ADC1STA[OVR] - ADC overrange bit. */
+#define ADC1STA_OVR_BBA (*(volatile unsigned long *) 0x42601004)
+#define ADC1STA_OVR_MSK (0x1 << 1 )
+#define ADC1STA_OVR (0x1 << 1 )
+#define ADC1STA_OVR_DIS (0x0 << 1 ) /* DIS */
+#define ADC1STA_OVR_EN (0x1 << 1 ) /* EN */
+
+/* ADC1STA[RDY] - valid conversion result */
+#define ADC1STA_RDY_BBA (*(volatile unsigned long *) 0x42601000)
+#define ADC1STA_RDY_MSK (0x1 << 0 )
+#define ADC1STA_RDY (0x1 << 0 )
+#define ADC1STA_RDY_DIS (0x0 << 0 ) /* DIS */
+#define ADC1STA_RDY_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ADC1MSKI*/
+#define ADC1MSKI_RVAL 0x0
+
+/* ADC1MSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
+#define ADC1MSKI_ATHEX_BBA (*(volatile unsigned long *) 0x4260108C)
+#define ADC1MSKI_ATHEX_MSK (0x1 << 3 )
+#define ADC1MSKI_ATHEX (0x1 << 3 )
+#define ADC1MSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
+#define ADC1MSKI_ATHEX_EN (0x1 << 3 ) /* EN */
+
+/* ADC1MSKI[THEX] - ADC comparator threshold mask */
+#define ADC1MSKI_THEX_BBA (*(volatile unsigned long *) 0x42601088)
+#define ADC1MSKI_THEX_MSK (0x1 << 2 )
+#define ADC1MSKI_THEX (0x1 << 2 )
+#define ADC1MSKI_THEX_DIS (0x0 << 2 ) /* DIS */
+#define ADC1MSKI_THEX_EN (0x1 << 2 ) /* EN */
+
+/* ADC1MSKI[OVR] - ADC overrange bit mask. */
+#define ADC1MSKI_OVR_BBA (*(volatile unsigned long *) 0x42601084)
+#define ADC1MSKI_OVR_MSK (0x1 << 1 )
+#define ADC1MSKI_OVR (0x1 << 1 )
+#define ADC1MSKI_OVR_DIS (0x0 << 1 ) /* DIS */
+#define ADC1MSKI_OVR_EN (0x1 << 1 ) /* EN */
+
+/* ADC1MSKI[RDY] - valid conversion result mask */
+#define ADC1MSKI_RDY_BBA (*(volatile unsigned long *) 0x42601080)
+#define ADC1MSKI_RDY_MSK (0x1 << 0 )
+#define ADC1MSKI_RDY (0x1 << 0 )
+#define ADC1MSKI_RDY_DIS (0x0 << 0 ) /* DIS */
+#define ADC1MSKI_RDY_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ADC1CON*/
+#define ADC1CON_RVAL 0x303FF
+
+/* ADC1CON[ADCEN] - Enable Bit */
+#define ADC1CON_ADCEN_BBA (*(volatile unsigned long *) 0x4260114C)
+#define ADC1CON_ADCEN_MSK (0x1 << 19 )
+#define ADC1CON_ADCEN (0x1 << 19 )
+#define ADC1CON_ADCEN_DIS (0x0 << 19 ) /* DIS */
+#define ADC1CON_ADCEN_EN (0x1 << 19 ) /* EN */
+
+/* ADC1CON[ADCCODE] - ADC Output Coding bits */
+#define ADC1CON_ADCCODE_BBA (*(volatile unsigned long *) 0x42601148)
+#define ADC1CON_ADCCODE_MSK (0x1 << 18 )
+#define ADC1CON_ADCCODE (0x1 << 18 )
+#define ADC1CON_ADCCODE_INT (0x0 << 18 ) /* INT */
+#define ADC1CON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
+
+/* ADC1CON[BUFPOWN] - Negative buffer power down */
+#define ADC1CON_BUFPOWN_BBA (*(volatile unsigned long *) 0x42601144)
+#define ADC1CON_BUFPOWN_MSK (0x1 << 17 )
+#define ADC1CON_BUFPOWN (0x1 << 17 )
+#define ADC1CON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
+#define ADC1CON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
+
+/* ADC1CON[BUFPOWP] - Positive buffer power down */
+#define ADC1CON_BUFPOWP_BBA (*(volatile unsigned long *) 0x42601140)
+#define ADC1CON_BUFPOWP_MSK (0x1 << 16 )
+#define ADC1CON_BUFPOWP (0x1 << 16 )
+#define ADC1CON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
+#define ADC1CON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
+
+/* ADC1CON[BUFBYPP] - Positive buffer bypass */
+#define ADC1CON_BUFBYPP_BBA (*(volatile unsigned long *) 0x4260113C)
+#define ADC1CON_BUFBYPP_MSK (0x1 << 15 )
+#define ADC1CON_BUFBYPP (0x1 << 15 )
+#define ADC1CON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
+#define ADC1CON_BUFBYPP_EN (0x1 << 15 ) /* EN */
+
+/* ADC1CON[BUFBYPN] - Negative buffer bypass */
+#define ADC1CON_BUFBYPN_BBA (*(volatile unsigned long *) 0x42601138)
+#define ADC1CON_BUFBYPN_MSK (0x1 << 14 )
+#define ADC1CON_BUFBYPN (0x1 << 14 )
+#define ADC1CON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
+#define ADC1CON_BUFBYPN_EN (0x1 << 14 ) /* EN */
+
+/* ADC1CON[ADCREF] - Reference selection */
+#define ADC1CON_ADCREF_MSK (0x3 << 12 )
+#define ADC1CON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
+#define ADC1CON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
+#define ADC1CON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
+#define ADC1CON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
+
+/* ADC1CON[ADCDIAG] - Diagnostic Current bits bits */
+#define ADC1CON_ADCDIAG_MSK (0x3 << 10 )
+#define ADC1CON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
+#define ADC1CON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
+#define ADC1CON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
+#define ADC1CON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
+
+/* ADC1CON[ADCCP] - AIN+ bits */
+#define ADC1CON_ADCCP_MSK (0x1F << 5 )
+#define ADC1CON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
+#define ADC1CON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
+#define ADC1CON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
+#define ADC1CON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
+#define ADC1CON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
+#define ADC1CON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
+#define ADC1CON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
+#define ADC1CON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
+#define ADC1CON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
+#define ADC1CON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
+#define ADC1CON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
+#define ADC1CON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
+#define ADC1CON_ADCCP_DAC (0xC << 5 ) /* DAC */
+#define ADC1CON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
+#define ADC1CON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
+#define ADC1CON_ADCCP_AGND (0xF << 5 ) /* AGND */
+#define ADC1CON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
+
+/* ADC1CON[ADCCN] - AIN- bits */
+#define ADC1CON_ADCCN_MSK (0x1F << 0 )
+#define ADC1CON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
+#define ADC1CON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
+#define ADC1CON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
+#define ADC1CON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
+#define ADC1CON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
+#define ADC1CON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
+#define ADC1CON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
+#define ADC1CON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
+#define ADC1CON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
+#define ADC1CON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
+#define ADC1CON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
+#define ADC1CON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
+#define ADC1CON_ADCCN_DAC (0xC << 0 ) /* DAC */
+#define ADC1CON_ADCCN_AGND (0xF << 0 ) /* AGND */
+#define ADC1CON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
+
+/* Reset Value for ADC1OF*/
+#define ADC1OF_RVAL 0x0
+
+/* ADC1OF[VALUE] - Offset */
+#define ADC1OF_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC1INTGN*/
+#define ADC1INTGN_RVAL 0x5555
+
+/* ADC1INTGN[VALUE] - Gain with Int Ref */
+#define ADC1INTGN_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC1EXTGN*/
+#define ADC1EXTGN_RVAL 0x5555
+
+/* ADC1EXTGN[VALUE] - Gain with Ext Ref */
+#define ADC1EXTGN_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC1VDDGN*/
+#define ADC1VDDGN_RVAL 0x5555
+
+/* ADC1VDDGN[VALUE] - Gain with Avdd Ref */
+#define ADC1VDDGN_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADCSCFG1*/
+#define ADCSCFG1_RVAL 0xF
+
+/* ADCSCFG1[SIMU] - Enable both ADCs */
+#define ADCSCFG1_SIMU_BBA (*(volatile unsigned long *) 0x426013BC)
+#define ADCSCFG1_SIMU_MSK (0x1 << 15 )
+#define ADCSCFG1_SIMU (0x1 << 15 )
+#define ADCSCFG1_SIMU_DIS (0x0 << 15 ) /* DIS */
+#define ADCSCFG1_SIMU_EN (0x1 << 15 ) /* EN */
+
+/* ADCSCFG1[BOOST30] - Boost the Vbias current source ability by 30 times */
+#define ADCSCFG1_BOOST30_BBA (*(volatile unsigned long *) 0x426013B4)
+#define ADCSCFG1_BOOST30_MSK (0x1 << 13 )
+#define ADCSCFG1_BOOST30 (0x1 << 13 )
+#define ADCSCFG1_BOOST30_DIS (0x0 << 13 ) /* DIS */
+#define ADCSCFG1_BOOST30_EN (0x1 << 13 ) /* EN */
+
+/* ADCSCFG1[PINSEL] - Enable vbias generator, send vbias to selected ain pin bits */
+#define ADCSCFG1_PINSEL_MSK (0x7 << 8 )
+#define ADCSCFG1_PINSEL_DIS (0x0 << 8 ) /* Disable VBIAS generator */
+#define ADCSCFG1_PINSEL_AIN7 (0x4 << 8 ) /* AIN7 */
+#define ADCSCFG1_PINSEL_AIN11 (0x6 << 8 ) /* AIN11 */
+
+/* ADCSCFG1[GNDSWON] - GND_SW */
+#define ADCSCFG1_GNDSWON_BBA (*(volatile unsigned long *) 0x4260139C)
+#define ADCSCFG1_GNDSWON_MSK (0x1 << 7 )
+#define ADCSCFG1_GNDSWON (0x1 << 7 )
+#define ADCSCFG1_GNDSWON_DIS (0x0 << 7 ) /* DIS */
+#define ADCSCFG1_GNDSWON_EN (0x1 << 7 ) /* EN */
+
+/* ADCSCFG1[GNDSWRESEN] - 20k resistor in series with GND_SW */
+#define ADCSCFG1_GNDSWRESEN_BBA (*(volatile unsigned long *) 0x42601398)
+#define ADCSCFG1_GNDSWRESEN_MSK (0x1 << 6 )
+#define ADCSCFG1_GNDSWRESEN (0x1 << 6 )
+#define ADCSCFG1_GNDSWRESEN_DIS (0x0 << 6 ) /* DIS */
+#define ADCSCFG1_GNDSWRESEN_EN (0x1 << 6 ) /* EN */
+
+/* ADCSCFG1[EXTBUF] - Control signals for ext_ref buffers bits */
+#define ADCSCFG1_EXTBUF_MSK (0x3 << 0 )
+#define ADCSCFG1_EXTBUF_OFF (0x0 << 0 ) /* OFF */
+#define ADCSCFG1_EXTBUF_VREFPN (0x1 << 0 ) /* VREFPN */
+#define ADCSCFG1_EXTBUF_VREFP_VREF2P (0x2 << 0 ) /* VREFP_VREF2P */
+
+/* Reset Value for ADC1FLT*/
+#define ADC1FLT_RVAL 0x7D
+
+/* ADC1FLT[CHOP] - Enables System-Chopping bits */
+#define ADC1FLT_CHOP_BBA (*(volatile unsigned long *) 0x4260143C)
+#define ADC1FLT_CHOP_MSK (0x1 << 15 )
+#define ADC1FLT_CHOP (0x1 << 15 )
+#define ADC1FLT_CHOP_OFF (0x0 << 15 ) /* OFF */
+#define ADC1FLT_CHOP_ON (0x1 << 15 ) /* ON */
+
+/* ADC1FLT[RAVG2] - Enables a running Average-By-2 bits */
+#define ADC1FLT_RAVG2_BBA (*(volatile unsigned long *) 0x42601438)
+#define ADC1FLT_RAVG2_MSK (0x1 << 14 )
+#define ADC1FLT_RAVG2 (0x1 << 14 )
+#define ADC1FLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
+#define ADC1FLT_RAVG2_ON (0x1 << 14 ) /* ON */
+
+/* ADC1FLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
+#define ADC1FLT_SINC4EN_BBA (*(volatile unsigned long *) 0x42601430)
+#define ADC1FLT_SINC4EN_MSK (0x1 << 12 )
+#define ADC1FLT_SINC4EN (0x1 << 12 )
+#define ADC1FLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
+#define ADC1FLT_SINC4EN_EN (0x1 << 12 ) /* EN */
+
+/* ADC1FLT[AF] - Averaging filter */
+#define ADC1FLT_AF_MSK (0xF << 8 )
+
+/* ADC1FLT[NOTCH2] - Inserts a notch at FNOTCH2 */
+#define ADC1FLT_NOTCH2_BBA (*(volatile unsigned long *) 0x4260141C)
+#define ADC1FLT_NOTCH2_MSK (0x1 << 7 )
+#define ADC1FLT_NOTCH2 (0x1 << 7 )
+#define ADC1FLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
+#define ADC1FLT_NOTCH2_EN (0x1 << 7 ) /* EN */
+
+/* ADC1FLT[SF] - SINC Filter value */
+#define ADC1FLT_SF_MSK (0x7F << 0 )
+
+/* Reset Value for ADC1MDE*/
+#define ADC1MDE_RVAL 0x0
+
+/* ADC1MDE[PGA] - PGA Gain Select bit */
+#define ADC1MDE_PGA_MSK (0xF << 4 )
+#define ADC1MDE_PGA_G1 (0x0 << 4 ) /* G1 */
+#define ADC1MDE_PGA_G2 (0x1 << 4 ) /* G2 */
+#define ADC1MDE_PGA_G4 (0x2 << 4 ) /* G4 */
+#define ADC1MDE_PGA_G8 (0x3 << 4 ) /* G8 */
+#define ADC1MDE_PGA_G16 (0x4 << 4 ) /* G16 */
+#define ADC1MDE_PGA_G32 (0x5 << 4 ) /* G32 */
+#define ADC1MDE_PGA_G64 (0x6 << 4 ) /* G64 */
+#define ADC1MDE_PGA_G128 (0x7 << 4 ) /* G128 */
+
+/* ADC1MDE[ADCMOD2] - ADC modulator gain of 2 control bits */
+#define ADC1MDE_ADCMOD2_BBA (*(volatile unsigned long *) 0x4260148C)
+#define ADC1MDE_ADCMOD2_MSK (0x1 << 3 )
+#define ADC1MDE_ADCMOD2 (0x1 << 3 )
+#define ADC1MDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
+#define ADC1MDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
+
+/* ADC1MDE[ADCMD] - ADC Mode bits */
+#define ADC1MDE_ADCMD_MSK (0x7 << 0 )
+#define ADC1MDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
+#define ADC1MDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
+#define ADC1MDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
+#define ADC1MDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
+#define ADC1MDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
+#define ADC1MDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
+#define ADC1MDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
+#define ADC1MDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
+
+/* Reset Value for ADC1RCR*/
+#define ADC1RCR_RVAL 0x1
+
+/* ADC1RCR[VALUE] - */
+#define ADC1RCR_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC1RCV*/
+#define ADC1RCV_RVAL 0x0
+
+/* ADC1RCV[VALUE] - */
+#define ADC1RCV_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC1TH*/
+#define ADC1TH_RVAL 0x0
+
+/* ADC1TH[VALUE] - */
+#define ADC1TH_VALUE_MSK (0xFFFF << 0 )
+
+/* Reset Value for ADC1THC*/
+#define ADC1THC_RVAL 0x1
+
+/* ADC1THC[VALUE] - */
+#define ADC1THC_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for ADC1THV*/
+#define ADC1THV_RVAL 0x0
+
+/* ADC1THV[VALUE] - */
+#define ADC1THV_VALUE_MSK (0xFF << 0 )
+
+/* Reset Value for ADC1ACC*/
+#define ADC1ACC_RVAL 0x0
+
+/* ADC1ACC[VALUE] - */
+#define ADC1ACC_VALUE_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for ADC1ATH*/
+#define ADC1ATH_RVAL 0x0
+
+/* ADC1ATH[VALUE] - */
+#define ADC1ATH_VALUE_MSK (0xFFFFFFFF << 0 )
+
+/* Reset Value for ADC1PRO*/
+#define ADC1PRO_RVAL 0x0
+
+/* ADC1PRO[ACCEN] - ADC Accumulator Enable bits */
+#define ADC1PRO_ACCEN_MSK (0x3 << 4 )
+#define ADC1PRO_ACCEN_Off (0x0 << 4 ) /* Off */
+#define ADC1PRO_ACCEN_En (0x1 << 4 ) /* En */
+#define ADC1PRO_ACCEN_EnNDec (0x2 << 4 ) /* EnNDec */
+#define ADC1PRO_ACCEN_EnAccCnt (0x3 << 4 ) /* EnAccCnt */
+
+/* ADC1PRO[CMPEN] - ADC Comparator Enable bits */
+#define ADC1PRO_CMPEN_MSK (0x3 << 2 )
+#define ADC1PRO_CMPEN_Off (0x0 << 2 ) /* Off */
+#define ADC1PRO_CMPEN_En (0x1 << 2 ) /* En */
+#define ADC1PRO_CMPEN_EnCnt (0x2 << 2 ) /* EnCnt */
+#define ADC1PRO_CMPEN_EnCntDec (0x3 << 2 ) /* EnCntDec */
+
+/* ADC1PRO[OREN] - ADC OverRange Enable */
+#define ADC1PRO_OREN_BBA (*(volatile unsigned long *) 0x42601884)
+#define ADC1PRO_OREN_MSK (0x1 << 1 )
+#define ADC1PRO_OREN (0x1 << 1 )
+#define ADC1PRO_OREN_DIS (0x0 << 1 ) /* DIS */
+#define ADC1PRO_OREN_EN (0x1 << 1 ) /* EN */
+
+/* ADC1PRO[RCEN] - ADC Result Counter Enable */
+#define ADC1PRO_RCEN_BBA (*(volatile unsigned long *) 0x42601880)
+#define ADC1PRO_RCEN_MSK (0x1 << 0 )
+#define ADC1PRO_RCEN (0x1 << 0 )
+#define ADC1PRO_RCEN_DIS (0x0 << 0 ) /* DIS */
+#define ADC1PRO_RCEN_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for ADC1DAT*/
+#define ADC1DAT_RVAL 0x0
+
+/* ADC1DAT[VALUE] - */
+#define ADC1DAT_VALUE_MSK (0xFFFFFFFF << 0 )
+// ------------------------------------------------------------------------------------------------
+// ----- ADCSTEP -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Analog to Digital Converter (pADI_ADCSTEP)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_ADCSTEP Structure */
+ __IO uint16_t
+ DETCON; /*!< Control register for reference detection and the step detection filter */
+ __I uint16_t RESERVED0;
+ __IO uint8_t
+ DETSTA; /*!< Status register for detection */
+ __I uint8_t RESERVED1[3];
+ __IO uint16_t
+ STEPTH; /*!< Threshold for step detection filter */
+ __I uint16_t RESERVED2;
+ __IO uint32_t
+ STEPDAT; /*!< Offers coarse data from the output of the step detection filter */
+} ADI_ADCSTEP_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define DETCON (*(volatile unsigned short int *) 0x400300E0)
+#define DETSTA (*(volatile unsigned char *) 0x400300E4)
+#define STEPTH (*(volatile unsigned short int *) 0x400300E8)
+#define STEPDAT (*(volatile unsigned long *) 0x400300EC)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for DETCON*/
+#define DETCON_RVAL 0x0
+
+/* DETCON[REFDET] - Enable external reference detection circuit */
+#define DETCON_REFDET_BBA (*(volatile unsigned long *) 0x42601C20)
+#define DETCON_REFDET_MSK (0x1 << 8 )
+#define DETCON_REFDET (0x1 << 8 )
+#define DETCON_REFDET_DIS (0x0 << 8 ) /* DIS */
+#define DETCON_REFDET_EN (0x1 << 8 ) /* EN */
+
+/* DETCON[SINC2] - Enable Sinc2 filter */
+#define DETCON_SINC2_BBA (*(volatile unsigned long *) 0x42601C1C)
+#define DETCON_SINC2_MSK (0x1 << 7 )
+#define DETCON_SINC2 (0x1 << 7 )
+#define DETCON_SINC2_DIS (0x0 << 7 ) /* DIS */
+#define DETCON_SINC2_EN (0x1 << 7 ) /* EN */
+
+/* DETCON[STEPCTRL] - Control the method to generate the step flag */
+#define DETCON_STEPCTRL_BBA (*(volatile unsigned long *) 0x42601C0C)
+#define DETCON_STEPCTRL_MSK (0x1 << 3 )
+#define DETCON_STEPCTRL (0x1 << 3 )
+#define DETCON_STEPCTRL_DIS (0x0 << 3 ) /* DIS */
+#define DETCON_STEPCTRL_EN (0x1 << 3 ) /* EN */
+
+/* DETCON[ADCSEL] - Select ADC */
+#define DETCON_ADCSEL_BBA (*(volatile unsigned long *) 0x42601C08)
+#define DETCON_ADCSEL_MSK (0x1 << 2 )
+#define DETCON_ADCSEL (0x1 << 2 )
+#define DETCON_ADCSEL_DIS (0x0 << 2 ) /* DIS */
+#define DETCON_ADCSEL_EN (0x1 << 2 ) /* EN */
+
+/* DETCON[RATE] - Control the sinc2 filter's time interval */
+#define DETCON_RATE_MSK (0x3 << 0 )
+
+/* Reset Value for DETSTA*/
+#define DETSTA_RVAL 0x0
+
+/* DETSTA[REFSTA] - */
+#define DETSTA_REFSTA_BBA (*(volatile unsigned long *) 0x42601C90)
+#define DETSTA_REFSTA_MSK (0x1 << 4 )
+#define DETSTA_REFSTA (0x1 << 4 )
+#define DETSTA_REFSTA_DIS (0x0 << 4 ) /* DIS */
+#define DETSTA_REFSTA_EN (0x1 << 4 ) /* EN */
+
+/* DETSTA[DATOF] - STEPDAT Overflow */
+#define DETSTA_DATOF_BBA (*(volatile unsigned long *) 0x42601C8C)
+#define DETSTA_DATOF_MSK (0x1 << 3 )
+#define DETSTA_DATOF (0x1 << 3 )
+#define DETSTA_DATOF_DIS (0x0 << 3 ) /* DIS */
+#define DETSTA_DATOF_EN (0x1 << 3 ) /* EN */
+
+/* DETSTA[STEPERR] - */
+#define DETSTA_STEPERR_BBA (*(volatile unsigned long *) 0x42601C88)
+#define DETSTA_STEPERR_MSK (0x1 << 2 )
+#define DETSTA_STEPERR (0x1 << 2 )
+#define DETSTA_STEPERR_DIS (0x0 << 2 ) /* DIS */
+#define DETSTA_STEPERR_EN (0x1 << 2 ) /* EN */
+
+/* DETSTA[STEPFLAG] - */
+#define DETSTA_STEPFLAG_BBA (*(volatile unsigned long *) 0x42601C84)
+#define DETSTA_STEPFLAG_MSK (0x1 << 1 )
+#define DETSTA_STEPFLAG (0x1 << 1 )
+#define DETSTA_STEPFLAG_DIS (0x0 << 1 ) /* DIS */
+#define DETSTA_STEPFLAG_EN (0x1 << 1 ) /* EN */
+
+/* DETSTA[STEPDATRDY] - */
+#define DETSTA_STEPDATRDY_BBA (*(volatile unsigned long *) 0x42601C80)
+#define DETSTA_STEPDATRDY_MSK (0x1 << 0 )
+#define DETSTA_STEPDATRDY (0x1 << 0 )
+#define DETSTA_STEPDATRDY_DIS (0x0 << 0 ) /* DIS */
+#define DETSTA_STEPDATRDY_EN (0x1 << 0 ) /* EN */
+
+/* Reset Value for STEPTH*/
+#define STEPTH_RVAL 0x0
+
+/* STEPTH[VALUE] - */
+#define STEPTH_VALUE_MSK (0x1FF << 0 )
+
+/* Reset Value for STEPDAT*/
+#define STEPDAT_RVAL 0x0
+
+/* STEPDAT[VALUE] - */
+#define STEPDAT_VALUE_MSK (0xFFFFFFFF << 0 )
+// ------------------------------------------------------------------------------------------------
+// ----- ADCDMA -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Analog to Digital Converter (pADI_ADCDMA)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_ADCDMA Structure */
+ __I uint32_t RESERVED0[2];
+ __IO uint16_t
+ ADCDMACON; /*!< ADC DMA mode Configuration register */
+ __I uint16_t RESERVED1;
+} ADI_ADCDMA_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define ADCDMACON (*(volatile unsigned short int *) 0x400300F8)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for ADCDMACON*/
+#define ADCDMACON_RVAL 0x0
+
+/* ADCDMACON[SINC2DMAEN] - */
+#define ADCDMACON_SINC2DMAEN_BBA (*(volatile unsigned long *) 0x42601F10)
+#define ADCDMACON_SINC2DMAEN_MSK (0x1 << 4 )
+#define ADCDMACON_SINC2DMAEN (0x1 << 4 )
+#define ADCDMACON_SINC2DMAEN_DIS (0x0 << 4 ) /* DIS */
+#define ADCDMACON_SINC2DMAEN_EN (0x1 << 4 ) /* EN */
+
+/* ADCDMACON[ADC1DMAEN] - */
+#define ADCDMACON_ADC1DMAEN_BBA (*(volatile unsigned long *) 0x42601F0C)
+#define ADCDMACON_ADC1DMAEN_MSK (0x1 << 3 )
+#define ADCDMACON_ADC1DMAEN (0x1 << 3 )
+#define ADCDMACON_ADC1DMAEN_DIS (0x0 << 3 ) /* DIS */
+#define ADCDMACON_ADC1DMAEN_EN (0x1 << 3 ) /* EN */
+
+/* ADCDMACON[ADC1CTRL] - */
+#define ADCDMACON_ADC1CTRL_BBA (*(volatile unsigned long *) 0x42601F08)
+#define ADCDMACON_ADC1CTRL_MSK (0x1 << 2 )
+#define ADCDMACON_ADC1CTRL (0x1 << 2 )
+#define ADCDMACON_ADC1CTRL_DIS (0x0 << 2 ) /* DIS */
+#define ADCDMACON_ADC1CTRL_EN (0x1 << 2 ) /* EN */
+
+/* ADCDMACON[ADC0DMAEN] - */
+#define ADCDMACON_ADC0DMAEN_BBA (*(volatile unsigned long *) 0x42601F04)
+#define ADCDMACON_ADC0DMAEN_MSK (0x1 << 1 )
+#define ADCDMACON_ADC0DMAEN (0x1 << 1 )
+#define ADCDMACON_ADC0DMAEN_DIS (0x0 << 1 ) /* DIS */
+#define ADCDMACON_ADC0DMAEN_EN (0x1 << 1 ) /* EN */
+
+/* ADCDMACON[ADC0CTRL] - */
+#define ADCDMACON_ADC0CTRL_BBA (*(volatile unsigned long *) 0x42601F00)
+#define ADCDMACON_ADC0CTRL_MSK (0x1 << 0 )
+#define ADCDMACON_ADC0CTRL (0x1 << 0 )
+#define ADCDMACON_ADC0CTRL_DIS (0x0 << 0 ) /* DIS */
+#define ADCDMACON_ADC0CTRL_EN (0x1 << 0 ) /* EN */
+// ------------------------------------------------------------------------------------------------
+// ----- DAC -----
+// ------------------------------------------------------------------------------------------------
+
+
+/**
+ * @brief Digital To Analog Converter (pADI_DAC)
+ */
+
+#if (__NO_MMR_STRUCTS__==0)
+typedef struct { /*!< pADI_DAC Structure */
+ __IO uint16_t
+ DACCON; /*!< Control Register */
+ __I uint16_t RESERVED0;
+ __IO uint32_t
+ DACDAT; /*!< Data Register */
+} ADI_DAC_TypeDef;
+#else // (__NO_MMR_STRUCTS__==0)
+#define DACCON (*(volatile unsigned short int *) 0x40020000)
+#define DACDAT (*(volatile unsigned long *) 0x40020004)
+#endif // (__NO_MMR_STRUCTS__==0)
+
+/* Reset Value for DACCON*/
+#define DACCON_RVAL 0x200
+
+/* DACCON[DMAEN] - bits */
+#define DACCON_DMAEN_BBA (*(volatile unsigned long *) 0x42400028)
+#define DACCON_DMAEN_MSK (0x1 << 10 )
+#define DACCON_DMAEN (0x1 << 10 )
+#define DACCON_DMAEN_Off (0x0 << 10 ) /* Off */
+#define DACCON_DMAEN_On (0x1 << 10 ) /* On */
+
+/* DACCON[PD] - */
+#define DACCON_PD_BBA (*(volatile unsigned long *) 0x42400024)
+#define DACCON_PD_MSK (0x1 << 9 )
+#define DACCON_PD (0x1 << 9 )
+#define DACCON_PD_DIS (0x0 << 9 ) /* DIS */
+#define DACCON_PD_EN (0x1 << 9 ) /* EN */
+
+/* DACCON[NPN] - */
+#define DACCON_NPN_BBA (*(volatile unsigned long *) 0x42400020)
+#define DACCON_NPN_MSK (0x1 << 8 )
+#define DACCON_NPN (0x1 << 8 )
+#define DACCON_NPN_DIS (0x0 << 8 ) /* DIS */
+#define DACCON_NPN_EN (0x1 << 8 ) /* EN */
+
+/* DACCON[BUFBYP] - */
+#define DACCON_BUFBYP_BBA (*(volatile unsigned long *) 0x42400018)
+#define DACCON_BUFBYP_MSK (0x1 << 6 )
+#define DACCON_BUFBYP (0x1 << 6 )
+#define DACCON_BUFBYP_DIS (0x0 << 6 ) /* DIS */
+#define DACCON_BUFBYP_EN (0x1 << 6 ) /* EN */
+
+/* DACCON[CLK] - bits */
+#define DACCON_CLK_BBA (*(volatile unsigned long *) 0x42400014)
+#define DACCON_CLK_MSK (0x1 << 5 )
+#define DACCON_CLK (0x1 << 5 )
+#define DACCON_CLK_HCLK (0x0 << 5 ) /* HCLK */
+#define DACCON_CLK_Timer1 (0x1 << 5 ) /* Timer1 */
+
+/* DACCON[CLR] - bits */
+#define DACCON_CLR_BBA (*(volatile unsigned long *) 0x42400010)
+#define DACCON_CLR_MSK (0x1 << 4 )
+#define DACCON_CLR (0x1 << 4 )
+#define DACCON_CLR_Off (0x1 << 4 ) /* Off */
+#define DACCON_CLR_On (0x0 << 4 ) /* On */
+
+/* DACCON[MDE] - Mode bits */
+#define DACCON_MDE_MSK (0x3 << 2 )
+#define DACCON_MDE_12bit (0x0 << 2 ) /* 12bit */
+#define DACCON_MDE_16BitSlow (0x3 << 2 ) /* 16BitSlow */
+#define DACCON_MDE_16BitFast (0x2 << 2 ) /* 16BitFast */
+
+/* DACCON[RNG] - DAC Range bits */
+#define DACCON_RNG_MSK (0x3 << 0 )
+#define DACCON_RNG_IntVref (0x0 << 0 ) /* IntVref */
+#define DACCON_RNG_AVdd (0x3 << 0 ) /* AVdd */
+
+/* Reset Value for DACDAT*/
+#define DACDAT_RVAL 0x0
+
+/* DACDAT[VALUE] - Data */
+#define DACDAT_VALUE_MSK (0xFFFFF << 12 )
+/********************************************
+** End of section using anonymous unions **
+*********************************************/
+
+#if defined(__ARMCC_VERSION)
+#pragma pop
+#elif defined(__CWCC__)
+#pragma pop
+#elif defined(__GNUC__)
+/* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma language=default
+#else
+#error Not supported compiler type
+#endif
+
+/********************************************
+** Miscellaneous Definitions **
+*********************************************/
+
+//iEiNr in EiCfg()
+#define EXTINT0 0x0
+#define EXTINT1 0x1
+#define EXTINT2 0x2
+#define EXTINT3 0x3
+#define EXTINT4 0x4
+#define EXTINT5 0x5
+#define EXTINT6 0x6
+#define EXTINT7 0x7
+#define EXTINT8 0x8
+
+//iEnable in EiCfg()
+#define INT_DIS 0x0
+#define INT_EN 0x1
+
+//iMode in EiCfg()
+#define INT_RISE 0x0
+#define INT_FALL 0x1
+#define INT_EDGES 0x2
+#define INT_HIGH 0x3
+#define INT_LOW 0x4
+
+//Bit values.
+#define BIT0 1
+#define BIT1 2
+#define BIT2 4
+#define BIT3 8
+#define BIT4 0x10
+#define BIT5 0x20
+#define BIT6 0x40
+#define BIT7 0x80
+
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral memory map -----
+// ------------------------------------------------------------------------------------------------
+#define ADI_TM0_ADDR 0x40000000
+#define ADI_TM1_ADDR 0x40000400
+#define ADI_PWM_ADDR 0x40001000
+#define ADI_PWRCTL_ADDR 0x40002400
+#define ADI_RESET_ADDR 0x40002440
+#define ADI_INTERRUPT_ADDR 0x40002420
+#define ADI_WDT_ADDR 0x40002580
+#define ADI_WUT_ADDR 0x40002500
+#define ADI_CLKCTL_ADDR 0x40002000
+#define ADI_FEE_ADDR 0x40002800
+#define ADI_I2C_ADDR 0x40003000
+#define ADI_SPI0_ADDR 0x40004000
+#define ADI_SPI1_ADDR 0x40004400
+#define ADI_UART_ADDR 0x40005000
+#define ADI_GP0_ADDR 0x40006000
+#define ADI_GP1_ADDR 0x40006030
+#define ADI_GP2_ADDR 0x40006060
+#define ADI_ANA_ADDR 0x40008810
+#define ADI_DMA_ADDR 0x40010000
+#define ADI_NVIC_ADDR 0xE000E000
+#define ADI_ADC0_ADDR 0x40030000
+#define ADI_ADC1_ADDR 0x40030080
+#define ADI_ADCSTEP_ADDR 0x400300E0
+#define ADI_ADCTEST_ADDR 0x40030050
+#define ADI_ADCDMA_ADDR 0x400300F0
+#define ADI_EREFBUF_ADDR 0x400300D0
+#define ADI_DAC_ADDR 0x40020000
+
+// ------------------------------------------------------------------------------------------------
+// ----- Peripheral declaration -----
+// ------------------------------------------------------------------------------------------------
+#define pADI_TM0 ((ADI_TIMER_TypeDef *)ADI_TM0_ADDR)
+#define pADI_TM1 ((ADI_TIMER_TypeDef *)ADI_TM1_ADDR)
+#define pADI_PWM ((ADI_PWM_TypeDef *)ADI_PWM_ADDR)
+#define pADI_PWRCTL ((ADI_PWRCTL_TypeDef *)ADI_PWRCTL_ADDR)
+#define pADI_RESET ((ADI_RESET_TypeDef *)ADI_RESET_ADDR)
+#define pADI_INTERRUPT ((ADI_INTERRUPT_TypeDef *)ADI_INTERRUPT_ADDR)
+#define pADI_WDT ((ADI_WDT_TypeDef *)ADI_WDT_ADDR)
+#define pADI_WUT ((ADI_WUT_TypeDef *)ADI_WUT_ADDR)
+#define pADI_CLKCTL ((ADI_CLKCTL_TypeDef *)ADI_CLKCTL_ADDR)
+#define pADI_FEE ((ADI_FEE_TypeDef *)ADI_FEE_ADDR)
+#define pADI_I2C ((ADI_I2C_TypeDef *)ADI_I2C_ADDR)
+#define pADI_SPI0 ((ADI_SPI_TypeDef *)ADI_SPI0_ADDR)
+#define pADI_SPI1 ((ADI_SPI_TypeDef *)ADI_SPI1_ADDR)
+#define pADI_UART ((ADI_UART_TypeDef *)ADI_UART_ADDR)
+#define pADI_GP0 ((ADI_GPIO_TypeDef *)ADI_GP0_ADDR)
+#define pADI_GP1 ((ADI_GPIO_TypeDef *)ADI_GP1_ADDR)
+#define pADI_GP2 ((ADI_GPIO_TypeDef *)ADI_GP2_ADDR)
+#define pADI_ANA ((ADI_ANA_TypeDef *)ADI_ANA_ADDR)
+#define pADI_DMA ((ADI_DMA_TypeDef *)ADI_DMA_ADDR)
+#define pADI_ADC0 ((ADI_ADC_TypeDef *)ADI_ADC0_ADDR)
+#define pADI_ADC1 ((ADI_ADC_TypeDef *)ADI_ADC1_ADDR)
+#define pADI_ADCSTEP ((ADI_ADCSTEP_TypeDef *)ADI_ADCSTEP_ADDR)
+#define pADI_ADCDMA ((ADI_ADCDMA_TypeDef *)ADI_ADCDMA_ADDR)
+#define pADI_DAC ((ADI_DAC_TypeDef *)ADI_DAC_ADDR)
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group ADUCM360 */
+/** @} */ /* End of group CMSIS */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // __ADUCM360_H__
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/arm_common_tables.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/arm_common_tables.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/arm_common_tables.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. October 2015
+* $Revision: V.1.4.5 a
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t
+armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t
+armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t
+armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /* ARM_COMMON_TABLES_H */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/arm_const_structs.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/arm_const_structs.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/arm_const_structs.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/arm_math.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/arm_math.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/arm_math.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,7076 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+*
+* $Date: 20. October 2015
+* $Revision: V1.4.5 b
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * Introduction
+ * ------------
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * Using the Library
+ * ------------
+ *
+ * The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
+ *
+ * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * Examples
+ * --------
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * Toolchain Support
+ * ------------
+ *
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * Building the Library
+ * ------------
+ *
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
+ *
+ *
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
+ *
+ * Pre-processor Macros
+ * ------------
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
+ *
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size numRows X numCols
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ *
+ * pData[i*numCols + j]
+ *
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ *
+ * ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return
+ *
+ * ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ *
+ * ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined(ARM_MATH_CM7)
+#include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+/**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+/**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
+
+/**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+/* 1.31(q31) Fixed value of 2/360 */
+/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+/**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+#define ALIGN4
+#else
+#if defined (__GNUC__)
+#define ALIGN4 __attribute__((aligned(4)))
+#else
+#define ALIGN4 __align(4)
+#endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @brief Error status returned by some functions in the library.
+ */
+
+typedef enum {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+} arm_status;
+
+/**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+typedef int8_t q7_t;
+
+/**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+typedef int16_t q15_t;
+
+/**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+typedef int32_t q31_t;
+
+/**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+typedef int64_t q63_t;
+
+/**
+ * @brief 32-bit floating-point type definition.
+ */
+typedef float float32_t;
+
+/**
+ * @brief 64-bit floating-point type definition.
+ */
+typedef double float64_t;
+
+/**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+
+#elif defined __ICCARM__
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED
+
+#elif defined __CSMC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED
+
+#elif defined __TASKING__
+#define __SIMD32_TYPE __unaligned int32_t
+#define CMSIS_UNUSED
+
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+/**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+/**
+* @brief definition to pack four 8 bit values.
+*/
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+/**
+ * @brief Clips Q63 to Q31 values.
+ */
+static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+{
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+}
+
+/**
+ * @brief Clips Q63 to Q15 values.
+ */
+static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+{
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+}
+
+/**
+ * @brief Clips Q31 to Q7 values.
+ */
+static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+{
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+}
+
+/**
+ * @brief Clips Q31 to Q15 values.
+ */
+static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+{
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+}
+
+/**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+{
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+}
+
+/*
+ #if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+ #define __CLZ __clz
+ #endif
+ */
+/* note: function can be removed when all toolchain support __CLZ for Cortex-M0 */
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
+static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+static __INLINE uint32_t __CLZ(
+ q31_t data)
+{
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0) {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+}
+#endif
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+{
+ q31_t out;
+ uint32_t tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0) {
+ signBits = ((uint32_t) (__CLZ( in) - 1));
+ } else {
+ signBits = ((uint32_t) (__CLZ(-in) - 1));
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 24);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++) {
+ tempVal = (uint32_t) (((q63_t) in * out) >> 31);
+ tempVal = 0x7FFFFFFFu - tempVal;
+ /* 1.31 with exp 1 */
+ /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
+ out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+}
+
+
+/**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+{
+ q15_t out = 0;
+ uint32_t tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0) {
+ signBits = ((uint32_t)(__CLZ( in) - 17));
+ } else {
+ signBits = ((uint32_t)(__CLZ(-in) - 17));
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = (in << signBits);
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t)(in >> 8);
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++) {
+ tempVal = (uint32_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFFu - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+}
+
+
+/*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+{
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++) {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0) {
+ posMax = (posMax - 1);
+
+ if(x > posMax) {
+ x = posMax;
+ }
+ } else {
+ negMin = -posMax;
+
+ if(x < negMin) {
+ x = negMin;
+ }
+ }
+ return (x);
+}
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+/*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+/*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+static __INLINE uint32_t __QADD8(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)),
+ 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)),
+ 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)),
+ 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)),
+ 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+static __INLINE uint32_t __QSUB8(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s, t, u;
+
+ r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)),
+ 8) & (int32_t)0x000000FF;
+ s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)),
+ 8) & (int32_t)0x000000FF;
+ t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)),
+ 8) & (int32_t)0x000000FF;
+ u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)),
+ 8) & (int32_t)0x000000FF;
+
+ return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+static __INLINE uint32_t __QADD16(
+ uint32_t x,
+ uint32_t y)
+{
+ /* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
+ q31_t r = 0, s = 0;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+static __INLINE uint32_t __SHADD16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+static __INLINE uint32_t __QSUB16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+static __INLINE uint32_t __SHSUB16(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+static __INLINE uint32_t __QASX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+static __INLINE uint32_t __SHASX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+static __INLINE uint32_t __QSAX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+ s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)),
+ 16) & (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+static __INLINE uint32_t __SHSAX(
+ uint32_t x,
+ uint32_t y)
+{
+ q31_t r, s;
+
+ r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+ s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) &
+ (int32_t)0x0000FFFF;
+
+ return ((uint32_t)((s << 16) | (r )));
+}
+
+
+/*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+static __INLINE uint32_t __SMUSDX(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+}
+
+/*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+static __INLINE uint32_t __SMUADX(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+static __INLINE int32_t __QADD(
+ int32_t x,
+ int32_t y)
+{
+ return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+static __INLINE int32_t __QSUB(
+ int32_t x,
+ int32_t y)
+{
+ return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
+}
+
+
+/*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+static __INLINE uint32_t __SMLAD(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+static __INLINE uint32_t __SMLADX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+static __INLINE uint32_t __SMLSDX(
+ uint32_t x,
+ uint32_t y,
+ uint32_t sum)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q31_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+static __INLINE uint64_t __SMLALD(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+{
+ /* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+static __INLINE uint64_t __SMLALDX(
+ uint32_t x,
+ uint32_t y,
+ uint64_t sum)
+{
+ /* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
+ return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ( ((q63_t)sum ) ) ));
+}
+
+
+/*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+static __INLINE uint32_t __SMUAD(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+static __INLINE uint32_t __SMUSD(
+ uint32_t x,
+ uint32_t y)
+{
+ return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
+ ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
+}
+
+
+/*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+static __INLINE uint32_t __SXTB16(
+ uint32_t x)
+{
+ return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
+ ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
+}
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+/**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q7;
+
+/**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+} arm_fir_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+} arm_fir_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] S points to an instance of the Q7 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ */
+void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] S points to an instance of the Q15 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * numTaps is not a supported value.
+ */
+arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] S points to an instance of the Q31 FIR filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] S points to an instance of the floating-point FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ */
+void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+typedef struct {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q15;
+
+/**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+typedef struct {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+} arm_biquad_casd_df1_inst_q31;
+
+/**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+typedef struct {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_casd_df1_inst_f32;
+
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+
+/**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_f32;
+
+
+/**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_f64;
+
+/**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+} arm_matrix_instance_q31;
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+/**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+/**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+
+/**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+/**
+ * @brief Q15 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+
+/**
+ * @brief Q31 matrix transpose.
+ * @param[in] pSrc points to the input matrix
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either ARM_MATH_SIZE_MISMATCH
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+/**
+ * @brief Floating-point matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @param[in] pState points to the array for storing intermediate results
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+
+/**
+ * @brief Q15 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+
+/**
+ * @brief Q31 matrix subtraction
+ * @param[in] pSrcA points to the first input matrix structure
+ * @param[in] pSrcB points to the second input matrix structure
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in] pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] pDst points to the output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in] pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+/**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+
+/**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+
+/**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] pData points to the matrix data array.
+ */
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+/**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+typedef struct {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+} arm_pid_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+typedef struct {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+} arm_pid_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+typedef struct {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+} arm_pid_instance_f32;
+
+
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ */
+void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ */
+
+void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+
+/**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ */
+void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+
+/**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the q15 PID Control structure
+ */
+void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+/**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+typedef struct {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+} arm_linear_interp_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_f32;
+
+/**
+* @brief Instance structure for the Q31 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q31;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q15;
+
+/**
+* @brief Instance structure for the Q15 bilinear interpolation function.
+*/
+typedef struct {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+} arm_bilinear_interp_instance_q7;
+
+
+/**
+ * @brief Q7 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+/**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q15;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+/**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix2_instance_q31;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+/**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+} arm_cfft_radix4_instance_q31;
+
+/* Deprecated */
+void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+} arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+} arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+typedef struct {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+} arm_cfft_instance_f32;
+
+void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q15
+ *pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_q15;
+
+arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+/**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ const arm_cfft_instance_q31
+ *pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_q31;
+
+arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32
+ *pCfft; /**< points to the complex FFT instance. */
+} arm_rfft_instance_f32;
+
+arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+/**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+typedef struct {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+} arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+/**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_f32;
+
+
+/**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+ */
+arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q31;
+
+
+/**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q31 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+
+/**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+typedef struct {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+} arm_dct4_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+ */
+arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] S points to an instance of the Q15 DCT4 structure.
+ * @param[in] pState points to state buffer.
+ * @param[in,out] pInlineBuffer points to the in-place input and output buffer.
+ */
+void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] pSrc points to the input buffer
+ * @param[out] pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ */
+void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] result output result returned here
+ */
+void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ */
+void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ */
+void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ */
+void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+* @brief Convolution of Q7 sequences.
+* @param[in] pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+* @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+* @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+*/
+void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1.
+ */
+void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+typedef struct {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+} arm_fir_decimate_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * blockSize is not a multiple of M.
+ */
+arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+} arm_fir_interpolate_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+typedef struct {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+} arm_fir_interpolate_instance_f32;
+
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] pCoeffs points to the filter coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length numTaps is not a multiple of the interpolation factor L.
+ */
+arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+} arm_biquad_cas_df1_32x64_ins_q31;
+
+
+/**
+ * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ */
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_stereo_df2T_instance_f32;
+
+/**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+typedef struct {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+} arm_biquad_cascade_df2T_instance_f64;
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] S points to an instance of the filter data structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] pCoeffs points to the filter coefficients.
+ * @param[in] pState points to the state buffer.
+ */
+void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
+/**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+} arm_fir_lattice_instance_f32;
+
+
+/**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] pState points to the state buffer. The array is of length numStages.
+ */
+void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+/**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q15;
+
+/**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_q31;
+
+/**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+typedef struct {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+} arm_iir_lattice_instance_f32;
+
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ */
+void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+} arm_lms_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+} arm_lms_instance_q15;
+
+
+/**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to the coefficient buffer.
+ * @param[in] pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+} arm_lms_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q15 LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+
+/**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_f32;
+
+
+/**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_q31;
+
+
+/**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+} arm_lms_norm_instance_q15;
+
+
+/**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[in] pRef points to the block of reference data.
+ * @param[out] pOut points to the block of output data.
+ * @param[out] pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ */
+void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] pCoeffs points to coefficient buffer.
+ * @param[in] pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ */
+void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+/**
+* @brief Correlation of Q15 sequences
+* @param[in] pSrcA points to the first input sequence.
+* @param[in] srcALen length of the first input sequence.
+* @param[in] pSrcB points to the second input sequence.
+* @param[in] srcBLen length of the second input sequence.
+* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+* @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+*/
+void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+
+void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ */
+void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ */
+void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ */
+void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+/**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_f32;
+
+/**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q31;
+
+/**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q15;
+
+/**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+typedef struct {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+} arm_fir_sparse_instance_q7;
+
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] pSrc points to the block of input data.
+ * @param[out] pDst points to the block of output data
+ * @param[in] pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ */
+void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] pCoeffs points to the array of filter coefficients.
+ * @param[in] pState points to the state buffer.
+ * @param[in] pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ */
+void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cos output.
+ */
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal);
+
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] pSinVal points to the processed sine output.
+ * @param[out] pCosVal points to the processed cosine output.
+ */
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param[in] pSrc points to the input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * S points to an instance of the PID control data structure. in
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ *
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+{
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+}
+
+/**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+{
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+
+/**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+{
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+}
+
+/**
+ * @} end of PID group
+ */
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] src points to the instance of the input floating-point matrix structure.
+ * @param[out] dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+ * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+ * When Ialpha is superposed with Ia as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+ * can be calculated using only Ia and Ib.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where Ia and Ib are the instantaneous stator phases and
+ * pIalpha and pIbeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup clarke
+ * @{
+ */
+
+/**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ */
+static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+}
+
+
+/**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate a
+ * @param[in] Ib input three-phase coordinate b
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+{
+ q31_t product1,
+ product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+}
+
+/**
+ * @} end of clarke group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where pIa and pIb are the instantaneous stator phases and
+ * Ialpha and Ibeta are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Clarke transform
+* @param[in] Ialpha input two-phase orthogonal vector axis alpha
+* @param[in] Ibeta input two-phase orthogonal vector axis beta
+* @param[out] pIa points to output three-phase coordinate a
+* @param[out] pIb points to output three-phase coordinate b
+*/
+static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+{
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
+}
+
+
+/**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] pIa points to output three-phase coordinate a
+ * @param[out] pIb points to output three-phase coordinate b
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+{
+ q31_t product1,
+ product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+}
+
+/**
+ * @} end of inv_clarke group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] pSrc input pointer
+ * @param[out] pDst output pointer
+ * @param[in] blockSize number of samples to process
+ */
+void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where Ialpha and Ibeta are the stator vector components,
+ * pId and pIq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup park
+ * @{
+ */
+
+/**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+}
+
+
+/**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] pId points to output rotor reference frame d
+ * @param[out] pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+ q31_t product1,
+ product2; /* Temporary variables used to store intermediate results */
+ q31_t product3,
+ product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+}
+
+/**
+ * @} end of park group
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where pIalpha and pIbeta are the stator vector components,
+ * Id and Iq are rotor vector components and cosVal and sinVal are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup inv_park
+ * @{
+ */
+
+/**
+* @brief Floating-point Inverse Park transform
+* @param[in] Id input coordinate of rotor reference frame d
+* @param[in] Iq input coordinate of rotor reference frame q
+* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+* @param[in] sinVal sine value of rotation angle theta
+* @param[in] cosVal cosine value of rotation angle theta
+*/
+static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+{
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+}
+
+
+/**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ *
+ * Scaling and Overflow Behavior:
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+{
+ q31_t product1,
+ product2; /* Temporary variables used to store intermediate results */
+ q31_t product3,
+ product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+}
+
+/**
+ * @} end of Inverse park group
+ */
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ *
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ *
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * S points to an instance of the Linear Interpolate function data structure.
+ * x is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+/**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+/**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+{
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0) {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ } else if((uint32_t)i >= S->nValues) {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ } else {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+}
+
+
+/**
+*
+* @brief Process function for the Q31 Linear Interpolation Function.
+* @param[in] pYData pointer to Q31 Linear Interpolation table
+* @param[in] x input sample to process
+* @param[in] nValues number of table values
+* @return y processed output sample.
+*
+* \par
+* Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+* This function can support maximum of table size 2^12.
+*
+*/
+static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (q31_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+ } else if(index < 0) {
+ return (pYData[0]);
+ } else {
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & (int32_t)0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1)) {
+ return (pYData[nValues - 1]);
+ } else if(index < 0) {
+ return (pYData[0]);
+ } else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (q15_t) (y >> 20);
+ }
+}
+
+
+/**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+{
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0) {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+ if(index >= (nValues - 1)) {
+ return (pYData[nValues - 1]);
+ } else {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (q7_t) (y >> 20);
+ }
+}
+
+/**
+ * @} end of LinearInterpolate group
+ */
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+float32_t arm_sin_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q31_t arm_sin_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+q15_t arm_sin_q15(
+ q15_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+float32_t arm_cos_f32(
+ float32_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q31_t arm_cos_q31(
+ q31_t x);
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+q15_t arm_cos_q15(
+ q15_t x);
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+
+/**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ *
+ * x1 = x0 - f(x0)/f'(x0)
+ *
+ * where x1 is the current estimate,
+ * x0 is the previous estimate, and
+ * f'(x0) is the derivative of f() evaluated at x0.
+ * For the square root function, the algorithm reduces to:
+ *
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ *
+ */
+
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+{
+ if(in >= 0.0f) {
+
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined(__GNUC__)
+ *pOut = __builtin_sqrtf(in);
+#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)
+ __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ } else {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+
+/**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+
+/**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * in is negative value and returns zero output for negative values.
+ */
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+/**
+ * @} end of SQRT group
+ */
+
+
+/**
+ * @brief floating-point Circular write function.
+ */
+static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+
+/**
+ * @brief floating-point Circular Read function.
+ */
+static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q15 Circular write function.
+ */
+static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q15 Circular Read function.
+ */
+static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Q7 Circular write function.
+ */
+static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u) {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = (uint16_t)wOffset;
+}
+
+
+/**
+ * @brief Q7 Circular Read function.
+ */
+static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+{
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u) {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end) {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L) {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+}
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output value.
+ */
+void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+
+/**
+ * @brief Floating-point complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param[in] pSrc points to the complex input vector
+ * @param[out] pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ */
+void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q15 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+
+/**
+ * @brief Q31 complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+
+/**
+ * @brief Floating-point complex dot product
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] realResult real part of the result returned here
+ * @param[out] imagResult imaginary part of the result returned here
+ */
+void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] pSrcCmplx points to the complex input vector
+ * @param[in] pSrcReal points to the real input vector
+ * @param[out] pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ */
+void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[in] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] pResult is output pointer
+ * @param[out] pIndex is the array index of the minimum value in the input buffer.
+ */
+void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] pResult maximum value returned here
+ * @param[out] pIndex index of maximum value returned here
+ */
+void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] pSrcA points to the first input vector
+ * @param[in] pSrcB points to the second input vector
+ * @param[out] pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ */
+void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] pSrc points to the floating-point input vector
+ * @param[out] pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ */
+void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] pSrc is input pointer
+ * @param[out] pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ */
+void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @ingroup groupInterpolation
+ */
+
+/**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * Algorithm
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ *
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ *
+ *
+ * \par
+ * where numRows specifies the number of rows in the table;
+ * numCols specifies the number of columns in the table;
+ * and pData points to an array of size numRows*numCols values.
+ * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+ *
+ * \par
+ * Let (x, y) specify the desired interpolation point. Then define:
+ *
+ * XF = floor(x)
+ * YF = floor(y)
+ *
+ * \par
+ * The interpolated output point is computed as:
+ *
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ *
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+/**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+
+/**
+*
+* @brief Floating-point bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate.
+* @param[in] Y interpolation coordinate.
+* @return out interpolated value.
+*/
+static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+{
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+}
+
+
+/**
+*
+* @brief Q31 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+{
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData =
+ S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + (int32_t)nCols * (cI) ];
+ x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ];
+ y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return ((q31_t)(acc << 2));
+}
+
+
+/**
+* @brief Q15 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData =
+ S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return ((q15_t)(acc >> 36));
+}
+
+
+/**
+* @brief Q7 bilinear interpolation.
+* @param[in,out] S points to an instance of the interpolation structure.
+* @param[in] X interpolation coordinate in 12.20 format.
+* @param[in] Y interpolation coordinate in 12.20 format.
+* @return out interpolated value.
+*/
+static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+{
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData =
+ S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & (q31_t)0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & (q31_t)0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ];
+ x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & (q31_t)0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ];
+ y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return ((q7_t)(acc >> 40));
+}
+
+/**
+ * @} end of BilinearInterpolate group
+ */
+
+
+/* SMMLAR */
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMLSR */
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+/* SMMULR */
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+/* SMMLA */
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMLS */
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+/* SMMUL */
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM )
+/* Enter low optimization region - place directly above function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+#else
+#define LOW_OPTIMIZATION_EXIT
+#endif
+
+/* Enter low optimization region - place directly above function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__)
+/* Enter low optimization region - place directly above function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+#else
+#define LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define LOW_OPTIMIZATION_EXIT
+
+/* Enter low optimization region - place directly above function definition */
+#if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+#else
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#endif
+
+/* Exit low optimization region - place directly after end of function definition */
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__CSMC__)
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__)
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* _ARM_MATH_H */
+
+/**
+ *
+ * End of file.
+ */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_armcc.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_armcc.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_armcc.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,736 @@
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(
+ uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(
+ int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+#define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXB(value, ptr) __strex(value, ptr)
+#else
+#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#else
+#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+#define __STREXW(value, ptr) __strex(value, ptr)
+#else
+#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(
+ uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_armcc_V6.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_armcc_V6.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_armcc_V6.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,1908 @@
+/**************************************************************************//**
+ * @file cmsis_armcc_V6.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_V6_H
+#define __CMSIS_ARMCC_V6_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Control Register (non-secure)
+ \details Returns the content of the non-secure Control Register when in secure mode.
+ \return non-secure Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(
+ void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(
+ uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Control Register (non-secure)
+ \details Writes the given value to the non-secure Control Register when in secure state.
+ \param [in] control Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(
+ uint32_t control)
+{
+ __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get IPSR Register (non-secure)
+ \details Returns the content of the non-secure IPSR Register when in secure state.
+ \return IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_IPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get APSR Register (non-secure)
+ \details Returns the content of the non-secure APSR Register when in secure state.
+ \return APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_APSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get xPSR Register (non-secure)
+ \details Returns the content of the non-secure xPSR Register when in secure state.
+ \return xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_xPSR_NS(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Process Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+ \return PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(
+ uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(
+ uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Main Stack Pointer (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+ \return MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(
+ uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : "sp");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Main Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(
+ uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : "sp");
+}
+#endif
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Priority Mask (non-secure)
+ \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+ \return Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(
+ void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(
+ uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Priority Mask (non-secure)
+ \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+ \param [in] priMask Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(
+ uint32_t priMask)
+{
+ __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Base Priority (non-secure)
+ \details Returns the current value of the non-secure Base Priority register when in secure state.
+ \return Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(
+ void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(
+ uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority (non-secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(
+ uint32_t value)
+{
+ __ASM volatile ("MSR basepri_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(
+ uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Base Priority with condition (non_secure)
+ \details Assigns the given value to the non-secure Base Priority register when in secure state only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_MAX_NS(
+ uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max_ns, %0" : : "r" (value) : "memory");
+}
+#endif
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get Fault Mask (non-secure)
+ \details Returns the current value of the non-secure Fault Mask register when in secure state.
+ \return Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(
+ void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(
+ uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set Fault Mask (non-secure)
+ \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(
+ uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Get Process Stack Pointer Limit
+ \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim" : "=r" (result) );
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Process Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \return PSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Process Stack Pointer Limit
+ \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(
+ uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Process Stack Pointer (non-secure)
+ \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+ \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(
+ uint32_t ProcStackPtrLimit)
+{
+ __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+}
+#endif
+
+
+/**
+ \brief Get Main Stack Pointer Limit
+ \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+
+ return(result);
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Get Main Stack Pointer Limit (non-secure)
+ \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+ \return MSPLIM Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Set Main Stack Pointer Limit
+ \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+ \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(
+ uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+}
+
+
+#if (__ARM_FEATURE_CMSE == 3U) && (__ARM_ARCH_PROFILE == 'M') /* ToDo: ARMCC_V6: check predefined macro for mainline */
+/**
+ \brief Set Main Stack Pointer Limit (non-secure)
+ \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+ \param [in] MainStackPtrLimit Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(
+ uint32_t MainStackPtrLimit)
+{
+ __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+}
+#endif
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+
+#if ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=4 */
+
+/**
+ \brief Get FPSCR
+ \details eturns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+#define __get_FPSCR __builtin_arm_get_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Get FPSCR (non-secure)
+ \details Returns the current value of the non-secure Floating Point Status/Control register when in secure state.
+ \return Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FPSCR_NS(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMRS %0, fpscr_ns" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+#endif
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+#define __set_FPSCR __builtin_arm_set_fpscr
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#if (__ARM_FEATURE_CMSE == 3U)
+/**
+ \brief Set FPSCR (non-secure)
+ \details Assigns the given value to the non-secure Floating Point Status/Control register when in secure state.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FPSCR_NS(
+ uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ __ASM volatile (""); /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("VMSR fpscr_ns, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+#endif
+
+#endif /* ((__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __builtin_arm_nop
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __builtin_arm_wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __builtin_arm_wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __builtin_arm_sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() __builtin_arm_isb(0xF);
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __builtin_arm_dsb(0xF);
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __builtin_arm_dmb(0xF);
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __builtin_bswap32
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV16 __builtin_bswap16 /* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+#if 0
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) :
+ __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+/* ToDo: ARMCC_V6: check if __builtin_bswap16 could be used */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) :
+ __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] op1 Value to rotate
+ \param [in] op2 Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
+ uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+/* ToDo: ARMCC_V6: check if __builtin_arm_rbit is supported */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) /* ToDo: ARMCC_V6: check if this is ok for cortex >=3 */
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB (uint8_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH (uint16_t)__builtin_arm_ldrex
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW (uint32_t)__builtin_arm_ldrex
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW (uint32_t)__builtin_arm_strex
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __builtin_arm_clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+/*#define __SSAT __builtin_arm_ssat*/
+#define __SSAT(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __builtin_arm_usat
+#if 0
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+#endif
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) :
+ __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(
+ volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(
+ volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(
+ volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value,
+ volatile uint8_t *ptr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value,
+ volatile uint16_t *ptr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value,
+ volatile uint32_t *ptr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#endif /* ((__ARM_ARCH_7M__ == 1U) || (__ARM_ARCH_7EM__ == 1U) || (__ARM_ARCH_8M__ == 1U)) */
+
+
+#if (__ARM_ARCH_8M__ == 1U)
+
+/**
+ \brief Load-Acquire (8 bit)
+ \details Executes a LDAB instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(
+ volatile uint8_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint8_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (16 bit)
+ \details Executes a LDAH instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(
+ volatile uint16_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return ((uint16_t) result);
+}
+
+
+/**
+ \brief Load-Acquire (32 bit)
+ \details Executes a LDA instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(
+ volatile uint32_t *ptr)
+{
+ uint32_t result;
+
+ __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+ return(result);
+}
+
+
+/**
+ \brief Store-Release (8 bit)
+ \details Executes a STLB instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value,
+ volatile uint8_t *ptr)
+{
+ __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (16 bit)
+ \details Executes a STLH instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value,
+ volatile uint16_t *ptr)
+{
+ __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Store-Release (32 bit)
+ \details Executes a STL instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value,
+ volatile uint32_t *ptr)
+{
+ __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief Load-Acquire Exclusive (8 bit)
+ \details Executes a LDAB exclusive instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDAEXB (uint8_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (16 bit)
+ \details Executes a LDAH exclusive instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDAEXH (uint16_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Load-Acquire Exclusive (32 bit)
+ \details Executes a LDA exclusive instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDAEX (uint32_t)__builtin_arm_ldaex
+
+
+/**
+ \brief Store-Release Exclusive (8 bit)
+ \details Executes a STLB exclusive instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXB (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (16 bit)
+ \details Executes a STLH exclusive instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEXH (uint32_t)__builtin_arm_stlex
+
+
+/**
+ \brief Store-Release Exclusive (32 bit)
+ \details Executes a STL exclusive instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STLEX (uint32_t)__builtin_arm_stlex
+
+#endif /* (__ARM_ARCH_8M__ == 1U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__ARM_FEATURE_DSP == 1U) /* ToDo: ARMCC_V6: This should be ARCH >= ARMv7-M + SIMD */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1,
+ uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1,
+ uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1,
+ uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1,
+ uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1,
+ uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1,
+ uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1,
+ uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1,
+ uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1,
+ uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1,
+ int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1,
+ int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA (int32_t op1,
+ int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1U) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_V6_H */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_device.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_device.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_device.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,17 @@
+//
+// This file is part of the GNU ARM Eclipse distribution.
+// Copyright (c) 2015 Liviu Ionescu.
+//
+
+#ifndef _CMSIS_DEVICE_H_
+#define _CMSIS_DEVICE_H_
+
+#pragma GCC diagnostic push
+// Add pragmas if the header triggers warnings.
+// #pragma GCC diagnostic ignored "-Wpadded"
+
+#include "ADuCM360.h"
+
+#pragma GCC diagnostic pop
+
+#endif // _CMSIS_DEVICE_H_
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_gcc.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_gcc.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/cmsis_gcc.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,1474 @@
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(
+ uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(
+ uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(
+ uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(
+ uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(
+ void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(
+ uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(
+ uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(
+ void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(
+ uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(
+ uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) :
+ __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) :
+ __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) :
+ __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
+ uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U) {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(
+ volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(
+ volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(
+ volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value,
+ volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result),
+ "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value,
+ volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result),
+ "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value,
+ volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result),
+ "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) :
+ __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(
+ volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(
+ volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(
+ volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value,
+ volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value,
+ volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value,
+ volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1,
+ uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(
+ uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(
+ uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(
+ uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (
+ uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (
+ uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (
+ uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (
+ uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (
+ uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (
+ uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (
+ uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (
+ uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u {
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]),
+ "=r" (llr.w32[1]): "r" (op1), "r" (op2), "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]),
+ "=r" (llr.w32[0]): "r" (op1), "r" (op2), "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (
+ uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1,
+ int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1,
+ int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (
+ int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2),
+ "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/core_cm3.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/core_cm3.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/core_cm3.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,1895 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+#include
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M3
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+#define __ASM __asm /*!< asm keyword for ARM Compiler */
+#define __INLINE __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __ASM __asm /*!< asm keyword for ARM Compiler */
+#define __INLINE __inline /*!< inline keyword for ARM Compiler */
+#define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+#define __ASM __asm /*!< asm keyword for GNU Compiler */
+#define __INLINE inline /*!< inline keyword for GNU Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+#define __ASM __asm /*!< asm keyword for IAR Compiler */
+#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+#define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+#define __ASM __asm /*!< asm keyword for TASKING Compiler */
+#define __INLINE inline /*!< inline keyword for TASKING Compiler */
+#define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+#define __packed
+#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+#define __STATIC_INLINE static inline
+
+#else
+#error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
+*/
+#define __FPU_USED 0U
+
+#if defined ( __CC_ARM )
+#if defined __TARGET_FPU_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#if defined __ARM_PCS_VFP
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __GNUC__ )
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __ICCARM__ )
+#if defined __ARMVFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TMS470__ )
+#if defined __TI_VFP_SUPPORT__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __TASKING__ )
+#if defined __FPU_VFP__
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#elif defined ( __CSMC__ )
+#if ( __CSMC__ & 0x400U)
+#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+#endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+#ifndef __CM3_REV
+#define __CM3_REV 0x0200U
+#warning "__CM3_REV not defined in device header file; using default!"
+#endif
+
+#ifndef __MPU_PRESENT
+#define __MPU_PRESENT 0U
+#warning "__MPU_PRESENT not defined in device header file; using default!"
+#endif
+
+#ifndef __NVIC_PRIO_BITS
+#define __NVIC_PRIO_BITS 4U
+#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+#endif
+
+#ifndef __Vendor_SysTickConfig
+#define __Vendor_SysTickConfig 0U
+#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+#endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+#define __I volatile /*!< Defines 'read only' permissions */
+#else
+#define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union {
+ struct {
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+uint32_t Q:
+ 1; /*!< bit: 27 Saturation condition flag */
+uint32_t V:
+ 1; /*!< bit: 28 Overflow condition code flag */
+uint32_t C:
+ 1; /*!< bit: 29 Carry condition code flag */
+uint32_t Z:
+ 1; /*!< bit: 30 Zero condition code flag */
+uint32_t N:
+ 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union {
+ struct {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+uint32_t T:
+ 1; /*!< bit: 24 Thumb bit (read 0) */
+uint32_t IT:
+ 2; /*!< bit: 25..26 saved IT state (read 0) */
+uint32_t Q:
+ 1; /*!< bit: 27 Saturation condition flag */
+uint32_t V:
+ 1; /*!< bit: 28 Overflow condition code flag */
+uint32_t C:
+ 1; /*!< bit: 29 Carry condition code flag */
+uint32_t Z:
+ 1; /*!< bit: 30 Zero condition code flag */
+uint32_t N:
+ 1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union {
+ struct {
+uint32_t nPRIV:
+ 1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+ __IOM uint32_t
+ ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t
+ ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t
+ ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t
+ ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t
+ IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t
+ IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t
+ STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+ __IM uint32_t
+ CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t
+ ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t
+ VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t
+ AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t
+ SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t
+ CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t
+ SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t
+ SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t
+ CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t
+ HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t
+ DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t
+ MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t
+ BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t
+ AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t
+ PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t
+ DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t
+ ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t
+ MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t
+ ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t
+ CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if (__CM3_REV < 0x0201U) /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct {
+ uint32_t RESERVED0[1U];
+ __IM uint32_t
+ ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))
+ __IOM uint32_t
+ ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct {
+ __IOM uint32_t
+ CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t
+ LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t
+ VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t
+ CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct {
+ __OM union {
+ __OM uint8_t
+ u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t
+ u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t
+ u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t
+ TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t
+ TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t
+ TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t
+ IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t
+ IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t
+ IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t
+ LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t
+ LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t
+ PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t
+ PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t
+ PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t
+ PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t
+ PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t
+ PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t
+ PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t
+ PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t
+ CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t
+ CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t
+ CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t
+ CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+ __IOM uint32_t
+ CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t
+ CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t
+ CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t
+ EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t
+ SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t
+ LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t
+ FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t
+ PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t
+ COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t
+ MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t
+ FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t
+ COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t
+ MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t
+ FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t
+ COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t
+ MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t
+ FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t
+ COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t
+ MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t
+ FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct {
+ __IOM uint32_t
+ SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t
+ CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t
+ ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t
+ SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t
+ FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t
+ FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t
+ FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t
+ FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t
+ FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t
+ ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t
+ CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t
+ CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+ __IM uint32_t
+ TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t
+ CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t
+ RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t
+ RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t
+ RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t
+ RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t
+ RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t
+ RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t
+ RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t
+ RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t
+ RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+ __IOM uint32_t
+ DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t
+ DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t
+ DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t
+ DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)
+ 0x07UL); /* only values 0..7 are used */
+
+ reg_value =
+ SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk |
+ SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp <<
+ 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >>
+ SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(
+ int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(
+ int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((
+ uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(
+ int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(
+ int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((
+ uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority <<
+ (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ } else {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority <<
+ (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >>
+ (8U - __NVIC_PRIO_BITS)));
+ } else {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >>
+ (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup,
+ uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)
+ 0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(
+ __NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(
+ 7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) <
+ (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) +
+ (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) <<
+ SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority,
+ uint32_t PriorityGroup, uint32_t* const pPreemptPriority,
+ uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)
+ 0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(
+ __NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(
+ 7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) <
+ (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) +
+ (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL <<
+ (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL <<
+ (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) { /* wait until reset */
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks -
+ 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn,
+ (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL =
+ 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t
+ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
+ while (ITM->PORT[0U].u32 == 0UL) {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+// [ILG]
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GENERIC */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/core_cmFunc.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/core_cmFunc.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/core_cmFunc.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+#include
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+#include
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+#include
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/core_cmInstr.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/core_cmInstr.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/core_cmInstr.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,87 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+#pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if defined ( __CC_ARM )
+#include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+#include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+#include
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+#include
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+#include
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
Index: ADuCM360_demo_cn0359/src/system/include/cmsis/system_ADuCM360.h
===================================================================
diff -u
--- ADuCM360_demo_cn0359/src/system/include/cmsis/system_ADuCM360.h (revision 0)
+++ ADuCM360_demo_cn0359/src/system/include/cmsis/system_ADuCM360.h (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,98 @@
+/**************************************************************************//**
+ * @file system_ADuCM360.h
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File for
+ * ADuCM360 Device
+ * @version V0.1
+ * @date 11 September 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_ADUCM360_H /* ToDo: replace '' with your device name */
+#define SYSTEM_ADUCM360_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+extern uint32_t
+SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+ * @brief Sets the system external clock frequency
+ *
+ * @param ExtClkFreq External clock frequency in Hz
+ * @return none
+ *
+ * Sets the clock frequency of the source connected to P0.5 clock input source
+ */
+extern void SetSystemExtClkFreq (uint32_t ExtClkFreq);
+
+/**
+ * @brief Gets the system external clock frequency
+ *
+ * @return External Clock frequency
+ *
+ * Gets the clock frequency of the source connected to P0.5 clock input source
+ */
+extern uint32_t GetSystemExtClkFreq (void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ADUCM360_H */
Index: CN0_Python_Scripts/EVAL_CN0359_ADC_Hits.py
===================================================================
diff -u
--- CN0_Python_Scripts/EVAL_CN0359_ADC_Hits.py (revision 0)
+++ CN0_Python_Scripts/EVAL_CN0359_ADC_Hits.py (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,151 @@
+import numpy as np
+
+import time
+from datetime import datetime
+
+import pandas as pd
+
+import os
+
+### Function Definitions
+
+def get_adc_hits(polldata):
+
+ # parse the adc hits from the poll data
+
+ polldatalist = polldata.split('\n')
+ hits = int(polldatalist[15].strip().split(':')[1].strip())
+
+ return hits
+
+def get_conductivity(polldata):
+
+ # parse the conductivity from the poll data
+
+ polldatalist = polldata.split('\n')
+ conductivity = float(polldatalist[20].strip().split(':')[1].strip()[0:-4])
+
+ return conductivity
+
+###
+
+# load the Python API for the Analog Devices CN0359 evaluation board
+# from automatedtesting.instruments.analog_devices_conductivity_board import AnalogDevicesConductivityBoard
+from modules.analog_devices_conductivity_board import AnalogDevicesConductivityBoard
+
+
+# create an instance of the CN0359 Eval Board
+cond1 = AnalogDevicesConductivityBoard()
+#cond1.create_connection('/dev/ttyUSB0', '31')
+cond1.create_connection('COM3', '31')
+
+
+###
+### Parameters
+###
+
+# Set the number of data points to collect at each sampling frequency
+N = 100
+
+# Define frequency of the excitation signal on the CN0359
+# Fext = 1000
+
+# set the excitation frequency on the EVAL-CN0359 board
+# cond1.set_frequency(Fext)
+
+# Define the polling frequencies at which to collect data
+Fps = [1, 2, 5, 10, 20, 50, 100, 200, 500, 1000]
+
+# Define the excitation frequency at which to collect data
+Fexts = [100, 200, 500, 1000, 2000, 5000]
+
+# Define the path to the folder where the data will be stored
+# parentdirectory = '/mnt/VMShare/DavidC/data/CN0359/'
+parentdirectory = r'C:\Users\ven.asrivastava\Desktop\My_Folder\Project\Jira_tasks\Conductivity_sensor_decoding\New_conductivity _sensor\David_Python_Scripts\Data'
+
+# Define the directory that the data set will be stored in
+# the parent directory
+directory = 'diality_unmodified_fw'
+
+
+###
+### end parameters
+###
+
+# Create a timestamp for the current data set
+timestamp = datetime.now().strftime('%Y%m%d_%H%M')
+
+# append the timestamp to the data directory
+directory = directory + '_' + timestamp
+
+# create the data storage path
+os.makedirs(os.path.join(parentdirectory, directory), exist_ok=True)
+
+# loop over the list of excitation frequencies
+for Fext in Fexts:
+
+ # set the excitation frequency on the EVAL-CN0359 board
+ # DDC Note - I noticed that the excitation frequency was not being
+ # changed inside the loop at 1500h 2025-12-10. Any data collected
+ # before that time with this script is not valid.
+ cond1.set_frequency(Fext)
+
+ # create a Pandas dataframe in which to store the adc_hits data
+ hitsdf = pd.DataFrame()
+
+ # create a Pandas dataframe in which to store the conductivity data
+ conductivitydf = pd.DataFrame()
+
+ # Create filename in which to store the adc hits collected at the current polling frequency
+ adchitsfilename = 'adc_hits_{:.0f}.csv'.format(Fext)
+
+ # concatenate the data file path and the adc hits file name
+ adchitsfile = os.path.join(parentdirectory, directory, adchitsfilename)
+
+ # Create filename in which to store the conductivities collected at the current polling frequency
+ conductivitiesfilename = 'conductivities_{:.0f}.csv'.format(Fext)
+
+ # concatenate the date file path and the conductivity file name
+ conductivitiesfile = os.path.join(parentdirectory, directory, conductivitiesfilename)
+
+
+ # Loop over the list of polling frequencies
+ for Fp in Fps:
+
+ print('{}, {}'.format(Fp, Fext))
+ Tp = 1 / Fp # Calculate the polling period from the polling rate
+
+ # Create a list to keep the poll data frames in
+ # The poll data frames are not parsed in the loop to save time
+ polldata = []
+
+ # Collect N datapoints. Pause for the polling period between collecting poll data frames
+ for ii in range(N):
+
+ polldata.append(cond1.get_poll())
+ time.sleep(Tp)
+
+ # create a numpy array in which to keep the adc_hits data
+ hits = np.array([])
+ conductivities = np.array([])
+
+ for poll in polldata:
+ hits = np.append(hits, get_adc_hits(poll))
+ conductivities = np.append(conductivities, get_conductivity(poll))
+
+ # create a dataframe column label for the current polling frequency
+ collabel = 'Fp{}'.format(Fp)
+
+ # append the adc hits data to the adc hits dataframe
+ hitsdf[collabel] = hits
+
+ # append the conductivity data to the conductivity dataframe
+ conductivitydf[collabel] = conductivities
+
+ # after the loop over the polling frequency has been
+ # completed write the data in the dataframes to csv files
+ hitsdf.to_csv(adchitsfile)
+ conductivitydf.to_csv(conductivitiesfile)
+
+
+
Index: CN0_Python_Scripts/EVAL_CN0359_REV_B.py
===================================================================
diff -u
--- CN0_Python_Scripts/EVAL_CN0359_REV_B.py (revision 0)
+++ CN0_Python_Scripts/EVAL_CN0359_REV_B.py (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,59 @@
+import numpy as np
+import time
+from datetime import datetime
+import pandas as pd
+import os
+from serial import Serial
+import struct
+import commands_rev_b as commands
+
+# load the Python API for the Analog Devices CN0359 evaluation board
+# from automatedtesting.instruments.analog_devices_conductivity_board import AnalogDevicesConductivityBoard
+from modules.analog_devices_conductivity_board import AnalogDevicesConductivityBoard
+
+# create an instance of the CN0359 Eval Board
+cond1 = AnalogDevicesConductivityBoard()
+#cond1.create_connection('/dev/ttyUSB0', '30')
+cond1.create_connection('COM6', '30')
+print("connected")
+
+# commands.cmd_poll(cond1)
+# commands.cmd_poll_bin(cond1)
+
+# commands.cmd_voltage(cond1, 0.2)
+# commands.cmd_frequency_bin(cond1,10.1)
+# commands.cmd_cellconstant(cond1,0.06)
+# commands.cmd_coefficient_bin(cond1,5.0)
+# commands.cmd_setuptime_bin(cond1,0.1)
+# commands.cmd_holdtime_bin(cond1,0.2)
+# commands.cmd_poll(cond1)
+
+# commands.cmd_poll(cond1)
+# print('\n')
+# commands.cmd_cellconstant(cond1,0.06)
+# print('\n')
+# commands.cmd_poll(cond1)
+
+# commands.cmd_getCalData_bin(cond1)
+# print('\n')
+# commands.cmd_setcal(cond1, 1, 100.1)
+# commands.cmd_setcal(cond1, 2, 100.2)
+# commands.cmd_setcal(cond1, 3, 100.3)
+# commands.cmd_setcal(cond1, 4, 100.4)
+# commands.cmd_setcal(cond1, 5, 100.5)
+# commands.cmd_setcal(cond1, 6, 100.6)
+# commands.cmd_setcal(cond1, 7, 100.7)
+# commands.cmd_setcal(cond1, 8, 100.8)
+# commands.cmd_setcal(cond1, 9, 100.9)
+# commands.cmd_setcal(cond1, 10, 100.10)
+# commands.cmd_setcal(cond1, 11, 100.11)
+# commands.cmd_setcal(cond1, 12, 100.12)
+# print('\n')
+# commands.cmd_getCalData_bin(cond1)
+
+commands.cmd_getSerial_bin(cond1)
+# commands.cmd_setSerial_bin(cond1)
+# commands.cmd_getSerial_bin(cond1)
+
+# commands.cmd_poll(cond1)
+# commands.cmd_poll_bin(cond1)
\ No newline at end of file
Index: CN0_Python_Scripts/commands_rev_b.py
===================================================================
diff -u
--- CN0_Python_Scripts/commands_rev_b.py (revision 0)
+++ CN0_Python_Scripts/commands_rev_b.py (revision 509657069dd7ee800560a5c0b790077ce4cbd31a)
@@ -0,0 +1,150 @@
+import parser
+import struct
+########################################################################################################################
+# {"poll", cmd_poll},
+def cmd_poll(cond1):
+ cond1.ser.write(b'poll\n')
+ print("Sent command cmd_poll")
+
+ i = 0
+ poll = ""
+ while i <= 21: # decode by number of lines of data messages
+ current_line_text = str(cond1.ser.readline().decode())
+ poll = poll + current_line_text
+ i += 1
+ print(poll)
+
+########################################################################################################################
+# {"poll_bin", cmd_poll_bin},
+def cmd_poll_bin(cond1):
+ cond1.ser.write(b' poll_bin\n')
+ print("Sent command cmd_poll_bin")
+ data = cond1.ser.read(100)
+ print(data)
+ parsed = parser.parse_cmd_poll_bin(data)
+ parser.print_poll_readout(parsed)
+
+########################################################################################################################
+# {"setvolt", cmd_voltage}
+def cmd_voltage(cond1, value):
+ cond1.ser.write(f"setvolt {value}\n".encode())
+ print("Sent command cmd_voltage_bin")
+
+########################################################################################################################
+# {"setfreq_bin", cmd_frequency_bin},
+def cmd_frequency_bin(cond1, value):
+ cond1.ser.write(f"setfreq_bin {value}\n".encode())
+ print("Sent command cmd_frequency_bin")
+ data = cond1.ser.read(1)
+ print(data)
+
+########################################################################################################################
+# {"setk", cmd_cellconstant},
+def cmd_cellconstant(cond1, value):
+ cond1.ser.write(f"setk {value}\n".encode())
+ print("Sent command cmd_cellconstant_bin")
+
+########################################################################################################################
+# {"setcof_bin", cmd_coefficient_bin},
+def cmd_coefficient_bin(cond1, value):
+ cond1.ser.write(f"setcof_bin {value}\n".encode())
+ print("Sent command cmd_coefficient_bin")
+ data = cond1.ser.read(1)
+ print(data)
+
+########################################################################################################################
+# {"setstm_bin", cmd_setuptime_bin},
+def cmd_setuptime_bin(cond1, value):
+ cond1.ser.write(f"setstm_bin {value}\n".encode())
+ print("Sent command cmd_setuptime_bin")
+ data = cond1.ser.read(1)
+ print(data)
+
+########################################################################################################################
+# {"sethtm_bin", cmd_holdtime_bin},
+def cmd_holdtime_bin(cond1, value):
+ cond1.ser.write(f"sethtm_bin {value}\n".encode())
+ print("Sent command cmd_holdtime_bin")
+ data = cond1.ser.read(1)
+ print(data)
+
+########################################################################################################################
+# {"setcal_bin", cmd_setCalData_bin},
+
+
+def cmd_setCalData_bin(cond1):
+ # Prepare coefficients (floats as plain decimals)
+ coeffs = [
+ 0.016 * 10,
+ -0.010* 10,
+ -0.010 * 10,
+ 0.012 * 10,
+ 35.832 * 10,
+ -28.066 * 10,
+ ]
+
+ # coeffs = [
+ # 0.0162777400 / 10,
+ # -0.0108147500 / 10,
+ # -0.0109372700 / 10,
+ # 0.0122156087 / 10,
+ # 35.8320791500 / 10,
+ # -28.0662148100 / 10,
+ # ]
+
+ # Build: " setcal_bin v1 v2 v3 v4 v5 v6\n"
+ # Use fixed-point formatting to avoid scientific notation, ensure ASCII
+ payload = " ".join(f"{v:.10f}" for v in coeffs)
+ cmd = f"setcal_bin {payload}\n".encode("ascii")
+ print(cmd)
+
+ # Send command
+ cond1.ser.write(cmd)
+ print("Sent command cmd_setCalData_bin")
+ data = cond1.ser.readline()
+ # Read one byte status (same pattern as your other function)
+ # data = cond1.ser.read(1)
+ print(data)
+
+########################################################################################################################
+# {"getcal_bin", cmd_getCalData_bin}
+def cmd_getCalData_bin(cond1):
+ cond1.ser.write(b' c\n')
+ print("Sent command cmd_getCalData_bin")
+ data = cond1.ser.read(48)
+ print(data)
+ d = parser.parse_cal_file_bytes(data)
+ parser.print_cal_file(d)
+
+########################################################################################################################
+# {"setcal_bin", cmd_setCalData_bin},
+def cmd_setSerial_bin(cond1):
+ value = 0.2
+ # cmd = b'setsn 0x002\n'
+ cmd = f"setsn {value}\n".encode()
+ cond1.ser.write(cmd)
+ print("Sent command cmd_setSerial_bin")
+ data = cond1.ser.read(1)
+ print(data)
+
+########################################################################################################################
+# {"getcal_bin", cmd_getSerial_bin}
+def cmd_getSerial_bin(cond1):
+ cmd =b' n\n'
+ cond1.ser.write(cmd)
+ print("Sent command cmd_getSerial_bin")
+ data = cond1.ser.read(4)
+ print(data)
+ print(struct.unpack(' 44 bytes
+FLASH_FMT = struct.Struct(" 52 bytes
+# ADuCM360: unsigned long is 32-bit -> 'I'
+ADC_FMT = struct.Struct("<4f6if2I")
+
+# cmdPollBinStruct: flash_file + adc_file + float (conductivity) -> 100 bytes
+CMD_FMT = struct.Struct(" dict:
+ """
+ Parse a 100-byte binary payload of cmdPollBinStruct into a nested dict.
+
+ Expected layout (packed, little-endian):
+ struct cmdPollBinStruct {
+ flash_file flashData; // 44 bytes
+ adc_file adcData; // 52 bytes
+ float conductivity; // 4 bytes
+ }
+ """
+ if len(data) != CMD_SIZE:
+ raise ValueError(f"Expected {CMD_SIZE} bytes, got {len(data)}")
+
+ # Unpack top-level once, then split into sections
+ vals = CMD_FMT.unpack(data)
+
+ # Map flash_file (first 11 fields)
+ flash_keys = [
+ "baud_rate", "rs485_address",
+ "voltage", "frequency", "temp_coef", "cell_const", "setup", "hold",
+ "lcd_uc1601s_br", "lcd_uc1601s_pm", "lcd_uc1601s_tc",
+ ]
+ flash_vals = vals[0:11]
+ flash = dict(zip(flash_keys, flash_vals))
+
+ # Map adc_file (next 13 fields)
+ adc_keys = [
+ "p_curt", "n_curt", "p_volt", "n_volt",
+ "p_curt_gain", "p_volt_gain", "n_curt_gain", "n_volt_gain",
+ "rtd_type", "wire_mode", "temp",
+ "adc0_hit", "adc1_hit",
+ ]
+ adc_vals = vals[11:24]
+ adc = dict(zip(adc_keys, adc_vals))
+
+ # Conductivity (last float)
+ conductivity = vals[24]
+
+ return {
+ "flashData": flash,
+ "adcData": adc,
+ "conductivity": conductivity,
+ }
+
+
+# ---- Optional: reliable read helper for UART (PySerial) ----
+def read_exact(ser, n: int) -> bytes:
+ """Read exactly n bytes from a serial.Serial; returns empty on timeout."""
+ buf = bytearray()
+ while len(buf) < n:
+ chunk = ser.read(n - len(buf))
+ if not chunk: # timeout
+ break
+ buf.extend(chunk)
+ return bytes(buf)
+
+
+def read_cmd_poll_bin(ser) -> dict:
+ """
+ Read and parse one cmdPollBinStruct (100 bytes) from the serial port.
+ Assumes the device has already been commanded (e.g., 'poll_bin').
+ """
+ data = read_exact(ser, CMD_SIZE)
+ if len(data) != CMD_SIZE:
+ raise TimeoutError(f"Got {len(data)} / {CMD_SIZE} bytes")
+
+
+
+def print_poll_readout(d: dict) -> None:
+ """
+ Pretty-print the parsed cmdPollBinStruct dict in the required format.
+ Expects:
+ d = {
+ "flashData": {
+ "voltage", "frequency", "setup", "hold",
+ "temp_coef", "cell_const",
+ # (other fields may be present)
+ },
+ "adcData": {
+ "adc0_hit", "adc1_hit",
+ "p_curt_gain", "n_curt_gain", "p_volt_gain", "n_volt_gain",
+ "p_curt", "n_curt", "p_volt", "n_volt",
+ "rtd_type", "wire_mode", "temp",
+ },
+ "conductivity": float,
+ }
+ """
+ f = d["flashData"]
+ a = d["adcData"]
+ cond = d["conductivity"]
+
+ # 1) Excitation + cell setup
+ print(f"EXC V: {float(f['voltage']):.6f}V")
+ print(f"EXC FREQ: {float(f['frequency']):.6f}Hz")
+ print(f"EXC setup time: {float(f['setup']) * 100.0:.6f}%") # if 'setup' is fraction [0..1]
+ print(f"EXC hold time: {float(f['hold']) * 100.0:.6f}%") # if 'hold' is fraction [0..1]
+ print(f"TEMP COEF: {float(f['temp_coef']):.6f}%/'C")
+ print(f"cell K: {float(f['cell_const']):.6f}/cm")
+
+ # 2) ADC hits and gains + measured p-p values
+ print(f"ADC0 hits: {int(a['adc0_hit'])}")
+ print(f"+I gain: {int(a['p_curt_gain'])}")
+ print(f"+Ip-p: {float(a['p_curt']):.6e}A")
+ print(f"-I gain: {int(a['n_curt_gain'])}")
+ print(f"-Ip-p: {float(a['n_curt']):.6e}A")
+ print(f"+V gain: {int(a['p_volt_gain'])}")
+ print(f"+Vp-p: {float(a['p_volt']):.6e}V")
+ print(f"-V gain: {int(a['n_volt_gain'])}")
+ print(f"-Vp-p: {float(a['n_volt']):.6e}V")
+ print(f"ADC1 hits: {int(a['adc1_hit'])}")
+
+ # 3) RTD type/wire + temperature
+ # If your payload uses numeric codes, map them here; otherwise print as strings.
+ rtd_type = a['rtd_type']
+ wire_mode = a['wire_mode']
+ RTD_TYPES = {1000: "PT1000", 100: "PT100"} # adjust if you use enumerations
+ WIRE_MODES = {2: "2 wire", 3: "3 wire", 4: "4 wire"}
+
+ rtd_str = RTD_TYPES.get(rtd_type, str(rtd_type))
+ wire_str = WIRE_MODES.get(wire_mode, str(wire_mode))
+ print(f"RTD: {rtd_str}")
+ print(f"RTD wire: {wire_str}")
+ print(f"TEMP: {float(a['temp']):.6f}'C")
+
+ # 4) Blank line + conductivity
+ print() # blank line
+ print(f"conductivity: {float(cond):.6e}S/cm")
+
+
+########################################################################################################################
+
+def parse_cal_file_bytes(data: bytes) -> dict:
+ """Parse 48 bytes as 12 little-endian floats into a dict {coeff1..coeff12}."""
+ if len(data) != 12 * 4:
+ raise ValueError(f"Expected 48 bytes, got {len(data)}")
+ coeffs = struct.unpack('<12f', data)
+ return {f'coeff{i+1}': coeffs[i] for i in range(12)}
+
+def print_cal_file(d: dict) -> None:
+ for i in range(12):
+ v = d[f'coeff{i+1}']
+ print(f"coeff{i+1}: {v:.10f}")
+
+