Index: firmware/App/Services/FPGADD.c
===================================================================
diff -u -r8b8fff67b95805272f37855346d600599aaec03d -rcd3af1ebb7396ba3b2bec1d779510d29c30014f4
--- firmware/App/Services/FPGADD.c	(.../FPGADD.c)	(revision 8b8fff67b95805272f37855346d600599aaec03d)
+++ firmware/App/Services/FPGADD.c	(.../FPGADD.c)	(revision cd3af1ebb7396ba3b2bec1d779510d29c30014f4)
@@ -355,13 +355,13 @@
         else
         {
             result = SELF_TEST_STATUS_FAILED;
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_POST_TEST_FAILED, (U32)DG_FPGA_COMPATIBILITY_REV, (U32)fpgaSensorReadings.fpgaCompatibilityRev )
+            //SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_POST_TEST_FAILED, (U32)DG_FPGA_COMPATIBILITY_REV, (U32)fpgaSensorReadings.fpgaCompatibilityRev )
         }
     }
     else
     {
         result = SELF_TEST_STATUS_FAILED;
-        SET_ALARM_WITH_1_U32_DATA( ALARM_ID_DG_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaId )
+        //SET_ALARM_WITH_1_U32_DATA( ALARM_ID_DG_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaId )
     }
 
     return result;
@@ -392,13 +392,13 @@
     U32 const diffFPGATimerCount   = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
     U32 const diffTimerCount       = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms );
 
-    if ( getCurrentOperationMode() != DG_MODE_INIT )
+    if ( getCurrentOperationMode() != DD_MODE_INIT )
     {
         if ( abs( diffFPGATimerCount - diffTimerCount ) > PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE )
         {
             if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR ) )
             {
-                 SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
+                 //SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
             }
         }
     }
@@ -1632,12 +1632,12 @@
  * @details Outputs: none
  * @return  status of the hardware configuration
  *************************************************************************/
-HARDWARE_CONFIG_T getHardwareConfigStatus( void )
-{
-    HARDWARE_CONFIG_T configValue = (HARDWARE_CONFIG_T)fpgaSensorReadings.fpgaHWConfigReg;
-
-    return configValue;
-}
+//HARDWARE_CONFIG_T getHardwareConfigStatus( void )
+//{
+//    HARDWARE_CONFIG_T configValue = (HARDWARE_CONFIG_T)fpgaSensorReadings.fpgaHWConfigReg;
+//
+//    return configValue;
+//}
 #endif
 
 /*********************************************************************//**
@@ -2039,7 +2039,7 @@
     {
         if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES ) )
         {
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
+            //SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
         }
     }
 }
@@ -2065,7 +2065,7 @@
         {
             if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES ) )
             {
-                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
+                //SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
                 status = TRUE;
             }
         }