Index: firmware/App/Services/FpgaDD.c
===================================================================
diff -u -r78842b478a83315eda5d877a99b16f3b899b7727 -rd5b87d7dab8613f3963fb66f8833d210f127fa1f
--- firmware/App/Services/FpgaDD.c	(.../FpgaDD.c)	(revision 78842b478a83315eda5d877a99b16f3b899b7727)
+++ firmware/App/Services/FpgaDD.c	(.../FpgaDD.c)	(revision d5b87d7dab8613f3963fb66f8833d210f127fa1f)
@@ -74,6 +74,8 @@
 #define FPGA_ENABLE_BC_VALVES_PWM       0x00                    ///< FPGA enable Balancing chamber valves PWM.
 #define FPGA_ENABLE_UF_VALVES_PWM       0x00                    ///< FPGA enable Ultrafiltration valves PWM.
 
+#define FPGA_ADC_AUTO_READ_ENABLE       0x11                    ///< FPGA internal ADC auto read enable.
+
 #define CONCENTRATE_CAP_SWITCH_MASK     0x10                    ///< Concentrate cap switch bit mask.
 #define FPGA_CONC_PUMP_FAULT_BITS       0x03                    ///< Concentrate pump fault bits mask.
 #define FPGA_CPA_PARKED_BIT             0x04                    ///< Concentrate pump 1 parked status bit mask.
@@ -367,6 +369,7 @@
     fpgaActuatorSetPoints.fpgaBCValvePWMControl     = FPGA_ENABLE_BC_VALVES_PWM;
     fpgaActuatorSetPoints.fpgaUFValveControl        = FPGA_ENABLE_UF_VALVES_CONTROL;
     fpgaActuatorSetPoints.fpgaUFValvePWMControl     = FPGA_ENABLE_UF_VALVES_PWM;
+    fpgaActuatorSetPoints.fpgaADCControl            = FPGA_ADC_AUTO_READ_ENABLE;
 
     // initialize FPGA clock speed error time windowed count
     initTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES_WINDOW_MS);