Index: firmware/App/Services/FpgaDD.c =================================================================== diff -u -r799f26bec11423fa4894a8e01ebc50bf0e5f4a32 -r322747d530c1b8205be257557e53dcfe9caad50a --- firmware/App/Services/FpgaDD.c (.../FpgaDD.c) (revision 799f26bec11423fa4894a8e01ebc50bf0e5f4a32) +++ firmware/App/Services/FpgaDD.c (.../FpgaDD.c) (revision 322747d530c1b8205be257557e53dcfe9caad50a) @@ -42,32 +42,28 @@ #define MAX_COMM_ERROR_RETRIES 5 ///< Maximum number of communication error retries -#define DRAIN_PUMP_DAC_SHIFT_BITS 4 ///< Drain pump DAC shift bits. - -#define FPGA_FLUIDLEAK_STATE_MASK 0x0004 ///< Bit mask for fluid leak detector. - //TODO : Define the default values for the Valves ( 0: Deenergized, 1 : Energized) on power up. #define FPGA_ENABLE_VALVES_CONTROL 0x0000 ///< FPGA enable valves control. #define FPGA_ENABLE_BC_VALVES_CONTROL 0x00 ///< FPGA enable Balancing chamber valves control. #define FPGA_ENABLE_UF_VALVES_CONTROL 0x00 ///< FPGA enable Balancing Chamber valves control. -#define FPGA_CD1_RESET_BIT 0x01 ///< Conductivity Sensor CD1 reset bit mask. -#define FPGA_CD1_INIT_ENABLE_BIT 0x02 ///< Conductivity Sensor CD1 Initialization enable bit mask. -#define FPGA_CD1_WR_ENABLE_BIT 0x04 ///< Conductivity Sensor CD1 write enable bit mask. -#define FPGA_CD1_RD_ENABLE_BIT 0x08 ///< Conductivity Sensor CD1 read enable bit mask. -#define FPGA_CD2_RESET_BIT 0x10 ///< Conductivity Sensor CD2 reset bit mask. -#define FPGA_CD2_INIT_ENABLE_BIT 0x20 ///< Conductivity Sensor CD2 Initialization enable bit mask. -#define FPGA_CD2_WR_ENABLE_BIT 0x40 ///< Conductivity Sensor CD2 write enable bit mask. -#define FPGA_CD2_RD_ENABLE_BIT 0x80 ///< Conductivity Sensor CD2 read enable bit mask. +#define FPGA_D17_RESET_BIT 0x01 ///< Conductivity Sensor D17 reset bit mask. +#define FPGA_D17_INIT_ENABLE_BIT 0x02 ///< Conductivity Sensor D17 Initialization enable bit mask. +#define FPGA_D17_WR_ENABLE_BIT 0x04 ///< Conductivity Sensor D17 write enable bit mask. +#define FPGA_D17_RD_ENABLE_BIT 0x08 ///< Conductivity Sensor D17 read enable bit mask. +#define FPGA_D27_RESET_BIT 0x10 ///< Conductivity Sensor D27 reset bit mask. +#define FPGA_D27_INIT_ENABLE_BIT 0x20 ///< Conductivity Sensor D27 Initialization enable bit mask. +#define FPGA_D27_WR_ENABLE_BIT 0x40 ///< Conductivity Sensor D27 write enable bit mask. +#define FPGA_D27_RD_ENABLE_BIT 0x80 ///< Conductivity Sensor D27 read enable bit mask. -#define FPGA_CD3_RESET_BIT 0x01 ///< Conductivity Sensor CD3 reset bit mask. -#define FPGA_CD3_INIT_ENABLE_BIT 0x02 ///< Conductivity Sensor CD3 Initialization enable bit mask. -#define FPGA_CD3_WR_ENABLE_BIT 0x04 ///< Conductivity Sensor CD3 write enable bit mask. -#define FPGA_CD3_RD_ENABLE_BIT 0x08 ///< Conductivity Sensor CD3 read enable bit mask. -#define FPGA_CD4_RESET_BIT 0x10 ///< Conductivity Sensor CD4 reset bit mask. -#define FPGA_CD4_INIT_ENABLE_BIT 0x20 ///< Conductivity Sensor CD4 Initialization enable bit mask. -#define FPGA_CD4_WR_ENABLE_BIT 0x40 ///< Conductivity Sensor CD4 write enable bit mask. -#define FPGA_CD4_RD_ENABLE_BIT 0x80 ///< Conductivity Sensor CD4 read enable bit mask. +#define FPGA_D29_RESET_BIT 0x01 ///< Conductivity Sensor D29 reset bit mask. +#define FPGA_D29_INIT_ENABLE_BIT 0x02 ///< Conductivity Sensor D29 Initialization enable bit mask. +#define FPGA_D29_WR_ENABLE_BIT 0x04 ///< Conductivity Sensor D29 write enable bit mask. +#define FPGA_D29_RD_ENABLE_BIT 0x08 ///< Conductivity Sensor D29 read enable bit mask. +#define FPGA_D43_RESET_BIT 0x10 ///< Conductivity Sensor D43 reset bit mask. +#define FPGA_D43_INIT_ENABLE_BIT 0x20 ///< Conductivity Sensor D43 Initialization enable bit mask. +#define FPGA_D43_WR_ENABLE_BIT 0x40 ///< Conductivity Sensor D43 write enable bit mask. +#define FPGA_D43_RD_ENABLE_BIT 0x80 ///< Conductivity Sensor D43 read enable bit mask. // Assuming all valves are ON/OFF based control ( No PWM control used) #define FPGA_ENABLE_VALVES_PWM 0x0000 ///< FPGA enable valves PWM. @@ -92,9 +88,9 @@ #define FPGA_D12_PUMP_ERROR_BIT 0x01 ///< Fresh dialysate pump error bit mask. #define FPGA_D48_PUMP_ERROR_BIT 0x02 ///< Spent dialysate pump error bit mask. -#define FPGA_FLOATER_LEVEL_BIT 0x03 ///< Floater level bit mask. +#define FPGA_D6_FLOATER_LEVEL_BIT 0x03 ///< Floater level bit mask. -#define FPGA_PRIMARY_HEATER_CNTRL_BIT 0x01 ///< FPGA GIO Primary heater control bit mask +#define FPGA_D5_HEATER_CNTRL_BIT 0x01 ///< FPGA GIO D5 heater control bit mask /// FPGA size of V3 read bytes. #define FPGA_SIZE_OF_V3_READ_BYTES ( FPGA_READ_V3_END_BYTE_NUM - FPGA_READ_V3_START_BYTE_NUM ) @@ -189,11 +185,11 @@ U08 fpgaHallSensInputs; ///< Reg 350. Hall sensor Inputs - U08 fpgaBldTxFIFOCnt; ///< Reg 351. Blood leak sensor transmit FIFO count - U16 fpgaBldRxErrorCnt; ///< Reg 352. Blood leak sensor Receive error count - U16 fpgaBldRxFIFOCnt; ///< Reg 354. Blood leak sensor Receive FIFO count - U08 fpgaBldRxFIFODataOut; ///< Reg 356. Blood leak sensor Receive data - U08 fpgaBldPulseStatus; ///< Reg 357. Blood leak sensor status + U08 fpgaD42TxFIFOCnt; ///< Reg 351. Blood leak sensor transmit FIFO count + U16 fpgaD42RxErrorCnt; ///< Reg 352. Blood leak sensor Receive error count + U16 fpgaD42RxFIFOCnt; ///< Reg 354. Blood leak sensor Receive FIFO count + U08 fpgaD42RxFIFODataOut; ///< Reg 356. Blood leak sensor Receive data + U08 fpgaD42PulseStatus; ///< Reg 357. Blood leak sensor status U16 fpgaValveStates; ///< Reg 358. Valve status read U16 fpgaValvePWMEnableStates; ///< Reg 360. Valve PWM Enable status read @@ -311,9 +307,9 @@ U08 fpgaD10PumpControl; ///< Reg 121. BiCarb Concentrate Pump Control U16 fpgaD10PumpSpeed; ///< Reg 122. BiCarb Concentrate Pump Speed/RPM Control - U08 fpgaBloodLeakSensorTest; ///< Reg 124. Blood leak sensor test - U08 fpgaBloodLeakUARTControl; ///< Reg 125. Blood leak sensor UART control - U08 fpgaBloodLeakFIFOTx; ///< Reg 126. Blood leak sensor FIFO transmit control + U08 fpgaD42SensorTest; ///< Reg 124. Blood leak sensor test + U08 fpgaD42UARTControl; ///< Reg 125. Blood leak sensor UART control + U08 fpgaD42FIFOTx; ///< Reg 126. Blood leak sensor FIFO transmit control U08 fpgaD5HeaterPWMControl; ///< Reg 127. Primary heater PWM control U08 fpgaD45HeaterPWMControl; ///< Reg 128. Trimmer heater PWM control U08 fpgaNotUsed; ///< Reg 129. Not used @@ -484,14 +480,14 @@ * The setFPGABCValveStates function sets the DD balancing chamber valve states with a * 8-bit set of states - one bit per valve, with a 1 meaning "energized" and a 0 * meaning "de-energized". The bit positions for these bit states are as follows: - * 0 - V1.\n - * 1 - V2.\n - * 2 - V3.\n - * 3 - V4.\n - * 4 - V5.\n - * 5 - V6.\n - * 6 - V7.\n - * 7 - V8.\n + * 0 - D23.\n + * 1 - D19.\n + * 2 - D25.\n + * 3 - D21.\n + * 4 - D24.\n + * 5 - D20.\n + * 6 - D26.\n + * 7 - D22.\n * @details \b Inputs: none * @details \b Outputs: fpgaActuatorSetPoints.fpgaBCValveControl * @param valveStates bit mask for the balancing chamber valve states @@ -553,13 +549,13 @@ /*********************************************************************//** * @brief * The setFPGAD48PumpControl function sets the controls for - * dialysate out pump (SDP). - * bit 7: TBD - * bit 6: TBD - * bit 5: TBD - * bit 4: TBD - * bit 3: TBD - * bit 1-2: TBD + * dialysate out pump (D48). + * bit 7: Reserved + * bit 6: Reserved + * bit 5: Reserved + * bit 4: Reserved + * bit 3: Reserved + * bit 1-2: Reserved * bit 0: Run (1), stop (0) * @details \b Inputs: none * @details \b Outputs: fpgaActuatorSetPoints.fpgaD48PumpControl @@ -574,13 +570,13 @@ /*********************************************************************//** * @brief * The setFPGAD12PumpControl function sets the controls for - * dialysate In pump (DGP). - * bit 7: TBD - * bit 6: TBD - * bit 5: TBD - * bit 4: TBD - * bit 3: TBD - * bit 1-2: TBD + * De gassing pump (D12). + * bit 7: Reserved + * bit 6: Reserved + * bit 5: Reserved + * bit 4: Reserved + * bit 3: Reserved + * bit 1-2: Reserved * bit 0: Run (1), stop (0) * @details \b Inputs: none * @details \b Outputs: fpgaActuatorSetPoints.fpgaD12PumpControl @@ -705,7 +701,7 @@ *************************************************************************/ void setFPGAD17CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD1_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D17_RESET_BIT; } /*********************************************************************//** @@ -719,7 +715,7 @@ *************************************************************************/ void clearFPGAD17CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD1_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D17_RESET_BIT; } /*********************************************************************//** @@ -733,7 +729,7 @@ *************************************************************************/ void setFPGAD17CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD1_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D17_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -747,7 +743,7 @@ *************************************************************************/ void clearFPGAD17CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD1_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D17_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -764,7 +760,7 @@ *************************************************************************/ void setFPGAD17CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD1_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D17_WR_ENABLE_BIT; } /*********************************************************************//** @@ -778,7 +774,7 @@ *************************************************************************/ void clearFPGAD17CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD1_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D17_WR_ENABLE_BIT; } /*********************************************************************//** @@ -795,7 +791,7 @@ *************************************************************************/ void setFPGAD17CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD1_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D17_RD_ENABLE_BIT; } /*********************************************************************//** @@ -809,7 +805,7 @@ *************************************************************************/ void clearFPGAD17CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD1_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D17_RD_ENABLE_BIT; } /*********************************************************************//** @@ -823,7 +819,7 @@ *************************************************************************/ void setFPGAD27CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD2_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D27_RESET_BIT; } /*********************************************************************//** @@ -837,7 +833,7 @@ *************************************************************************/ void clearFPGAD27CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD2_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D27_RESET_BIT; } /*********************************************************************//** @@ -851,7 +847,7 @@ *************************************************************************/ void setFPGAD27CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD2_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D27_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -865,7 +861,7 @@ *************************************************************************/ void clearFPGAD27CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD2_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D27_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -882,7 +878,7 @@ *************************************************************************/ void setFPGAD27CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD2_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D27_WR_ENABLE_BIT; } /*********************************************************************//** @@ -896,7 +892,7 @@ *************************************************************************/ void clearFPGAD27CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD2_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D27_WR_ENABLE_BIT; } /*********************************************************************//** @@ -913,7 +909,7 @@ *************************************************************************/ void setFPGAD27CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_CD2_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control |= FPGA_D27_RD_ENABLE_BIT; } /*********************************************************************//** @@ -927,7 +923,7 @@ *************************************************************************/ void clearFPGAD27CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_CD2_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD12Control &= ~FPGA_D27_RD_ENABLE_BIT; } /*********************************************************************//** @@ -941,7 +937,7 @@ *************************************************************************/ void setFPGAD29CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD3_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D29_RESET_BIT; } /*********************************************************************//** @@ -955,7 +951,7 @@ *************************************************************************/ void clearFPGAD29CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD3_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D29_RESET_BIT; } /*********************************************************************//** @@ -969,7 +965,7 @@ *************************************************************************/ void setFPGAD29CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD3_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D29_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -983,7 +979,7 @@ *************************************************************************/ void clearFPGAD29CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD3_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D29_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -1000,7 +996,7 @@ *************************************************************************/ void setFPGAD29CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD3_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D29_WR_ENABLE_BIT; } /*********************************************************************//** @@ -1014,7 +1010,7 @@ *************************************************************************/ void clearFPGAD29CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD3_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D29_WR_ENABLE_BIT; } /*********************************************************************//** @@ -1031,7 +1027,7 @@ *************************************************************************/ void setFPGAD29CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD3_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D29_RD_ENABLE_BIT; } /*********************************************************************//** @@ -1045,7 +1041,7 @@ *************************************************************************/ void clearFPGAD29CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD3_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D29_RD_ENABLE_BIT; } /*********************************************************************//** @@ -1059,7 +1055,7 @@ *************************************************************************/ void setFPGAD43CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD4_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D43_RESET_BIT; } /*********************************************************************//** @@ -1073,7 +1069,7 @@ *************************************************************************/ void clearFPGAD43CondReset( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD4_RESET_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D43_RESET_BIT; } /*********************************************************************//** @@ -1087,7 +1083,7 @@ *************************************************************************/ void setFPGAD43CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD4_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D43_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -1101,7 +1097,7 @@ *************************************************************************/ void clearFPGAD43CondInitEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD4_INIT_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D43_INIT_ENABLE_BIT; } /*********************************************************************//** @@ -1118,7 +1114,7 @@ *************************************************************************/ void setFPGAD43CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD4_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D43_WR_ENABLE_BIT; } /*********************************************************************//** @@ -1132,7 +1128,7 @@ *************************************************************************/ void clearFPGAD43CondWriteEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD4_WR_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D43_WR_ENABLE_BIT; } /*********************************************************************//** @@ -1149,7 +1145,7 @@ *************************************************************************/ void setFPGAD43CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_CD4_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control |= FPGA_D43_RD_ENABLE_BIT; } /*********************************************************************//** @@ -1163,21 +1159,21 @@ *************************************************************************/ void clearFPGAD43CondReadEnable( void ) { - fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_CD4_RD_ENABLE_BIT; + fpgaActuatorSetPoints.fpgaConSensTD34Control &= ~FPGA_D43_RD_ENABLE_BIT; } /*********************************************************************//** * @brief * The setFpgaCD12Control function sets the FPGA Conductivity * Sensor control register for CD1&2. - * bit 7: Enables TD2 read transaction (1), address needed - * bit 6: Enables TD2 write transaction (1), address and data needs to be set - * bit 5: Enable TD2 Init procedure (1) - * bit 4: reset TD2 Conduct sensor (1) - * bit 3: Enables TD1 read transaction (1), address needed - * bit 2: Enables TD1 write transaction (1), address and data needs to be set - * bit 1: Enable TD1 Init procedure (1) - * bit 0: reset TD1 Conduct sensor (1) + * bit 7: Enables D27 read transaction (1), address needed + * bit 6: Enables D27 write transaction (1), address and data needs to be set + * bit 5: Enable D27 Init procedure (1) + * bit 4: reset D27 Conduct sensor (1) + * bit 3: Enables D17 read transaction (1), address needed + * bit 2: Enables D17 write transaction (1), address and data needs to be set + * bit 1: Enable D17 Init procedure (1) + * bit 0: reset D17 Conduct sensor (1) * @details \b Inputs: none * @details \b Outputs: fpgaActuatorSetPoints.fpgaConSensTD12Control * @param control Conductivity Sensor control set @@ -1192,14 +1188,14 @@ * @brief * The setFpgaCD34Control function sets the FPGA Conductivity * Sensor control register for CD3&4. - * bit 7: Enables TD4 read transaction (1), address needed - * bit 6: Enables TD4 write transaction (1), address and data needs to be set - * bit 5: Enable TD4 Init procedure (1) - * bit 4: reset TD4 Conduct sensor (1) - * bit 3: Enables TD3 read transaction (1), address needed - * bit 2: Enables TD3 write transaction (1), address and data needs to be set - * bit 1: Enable TD3 Init procedure (1) - * bit 0: reset TD3 Conduct sensor (1) + * bit 7: Enables D43 read transaction (1), address needed + * bit 6: Enables D43 write transaction (1), address and data needs to be set + * bit 5: Enable D43 Init procedure (1) + * bit 4: reset D43 Conduct sensor (1) + * bit 3: Enables D29 read transaction (1), address needed + * bit 2: Enables D29 write transaction (1), address and data needs to be set + * bit 1: Enable D29 Init procedure (1) + * bit 0: reset D29 Conduct sensor (1) * @details \b Inputs: none * @details \b Outputs: fpgaActuatorSetPoints.fpgaConSensTD34Control * @param control Conductivity sensor control set @@ -1268,28 +1264,28 @@ /*********************************************************************//** * @brief - * The setFPGAPrimaryHeaterPWMControl function sets the primary heater + * The setFPGAD5HeaterPWMControl function sets the primary heater * PWM input. * @details \b Inputs: none * @details \b Outputs: fpgaD5HeaterPWMControl * @param control the PWM dutycycle to control the heater * @return none *************************************************************************/ -void setFPGAPrimaryHeaterPWMControl( U08 control ) +void setFPGAD5HeaterPWMControl( U08 control ) { fpgaActuatorSetPoints.fpgaD5HeaterPWMControl = control; } /*********************************************************************//** * @brief - * The setFPGATrimmerHeaterPWMControl function sets the trimmer heater + * The setFPGAD45HeaterPWMControl function sets the trimmer heater * PWM input. * @details \b Inputs: none * @details \b Outputs: fpgaD45HeaterPWMControl * @param control the PWM dutycycle to control the heater * @return none *************************************************************************/ -void setFPGATrimmerHeaterPWMControl( U08 control ) +void setFPGAD45HeaterPWMControl( U08 control ) { fpgaActuatorSetPoints.fpgaD45HeaterPWMControl = control; } @@ -1324,22 +1320,22 @@ /*********************************************************************//** * @brief - * The setFPGACPrimaryHeaterOnOffControl function sets the primary heater + * The setFPGAD5HeaterOnOffControl function sets the primary heater * On/Off control. * @details \b Inputs: none * @details \b Outputs: fpgaGPIOControl * @param flag Turn heater ON when true, otherwise not. * @return none *************************************************************************/ -void setFPGACPrimaryHeaterOnOffControl( BOOL flag ) +void setFPGAD5HeaterOnOffControl( BOOL flag ) { if ( TRUE == flag) { - fpgaActuatorSetPoints.fpgaGPIOControl |= FPGA_PRIMARY_HEATER_CNTRL_BIT; + fpgaActuatorSetPoints.fpgaGPIOControl |= FPGA_D5_HEATER_CNTRL_BIT; } else { - fpgaActuatorSetPoints.fpgaGPIOControl &= ~FPGA_PRIMARY_HEATER_CNTRL_BIT; + fpgaActuatorSetPoints.fpgaGPIOControl &= ~FPGA_D5_HEATER_CNTRL_BIT; } } @@ -2331,7 +2327,7 @@ *************************************************************************/ U08 getFPGAD6LevelStatus( void ) { - return ( fpgaSensorReadings.fpgaD6FloaterStatus & FPGA_FLOATER_LEVEL_BIT ); + return ( fpgaSensorReadings.fpgaD6FloaterStatus & FPGA_D6_FLOATER_LEVEL_BIT ); } /*********************************************************************//**