Index: firmware/source/sys_link.cmd
===================================================================
diff -u -r8b8fff67b95805272f37855346d600599aaec03d -r0912db0c205c38ec57140f53934cfbedffe6f981
--- firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 8b8fff67b95805272f37855346d600599aaec03d)
+++ firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision 0912db0c205c38ec57140f53934cfbedffe6f981)
@@ -49,6 +49,13 @@
 /* USER CODE BEGIN (1) */
 /* IGNORE the generated Memory code, overridden below */
 #if 0
+/* NOTE: the default memory map is created by HALCoGen and it starts from 0x00000000
+   The memory map cannot be changed in HALCoGen so the memory map that starts from
+   0x00010000 shall be created directly in sys_link.cmd below. So #if 1 and #if 0 were
+   added to disregard the auto generated memroy map. The edited memory map should
+   be in the user defined code to map sure it is not removed every time HALCoGen is
+   created.
+*/
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
@@ -64,22 +71,34 @@
 /* USER CODE BEGIN (2) */
 #endif
 /* Override Memory Segments with CRC here */
-#if 1
 MEMORY
 {
-    VECTORS (X)  : origin=0x00000000 length=0x00000020
-    CRCMEM  (RX) : origin=0x00000020 length=0x000001E0
-    FLASH0  (RX) : origin=0x00000200 length=0x0013FE00
-    STACKS  (RW) : origin=0x08000000 length=0x00003400
-    RAM     (RW) : origin=0x08003400 length=0x0002cc00
+    VECTORS (X)  : origin=0x00010000
+                   length=0x00000020
+                   vfill = 0xffffffff
 
-#endif
+    CRCMEM  (RX) : origin=end(VECTORS)
+                   length=0x000001E0
+                   vfill = 0xffffffff
+
+    FLASH0  (RX) : origin=end(CRCMEM)
+                   length=(0x0013FFFF - end(CRCMEM))
+                   vfill = 0xffffffff
+
+    STACKS  (RW) : origin=0x08000000
+                   length=0x00004c00
+
+    RAM     (RW) : origin=0x08004c00
+                   length=0x0002b400
 /* USER CODE END */
 }
 
 /* USER CODE BEGIN (3) */
 /* IGNORE the generated Sections code, overridden below */
 #if 0
+/* NOTE: the default section has been disabled to run crc check of the image
+   in the user defined section below.
+*/
 /* USER CODE END */
 
 /*----------------------------------------------------------------------------*/
@@ -100,7 +119,6 @@
 /* USER CODE BEGIN (4) */
 #endif
 /* Override Sections with CRCs here */
-#if 1
 SECTIONS
 {
     .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C )
@@ -113,7 +131,6 @@
     .sysmem  : {} > RAM
 
     .TI.crctab : {} > CRCMEM
-#endif
 /* USER CODE END */
 }