Index: firmware/DD.dil
===================================================================
diff -u -r61ae50ebf0659ebf2deb9c68b2101d7d8d6a9688 -r8bd2386ed976da1b73ad6e29ddafa5e493b29964
--- firmware/DD.dil	(.../DD.dil)	(revision 61ae50ebf0659ebf2deb9c68b2101d7d8d6a9688)
+++ firmware/DD.dil	(.../DD.dil)	(revision 8bd2386ed976da1b73ad6e29ddafa5e493b29964)
@@ -1,4 +1,4 @@
-# RM46L852PGE 05/03/26 15:38:31
+# RM46L852PGE 05/17/26 17:30:16
 # 
 ARCH=RM46L852PGE
 # 
@@ -707,7 +707,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_PARITY_AVAILABLE.VALUE=TRUE
 DRIVER.SYSTEM.VAR.SAFETY_INIT_CAN3_RAMPARITYCHECK_ENA.VALUE=1
-DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=1
+DRIVER.SYSTEM.VAR.SAFETY_INIT_RAMECC_SELFCHECK_ENA.VALUE=0
 DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=104.000
 DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=165.0
@@ -4233,7 +4233,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31
 DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23
-DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=0x40
+DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=0x50
 DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_41_EOB.VALUE=0x00000000
@@ -4289,7 +4289,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40
 DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32
 DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24
-DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=0x41
+DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=0x51
 DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8
Index: firmware/source/can.c
===================================================================
diff -u -r61ae50ebf0659ebf2deb9c68b2101d7d8d6a9688 -r8bd2386ed976da1b73ad6e29ddafa5e493b29964
--- firmware/source/can.c	(.../can.c)	(revision 61ae50ebf0659ebf2deb9c68b2101d7d8d6a9688)
+++ firmware/source/can.c	(.../can.c)	(revision 8bd2386ed976da1b73ad6e29ddafa5e493b29964)
@@ -463,7 +463,7 @@
     } /* Wait */
 
     canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x40U & (uint32)0x000007FFU) << (uint32)18U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x50U & (uint32)0x000007FFU) << (uint32)18U);
     canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 15U;
@@ -482,7 +482,7 @@
     } /* Wait */
 
     canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x41U & (uint32)0x000007FFU) << (uint32)18U);
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x51U & (uint32)0x000007FFU) << (uint32)18U);
     canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 16U;
Index: firmware/source/sys_main.c
===================================================================
diff -u -r89c8709e3b27648926fbb20f25c9a67cbeb99adc -r8bd2386ed976da1b73ad6e29ddafa5e493b29964
--- firmware/source/sys_main.c	(.../sys_main.c)	(revision 89c8709e3b27648926fbb20f25c9a67cbeb99adc)
+++ firmware/source/sys_main.c	(.../sys_main.c)	(revision 8bd2386ed976da1b73ad6e29ddafa5e493b29964)
@@ -80,6 +80,7 @@
 #include "FpgaDD.h"
 #include "FPInterface.h"
 #include "Heaters.h"
+#include "Integrity.h"
 #include "Interrupts.h"
 #include "Level.h"
 #include "ModeGenPermeateDefeatured.h"
@@ -208,6 +209,7 @@
     initUltrafiltration();
     initRinsePump();
     initDryBiCart();
+    initIntegrity();
 
     // FP Modules
 
Index: firmware/source/sys_startup.c
===================================================================
diff -u -r0912db0c205c38ec57140f53934cfbedffe6f981 -r8bd2386ed976da1b73ad6e29ddafa5e493b29964
--- firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 0912db0c205c38ec57140f53934cfbedffe6f981)
+++ firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 8bd2386ed976da1b73ad6e29ddafa5e493b29964)
@@ -399,18 +399,6 @@
 
 /* USER CODE BEGIN (40) */
 /* USER CODE END */
-
-    /* Test the CPU ECC mechanism for RAM accesses.
-     * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
-     * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
-     * in the ECC causes a data abort exception. The data abort handler is written to look for
-     * deliberately caused exception and to return the code execution to the instruction
-     * following the one that caused the abort.
-     */
-    checkRAMECC();
-
-/* USER CODE BEGIN (41) */
-/* USER CODE END */
 /* USER CODE BEGIN (43) */
 /* USER CODE END */