Index: firmware/App/Controllers/RinsePump.c =================================================================== diff -u -rb569bc796c56acd5d94d468386f5f42c350cad65 -r9ed40798a5f4779db8a07bb6e256f7de99660108 --- firmware/App/Controllers/RinsePump.c (.../RinsePump.c) (revision b569bc796c56acd5d94d468386f5f42c350cad65) +++ firmware/App/Controllers/RinsePump.c (.../RinsePump.c) (revision 9ed40798a5f4779db8a07bb6e256f7de99660108) @@ -36,7 +36,7 @@ #define RINSE_PUMP_OFF_COUNT 0U ///< Rinse Pump OFF value in count #define RINSE_PUMP_DEFAULT_PWM_PERCENT 10.0F ///< Initial Rinse pump PWM percentage #define RINSE_PUMP_MAX_PWM_PERCENT 100.0F ///< Max Rinse pump PWM percentage -#define RINSE_PUMP_PWM_IN_COUNT_MAX 255.0F ///< Rinse pump max count (100% PWM = 255) +#define RINSE_PUMP_PWM_IN_COUNT_MAX 250.0F ///< Rinse pump max count (100% PWM = 250) #define RINSE_PUMP_PWM_PULSE_RESOLUTION_US 10 ///< Rinse pump PWM pulse resolution in 10us // TODO remove once PMW control is implemented @@ -57,6 +57,7 @@ static RINSE_PUMP_STATE_T handleRinsePumpOffState( void ); static RINSE_PUMP_STATE_T handleRinsePumpOnState ( void ); static void publishRinsePumpData( void ); +static void setRinsePumpPwmCount( RINSE_PUMP_ID_T pumpId, U32 pwmCount ); /*********************************************************************//** * @brief @@ -126,10 +127,19 @@ { // Pulse width in 10us resolution U16 pumpPulseWidth = getFPGAD79RinsePumpPulseWidth(); - U32 pumpSpeedPerSec = US_PER_SECOND / ( pumpPulseWidth * RINSE_PUMP_PWM_PULSE_RESOLUTION_US ); + U32 pumpSpeedPerSec = 0U; - //Speed in RPM - rinsePumpMeasuredSpeed = pumpSpeedPerSec * SEC_PER_MIN; + if ( ( 0U != pumpPulseWidth ) && ( 0xFFFFU != pumpPulseWidth ) ) + { + pumpSpeedPerSec = US_PER_SECOND / ( pumpPulseWidth * RINSE_PUMP_PWM_PULSE_RESOLUTION_US ); + + // Speed in RPM + rinsePumpMeasuredSpeed = pumpSpeedPerSec * SEC_PER_MIN; + } + else + { + rinsePumpMeasuredSpeed = 0U; + } } /*********************************************************************//** @@ -161,6 +171,7 @@ break; } + calculateRinsePumpSpeed(); publishRinsePumpData(); } @@ -189,16 +200,8 @@ { RINSE_PUMP_STATE_T state = RINSE_PUMP_STATE_OFF; - if ( TRUE == getTestConfigStatus( TEST_CONFIG_DD_ENABLE_D79_PWM_CONTROL ) ) - { - // Set PWM count zero to stop the pump - setFPGAD79RinsePumpPWMControl( RINSE_PUMP_OFF_COUNT ); - } - else - { - // Current Beta 1.9 system uses on/off bit - setValveState( D79_PMP_VALV, VALVE_STATE_CLOSED ); - } + // Set PWM count zero to stop the logical rinse pump + setRinsePumpPwmCount( D79_RINSE_PUMP, RINSE_PUMP_OFF_COUNT ); return state; } @@ -214,25 +217,41 @@ { RINSE_PUMP_STATE_T state = RINSE_PUMP_STATE_ON; - if ( TRUE == getTestConfigStatus( TEST_CONFIG_DD_ENABLE_D79_PWM_CONTROL ) ) - { - F32 pwmPercent = getF32OverrideValue( &rinsePumpPwmPercentage ); - U32 pwmInCount = (U32)( ( pwmPercent / RINSE_PUMP_MAX_PWM_PERCENT ) * RINSE_PUMP_PWM_IN_COUNT_MAX ); + F32 pwmPercent = getF32OverrideValue( &rinsePumpPwmPercentage ); + U32 pwmInCount = (U32)( ( pwmPercent / RINSE_PUMP_MAX_PWM_PERCENT ) * RINSE_PUMP_PWM_IN_COUNT_MAX ); - //Turn on Rinse pump with given PWM value - setFPGAD79RinsePumpPWMControl( pwmInCount ); - } - else - { - // Current Beat 1.9 system uses on/off bit - setValveState( D79_PMP_VALV, VALVE_STATE_OPEN ); - } + // Turn on logical rinse pump with given PWM value + setRinsePumpPwmCount( D79_RINSE_PUMP, pwmInCount ); return state; } /*********************************************************************//** * @brief + * The setRinsePumpPwmCount function maps a logical rinse pump ID to the + * underlying FPGA control and applies the requested PWM count. + * @details \b Inputs: pumpId, pwmCount + * @details \b Outputs: FPGA rinse pump control register + * @param pumpId Logical rinse pump identifier + * @param pwmCount PWM magnitude (0..RINSE_PUMP_PWM_IN_COUNT_MAX) + * @return none + *************************************************************************/ +static void setRinsePumpPwmCount( RINSE_PUMP_ID_T pumpId, U32 pwmCount ) +{ + switch ( pumpId ) + { + case D79_RINSE_PUMP: + setFPGAD79RinsePumpPWMControl( (U08)pwmCount ); + break; + + default: + // No other rinse pumps defined yet; ignore for now. + break; + } +} + +/*********************************************************************//** + * @brief * The publishRinsePumpData function constructs and sends the rinse pump data * broadcast message. * @details \b Message \b Sent: MSG_ID_DD_RINSE_PUMP_DATA @@ -336,4 +355,3 @@ } /**@}*/ - Index: firmware/App/Controllers/RinsePump.h =================================================================== diff -u -r830213bc6dcc1a684610caf78c79d55f2cb41e93 -r9ed40798a5f4779db8a07bb6e256f7de99660108 --- firmware/App/Controllers/RinsePump.h (.../RinsePump.h) (revision 830213bc6dcc1a684610caf78c79d55f2cb41e93) +++ firmware/App/Controllers/RinsePump.h (.../RinsePump.h) (revision 9ed40798a5f4779db8a07bb6e256f7de99660108) @@ -42,6 +42,13 @@ } RINSE_PUMP_PAYLOAD_T; #pragma pack(pop) +/// Enumeration of rinse pump +typedef enum RinsePumpIds +{ + D79_RINSE_PUMP = 0, ///< Rinse pump D79 + NUM_OF_RINSE_PUMPS ///< Number of rinse pumps +} RINSE_PUMP_ID_T; + /// Enumeration of air pump states. typedef enum RinsePumpControllerStates { @@ -65,4 +72,3 @@ /**@}*/ #endif - Index: firmware/App/Controllers/Valves.c =================================================================== diff -u -r9f6510dd156bb7284e500399f4227bbcbb9f06bf -r9ed40798a5f4779db8a07bb6e256f7de99660108 --- firmware/App/Controllers/Valves.c (.../Valves.c) (revision 9f6510dd156bb7284e500399f4227bbcbb9f06bf) +++ firmware/App/Controllers/Valves.c (.../Valves.c) (revision 9ed40798a5f4779db8a07bb6e256f7de99660108) @@ -330,7 +330,7 @@ ( D65_VALV == valveID ) || ( D64_VALV == valveID ) || ( D31_VALV == valveID ) || ( D34_VALV == valveID ) || ( D35_VALV == valveID ) || ( D40_VALV == valveID ) || ( D47_VALV == valveID ) || ( D3_VALV == valveID ) || ( M4_VALV == valveID ) || ( D23_VALV == valveID ) || ( D19_VALV == valveID ) || ( D25_VALV == valveID ) || ( D21_VALV == valveID ) || ( D24_VALV == valveID ) || ( D20_VALV == valveID ) || - ( D26_VALV == valveID ) || ( D22_VALV == valveID ) || ( D80_VALV == valveID ) || ( D81_VALV == valveID ) || ( D79_PMP_VALV == valveID ) || + ( D26_VALV == valveID ) || ( D22_VALV == valveID ) || ( D80_VALV == valveID ) || ( D81_VALV == valveID ) || ( D88_VALV == valveID ) || ( P11_VALV == valveID ) || ( P33_VALV == valveID ) || ( P34_VALV == valveID ) || ( P37_VALV == valveID ) || ( P6_VALV == valveID ) || ( M12_VALV == valveID ) || ( P39_VALV == valveID ) || ( D83_VALV == valveID ) || ( D91_VALV == valveID ) || ( D100_VALV == valveID ) || ( D85_VALV == valveID ) ) { Index: firmware/App/Drivers/GPIO.c =================================================================== diff -u -r830213bc6dcc1a684610caf78c79d55f2cb41e93 -r9ed40798a5f4779db8a07bb6e256f7de99660108 --- firmware/App/Drivers/GPIO.c (.../GPIO.c) (revision 830213bc6dcc1a684610caf78c79d55f2cb41e93) +++ firmware/App/Drivers/GPIO.c (.../GPIO.c) (revision 9ed40798a5f4779db8a07bb6e256f7de99660108) @@ -14,18 +14,19 @@ * @date (original) 29-Aug-2024 * ***************************************************************************/ - -#include "gio.h" -#include "mibspi.h" - + +#include "gio.h" +#include "mibspi.h" + +#include "FpgaDD.h" #include "GPIO.h" - + /** * @addtogroup GPIO * @{ */ -// ********** private definitions ********** +// ********** private definitions ********** #define WD_PET_GIO_PORT_PIN 1U ///< Watchdog pet GPIO pin number. #define WD_EXP_GIO_PORT_PIN 0U ///< Watchdog expired GPIO pin number. @@ -90,4 +91,17 @@ return level; } +/*********************************************************************//** + * @brief + * The getGPIOStatusFromFPGA function returns the latest GPIO status register + * value reported by the DD FPGA. + * @details \b Inputs: fpgaSensorReadings.fpgaGPIOStatus + * @details \b Outputs: none + * @return GPIO status register value (bit-mapped per HDD definition) + *************************************************************************/ +U08 getGPIOStatusFromFPGA( void ) +{ + return getFPGAGPIOStatus(); +} + /**@}*/ Index: firmware/App/Drivers/GPIO.h =================================================================== diff -u -r830213bc6dcc1a684610caf78c79d55f2cb41e93 -r9ed40798a5f4779db8a07bb6e256f7de99660108 --- firmware/App/Drivers/GPIO.h (.../GPIO.h) (revision 830213bc6dcc1a684610caf78c79d55f2cb41e93) +++ firmware/App/Drivers/GPIO.h (.../GPIO.h) (revision 9ed40798a5f4779db8a07bb6e256f7de99660108) @@ -14,12 +14,12 @@ * @date (original) 29-Aug-2024 * ***************************************************************************/ - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#include "DDCommon.h" - + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#include "DDCommon.h" + /** * @defgroup GPIO GPIO * @brief The GPIO unit provides definitions and GPIO pin access abstraction @@ -34,8 +34,9 @@ void toggleWatchdogPetSignal( void ); void setWatchdogPetSignal( void ); void clrWatchdogPetSignal( void ); -PIN_SIGNAL_STATE_T getCPLDWatchdogExpired( void ); +PIN_SIGNAL_STATE_T getWatchdogExpired( void ); +U08 getGPIOStatusFromFPGA( void ); /**@}*/ -#endif +#endif Index: firmware/App/Monitors/Level.c =================================================================== diff -u -r4440a7a6b86afcaed7573596abe30bcf5820aba4 -r9ed40798a5f4779db8a07bb6e256f7de99660108 --- firmware/App/Monitors/Level.c (.../Level.c) (revision 4440a7a6b86afcaed7573596abe30bcf5820aba4) +++ firmware/App/Monitors/Level.c (.../Level.c) (revision 9ed40798a5f4779db8a07bb6e256f7de99660108) @@ -131,15 +131,36 @@ break; case D63_LEVL: - currentLevelStatus = ( processLevelCount( getFPGAD63LevelSensor() ) == 0 ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH ); + if ( TRUE == getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) ) + { + currentLevelStatus = ( 0U == getFPGAD63LevelSensor() ) ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH; + } + else + { + currentLevelStatus = ( processLevelCount( getFPGAD63LevelSensor() ) == 0 ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH ); + } break; case D98_LEVL: - currentLevelStatus = ( processLevelCount( getFPGAD98LevelSensor() ) == 0 ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH ); + if ( TRUE == getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) ) + { + currentLevelStatus = ( 0U == getFPGAD98LevelSensor() ) ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH; + } + else + { + currentLevelStatus = ( processLevelCount( getFPGAD98LevelSensor() ) == 0 ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH ); + } break; case D46_LEVL: - currentLevelStatus = ( processLevelCount( getFPGAD46LevelSensor() ) == 0 ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH ); + if ( TRUE == getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) ) + { + currentLevelStatus = ( 0U == getFPGAD46LevelSensor() ) ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH; + } + else + { + currentLevelStatus = ( processLevelCount( getFPGAD46LevelSensor() ) == 0 ? LEVEL_STATE_LOW : LEVEL_STATE_HIGH ); + } break; case P25_LEVL: @@ -260,6 +281,116 @@ /*********************************************************************//** * @brief + * The getLevelStateBeta19 function maps the raw floater/level status reported + * by FPGA to the corresponding LEVEL_STATE_T for Beta 1.9 hardware. + * @details \b Inputs: levelStatus + * @details \b Outputs: none + * @param levelStatus Raw FPGA level status value + * @return mapped level state + *************************************************************************/ +static LEVEL_STATE_T getLevelStateBeta19( U32 levelStatus ) +{ + LEVEL_STATE_T currentLevelStatus = LEVEL_STATE_ILLEGAL; + + if ( FPGA_LEVEL_EMPTY == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_EMPTY; + } + else if ( FPGA_LEVEL_LOW == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_LOW; + } + else if ( FPGA_LEVEL_MEDIUM == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_MEDIUM; + } + else if ( FPGA_LEVEL_HIGH == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_HIGH; + } + else + { + // TODO - Handle invalid level alarm + currentLevelStatus = LEVEL_STATE_ILLEGAL; + } + + return currentLevelStatus; +} + +/*********************************************************************//** + * @brief + * The getLevelStateBeta20 function maps the raw floater/level status reported + * by FPGA to the corresponding LEVEL_STATE_T for Beta 2.0 hardware. + * @details \b Inputs: levelStatus + * @details \b Outputs: none + * @param levelStatus Raw FPGA level status value + * @return mapped level state + *************************************************************************/ +static LEVEL_STATE_T getLevelStateBeta20( U32 levelStatus ) +{ + LEVEL_STATE_T currentLevelStatus = LEVEL_STATE_ILLEGAL; + + if ( FPGA_B2_LEVEL_EMPTY == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_EMPTY; + } + else if ( FPGA_B2_LEVEL_LOW == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_LOW; + } + else if ( FPGA_B2_LEVEL_MEDIUM == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_MEDIUM; + } + else if ( FPGA_B2_LEVEL_HIGH == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_HIGH; + } + else + { + // TODO - Handle invalid level alarm + currentLevelStatus = LEVEL_STATE_ILLEGAL; + } + + return currentLevelStatus; +} + +/*********************************************************************//** + * @brief + * The getLevelStateBeta10 function maps the raw floater/level status reported + * by FPGA to the corresponding LEVEL_STATE_T for Beta 1.0 hardware. + * @details \b Inputs: levelStatus + * @details \b Outputs: none + * @param levelStatus Raw FPGA level status value + * @return mapped level state + *************************************************************************/ +static LEVEL_STATE_T getLevelStateBeta10( U32 levelStatus ) +{ + LEVEL_STATE_T currentLevelStatus = LEVEL_STATE_ILLEGAL; + + if ( FPGA_B1_HW_LEVEL_LOW == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_LOW; + } + else if ( FPGA_B1_HW_LEVEL_MEDIUM == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_MEDIUM; + } + else if ( FPGA_B1_HW_LEVEL_HIGH == levelStatus ) + { + currentLevelStatus = LEVEL_STATE_HIGH; + } + else + { + // TODO - Handle invalid level alarm + currentLevelStatus = LEVEL_STATE_ILLEGAL; + } + + return currentLevelStatus; +} + +/*********************************************************************//** + * @brief * The getFloaterLevelstatus function gets the floater level reported by FPGA * @details \b Alarm: ALARM_ID_DD_SOFTWARE_FAULT if the current state is invalid. * @details \b Inputs: FPGA level sensor data @@ -274,153 +405,44 @@ if ( D6_LEVL == levelId ) { levelStatus = getFPGAD6LevelStatus(); - if ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_1_0_HW ) != TRUE && getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) != TRUE ) + + if ( ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_1_0_HW ) != TRUE ) && + ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) != TRUE ) ) { // Beta 1.9 behavior - if ( FPGA_LEVEL_EMPTY == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_EMPTY; - } - else if ( FPGA_LEVEL_LOW == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_LOW; - } - else if ( FPGA_LEVEL_MEDIUM == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_MEDIUM; - } - else if ( FPGA_LEVEL_HIGH == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_HIGH; - } - else - { - // TODO - Handle invalid level alarm - currentLevelStatus = LEVEL_STATE_ILLEGAL; - } + currentLevelStatus = getLevelStateBeta19( levelStatus ); } else if ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) == TRUE ) { // Beta 2.0 behavior - if ( FPGA_B2_LEVEL_EMPTY == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_EMPTY; - } - else if ( FPGA_B2_LEVEL_LOW == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_LOW; - } - else if ( FPGA_B2_LEVEL_MEDIUM == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_MEDIUM; - } - else if ( FPGA_B2_LEVEL_HIGH == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_HIGH; - } - else - { - // TODO - Handle invalid level alarm - currentLevelStatus = LEVEL_STATE_ILLEGAL; - } + currentLevelStatus = getLevelStateBeta20( levelStatus ); } else { // Beta 1.0 behavior - if ( FPGA_B1_HW_LEVEL_LOW == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_LOW; - } - else if ( FPGA_B1_HW_LEVEL_MEDIUM == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_MEDIUM; - } - else if ( FPGA_B1_HW_LEVEL_HIGH == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_HIGH; - } - else - { - // TODO - Handle invalid level alarm - currentLevelStatus = LEVEL_STATE_ILLEGAL; - } + currentLevelStatus = getLevelStateBeta10( levelStatus ); } } else if ( P25_LEVL == levelId ) { levelStatus = getFPGAP25FloaterState(); - if ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_1_0_HW ) != TRUE && getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) != TRUE) + if ( ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_1_0_HW ) != TRUE ) && + ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) != TRUE ) ) { // Beta 1.9 behavior - if ( FPGA_LEVEL_EMPTY == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_EMPTY; - } - else if ( FPGA_LEVEL_LOW == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_LOW; - } - else if ( FPGA_LEVEL_MEDIUM == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_MEDIUM; - } - else if ( FPGA_LEVEL_HIGH == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_HIGH; - } - else - { - // TODO - Handle invalid level alarm - currentLevelStatus = LEVEL_STATE_ILLEGAL; - } + currentLevelStatus = getLevelStateBeta19( levelStatus ); } else if ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) == TRUE ) { // Beta 2.0 behavior - if ( FPGA_B2_LEVEL_EMPTY == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_EMPTY; - } - else if ( FPGA_B2_LEVEL_LOW == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_LOW; - } - else if ( FPGA_B2_LEVEL_MEDIUM == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_MEDIUM; - } - else if ( FPGA_B2_LEVEL_HIGH == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_HIGH; - } - else - { - // TODO - Handle invalid level alarm - currentLevelStatus = LEVEL_STATE_ILLEGAL; - } + currentLevelStatus = getLevelStateBeta20( levelStatus ); } else { // Beta 1.0 behavior - if ( FPGA_B1_HW_LEVEL_LOW == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_LOW; - } - else if ( FPGA_B1_HW_LEVEL_MEDIUM == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_MEDIUM; - } - else if ( FPGA_B1_HW_LEVEL_HIGH == levelStatus ) - { - currentLevelStatus = LEVEL_STATE_HIGH; - } - else - { - // TODO - Handle invalid level alarm - currentLevelStatus = LEVEL_STATE_ILLEGAL; - } + currentLevelStatus = getLevelStateBeta10( levelStatus ); } } Index: firmware/App/Services/FpgaDD.c =================================================================== diff -u -rdcdc84e87fe5d67c15e83bc4e4a4bbacb0f4b63b -r9ed40798a5f4779db8a07bb6e256f7de99660108 --- firmware/App/Services/FpgaDD.c (.../FpgaDD.c) (revision dcdc84e87fe5d67c15e83bc4e4a4bbacb0f4b63b) +++ firmware/App/Services/FpgaDD.c (.../FpgaDD.c) (revision 9ed40798a5f4779db8a07bb6e256f7de99660108) @@ -144,7 +144,7 @@ U08 fpgaRevLab; ///< Reg 3. FPGA revision (lab) being reported } FPGA_HEADER_T; // read only on FPGA -#if 1 // Remove when Beta 1.9 is obsolete +// Remove when Beta 1.9 is obsolete /// FPGA sensor readings struct. typedef struct { @@ -283,9 +283,7 @@ U16 fpgaD74CondTemp; ///< Reg 756. D74 Temperature U08 fpgaD74CondReadCnt; ///< Reg 758. D74 successful read count U08 fpgaD74CondErrorCnt; ///< Reg 759. D74 error read count - } DD_FPGA_SENSORS_BETA_1_9_T; -#endif typedef struct {