Index: firmware/App/Services/FpgaDD.c
===================================================================
diff -u -rb9a6c61d168d8aad9314f05b749645c73158b621 -rb4c343fde01f77b96c50d7f76e3f8f9d011b56a4
--- firmware/App/Services/FpgaDD.c	(.../FpgaDD.c)	(revision b9a6c61d168d8aad9314f05b749645c73158b621)
+++ firmware/App/Services/FpgaDD.c	(.../FpgaDD.c)	(revision b4c343fde01f77b96c50d7f76e3f8f9d011b56a4)
@@ -112,6 +112,9 @@
 #define FPGA_D12_PUMP_ERROR_BIT         0x01                    ///< Fresh dialysate pump error bit mask.
 #define FPGA_D48_PUMP_ERROR_BIT         0x02                    ///< Spent dialysate pump error bit mask.
 #define FPGA_FLOATER_LEVEL_BIT          0x0F                    ///< Floater level bit mask(D6 and P25).
+#define FPGA_D46_LEVEL_BIT              0x01                    ///< D46 conductive level sensor bit mask.
+#define FPGA_D63_LEVEL_BIT              0x02                    ///< D63 conductive level sensor bit mask.
+#define FPGA_D98_LEVEL_BIT              0x04                    ///< D98 conductive level sensor bit mask.
 
 #define FPGA_D5_HEATER_CNTRL_BIT        0x01                    ///< FPGA GIO D5 heater control bit mask
 #define FPGA_D5_HEATER_PWM_ENABLE_BIT   0x02                    ///< FPGA D5 PWM based heater control bit mask
@@ -3078,7 +3081,7 @@
 #if 1    // Remove when Beta 1.9 is obsolete
     if ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) == TRUE )
     {
-        return fpgaSensorReadings.fpgaConductiveLevelStatus;
+        return ( fpgaSensorReadings.fpgaConductiveLevelStatus & FPGA_D63_LEVEL_BIT );
     }
     else
     {
@@ -3102,7 +3105,7 @@
 #if 1    // Remove when Beta 1.9 is obsolete
     if ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) == TRUE )
     {
-        return fpgaSensorReadings.fpgaConductiveLevelStatus;
+        return ( fpgaSensorReadings.fpgaConductiveLevelStatus & FPGA_D98_LEVEL_BIT );
     }
     else
     {
@@ -3126,7 +3129,7 @@
 #if 1    // Remove when Beta 1.9 is obsolete
     if ( getTestConfigStatus( TEST_CONFIG_DD_FP_ENABLE_BETA_2_0_HW ) == TRUE )
     {
-        return fpgaSensorReadings.fpgaConductiveLevelStatus;
+        return ( fpgaSensorReadings.fpgaConductiveLevelStatus & FPGA_D46_LEVEL_BIT );
     }
     else
     {