Index: firmware/DD.dil
===================================================================
diff -u -r8b8fff67b95805272f37855346d600599aaec03d -re14686745aa9e4650a3112d108be02ba89d0dd97
--- firmware/DD.dil	(.../DD.dil)	(revision 8b8fff67b95805272f37855346d600599aaec03d)
+++ firmware/DD.dil	(.../DD.dil)	(revision e14686745aa9e4650a3112d108be02ba89d0dd97)
@@ -1,4 +1,4 @@
-# RM46L852PGE 08/02/24 11:29:39
+# RM46L852PGE 08/07/24 14:30:57
 # 
 ARCH=RM46L852PGE
 # 
@@ -3310,7 +3310,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000800
 DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005
 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8
@@ -3397,8 +3397,8 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x80000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
@@ -3415,7 +3415,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000
@@ -3430,7 +3430,7 @@
 DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00002000
@@ -3610,7 +3610,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51
@@ -3919,7 +3919,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=0x200
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=0x101
 DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8
@@ -3981,7 +3981,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_5_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=0x402
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=0x102
 DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=16
 DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000
@@ -4001,7 +4001,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1
 DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000800
 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1
 DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58
@@ -4031,12 +4031,12 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_3_MESSAGE_57_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_49_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20
-DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=0x403
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=0x103
 DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8
@@ -4113,7 +4113,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_11_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_6_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21
-DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=402
 DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000200
 DRIVER.CAN.VAR.CAN_2_MESSAGE_40_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000
@@ -4169,7 +4169,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22
-DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=403
 DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8
@@ -4267,7 +4267,7 @@
 DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=75.000
 DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=1
 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000001
 DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005
@@ -4396,7 +4396,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0
@@ -4669,7 +4669,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF
@@ -4721,7 +4721,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=0x40
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=0x11
 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8
@@ -4791,7 +4791,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1
-DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=0x70
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=0x20
 DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000
@@ -4853,7 +4853,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_45_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_37_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_29_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=0x80
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=0x21
 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8
@@ -4917,7 +4917,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF
-DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41
 DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33
 DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25
@@ -4928,7 +4928,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=0x110
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=0x100
 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_SJW.VALUE=4
@@ -5213,7 +5213,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=62.500
 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0
@@ -5430,7 +5430,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF
@@ -5528,7 +5528,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_6_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21
Index: firmware/DD.hcg
===================================================================
diff -u -r8b8fff67b95805272f37855346d600599aaec03d -re14686745aa9e4650a3112d108be02ba89d0dd97
--- firmware/DD.hcg	(.../DD.hcg)	(revision 8b8fff67b95805272f37855346d600599aaec03d)
+++ firmware/DD.hcg	(.../DD.hcg)	(revision e14686745aa9e4650a3112d108be02ba89d0dd97)
@@ -29,4 +29,849 @@
       </HET2ASMSRC>
     </FILENAME>
   </HET2>
+  <SYSTEM>
+    <FILENAMES>
+      <HDRHAL>
+        <NAME>hal_stdtypes.h</NAME>
+        <PATH>include\hal_stdtypes.h</PATH>
+      </HDRHAL>
+      <HDRCOMMON>
+        <NAME>sys_common.h</NAME>
+        <PATH>include\sys_common.h</PATH>
+      </HDRCOMMON>
+      <HDRSYSTEM_R>
+        <NAME>reg_system.h</NAME>
+        <PATH>include\reg_system.h</PATH>
+      </HDRSYSTEM_R>
+      <HDRFLASH_R>
+        <NAME>reg_flash.h</NAME>
+        <PATH>include\reg_flash.h</PATH>
+      </HDRFLASH_R>
+      <HDRTCRAM_R>
+        <NAME>reg_tcram.h</NAME>
+        <PATH>include\reg_tcram.h</PATH>
+      </HDRTCRAM_R>
+      <HDRVIM_R>
+        <NAME>reg_vim.h</NAME>
+        <PATH>include\reg_vim.h</PATH>
+      </HDRVIM_R>
+      <HDRPBIST_R>
+        <NAME>reg_pbist.h</NAME>
+        <PATH>include\reg_pbist.h</PATH>
+      </HDRPBIST_R>
+      <HDRSTC_R>
+        <NAME>reg_stc.h</NAME>
+        <PATH>include\reg_stc.h</PATH>
+      </HDRSTC_R>
+      <HDREFC_R>
+        <NAME>reg_efc.h</NAME>
+        <PATH>include\reg_efc.h</PATH>
+      </HDREFC_R>
+      <HDRPCR_R>
+        <NAME>reg_pcr.h</NAME>
+        <PATH>include\reg_pcr.h</PATH>
+      </HDRPCR_R>
+      <HDRPMM_R>
+        <NAME>reg_pmm.h</NAME>
+        <PATH>include\reg_pmm.h</PATH>
+      </HDRPMM_R>
+      <HDRDMA_R>
+        <NAME>reg_dma.h</NAME>
+        <PATH>include\reg_dma.h</PATH>
+      </HDRDMA_R>
+      <HDRSYSTEM>
+        <NAME>system.h</NAME>
+        <PATH>include\system.h</PATH>
+      </HDRSYSTEM>
+      <HDRVIM>
+        <NAME>sys_vim.h</NAME>
+        <PATH>include\sys_vim.h</PATH>
+      </HDRVIM>
+      <HDRCORE>
+        <NAME>sys_core.h</NAME>
+        <PATH>include\sys_core.h</PATH>
+      </HDRCORE>
+      <HDRMPU>
+        <NAME>sys_mpu.h</NAME>
+        <PATH>include\sys_mpu.h</PATH>
+      </HDRMPU>
+      <HDRPMU>
+        <NAME>sys_pmu.h</NAME>
+        <PATH>include\sys_pmu.h</PATH>
+      </HDRPMU>
+      <HDRPCR>
+        <NAME>sys_pcr.h</NAME>
+        <PATH>include\sys_pcr.h</PATH>
+      </HDRPCR>
+      <HDRPMM>
+        <NAME>sys_pmm.h</NAME>
+        <PATH>include\sys_pmm.h</PATH>
+      </HDRPMM>
+      <HDRDMA>
+        <NAME>sys_dma.h</NAME>
+        <PATH>include\sys_dma.h</PATH>
+      </HDRDMA>
+      <HDRSLF>
+        <NAME>sys_selftest.h</NAME>
+        <PATH>include\sys_selftest.h</PATH>
+      </HDRSLF>
+      <SRCCORE>
+        <NAME>sys_core.asm</NAME>
+        <PATH>source\sys_core.asm</PATH>
+      </SRCCORE>
+      <SRCINTVECS>
+        <NAME>sys_intvecs.asm</NAME>
+        <PATH>source\sys_intvecs.asm</PATH>
+      </SRCINTVECS>
+      <SRCMPU>
+        <NAME>sys_mpu.asm</NAME>
+        <PATH>source\sys_mpu.asm</PATH>
+      </SRCMPU>
+      <SRCPMU>
+        <NAME>sys_pmu.asm</NAME>
+        <PATH>source\sys_pmu.asm</PATH>
+      </SRCPMU>
+      <SRCDABORT>
+        <NAME>dabort.asm</NAME>
+        <PATH>source\dabort.asm</PATH>
+      </SRCDABORT>
+      <SRCPCR>
+        <NAME>sys_pcr.c</NAME>
+        <PATH>source\sys_pcr.c</PATH>
+      </SRCPCR>
+      <SRCPMM>
+        <NAME>sys_pmm.c</NAME>
+        <PATH>source\sys_pmm.c</PATH>
+      </SRCPMM>
+      <SRCDMA>
+        <NAME>sys_dma.c</NAME>
+        <PATH>source\sys_dma.c</PATH>
+      </SRCDMA>
+      <SRCSYSTEM>
+        <NAME>system.c</NAME>
+        <PATH>source\system.c</PATH>
+      </SRCSYSTEM>
+      <SRCPHANTOM>
+        <NAME>sys_phantom.c</NAME>
+        <PATH>source\sys_phantom.c</PATH>
+      </SRCPHANTOM>
+      <SRCSTARTUP>
+        <NAME>sys_startup.c</NAME>
+        <PATH>source\sys_startup.c</PATH>
+      </SRCSTARTUP>
+      <SRCSLF>
+        <NAME>sys_selftest.c</NAME>
+        <PATH>source\sys_selftest.c</PATH>
+      </SRCSLF>
+      <SRCVIM>
+        <NAME>sys_vim.c</NAME>
+        <PATH>source\sys_vim.c</PATH>
+      </SRCVIM>
+      <SRCMAIN>
+        <NAME>sys_main.c</NAME>
+        <PATH>source\sys_main.c</PATH>
+      </SRCMAIN>
+      <SRCNOTIFY>
+        <NAME>notification.c</NAME>
+        <PATH>source\notification.c</PATH>
+      </SRCNOTIFY>
+      <SRCCMD>
+        <NAME>sys_link.cmd</NAME>
+        <PATH>source\sys_link.cmd</PATH>
+      </SRCCMD>
+      <HDRTEST>
+        <NAME>HL_Test.h</NAME>
+      </HDRTEST>
+      <SSWFHDRERRATA>
+        <NAME>errata_SSWF021_45.h</NAME>
+        <PATH>include\errata_SSWF021_45.h</PATH>
+      </SSWFHDRERRATA>
+      <SSWFHDREGERRATA>
+        <NAME>errata_SSWF021_45_defs.h</NAME>
+        <PATH>include\errata_SSWF021_45_defs.h</PATH>
+      </SSWFHDREGERRATA>
+      <SSWFSRCERRATA>
+        <NAME>errata_SSWF021_45.c</NAME>
+        <PATH>source\errata_SSWF021_45.c</PATH>
+      </SSWFSRCERRATA>
+      <HDRMUX_R>
+        <NAME>reg_pinmux.h</NAME>
+      </HDRMUX_R>
+      <HDRMUX>
+        <NAME>pinmux.h</NAME>
+      </HDRMUX>
+      <SRCMUX>
+        <NAME>pinmux.c</NAME>
+      </SRCMUX>
+      <HDRRTI_R>
+        <NAME>reg_rti.h</NAME>
+      </HDRRTI_R>
+      <HDRRTI>
+        <NAME>rti.h</NAME>
+      </HDRRTI>
+      <SRCRTI>
+        <NAME>rti.c</NAME>
+      </SRCRTI>
+      <HDRGIO_R>
+        <NAME>reg_gio.h</NAME>
+      </HDRGIO_R>
+      <HDRGIO>
+        <NAME>gio.h</NAME>
+      </HDRGIO>
+      <SRCGIO>
+        <NAME>gio.c</NAME>
+      </SRCGIO>
+      <HDRSCI_R>
+        <NAME>reg_sci.h</NAME>
+      </HDRSCI_R>
+      <HDRSCI>
+        <NAME>sci.h</NAME>
+      </HDRSCI>
+      <SRCSCI>
+        <NAME>sci.c</NAME>
+      </SRCSCI>
+      <HDRLIN_R>
+        <NAME>reg_lin.h</NAME>
+      </HDRLIN_R>
+      <HDRLIN>
+        <NAME>lin.h</NAME>
+      </HDRLIN>
+      <SRCLIN/>
+      <HDRMIBSPI_R>
+        <NAME>reg_mibspi.h</NAME>
+      </HDRMIBSPI_R>
+      <HDRMIBSPI>
+        <NAME>mibspi.h</NAME>
+      </HDRMIBSPI>
+      <SRCMIBSPI>
+        <NAME>mibspi.c</NAME>
+      </SRCMIBSPI>
+      <HDRSPI_R>
+        <NAME>reg_spi.h</NAME>
+      </HDRSPI_R>
+      <HDRSPI>
+        <NAME>spi.h</NAME>
+      </HDRSPI>
+      <SRCSPI/>
+      <HDRCAN_R>
+        <NAME>reg_can.h</NAME>
+      </HDRCAN_R>
+      <HDRCAN>
+        <NAME>can.h</NAME>
+      </HDRCAN>
+      <SRCCAN>
+        <NAME>can.c</NAME>
+      </SRCCAN>
+      <HDRADC_R>
+        <NAME>reg_adc.h</NAME>
+      </HDRADC_R>
+      <HDRADC>
+        <NAME>adc.h</NAME>
+      </HDRADC>
+      <SRCADC>
+        <NAME>adc.c</NAME>
+      </SRCADC>
+      <HET1ASMHDR>
+        <NAME/>
+      </HET1ASMHDR>
+      <HET1ASMSRC>
+        <NAME/>
+      </HET1ASMSRC>
+      <STDHDRHET>
+        <NAME>std_nhet.h</NAME>
+      </STDHDRHET>
+      <HDRHET_R>
+        <NAME>reg_het.h</NAME>
+      </HDRHET_R>
+      <HDRHET>
+        <NAME>het.h</NAME>
+      </HDRHET>
+      <SRCHET>
+        <NAME>het.c</NAME>
+      </SRCHET>
+      <HDRHTU_R>
+        <NAME>reg_htu.h</NAME>
+      </HDRHTU_R>
+      <HDRHTU>
+        <NAME>htu.h</NAME>
+      </HDRHTU>
+      <HET2ASMHDR>
+        <NAME/>
+      </HET2ASMHDR>
+      <HET2ASMSRC>
+        <NAME/>
+      </HET2ASMSRC>
+      <HDRESM_R>
+        <NAME>reg_esm.h</NAME>
+      </HDRESM_R>
+      <HDRESM>
+        <NAME>esm.h</NAME>
+      </HDRESM>
+      <SRCESM>
+        <NAME>esm.c</NAME>
+      </SRCESM>
+      <HDRI2C_R>
+        <NAME>reg_i2c.h</NAME>
+      </HDRI2C_R>
+      <HDRI2C>
+        <NAME>i2c.h</NAME>
+      </HDRI2C>
+      <SRCI2C/>
+      <HDR1EMAC>
+        <NAME>emac.h</NAME>
+      </HDR1EMAC>
+      <HDR2EMAC>
+        <NAME>hw_emac.h</NAME>
+      </HDR2EMAC>
+      <HDR3EMAC>
+        <NAME>hw_emac_ctrl.h</NAME>
+      </HDR3EMAC>
+      <HDR4EMAC>
+        <NAME>hw_mdio.h</NAME>
+      </HDR4EMAC>
+      <HDR5EMAC>
+        <NAME>hw_reg_access.h</NAME>
+      </HDR5EMAC>
+      <HDR6EMAC>
+        <NAME>mdio.h</NAME>
+      </HDR6EMAC>
+      <HDRPHY>
+        <NAME>phy_dp83640.h</NAME>
+      </HDRPHY>
+      <SRC1EMAC/>
+      <SRC2EMAC/>
+      <SRCPHY/>
+      <HDRDCC_R>
+        <NAME>reg_dcc.h</NAME>
+      </HDRDCC_R>
+      <HDRDCC>
+        <NAME>dcc.h</NAME>
+      </HDRDCC>
+      <SRCDCC/>
+      <HDRPOM_R>
+        <NAME>reg_pom.h</NAME>
+      </HDRPOM_R>
+      <HDRPOM>
+        <NAME>pom.h</NAME>
+      </HDRPOM>
+      <SRCPOM/>
+      <HDR1USB>
+        <NAME>usbcdc.h</NAME>
+      </HDR1USB>
+      <HDR2USB>
+        <NAME>usb_serial_structs.h</NAME>
+      </HDR2USB>
+      <HDR3USB>
+        <NAME>usbdcdc.h</NAME>
+      </HDR3USB>
+      <HDR4USB>
+        <NAME>usbdevice.h</NAME>
+      </HDR4USB>
+      <HDR5USB>
+        <NAME>usbdevicepriv.h</NAME>
+      </HDR5USB>
+      <HDR6USB>
+        <NAME>usb-ids.h</NAME>
+      </HDR6USB>
+      <HDR7USB>
+        <NAME>usblib.h</NAME>
+      </HDR7USB>
+      <HDR8USB>
+        <NAME>usb.h</NAME>
+      </HDR8USB>
+      <HDR9USB>
+        <NAME>hw_usb.h</NAME>
+      </HDR9USB>
+      <SRC1USB/>
+      <SRC2USB/>
+      <SRC3USB/>
+      <SRC5USB/>
+      <SRC6USB/>
+      <SRC7USB/>
+      <SRC8USB/>
+      <SRC9USB/>
+      <SRC10USB/>
+      <HDRCRC_R>
+        <NAME>reg_crc.h</NAME>
+      </HDRCRC_R>
+      <HDRCRC>
+        <NAME>crc.h</NAME>
+      </HDRCRC>
+      <SRCCRC/>
+      <HDRETPWM_R>
+        <NAME>reg_etpwm.h</NAME>
+      </HDRETPWM_R>
+      <HDRETPWM>
+        <NAME>etpwm.h</NAME>
+      </HDRETPWM>
+      <SRCETPWM>
+        <NAME>etpwm.c</NAME>
+      </SRCETPWM>
+      <HDRECAP_R>
+        <NAME>reg_ecap.h</NAME>
+      </HDRECAP_R>
+      <HDRECAP>
+        <NAME>ecap.h</NAME>
+      </HDRECAP>
+      <SRCECAP/>
+      <HDREQEP_R>
+        <NAME>reg_eqep.h</NAME>
+      </HDREQEP_R>
+      <HDREQEP>
+        <NAME>eqep.h</NAME>
+      </HDREQEP>
+      <SRCEQEP/>
+      <HDR1FEE>
+        <NAME>Device_RM46.h</NAME>
+      </HDR1FEE>
+      <HDR2FEE>
+        <NAME>Device_header.h</NAME>
+      </HDR2FEE>
+      <HDR3FEE>
+        <NAME>Device_types.h</NAME>
+      </HDR3FEE>
+      <HDR4FEE>
+        <NAME>ti_fee_cfg.h</NAME>
+      </HDR4FEE>
+      <HDR5FEE>
+        <NAME>MemMap.h</NAME>
+      </HDR5FEE>
+      <HDR6FEE>
+        <NAME>ti_fee_types.h</NAME>
+      </HDR6FEE>
+      <HDR7FEE>
+        <NAME>ti_fee.h</NAME>
+      </HDR7FEE>
+      <HDR8FEE>
+        <NAME>fee_interface.h</NAME>
+      </HDR8FEE>
+      <SRC1FEE/>
+      <SRC2FEE/>
+      <SRC3FEE/>
+      <SRC4FEE/>
+      <SRC5FEE/>
+      <SRC6FEE/>
+      <SRC7FEE/>
+      <SRC8FEE/>
+      <SRC9FEE/>
+      <SRC10FEE/>
+      <SRC11FEE/>
+      <SRC12FEE/>
+      <SRC13FEE/>
+      <SRC14FEE/>
+      <SRC15FEE/>
+      <SRC16FEE/>
+    </FILENAMES>
+  </SYSTEM>
+  <PINMUX>
+    <FILENAMES>
+      <HDRMUX_R>
+        <PATH>include\reg_pinmux.h</PATH>
+      </HDRMUX_R>
+      <HDRMUX>
+        <PATH>include\pinmux.h</PATH>
+      </HDRMUX>
+      <SRCMUX>
+        <PATH>source\pinmux.c</PATH>
+      </SRCMUX>
+    </FILENAMES>
+  </PINMUX>
+  <RTI>
+    <FILENAMES>
+      <HDRRTI_R>
+        <PATH>include\reg_rti.h</PATH>
+      </HDRRTI_R>
+      <HDRRTI>
+        <PATH>include\rti.h</PATH>
+      </HDRRTI>
+      <SRCRTI>
+        <PATH>source\rti.c</PATH>
+      </SRCRTI>
+    </FILENAMES>
+  </RTI>
+  <GIO>
+    <FILENAMES>
+      <HDRGIO_R>
+        <PATH>include\reg_gio.h</PATH>
+      </HDRGIO_R>
+      <HDRGIO>
+        <PATH>include\gio.h</PATH>
+      </HDRGIO>
+      <SRCGIO>
+        <PATH>source\gio.c</PATH>
+      </SRCGIO>
+    </FILENAMES>
+  </GIO>
+  <SCI>
+    <FILENAMES>
+      <HDRSCI_R>
+        <PATH>include\reg_sci.h</PATH>
+      </HDRSCI_R>
+      <HDRSCI>
+        <PATH>include\sci.h</PATH>
+      </HDRSCI>
+      <SRCSCI>
+        <PATH>source\sci.c</PATH>
+      </SRCSCI>
+    </FILENAMES>
+  </SCI>
+  <LIN>
+    <FILENAMES>
+      <HDRLIN_R>
+        <PATH>include\reg_lin.h</PATH>
+      </HDRLIN_R>
+      <HDRLIN>
+        <PATH>include\lin.h</PATH>
+      </HDRLIN>
+      <SRCLIN>
+        <PATH/>
+      </SRCLIN>
+    </FILENAMES>
+  </LIN>
+  <MIBSPI>
+    <FILENAMES>
+      <HDRMIBSPI_R>
+        <PATH>include\reg_mibspi.h</PATH>
+      </HDRMIBSPI_R>
+      <HDRMIBSPI>
+        <PATH>include\mibspi.h</PATH>
+      </HDRMIBSPI>
+      <SRCMIBSPI>
+        <PATH>source\mibspi.c</PATH>
+      </SRCMIBSPI>
+    </FILENAMES>
+  </MIBSPI>
+  <SPI>
+    <FILENAMES>
+      <HDRSPI_R>
+        <PATH>include\reg_spi.h</PATH>
+      </HDRSPI_R>
+      <HDRSPI>
+        <PATH>include\spi.h</PATH>
+      </HDRSPI>
+      <SRCSPI>
+        <PATH/>
+      </SRCSPI>
+    </FILENAMES>
+  </SPI>
+  <CAN>
+    <FILENAMES>
+      <HDRCAN_R>
+        <PATH>include\reg_can.h</PATH>
+      </HDRCAN_R>
+      <HDRCAN>
+        <PATH>include\can.h</PATH>
+      </HDRCAN>
+      <SRCCAN>
+        <PATH>source\can.c</PATH>
+      </SRCCAN>
+    </FILENAMES>
+  </CAN>
+  <ADC>
+    <FILENAMES>
+      <HDRADC_R>
+        <PATH>include\reg_adc.h</PATH>
+      </HDRADC_R>
+      <HDRADC>
+        <PATH>include\adc.h</PATH>
+      </HDRADC>
+      <SRCADC>
+        <PATH>source\adc.c</PATH>
+      </SRCADC>
+    </FILENAMES>
+  </ADC>
+  <HET>
+    <FILENAMES>
+      <STDHDRHET>
+        <PATH>include\std_nhet.h</PATH>
+      </STDHDRHET>
+      <HDRHET_R>
+        <PATH>include\reg_het.h</PATH>
+      </HDRHET_R>
+      <HDRHET>
+        <PATH>include\het.h</PATH>
+      </HDRHET>
+      <SRCHET>
+        <PATH>source\het.c</PATH>
+      </SRCHET>
+      <HDRHTU_R>
+        <PATH>include\reg_htu.h</PATH>
+      </HDRHTU_R>
+      <HDRHTU>
+        <PATH>include\htu.h</PATH>
+      </HDRHTU>
+    </FILENAMES>
+  </HET>
+  <ESM>
+    <FILENAMES>
+      <HDRESM_R>
+        <PATH>include\reg_esm.h</PATH>
+      </HDRESM_R>
+      <HDRESM>
+        <PATH>include\esm.h</PATH>
+      </HDRESM>
+      <SRCESM>
+        <PATH>source\esm.c</PATH>
+      </SRCESM>
+    </FILENAMES>
+  </ESM>
+  <I2C>
+    <FILENAMES>
+      <HDRI2C_R>
+        <PATH>include\reg_i2c.h</PATH>
+      </HDRI2C_R>
+      <HDRI2C>
+        <PATH>include\i2c.h</PATH>
+      </HDRI2C>
+      <SRCI2C>
+        <PATH/>
+      </SRCI2C>
+    </FILENAMES>
+  </I2C>
+  <EMAC>
+    <FILENAMES>
+      <HDR1EMAC>
+        <PATH>include\emac.h</PATH>
+      </HDR1EMAC>
+      <HDR2EMAC>
+        <PATH>include\hw_emac.h</PATH>
+      </HDR2EMAC>
+      <HDR3EMAC>
+        <PATH>include\hw_emac_ctrl.h</PATH>
+      </HDR3EMAC>
+      <HDR4EMAC>
+        <PATH>include\hw_mdio.h</PATH>
+      </HDR4EMAC>
+      <HDR5EMAC>
+        <PATH>include\hw_reg_access.h</PATH>
+      </HDR5EMAC>
+      <HDR6EMAC>
+        <PATH>include\mdio.h</PATH>
+      </HDR6EMAC>
+      <HDRPHY>
+        <PATH>include\phy_dp83640.h</PATH>
+      </HDRPHY>
+      <SRC1EMAC>
+        <PATH/>
+      </SRC1EMAC>
+      <SRC2EMAC>
+        <PATH/>
+      </SRC2EMAC>
+      <SRCPHY>
+        <PATH/>
+      </SRCPHY>
+    </FILENAMES>
+  </EMAC>
+  <DCC>
+    <FILENAMES>
+      <HDRDCC_R>
+        <PATH>include\reg_dcc.h</PATH>
+      </HDRDCC_R>
+      <HDRDCC>
+        <PATH>include\dcc.h</PATH>
+      </HDRDCC>
+      <SRCDCC>
+        <PATH/>
+      </SRCDCC>
+    </FILENAMES>
+  </DCC>
+  <POM>
+    <FILENAMES>
+      <HDRPOM_R>
+        <PATH>include\reg_pom.h</PATH>
+      </HDRPOM_R>
+      <HDRPOM>
+        <PATH>include\pom.h</PATH>
+      </HDRPOM>
+      <SRCPOM>
+        <PATH/>
+      </SRCPOM>
+    </FILENAMES>
+  </POM>
+  <USB>
+    <FILENAMES>
+      <HDR1USB>
+        <PATH>include\usbcdc.h</PATH>
+      </HDR1USB>
+      <HDR2USB>
+        <PATH>include\usb_serial_structs.h</PATH>
+      </HDR2USB>
+      <HDR3USB>
+        <PATH>include\usbdcdc.h</PATH>
+      </HDR3USB>
+      <HDR4USB>
+        <PATH>include\usbdevice.h</PATH>
+      </HDR4USB>
+      <HDR5USB>
+        <PATH>include\usbdevicepriv.h</PATH>
+      </HDR5USB>
+      <HDR6USB>
+        <PATH>include\usb-ids.h</PATH>
+      </HDR6USB>
+      <HDR7USB>
+        <PATH>include\usblib.h</PATH>
+      </HDR7USB>
+      <HDR8USB>
+        <PATH>include\usb.h</PATH>
+      </HDR8USB>
+      <HDR9USB>
+        <PATH>include\hw_usb.h</PATH>
+      </HDR9USB>
+      <SRC1USB>
+        <PATH/>
+      </SRC1USB>
+      <SRC2USB>
+        <PATH/>
+      </SRC2USB>
+      <SRC3USB>
+        <PATH/>
+      </SRC3USB>
+      <SRC5USB>
+        <PATH/>
+      </SRC5USB>
+      <SRC6USB>
+        <PATH/>
+      </SRC6USB>
+      <SRC7USB>
+        <PATH/>
+      </SRC7USB>
+      <SRC8USB>
+        <PATH/>
+      </SRC8USB>
+      <SRC9USB>
+        <PATH/>
+      </SRC9USB>
+      <SRC10USB>
+        <PATH/>
+      </SRC10USB>
+    </FILENAMES>
+  </USB>
+  <CRC>
+    <FILENAMES>
+      <HDRCRC_R>
+        <PATH>include\reg_crc.h</PATH>
+      </HDRCRC_R>
+      <HDRCRC>
+        <PATH>include\crc.h</PATH>
+      </HDRCRC>
+      <SRCCRC>
+        <PATH/>
+      </SRCCRC>
+    </FILENAMES>
+  </CRC>
+  <ETPWM>
+    <FILENAMES>
+      <HDRETPWM_R>
+        <PATH>include\reg_etpwm.h</PATH>
+      </HDRETPWM_R>
+      <HDRETPWM>
+        <PATH>include\etpwm.h</PATH>
+      </HDRETPWM>
+      <SRCETPWM>
+        <PATH>source\etpwm.c</PATH>
+      </SRCETPWM>
+    </FILENAMES>
+  </ETPWM>
+  <ECAP>
+    <FILENAMES>
+      <HDRECAP_R>
+        <PATH>include\reg_ecap.h</PATH>
+      </HDRECAP_R>
+      <HDRECAP>
+        <PATH>include\ecap.h</PATH>
+      </HDRECAP>
+      <SRCECAP>
+        <PATH/>
+      </SRCECAP>
+    </FILENAMES>
+  </ECAP>
+  <EQEP>
+    <FILENAMES>
+      <HDREQEP_R>
+        <PATH>include\reg_eqep.h</PATH>
+      </HDREQEP_R>
+      <HDREQEP>
+        <PATH>include\eqep.h</PATH>
+      </HDREQEP>
+      <SRCEQEP>
+        <PATH/>
+      </SRCEQEP>
+    </FILENAMES>
+  </EQEP>
+  <FEE>
+    <FILENAMES>
+      <HDR1FEE>
+        <PATH>include\Device_RM46.h</PATH>
+      </HDR1FEE>
+      <HDR2FEE>
+        <PATH>include\Device_header.h</PATH>
+      </HDR2FEE>
+      <HDR3FEE>
+        <PATH>include\Device_types.h</PATH>
+      </HDR3FEE>
+      <HDR4FEE>
+        <PATH>include\ti_fee_cfg.h</PATH>
+      </HDR4FEE>
+      <HDR5FEE>
+        <PATH>include\MemMap.h</PATH>
+      </HDR5FEE>
+      <HDR6FEE>
+        <PATH>include\ti_fee_types.h</PATH>
+      </HDR6FEE>
+      <HDR7FEE>
+        <PATH>include\ti_fee.h</PATH>
+      </HDR7FEE>
+      <HDR8FEE>
+        <PATH>include\fee_interface.h</PATH>
+      </HDR8FEE>
+      <SRC1FEE>
+        <PATH/>
+      </SRC1FEE>
+      <SRC2FEE>
+        <PATH/>
+      </SRC2FEE>
+      <SRC3FEE>
+        <PATH/>
+      </SRC3FEE>
+      <SRC4FEE>
+        <PATH/>
+      </SRC4FEE>
+      <SRC5FEE>
+        <PATH/>
+      </SRC5FEE>
+      <SRC6FEE>
+        <PATH/>
+      </SRC6FEE>
+      <SRC7FEE>
+        <PATH/>
+      </SRC7FEE>
+      <SRC8FEE>
+        <PATH/>
+      </SRC8FEE>
+      <SRC9FEE>
+        <PATH/>
+      </SRC9FEE>
+      <SRC10FEE>
+        <PATH/>
+      </SRC10FEE>
+      <SRC11FEE>
+        <PATH/>
+      </SRC11FEE>
+      <SRC12FEE>
+        <PATH/>
+      </SRC12FEE>
+      <SRC13FEE>
+        <PATH/>
+      </SRC13FEE>
+      <SRC14FEE>
+        <PATH/>
+      </SRC14FEE>
+      <SRC15FEE>
+        <PATH/>
+      </SRC15FEE>
+      <SRC16FEE>
+        <PATH/>
+      </SRC16FEE>
+    </FILENAMES>
+  </FEE>
 </SETTINGS>
Index: firmware/source/can.c
===================================================================
diff -u -r8b8fff67b95805272f37855346d600599aaec03d -re14686745aa9e4650a3112d108be02ba89d0dd97
--- firmware/source/can.c	(.../can.c)	(revision 8b8fff67b95805272f37855346d600599aaec03d)
+++ firmware/source/can.c	(.../can.c)	(revision e14686745aa9e4650a3112d108be02ba89d0dd97)
@@ -273,8 +273,8 @@
     } /* Wait */
 
     canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x10U & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x10U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 5U;
 
@@ -292,8 +292,8 @@
     } /* Wait */
 
     canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x40U & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x11U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 6U;
 
@@ -311,7 +311,7 @@
     } /* Wait */
 
     canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x70U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x20U & (uint32)0x1FFFFFFFU) << (uint32)0U);
     canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 7U;
@@ -330,8 +330,8 @@
     } /* Wait */
 
     canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x80U & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x21U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 8U;
 
@@ -349,7 +349,7 @@
     } /* Wait */
 
     canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x110U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x100U & (uint32)0x1FFFFFFFU) << (uint32)0U);
     canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 9U;
@@ -368,8 +368,8 @@
     } /* Wait */
 
     canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x200U & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x101U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 10U;
 
@@ -387,7 +387,7 @@
     } /* Wait */
 
     canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x402U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x102U & (uint32)0x1FFFFFFFU) << (uint32)0U);
     canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 11U;
@@ -406,11 +406,49 @@
     } /* Wait */
 
     canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x403U & (uint32)0x1FFFFFFFU) << (uint32)0U);
-    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x103U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 12U;
 
+    /** - Initialize message 13 
+    *     - Wait until IF1 is ready for use 
+    *     - Set message mask
+    *     - Set message control word
+    *     - Set message arbitration
+    *     - Set IF1 control byte
+    *     - Set IF1 message number
+    */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
+
+    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)402U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF1CMD  = (uint8) 0xF8U;
+    canREG1->IF1NO   = 13U;
+
+    /** - Initialize message 14 
+    *     - Wait until IF2 is ready for use 
+    *     - Set message mask
+    *     - Set message control word
+    *     - Set message arbitration
+    *     - Set IF2 control byte
+    *     - Set IF2 message number
+    */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
+
+    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)403U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2CMD  = (uint8) 0xF8U;
+    canREG1->IF2NO   = 14U;
+
     /** - Setup IF1 for data transmission 
     *     - Wait until IF1 is ready for use 
     *     - Set IF1 control byte