Index: App/Drivers/CPLD.c
===================================================================
diff -u -rad8ad611c910747eef92336a30b6520a83409532 -r1748019d93f9e95a125b0c6181c695b17fb63241
--- App/Drivers/CPLD.c	(.../CPLD.c)	(revision ad8ad611c910747eef92336a30b6520a83409532)
+++ App/Drivers/CPLD.c	(.../CPLD.c)	(revision 1748019d93f9e95a125b0c6181c695b17fb63241)
@@ -48,15 +48,15 @@
 #define TGL_OFF_REQ()      gioToggleBit( gioPORTB, OFF_REQUEST_GIO_PORT_PIN)
 #define SET_WD_PET()       gioSetBit( gioPORTB, WD_PET_GIO_PORT_PIN, PIN_SIGNAL_HIGH )
 #define SET_OFF_REQ()      gioSetBit( gioPORTB, OFF_REQUEST_GIO_PORT_PIN, PIN_SIGNAL_HIGH )
-#define SET_GREEN()        mibspiREG5->PC4 |= GREEN_SPI5_PORT_MASK
-#define SET_YELLOW()       mibspiREG5->PC4 |= RED_SPI5_PORT_MASK
-#define SET_RED()          mibspiREG5->PC4 |= YELLOW_SPI5_PORT_MASK
+#define SET_GREEN()        mibspiREG5->PC3 |= GREEN_SPI5_PORT_MASK
+#define SET_YELLOW()       mibspiREG5->PC3 |= YELLOW_SPI5_PORT_MASK
+#define SET_RED()          mibspiREG5->PC3 |= RED_SPI5_PORT_MASK
 
 #define CLR_WD_PET()       gioSetBit( gioPORTB, WD_PET_GIO_PORT_PIN, PIN_SIGNAL_LOW )
 #define CLR_OFF_REQ()      gioSetBit( gioPORTB, OFF_REQUEST_GIO_PORT_PIN, PIN_SIGNAL_LOW )
-#define CLR_GREEN()        mibspiREG5->PC5 |= GREEN_SPI5_PORT_MASK
-#define CLR_YELLOW()       mibspiREG5->PC5 |= YELLOW_SPI5_PORT_MASK
-#define CLR_RED()          mibspiREG5->PC5 |= RED_SPI5_PORT_MASK
+#define CLR_GREEN()        mibspiREG5->PC3 &= ~GREEN_SPI5_PORT_MASK
+#define CLR_YELLOW()       mibspiREG5->PC3 &= ~YELLOW_SPI5_PORT_MASK
+#define CLR_RED()          mibspiREG5->PC3 &= ~RED_SPI5_PORT_MASK
 
 /*************************************************************************
  * @brief initCPLD