Index: App/Services/CommInterrupts.c
===================================================================
diff -u -r38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9 -r81ca79980a75ab71985d3d610bcef45fd6730458
--- App/Services/CommInterrupts.c	(.../CommInterrupts.c)	(revision 38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9)
+++ App/Services/CommInterrupts.c	(.../CommInterrupts.c)	(revision 81ca79980a75ab71985d3d610bcef45fd6730458)
@@ -15,6 +15,7 @@
  *
  **************************************************************************/
 
+#include "can.h"
 #include "sci.h"
 #include "sys_dma.h"
 
@@ -35,6 +36,21 @@
 
 
 /*************************************************************************
+ * @brief canMessageNotification
+ * The canMessageNotification function handles CAN message notifications.
+ * @details
+ * Inputs : none
+ * Outputs : CAN message notification handled.
+ * @param node : which CAN controller
+ * @param messageBox : which message box triggered the message notification
+ * @return none
+ *************************************************************************/
+void canMessageNotification(canBASE_t *node, uint32 messageBox)
+{
+    handleCANMsgInterrupt( (CAN_MESSAGE_BOX_T)messageBox );
+}
+
+/*************************************************************************
  * @brief sciNotification
  * The sciNotification function handles UART communication error interrupts. \n
  * Frame and Over-run errors are handled.
@@ -74,27 +90,23 @@
         switch ( channel )
         {
             case DMA_CH0:  // FPGA receive channel
-                // clear DMA receipt
-                scilinREG->CLEARINT = SCI_DMA_RECEIVE_INT;
+                clearSCI2DMAReceiveInterrupt();
                 signalFPGAReceiptCompleted();
                 break;
 
             case DMA_CH1:  // PC receive channel
-                // clear DMA receipt
-                sciREG->CLEARINT = SCI_DMA_RECEIVE_INT;
+                clearSCI1DMAReceiveInterrupt();
                 // handle received packet from PC
                 handleUARTMsgRecvPacketInterrupt();
                 break;
 
             case DMA_CH2:  // FPGA transmit channel
-                // clear DMA xmit
-                scilinREG->CLEARINT = SCI_DMA_TRANSMIT_INT;
+                clearSCI2DMATransmitInterrupt();
                 signalFPGATransmitCompleted();
                 break;
 
             case DMA_CH3:  // PC transmit channel
-                // clear DMA xmit
-                sciREG->CLEARINT = SCI_DMA_TRANSMIT_INT;
+                clearSCI1DMATransmitInterrupt();
                 // send next pending packet to PC (if any)
                 handleUARTMsgXmitPacketInterrupt();
                 break;
@@ -106,3 +118,60 @@
     }
 }
 
+void setSCI1DMAReceiveInterrupt( void )
+{
+    sciREG->SETINT = SCI_DMA_RECEIVE_INT;
+}
+
+void setSCI1DMATransmitInterrupt( void )
+{
+    sciREG->SETINT = SCI_DMA_TRANSMIT_INT;
+}
+
+void clearSCI1DMAReceiveInterrupt( void )
+{
+    sciREG->CLEARINT = SCI_DMA_RECEIVE_INT;
+}
+
+void clearSCI1DMATransmitInterrupt( void )
+{
+    sciREG->CLEARINT = SCI_DMA_TRANSMIT_INT;
+}
+
+void setSCI2DMAReceiveInterrupt( void )
+{
+    scilinREG->SETINT = SCI_DMA_RECEIVE_INT;
+}
+
+void setSCI2DMATransmitInterrupt( void )
+{
+    scilinREG->SETINT = SCI_DMA_TRANSMIT_INT;
+}
+
+void clearSCI2DMAReceiveInterrupt( void )
+{
+    scilinREG->CLEARINT = SCI_DMA_RECEIVE_INT;
+}
+
+void clearSCI2DMATransmitInterrupt( void )
+{
+    scilinREG->CLEARINT = SCI_DMA_TRANSMIT_INT;
+}
+
+BOOL isSCI1DMATransmitInProgress( void )
+{
+    BOOL transmitterBusy = ( ( sciREG->FLR & (uint32)SCI_TX_INT ) == 0U ? TRUE : FALSE );
+    BOOL dmaTransmitterBusy = ( ( sciREG->CLEARINT & SCI_DMA_RECEIVE_INT ) != 0 ? TRUE : FALSE );
+
+    return ( ( transmitterBusy == TRUE ) || ( dmaTransmitterBusy == TRUE ) ? TRUE : FALSE );
+}
+
+BOOL isSCI2DMATransmitInProgress( void )
+{
+    BOOL transmitterBusy = ( ( scilinREG->FLR & (uint32)SCI_TX_INT ) == 0U ? TRUE : FALSE );
+    BOOL dmaTransmitterBusy = ( ( scilinREG->CLEARINT & SCI_DMA_RECEIVE_INT ) != 0 ? TRUE : FALSE );
+
+    return ( ( transmitterBusy == TRUE ) || ( dmaTransmitterBusy == TRUE ) ? TRUE : FALSE );
+}
+
+