Index: App/Services/FPGA.c =================================================================== diff -u -rcb47c5f896477ceae7597cb1a4191b3972e93f0d -r38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9 --- App/Services/FPGA.c (.../FPGA.c) (revision cb47c5f896477ceae7597cb1a4191b3972e93f0d) +++ App/Services/FPGA.c (.../FPGA.c) (revision 38ff7a6fbf82b86ab1bac3b7b24c4ea33d5419f9) @@ -16,20 +16,46 @@ * **************************************************************************/ -#include // for memcpy() +//#include // for memcpy() #include "sci.h" #include "sys_dma.h" -#include "Common.h" +#include "CommInterrupts.h" +#include "SystemCommMessages.h" +#include "FPGA.h" // ********** private definitions ********** +typedef enum FPGA_States +{ + FPGA_STATE_START = 0, + FPGA_STATE_READ_VERS_AND_DIAG, + FPGA_STATE_RCV_VERS_AND_DIAG, + FPGA_STATE_WRITE_ALL_ACTUATORS, + FPGA_STATE_RCV_ALL_SENSORS, + FPGA_STATE_FAILED, + NUM_OF_FPGA_STATES +} FPGA_STATE_T; + #define FPGA_WRITE_CMD_BUFFER_LEN 16 #define FPGA_READ_CMD_BUFFER_LEN 8 -#define FPGA_WRITE_RSP_BUFFER_LEN 10 +#define FPGA_WRITE_RSP_BUFFER_LEN 8 #define FPGA_READ_RSP_BUFFER_LEN 100 +#define FPGA_WRITE_CMD_CODE 0x55 +#define FPGA_READ_CMD_CODE 0x5A +#define FPGA_WRITE_CMD_ACK 0xA5 +#define FPGA_WRITE_CMD_NAK 0xAE +#define FPGA_READ_CMD_ACK 0xAA +#define FPGA_READ_CMD_NAK 0xAF + +#define FPGA_CRC_LEN 2 +#define FPGA_WRITE_CMD_HDR_LEN 5 +#define FPGA_READ_CMD_HDR_LEN 4 +#define FPGA_WRITE_RSP_HDR_LEN 1 +#define FPGA_READ_RSP_HDR_LEN 1 + #define SCI2_RECEIVE_DMA_REQUEST 28 #define SCI2_TRANSMIT_DMA_REQUEST 29 @@ -44,18 +70,27 @@ typedef struct { U08 artBloodValveState; // arterial blood valve set state + U08 venBloodValveState; // venous blood valve set state } FPGA_ACTUATORS_T; #pragma pack(pop) // ********** private data ********** +// FPGA state +static FPGA_STATE_T fpgaState = FPGA_STATE_START; + +static U32 fpgaReceiptCounter = 0; +static U32 fpgaTransmitCounter = 0; + // FPGA received sensor data from DMA bulk read -static FPGA_SENSORS_T fpgaSensors; +static FPGA_SENSORS_T fpgaSensorReadings; +// FPGA transmit actuator set points via DMA bulk write +static FPGA_ACTUATORS_T fpgaActuatorSetPoints; // FPGA comm buffers -static U08 fpgaWriteCmdBuffer[FPGA_WRITE_CMD_BUFFER_LEN] = {1,2,3,4,5,6,7,8,0,0,0,0,0,0,0,0}; -static U08 fpgaReadCmdBuffer[FPGA_READ_CMD_BUFFER_LEN] = {0,0,0,0,0,0,0,0}; -static U08 fpgaWriteResponseBuffer[FPGA_WRITE_RSP_BUFFER_LEN] = {0,0,0,0,0,0,0,0,0,0}; +static U08 fpgaWriteCmdBuffer[FPGA_WRITE_CMD_BUFFER_LEN];// = {1,2,3,4,5,6,7,8,0,0,0,0,0,0,0,0}; +static U08 fpgaReadCmdBuffer[FPGA_READ_CMD_BUFFER_LEN];// = {0,0,0,0,0,0,0,0}; +static U08 fpgaWriteResponseBuffer[FPGA_WRITE_RSP_BUFFER_LEN];// = {0,0,0,0,0,0,0,0}; static U08 fpgaReadResponseBuffer[FPGA_READ_RSP_BUFFER_LEN]; // DMA control records @@ -66,20 +101,33 @@ // FPGA data -U08 version; // FPGA version -U08 diagnostic; // FPGA diagnostic register +U08 fpgaId; // FPGA Id +U08 fpgaRev; // FPGA Revision +U08 fpgaDiag; // FPGA diagnostic register -DATA_DECL( TWO_WAY_STATE_T, BloodValveState, dataArterialBloodValveState, STATE_CLOSED, STATE_CLOSED ); +// sensor readings +DATA_DECL( OPN_CLS_STATE_T, ArtBloodValveState, dataArterialBloodValveState, STATE_CLOSED, STATE_CLOSED ); +DATA_DECL( OPN_CLS_STATE_T, VenBloodValveState, dataVenousBloodValveState, STATE_CLOSED, STATE_CLOSED ); +// actuator set points +DATA_DECL( OPN_CLS_STATE_T, ArtBloodValveSetState, dataArterialBloodValveSetState, STATE_CLOSED, STATE_CLOSED ); +DATA_DECL( OPN_CLS_STATE_T, VenBloodValveSetState, dataVenousBloodValveSetState, STATE_CLOSED, STATE_CLOSED ); + // ********** private function prototypes ********** +static FPGA_STATE_T handleFPGAReadVersionAndDiagnosticState( void ); +static FPGA_STATE_T handleFPGAReceiveVersionAndDiagnosticState( void ); +static FPGA_STATE_T handleFPGAWriteAllActuatorsState( void ); +static FPGA_STATE_T handleFPGAReceiveAllSensorsState( void ); + static void setupDMAForWriteCmd( U32 bytes2Transmit ); static void startDMAWriteCmd( void ); static void setupDMAForWriteResp( U32 bytes2Receive ); static void startDMAReceiptOfWriteResp( void ); static void setupDMAForReadCmd( U32 bytes2Transmit ); static void startDMAReadCmd( void ); static void setupDMAForReadResp( U32 bytes2Receive ); +static void startDMAReceiptOfReadResp( void ); /************************************************************************* * @brief initFPGA @@ -92,39 +140,35 @@ *************************************************************************/ void initFPGA( void ) { - sciEnableLoopback( scilinREG, Digital_Lbk ); // TODO - for test only - // enable interrupt notifications for FPGA serial port - //sciEnableNotification( scilinREG, SCI_TX_INT | SCI_RX_INT | SCI_OE_INT | SCI_FE_INT ); - //sciEnableNotification( scilinREG, SCI_RX_INT | SCI_OE_INT | SCI_FE_INT ); sciEnableNotification( scilinREG, SCI_OE_INT | SCI_FE_INT ); - // Enable DMA block transfer complete interrupts - dmaEnableInterrupt( DMA_CH0, BTC ); - dmaEnableInterrupt( DMA_CH2, BTC ); // assign DMA channels to h/w DMA requests dmaReqAssign( DMA_CH0, SCI2_RECEIVE_DMA_REQUEST ); dmaReqAssign( DMA_CH2, SCI2_TRANSMIT_DMA_REQUEST ); // set DMA channel priorities dmaSetPriority( DMA_CH0, HIGHPRIORITY ); dmaSetPriority( DMA_CH2, LOWPRIORITY ); + // Enable DMA block transfer complete interrupts + dmaEnableInterrupt( DMA_CH0, BTC ); + dmaEnableInterrupt( DMA_CH2, BTC ); // initialize FPGA DMA Write Control Record fpgaDMAWriteControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + fpgaDMAWriteControlRecord.SADD = (U32)fpgaWriteCmdBuffer; // transfer source address fpgaDMAWriteControlRecord.DADD = (U32)(&(scilinREG->TD)); // dest. is SCI2 xmit register - fpgaDMAWriteControlRecord.SADD = (U32)fpgaWriteResponseBuffer; // transfer source address fpgaDMAWriteControlRecord.CHCTRL = 0; // no chaining fpgaDMAWriteControlRecord.ELCNT = 1; // frame is 1 element fpgaDMAWriteControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known fpgaDMAWriteControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte fpgaDMAWriteControlRecord.WRSIZE = ACCESS_8_BIT; // fpgaDMAWriteControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer - fpgaDMAWriteControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed fpgaDMAWriteControlRecord.ADDMODERD = ADDR_INC1; // source addressing mode is post-increment + fpgaDMAWriteControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed fpgaDMAWriteControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAWriteControlRecord.ELSOFFSET = 0; // # of bytes to advance at source memory after each element + fpgaDMAWriteControlRecord.ELSOFFSET = 0; // not used fpgaDMAWriteControlRecord.ELDOFFSET = 0; // not used - fpgaDMAWriteControlRecord.FRSOFFSET = 0; // # of bytes to advance at source memory after each frame + fpgaDMAWriteControlRecord.FRSOFFSET = 0; // not used fpgaDMAWriteControlRecord.FRDOFFSET = 0; // not used // initialize FPGA DMA Write Response Control Record @@ -140,33 +184,33 @@ fpgaDMAWriteRespControlRecord.ADDMODERD = ADDR_FIXED; // source addressing mode is fixed fpgaDMAWriteRespControlRecord.ADDMODEWR = ADDR_INC1; // dest. addressing mode is post-increment fpgaDMAWriteRespControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAWriteRespControlRecord.ELDOFFSET = 0; // # of bytes to advance at destination memory after each element + fpgaDMAWriteRespControlRecord.ELDOFFSET = 0; // not used fpgaDMAWriteRespControlRecord.ELSOFFSET = 0; // not used - fpgaDMAWriteRespControlRecord.FRDOFFSET = 0; // # of bytes to advance at destination memory after each frame + fpgaDMAWriteRespControlRecord.FRDOFFSET = 0; // not used fpgaDMAWriteRespControlRecord.FRSOFFSET = 0; // not used // initialize FPGA DMA Read Control Record fpgaDMAReadControlRecord.PORTASGN = 4; // port B (only choice per datasheet) + fpgaDMAReadControlRecord.SADD = (U32)fpgaReadCmdBuffer; // transfer source address fpgaDMAReadControlRecord.DADD = (U32)(&(scilinREG->TD)); // dest. is SCI2 xmit register - fpgaDMAReadControlRecord.SADD = (U32)fpgaWriteResponseBuffer;// transfer source address fpgaDMAReadControlRecord.CHCTRL = 0; // no chaining fpgaDMAReadControlRecord.ELCNT = 1; // frame is 1 element fpgaDMAReadControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known fpgaDMAReadControlRecord.RDSIZE = ACCESS_8_BIT; // element size is 1 byte fpgaDMAReadControlRecord.WRSIZE = ACCESS_8_BIT; // fpgaDMAReadControlRecord.TTYPE = FRAME_TRANSFER; // transfer type is block transfer - fpgaDMAReadControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed fpgaDMAReadControlRecord.ADDMODERD = ADDR_INC1; // source addressing mode is post-increment + fpgaDMAReadControlRecord.ADDMODEWR = ADDR_FIXED; // dest. addressing mode is fixed fpgaDMAReadControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAReadControlRecord.ELSOFFSET = 0; // # of bytes to advance at source memory after each element + fpgaDMAReadControlRecord.ELSOFFSET = 0; // not used fpgaDMAReadControlRecord.ELDOFFSET = 0; // not used - fpgaDMAReadControlRecord.FRSOFFSET = 0; // # of bytes to advance at source memory after each frame + fpgaDMAReadControlRecord.FRSOFFSET = 0; // not used fpgaDMAReadControlRecord.FRDOFFSET = 0; // not used // initialize FPGA DMA Read Response Control Record fpgaDMAReadRespControlRecord.PORTASGN = 4; // port B (only choice per datasheet) fpgaDMAReadRespControlRecord.SADD = (U32)(&(scilinREG->RD)); // source is SCI2 recv register - fpgaDMAReadRespControlRecord.DADD = (U32)fpgaWriteResponseBuffer; // transfer destination address + fpgaDMAReadRespControlRecord.DADD = (U32)fpgaReadResponseBuffer; // transfer destination address fpgaDMAReadRespControlRecord.CHCTRL = 0; // no chaining fpgaDMAReadRespControlRecord.ELCNT = 1; // frame is 1 element fpgaDMAReadRespControlRecord.FRCNT = 0; // block is TBD frames - will be populated later when known @@ -176,19 +220,49 @@ fpgaDMAReadRespControlRecord.ADDMODERD = ADDR_FIXED; // source addressing mode is fixed fpgaDMAReadRespControlRecord.ADDMODEWR = ADDR_INC1; // dest. addressing mode is post-increment fpgaDMAReadRespControlRecord.AUTOINIT = AUTOINIT_OFF; // auto-init off - fpgaDMAReadRespControlRecord.ELDOFFSET = 0; // # of bytes to advance at destination memory after each element + fpgaDMAReadRespControlRecord.ELDOFFSET = 0; // not used fpgaDMAReadRespControlRecord.ELSOFFSET = 0; // not used - fpgaDMAReadRespControlRecord.FRDOFFSET = 0; // # of bytes to advance at destination memory after each frame + fpgaDMAReadRespControlRecord.FRDOFFSET = 0; // not used fpgaDMAReadRespControlRecord.FRSOFFSET = 0; // not used // TODO - this is a DMA xmit and recv via loopback test - setupDMAForWriteResp( 8 ); - startDMAReceiptOfWriteResp(); - setupDMAForWriteCmd( 8 ); - startDMAWriteCmd(); +// setupDMAForWriteResp( 8 ); +// setupDMAForWriteCmd( 8 ); +// startDMAReceiptOfWriteResp(); +// startDMAWriteCmd(); } /************************************************************************* + * @brief signalFPGAReceiptCompleted + * The signalFPGAReceiptCompleted function increments a counter to indicate \n + * that another DMA receipt from the FPGA has completed. + * @details + * Inputs : none + * Outputs : fpgaReceiptCounter + * @param none + * @return none + *************************************************************************/ +void signalFPGAReceiptCompleted( void ) +{ + fpgaReceiptCounter++; +} + +/************************************************************************* + * @brief signalFPGATransmitCompleted + * The signalFPGATransmitCompleted function increments a counter to indicate \n + * that another DMA transmit to the FPGA has completed. + * @details + * Inputs : none + * Outputs : fpgaReceiptCounter + * @param none + * @return none + *************************************************************************/ +void signalFPGATransmitCompleted( void ) +{ + fpgaTransmitCounter++; +} + +/************************************************************************* * @brief execFPGA * The execFPGA function manages data exchanges with the FPGA. * @details @@ -199,113 +273,416 @@ *************************************************************************/ void execFPGA( void ) { - U08 x; - x = fpgaWriteResponseBuffer[0]; + switch ( fpgaState ) + { + case FPGA_STATE_START: + fpgaState = FPGA_STATE_READ_VERS_AND_DIAG; + break; + + case FPGA_STATE_READ_VERS_AND_DIAG: + fpgaState = handleFPGAReadVersionAndDiagnosticState(); + break; + + case FPGA_STATE_RCV_VERS_AND_DIAG: + fpgaState = handleFPGAReceiveVersionAndDiagnosticState(); + break; + + case FPGA_STATE_WRITE_ALL_ACTUATORS: + fpgaState = handleFPGAWriteAllActuatorsState(); + break; + + case FPGA_STATE_RCV_ALL_SENSORS: + fpgaState = handleFPGAReceiveAllSensorsState(); + break; + + case FPGA_STATE_FAILED: + // do nothing - we'll be stuck here + break; + + default: + // TODO - fault + break; + } } +/************************************************************************* + * @brief handleFPGAReadVersionAndDiagnosticState + * The handleFPGAReadVersionAndDiagnosticState function handles the FPGA state \n + * where the read version/diag command is sent to the FPGA. + * @details + * Inputs : none + * Outputs : read command sent to FPGA + * @param none + * @return next FPGA state + *************************************************************************/ +static FPGA_STATE_T handleFPGAReadVersionAndDiagnosticState( void ) +{ + FPGA_STATE_T result = FPGA_STATE_RCV_VERS_AND_DIAG; + // construct read command to read 3 registers starting at address 0 + fpgaReadCmdBuffer[0] = FPGA_READ_CMD_CODE; + fpgaReadCmdBuffer[1] = 0x00; // start at FPGA address 0 + fpgaReadCmdBuffer[2] = 0x00; + fpgaReadCmdBuffer[3] = 0x03; // read 3 registers + fpgaReadCmdBuffer[4] = 0x00; // no CRC for now + fpgaReadCmdBuffer[5] = 0x00; // TODO - add a 16-bit CRC function to calculate CRC + // prep DMA for sending the read cmd and receiving the response + setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + 3 + FPGA_CRC_LEN ); + setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN ); + startDMAReceiptOfReadResp(); + startDMAReadCmd(); + return result; +} +/************************************************************************* + * @brief handleFPGAReceiveVersionAndDiagnosticState + * The handleFPGAReceiveVersionAndDiagnosticState function handles the FPGA state \n + * where the version/diag read response should be ready to parse. + * @details + * Inputs : none + * Outputs : version/diag values updated + * @param none + * @return next FPGA state + *************************************************************************/ +static FPGA_STATE_T handleFPGAReceiveVersionAndDiagnosticState( void ) +{ + FPGA_STATE_T result = FPGA_STATE_READ_VERS_AND_DIAG; + // did FPGA response? + if ( fpgaReceiptCounter > 0 ) + { + fpgaReceiptCounter = 0; + fpgaTransmitCounter = 0; + // did FPGA Ack the read command? + if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK ) + { + // does the FPGA response CRC check out? + if ( 1 ) // TODO - check response CRC + { // capture the read values + fpgaId = fpgaReadResponseBuffer[1]; + fpgaRev = fpgaReadResponseBuffer[2]; + fpgaDiag = fpgaReadResponseBuffer[3]; + result = FPGA_STATE_WRITE_ALL_ACTUATORS; + } + } + } + + return result; +} + +/************************************************************************* + * @brief handleFPGAWriteAllActuatorsState + * The handleFPGAWriteAllActuatorsState function handles the FPGA state \n + * where the bulk write command is sent to the FPGA. + * @details + * Inputs : actuator set points + * Outputs : actuator set points sent to FPGA + * @param none + * @return next FPGA state + *************************************************************************/ +static FPGA_STATE_T handleFPGAWriteAllActuatorsState( void ) +{ + FPGA_STATE_T result = FPGA_STATE_RCV_ALL_SENSORS; + + return result; +} + +/************************************************************************* + * @brief handleFPGAReceiveAllSensorsState + * The handleFPGAReceiveAllSensorsState function handles the FPGA state \n + * where the bulk read response should be ready to parse. + * @details + * Inputs : none + * Outputs : sensor values updated + * @param none + * @return next FPGA state + *************************************************************************/ +static FPGA_STATE_T handleFPGAReceiveAllSensorsState( void ) +{ + FPGA_STATE_T result = FPGA_STATE_WRITE_ALL_ACTUATORS; + + return result; +} + +/************************************************************************* + * @brief setupDMAForWriteCmd + * The setupDMAForWriteCmd function sets the byte count for the next DMA \n + * write command to the FPGA. + * @details + * Inputs : none + * Outputs : # of bytes for next FPGA write command is set + * @param bytes2Transmit : # of bytes to be transmitted via DMA to the FPGA. + * @return none + *************************************************************************/ static void setupDMAForWriteCmd( U32 bytes2Transmit ) { fpgaDMAWriteControlRecord.FRCNT = bytes2Transmit; } +/************************************************************************* + * @brief startDMAWriteCmd + * The startDMAWriteCmd function initiates the DMA transmit for the next \n + * DMA write command to the FPGA. + * @details + * Inputs : none + * Outputs : DMA write command to FPGA is initiated + * @param none + * @return none + *************************************************************************/ static void startDMAWriteCmd( void ) { dmaSetCtrlPacket( DMA_CH2, fpgaDMAWriteControlRecord ); dmaSetChEnable( DMA_CH2, DMA_HW ); - scilinREG->SETINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ + scilinREG->SETINT = SCI_DMA_TRANSMIT_INT; } +/************************************************************************* + * @brief setupDMAForWriteResp + * The setupDMAForWriteResp function sets the expected byte count for the \n + * next DMA write command response from the FPGA. + * @details + * Inputs : none + * Outputs : # of expected bytes for next FPGA write command response is set + * @param bytes2Receive : # of bytes expected to be transmitted via DMA from the FPGA. + * @return none + *************************************************************************/ static void setupDMAForWriteResp( U32 bytes2Receive ) { fpgaDMAWriteRespControlRecord.FRCNT = bytes2Receive; } +/************************************************************************* + * @brief startDMAReceiptOfWriteResp + * The startDMAReceiptOfWriteResp function initiates readiness of the DMA \n + * receiver for the next DMA write command response from the FPGA. + * @details + * Inputs : none + * Outputs : DMA write command response is ready to be received from the FPGA + * @param none + * @return none + *************************************************************************/ static void startDMAReceiptOfWriteResp( void ) { dmaSetCtrlPacket( DMA_CH0, fpgaDMAWriteRespControlRecord ); dmaSetChEnable( DMA_CH0, DMA_HW ); - scilinREG->SETINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ - scilinREG->SETINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ + scilinREG->SETINT = SCI_DMA_RECEIVE_INT; } +/************************************************************************* + * @brief setupDMAForReadCmd + * The setupDMAForReadCmd function sets the byte count for the next DMA \n + * read command to the FPGA. + * @details + * Inputs : none + * Outputs : # of bytes for next FPGA read command is set + * @param bytes2Transmit : # of bytes to be transmitted via DMA to the FPGA. + * @return none + *************************************************************************/ static void setupDMAForReadCmd( U32 bytes2Transmit ) { fpgaDMAReadControlRecord.FRCNT = bytes2Transmit; } +/************************************************************************* + * @brief startDMAReadCmd + * The startDMAReadCmd function initiates the DMA transmit for the next \n + * DMA read command to the FPGA. + * @details + * Inputs : none + * Outputs : DMA read command to FPGA is initiated + * @param none + * @return none + *************************************************************************/ static void startDMAReadCmd( void ) { dmaSetCtrlPacket( DMA_CH2, fpgaDMAReadControlRecord ); dmaSetChEnable( DMA_CH2, DMA_HW ); - scilinREG->SETINT = (uint32)((uint32)1U << 16U); /* Tx DMA */ + scilinREG->SETINT = SCI_DMA_TRANSMIT_INT; } +/************************************************************************* + * @brief setupDMAForReadResp + * The setupDMAForReadResp function sets the expected byte count for the \n + * next DMA read command response from the FPGA. + * @details + * Inputs : none + * Outputs : # of expected bytes for next FPGA read command response is set + * @param bytes2Receive : # of expected bytes to be transmitted via DMA from the FPGA. + * @return none + *************************************************************************/ static void setupDMAForReadResp( U32 bytes2Receive ) { fpgaDMAReadRespControlRecord.FRCNT = bytes2Receive; } +/************************************************************************* + * @brief startDMAReceiptOfReadResp + * The startDMAReceiptOfReadResp function initiates readiness of the DMA \n + * receiver for the next DMA read command response from the FPGA. + * @details + * Inputs : none + * Outputs : DMA read command response is ready to be received from the FPGA + * @param none + * @return none + *************************************************************************/ static void startDMAReceiptOfReadResp( void ) { dmaSetCtrlPacket( DMA_CH0, fpgaDMAReadRespControlRecord ); dmaSetChEnable( DMA_CH0, DMA_HW ); - scilinREG->SETINT = (uint32)((uint32)1U << 18U); /* Rx DMA All */ - scilinREG->SETINT = (uint32)((uint32)1U << 17U); /* Rx DMA */ + scilinREG->SETINT = SCI_DMA_RECEIVE_INT; } - - -U08 getFPGAVersion( void ) +/************************************************************************* + * @brief getFPGAId + * The getFPGAId function gets the version read from the Id register \n + * of the FPGA. + * @details + * Inputs : fpgaId + * Outputs : none + * @param none + * @return Id + *************************************************************************/ +U08 getFPGAId( void ) { + return fpgaId; +} +/************************************************************************* + * @brief getFPGARev + * The getFPGARev function gets the revision read from the Rev register \n + * of the FPGA. + * @details + * Inputs : fpgaRev + * Outputs : none + * @param none + * @return Revision + *************************************************************************/ +U08 getFPGARev( void ) +{ + return fpgaRev; } +/************************************************************************* + * @brief getFPGADiag + * The getFPGADiag function gets the version read from the diagnostic register \n + * of the FPGA. + * @details + * Inputs : fpgaDiag + * Outputs : none + * @param none + * @return fpgaDiag + *************************************************************************/ U08 getFPGADiag( void ) { - U08 result = 0; - - return result; + return fpgaDiag; } -void setFPGADiag( void ) -{ +/************************************************************************* + * @brief getArterialBloodValveState + * The getArterialBloodValveState function gets the latest arterial blood \n + * valve state read from the FPGA. + * @details + * Inputs : dataArterialBloodValveState + * Outputs : none + * @param none + * @return The last read state for the arterial blood valve + *************************************************************************/ +DATA_GET( OPN_CLS_STATE_T, getArterialBloodValveState, dataArterialBloodValveState ) -} +/************************************************************************* + * @brief getArterialBloodValveSetState + * The getArterialBloodValveSetState function gets the current arterial blood \n + * valve set state that is being sent to the FPGA. + * @details + * Inputs : dataArterialBloodValveSetState + * Outputs : none + * @param none + * @return The current set state for the arterial blood valve + *************************************************************************/ +DATA_GET( OPN_CLS_STATE_T, getArterialBloodValveSetState, dataArterialBloodValveSetState ) -DATA_GET( TWO_WAY_STATE_T, getArterialBloodValveState, dataArterialBloodValveState ) +/************************************************************************* + * @brief getVenousBloodValveState + * The getVenousBloodValveState function gets the latest venous blood \n + * valve state read from the FPGA. + * @details + * Inputs : dataVenousBloodValveState + * Outputs : none + * @param none + * @return The last read state for the venous blood valve + *************************************************************************/ +DATA_GET( OPN_CLS_STATE_T, getVenousBloodValveState, dataVenousBloodValveState ) -BOOL dialinSetArterialBloodValveStateOverride( TWO_WAY_STATE_T state ) -{ - BOOL result = FALSE; +/************************************************************************* + * @brief getVenousBloodValveSetState + * The getVenousBloodValveSetState function gets the current venous blood \n + * valve set state that is being sent to the FPGA. + * @details + * Inputs : dataVenousBloodValveSetState + * Outputs : none + * @param none + * @return The current set state for the venous blood valve + *************************************************************************/ +DATA_GET( OPN_CLS_STATE_T, getVenousBloodValveSetState, dataVenousBloodValveSetState ) - // verify dialin login successfully completed before executing override - if ( 1 ) // TODO - call function to check login - { - result = TRUE; - dataArterialBloodValveState.ovData = state; - dataArterialBloodValveState.override = OVERRIDE_KEY; - } - return result; -} -BOOL dialinResetArterialBloodValveStateOverride( void ) -{ - BOOL result = FALSE; - // verify dialin login successfully completed before executing override reset - if ( 1 ) // TODO - call function to check login - { - result = TRUE; - dataArterialBloodValveState.override = OVERRIDE_RESET; - dataArterialBloodValveState.ovData = dataArterialBloodValveState.ovInitData; - } +/************************************************************************* + * @brief testSetArterialBloodValveStateOverride and testResetArterialBloodValveStateOverride + * The testSetArterialBloodValveStateOverride function overrides the \n + * arterial blood valve state that is being read from the FPGA. \n + * The testResetArterialBloodValveStateOverride function resets a previous \n + * override of the arterial blood valve state back to sensed state. \n + * @details + * Inputs : none + * Outputs : dataArterialBloodValveState + * @param none + * @return TRUE if successful, FALSE if not + *************************************************************************/ +DATA_OVERRIDE_FUNC( OPN_CLS_STATE_T, testSetArterialBloodValveStateOverride, testResetArterialBloodValveStateOverride, dataArterialBloodValveState ) - return result; -} +/************************************************************************* + * @brief testSetArterialBloodValveSetStateOverride and testResetArterialBloodValveSetStateOverride + * The testSetArterialBloodValveSetStateOverride function overrides the \n + * arterial blood valve set state that is being sent to the FPGA. \n + * The testResetArterialBloodValveSetStateOverride function resets a previous \n + * override of the arterial blood valve set state back to controlled state. + * @details + * Inputs : none + * Outputs : dataArterialBloodValveSetState + * @param none + * @return TRUE if successful, FALSE if not + *************************************************************************/ +DATA_OVERRIDE_FUNC( OPN_CLS_STATE_T, testSetArterialBloodValveSetStateOverride, testResetArterialBloodValveSetStateOverride, dataArterialBloodValveSetState ) +/************************************************************************* + * @brief testSetVenousBloodValveStateOverride and testResetVenousBloodValveStateOverride + * The testSetVenousBloodValveStateOverride function overrides the \n + * venous blood valve state that is being read from the FPGA. \n + * The testResetVenousBloodValveStateOverride function resets a previous \n + * override of the venous blood valve state back to sensed state. + * @details + * Inputs : none + * Outputs : dataVenousBloodValveState + * @param none + * @return TRUE if successful, FALSE if not + *************************************************************************/ +DATA_OVERRIDE_FUNC( OPN_CLS_STATE_T, testSetVenousBloodValveStateOverride, testResetVenousBloodValveStateOverride, dataVenousBloodValveState ) +/************************************************************************* + * @brief testSetVenousBloodValveSetStateOverride and testResetVenousBloodValveSetStateOverride + * The testSetVenousBloodValveSetStateOverride function overrides the \n + * venous blood valve state that is being read from the FPGA. \n + * The testResetVenousBloodValveSetStateOverride function resets a previous \n + * override of the venous blood valve set state back to controlled state. \n + * @details + * Inputs : none + * Outputs : dataVenousBloodValveSetState + * @param none + * @return TRUE if successful, FALSE if not + *************************************************************************/ +DATA_OVERRIDE_FUNC( OPN_CLS_STATE_T, testSetVenousBloodValveSetStateOverride, testResetVenousBloodValveSetStateOverride, dataVenousBloodValveSetState ) + +