Index: App/Services/FPGA.c =================================================================== diff -u -rf97f667f6147c200e47e46d50306a89ee57c19f3 -rc8c2c1b2a5b2d4836d19fa3c719446c3089c4a36 --- App/Services/FPGA.c (.../FPGA.c) (revision f97f667f6147c200e47e46d50306a89ee57c19f3) +++ App/Services/FPGA.c (.../FPGA.c) (revision c8c2c1b2a5b2d4836d19fa3c719446c3089c4a36) @@ -63,6 +63,8 @@ #define SCI2_RECEIVE_DMA_REQUEST 28 #define SCI2_TRANSMIT_DMA_REQUEST 29 +#define MAX_COMM_ERROR_RETRIES 5 + // FPGA Sensors Record #pragma pack(push,1) typedef struct @@ -98,6 +100,7 @@ // FPGA state static FPGA_STATE_T fpgaState = FPGA_STATE_START; +static U32 fpgaCommRetryCount = 0; static U32 fpgaReceiptCounter = 0; static U32 fpgaTransmitCounter = 0; static BOOL fpgaWriteCommandInProgress = FALSE; @@ -302,13 +305,11 @@ // see if we want to follow up with a bulk read command if ( TRUE == fpgaBulkWriteAndReadInProgress ) { - // first receipt? - if ( 1 == fpgaReceiptCounter ) - { - fpgaBulkWriteAndReadInProgress = FALSE; - fpgaReadCommandInProgress = TRUE; - // TODO - initiate bulk read command - } + fpgaBulkWriteAndReadInProgress = FALSE; + fpgaReadCommandInProgress = TRUE; + // initiate bulk read command + startDMAReceiptOfReadResp(); + startDMAReadCmd(); } } @@ -349,8 +350,8 @@ fpgaState = handleFPGAReceiveHeaderState(); break; + // TODO - sensor/ADC init/configuration states - case FPGA_STATE_RCV_ALL_SENSORS: fpgaState = handleFPGAReceiveAllSensorsState(); break; @@ -371,6 +372,12 @@ break; } + // if retries for commands exceeds limit, fault + if ( fpgaCommRetryCount > MAX_COMM_ERROR_RETRIES ) + { + // TODO - FPGA comm fault + } + // reset comm flags after processing incoming responses resetFPGACommFlags(); } @@ -393,8 +400,8 @@ fpgaState = handleFPGAReadHeaderState(); break; + // TODO - sensor/ADC init/configuration states - case FPGA_STATE_WRITE_ALL_ACTUATORS: fpgaState = handleFPGAWriteAllActuatorsState(); break; @@ -471,15 +478,25 @@ { // does the FPGA response CRC check out? if ( 1 ) // TODO - check response CRC - { // capture the read values + { + fpgaCommRetryCount = 0; + // capture the read values memcpy( &fpgaHeader, &fpgaReadResponseBuffer[1], sizeof(FPGA_HEADER_T) ); result = FPGA_STATE_WRITE_ALL_ACTUATORS; } + else + { + fpgaCommRetryCount++; + } } + else // header read was NAK'd + { + fpgaCommRetryCount++; + } } - else // + else // no response to read command { - + fpgaCommRetryCount++; } // shouldn't be any data received at this time @@ -505,7 +522,7 @@ // construct bulk write command to write actuator data registers starting at address 3 (TODO - change address later) fpgaWriteCmdBuffer[0] = FPGA_WRITE_CMD_CODE; - fpgaWriteCmdBuffer[1] = 0x02; // start at FPGA address 8 + fpgaWriteCmdBuffer[1] = 0x08; // start at FPGA address 8 fpgaWriteCmdBuffer[2] = 0x00; fpgaWriteCmdBuffer[3] = 1; // TODO - replace 1 with sizeof(FPGA_ACTUATORS_T) // memcpy( &(fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN]), &fpgaActuatorSetPoints, sizeof(FPGA_ACTUATORS_T) ); @@ -565,15 +582,25 @@ { // does the FPGA response CRC check out? if ( 1 ) // TODO - check response CRC - { // capture the read values + { + fpgaCommRetryCount = 0; + // capture the read values memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[1], sizeof(FPGA_SENSORS_T) ); result = FPGA_STATE_WRITE_ALL_ACTUATORS; } + else // bad CRC + { + fpgaCommRetryCount++; + } } + else // read command was NAK'd + { + fpgaCommRetryCount++; + } } - else + else // no response to read command { - // TODO - ??? + fpgaCommRetryCount++; } // shouldn't be any data received at this time