Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r037f0edb0b880130563058c809ba50308f2a63e9 -re6f3a632890f96a5aa282922d11df148bdd06587
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 037f0edb0b880130563058c809ba50308f2a63e9)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision e6f3a632890f96a5aa282922d11df148bdd06587)
@@ -18,12 +18,14 @@
 
 #include <string.h>     // for memset(), memcpy()
 
+#include "gio.h"
 #include "sci.h"
 #include "sys_dma.h"
 
-#include "FPGA.h"
 #include "Comm.h"
 #include "Compatible.h"
+#include "FPGA.h"
+#include "PersistentAlarm.h"
 #include "SystemCommMessages.h"
 #include "Utilities.h"
 
@@ -79,6 +81,12 @@
 
 #define FPGA_FLUIDLEAK_STATE_MASK       0x0004                  ///< Bit mask for fluid leak detector.
 
+#define FLUID_DOOR_SWITCH_MASK          0x08                    ///< Fluid door switch bit mask.
+#define DIALYSATE_CAP_SWITCH_MASK       0x10                    ///< Dialysate cap switch bit mask.
+#define CONCENTRATE_CAP_SWITCH_MASK     0x1A                    ///< Concentrate cap switch bit mask.
+#define FPGA_POWER_OUT_TIMEOUT_MS       ( 2 * MS_PER_SECOND )   ///< FPGA power out timeout in milliseconds.
+#define FPGA_GPIO_POWER_STATUS_PIN      7                       ///< FPGA GPIO power status pin
+
 // FPGA header struct.
 #pragma pack(push,1)
 typedef struct
@@ -245,6 +253,7 @@
 static void startDMAReceiptOfReadResp( void );
 
 static void consumeUnexpectedData( void );
+static void monitorFPGAPowerStatus( void );
 
 /*********************************************************************//**
  * @brief
@@ -358,6 +367,9 @@
 
     // there shouldn't be any data pending yet
     consumeUnexpectedData();
+
+    // Initialize the persistent alarm for FPGA power out
+    initPersistentAlarm( ALARM_ID_DG_FPGA_POWER_OUT_TIMEOUT, FPGA_POWER_OUT_TIMEOUT_MS, FPGA_POWER_OUT_TIMEOUT_MS );
 }
 
 /*********************************************************************//**
@@ -480,6 +492,9 @@
 
     // reset comm flags after processing incoming responses
     resetFPGACommFlags();
+
+    // Check the FPGA power status
+    monitorFPGAPowerStatus();
 }
 
 /*********************************************************************//**
@@ -924,6 +939,22 @@
 
 /*********************************************************************//**
  * @brief
+ * The monitorFPGAPowerStatus function monitors the status of the FPGA power source.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return none
+ *************************************************************************/
+static void monitorFPGAPowerStatus( void )
+{
+    // If the GIO bit returned a 0 it mean the power is out, otherwise the power is not out
+    BOOL isPowerOut = ( TRUE == (BOOL)gioGetBit( gioPORTA, FPGA_GPIO_POWER_STATUS_PIN ) ? FALSE : TRUE );
+
+    // TODO check to make sure alarm is not raised when the power is good
+    checkPersistentAlarm( ALARM_ID_DG_FPGA_POWER_OUT_TIMEOUT, isPowerOut, 0, FPGA_POWER_OUT_TIMEOUT_MS );
+}
+
+/*********************************************************************//**
+ * @brief
  * The setFPGAValveStates function sets the DG valve states with a 16-bit
  * set of states - one bit per valve, with a 1 meaning "energized" and a 0
  * meaning "de-energized".  The bit positions for these bit states are as follows:
@@ -1856,4 +1887,43 @@
     return ( 0 == noFluidLeakDetected ? FALSE : TRUE );
 }
 
+/*********************************************************************//**
+ * @brief
+ * The getFPGAGFluidDoorStatus function gets the FPGA fluid door status
+ * bit.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return fluid door status bit
+ *************************************************************************/
+U08 getFPGAGFluidDoorStatus( void )
+{
+    return ( fpgaSensorReadings.fpgaGPIO & FLUID_DOOR_SWITCH_MASK );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGADialysateCapStatus function gets the FPGA dialysate cap status
+ * bit.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return dialysate cap status bit
+ *************************************************************************/
+U08 getFPGADialysateCapStatus( void )
+{
+    return ( fpgaSensorReadings.fpgaGPIO & DIALYSATE_CAP_SWITCH_MASK );
+}
+
+/*********************************************************************//**
+ * @brief
+ * The getFPGAConcentrateCapStatus function gets the FPGA concentrate cap
+ * status bit.
+ * @details Inputs: fpgaSensorReadings
+ * @details Outputs: none
+ * @return concentrate cap status bit
+ *************************************************************************/
+U08 getFPGAConcentrateCapStatus( void )
+{
+    return ( fpgaSensorReadings.fpgaGPIO & CONCENTRATE_CAP_SWITCH_MASK );
+}
+
 /**@}*/