Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r19056bcb960b73405326d038abcea63b6862e344 -r66137c87d01cef2f8d20796a29efc928bdb59d50
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 19056bcb960b73405326d038abcea63b6862e344)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 66137c87d01cef2f8d20796a29efc928bdb59d50)
@@ -93,6 +93,8 @@
 /// FPGA size of V3 read bytes.
 #define FPGA_SIZE_OF_V3_READ_BYTES      ( FPGA_READ_V3_END_BYTE_NUM - FPGA_READ_V3_START_BYTE_NUM )
 
+#define PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE     1               ///< Tolerance for processor clock speed check against FPGA clock.
+
 // FPGA header struct.
 #pragma pack(push,1)
 typedef struct
@@ -340,6 +342,11 @@
 static FPGA_ACTUATORS_T     fpgaActuatorSetPoints;                  ///< FPGA actuator set points structure.
 static U08 fpgaReadByteSize;                                        ///< FPGA read byte size.
 
+//#ifndef DEBUG_ENABLED - TODO: uncomment it DN-15SEPT2022
+static U16 currentFPGATimerCount_ms;                                    ///< Current FPGA timer count in ms.
+static U32 currentTimerCount_ms;                                        ///< Current processor timer count in ms.
+//#endif
+
 // ********** private function prototypes **********
 
 static FPGA_STATE_T handleFPGAReadHeaderState( void );
@@ -895,23 +902,27 @@
  *************************************************************************/
 void execFPGAClockSpeedTest( void )
 {
-#ifndef DEBUG_ENABLED
+//#ifndef DEBUG_ENABLED - TODO: uncomment it DN-15SEPT2022
     U16 const newFPGATimerCount_ms = getFPGATimerCount();
     U32 const newTimerCount_ms = getMSTimerCount();
     U32 const diffFPGATimerCount = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
     U32 const diffTimerCount = u32DiffWithWrap( currentTimerCount_ms, newTimerCount_ms );
 
-    if ( getCurrentOperationMode() > MODE_INIT )
+    if ( getCurrentOperationMode() != DG_MODE_INIT )
     {
         if ( abs( diffFPGATimerCount - diffTimerCount ) > PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE )
         {
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
+            if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_CLOCK_SPEED_ERROR ) )   // DN-16SEPT2022
+            {
+                 SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_CLOCK_SPEED_CHECK_FAILURE, diffFPGATimerCount, diffTimerCount );
+            }
+
         }
     }
 
     currentFPGATimerCount_ms = newFPGATimerCount_ms;
     currentTimerCount_ms = newTimerCount_ms;
-#endif
+//#endif
 }
 /*********************************************************************//**
  * @brief