Index: firmware/App/Services/FPGA.c =================================================================== diff -u -r5f86e35ac3c021b68708457d17d4ef51b20aef9c -r94a190522ce398399c7b93c59f788d7666ec0060 --- firmware/App/Services/FPGA.c (.../FPGA.c) (revision 5f86e35ac3c021b68708457d17d4ef51b20aef9c) +++ firmware/App/Services/FPGA.c (.../FPGA.c) (revision 94a190522ce398399c7b93c59f788d7666ec0060) @@ -1,29 +1,31 @@ /************************************************************************** * -* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* Copyright (c) 2019-2021 Diality Inc. - All Rights Reserved. * * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. * -* @file FPGA.c +* @file FPGA.c * -* @author (last) Peman Montazemi -* @date (last) 09-Mar-2021 +* @author (last) Dara Navaei +* @date (last) 09-Nov-2021 * -* @author (original) Dara Navaei -* @date (original) 05-Nov-2019 +* @author (original) Dara Navaei +* @date (original) 05-Nov-2019 * ***************************************************************************/ #include // for memset(), memcpy() +#include "gio.h" #include "sci.h" #include "sys_dma.h" -#include "FPGA.h" #include "Comm.h" #include "Compatible.h" +#include "FPGA.h" +#include "PersistentAlarm.h" #include "SystemCommMessages.h" #include "Utilities.h" @@ -47,7 +49,7 @@ } FPGA_STATE_T; #define FPGA_PAGE_SIZE 256 ///< FPGA page size. -#define FPGA_EXPECTED_ID 0x60 ///< FPGA expected ID. +#define FPGA_EXPECTED_ID 0x61 ///< FPGA expected ID. #define FPGA_HEADER_START_ADDR 0x0000 ///< FPGA header start address. #define FPGA_BULK_READ_START_ADDR 0x0100 ///< FPGA bulk read start address. @@ -79,6 +81,12 @@ #define FPGA_FLUIDLEAK_STATE_MASK 0x0004 ///< Bit mask for fluid leak detector. +#define FLUID_DOOR_SWITCH_MASK 0x08 ///< Fluid door switch bit mask. +#define CONCENTRATE_CAP_SWITCH_MASK 0x10 ///< Concentrate cap switch bit mask +#define DIALYSATE_CAP_SWITCH_MASK 0x20 ///< Dialysate cap switch bit mask.. +#define FPGA_POWER_OUT_TIMEOUT_MS ( 2 * MS_PER_SECOND ) ///< FPGA power out timeout in milliseconds. +#define FPGA_GPIO_POWER_STATUS_PIN 7 ///< FPGA GPIO power status pin + // FPGA header struct. #pragma pack(push,1) typedef struct @@ -177,7 +185,17 @@ U16 fpgaFanOut2Pulse; ///< Reg 398. Fan outlet 2 pulse time in 2.5 resolution U16 fpgaFanIn3Pulse; ///< Reg 400. Fan inlet 3 pulse time in 2.5 resolution U16 fpgaFanOut3Pulse; ///< Reg 402. Fan outlet 3 pulse time in 2.5 resolution + U16 fpgaTimerCount_ms; ///< Reg 404. Internal FPGA timer count in ms. + U16 fpgaADCVccInt; ///< Reg 406. Internal FPGA Vcc Voltage. + U16 fpgaADCVccAux; ///< Reg 408. Internal FPGA Vcc auxiliary voltage. + U16 fpgaADCVPVN; ///< Reg 410. Internal FPGA VPVN voltage. + + U16 fpgaOpenRegister; ///< Reg 412. Open register. + U16 fpgaDrainPumpSpeedFeedback; ///< Reg 414. Drain pump speed feedback. + U16 fpgaDrainPumpCurrentFeedback; ///< Reg 416. Drain pump current feedback. + + U16 fpgaFMPROFlowTemporary; ///< Reg 418. FMP flow sensor temporary register. } DG_FPGA_SENSORS_T; typedef struct @@ -245,6 +263,7 @@ static void startDMAReceiptOfReadResp( void ); static void consumeUnexpectedData( void ); +static void monitorFPGAPowerStatus( void ); /*********************************************************************//** * @brief @@ -358,6 +377,9 @@ // there shouldn't be any data pending yet consumeUnexpectedData(); + + // Initialize the persistent alarm for FPGA power out + initPersistentAlarm( ALARM_ID_DG_FPGA_POWER_OUT_TIMEOUT, FPGA_POWER_OUT_TIMEOUT_MS, FPGA_POWER_OUT_TIMEOUT_MS ); } /*********************************************************************//** @@ -480,6 +502,9 @@ // reset comm flags after processing incoming responses resetFPGACommFlags(); + + // Check the FPGA power status + monitorFPGAPowerStatus(); } /*********************************************************************//** @@ -924,6 +949,22 @@ /*********************************************************************//** * @brief + * The monitorFPGAPowerStatus function monitors the status of the FPGA power source. + * @details Inputs: none + * @details Outputs: none + * @return none + *************************************************************************/ +static void monitorFPGAPowerStatus( void ) +{ + // If the GIO bit returned a 0 it mean the power is out, otherwise the power is not out + BOOL isPowerOut = ( TRUE == (BOOL)gioGetBit( gioPORTA, FPGA_GPIO_POWER_STATUS_PIN ) ? FALSE : TRUE ); + + // TODO check to make sure alarm is not raised when the power is good + checkPersistentAlarm( ALARM_ID_DG_FPGA_POWER_OUT_TIMEOUT, isPowerOut, 0, FPGA_POWER_OUT_TIMEOUT_MS ); +} + +/*********************************************************************//** + * @brief * The setFPGAValveStates function sets the DG valve states with a 16-bit * set of states - one bit per valve, with a 1 meaning "energized" and a 0 * meaning "de-energized". The bit positions for these bit states are as follows: @@ -1562,6 +1603,19 @@ /*********************************************************************//** * @brief + * The getFPGAConcentratePumpsFault function gets concentrate pumps fault + * reported by FGPA. + * @details Inputs: fpgaSensorReadings.fpgaCP1CP2Fault + * @details Outputs: none + * @return Latest concentrate pumps fault value + *************************************************************************/ +U08 getFPGAConcentratePumpsFault( void ) +{ + return fpgaSensorReadings.fpgaCP1CP2Fault; +} + +/*********************************************************************//** + * @brief * The getFPGAEmstatOutByte function gets Emstat conductivity sensor output byte. * @details Inputs: fpgaSensorReadings.fpgaEmstatOutByte * @details Outputs: none @@ -1818,6 +1872,18 @@ /*********************************************************************//** * @brief + * The getFPGATimerCount function gets the latest FPGA timer millisecond count. + * @details Inputs: fpgaSensorReadings + * @details Outputs: none + * @return last FPGA timer count + *************************************************************************/ +U16 getFPGATimerCount( void ) +{ + return fpgaSensorReadings.fpgaTimerCount_ms; +} + +/*********************************************************************//** + * @brief * The noFluidLeakDetected function returns TRUE if no fluid leak has been * detected (dry) and FALSE if a fluid leak has been detected (wet). * @details Inputs: fpgaSensorReadings @@ -1831,4 +1897,43 @@ return ( 0 == noFluidLeakDetected ? FALSE : TRUE ); } +/*********************************************************************//** + * @brief + * The getFPGAGFluidDoorStatus function gets the FPGA fluid door status + * bit. + * @details Inputs: fpgaSensorReadings + * @details Outputs: none + * @return fluid door status bit + *************************************************************************/ +U08 getFPGAGFluidDoorStatus( void ) +{ + return ( fpgaSensorReadings.fpgaGPIO & FLUID_DOOR_SWITCH_MASK ); +} + +/*********************************************************************//** + * @brief + * The getFPGADialysateCapStatus function gets the FPGA dialysate cap status + * bit. + * @details Inputs: fpgaSensorReadings + * @details Outputs: none + * @return dialysate cap status bit + *************************************************************************/ +U08 getFPGADialysateCapStatus( void ) +{ + return ( fpgaSensorReadings.fpgaGPIO & DIALYSATE_CAP_SWITCH_MASK ); +} + +/*********************************************************************//** + * @brief + * The getFPGAConcentrateCapStatus function gets the FPGA concentrate cap + * status bit. + * @details Inputs: fpgaSensorReadings + * @details Outputs: none + * @return concentrate cap status bit + *************************************************************************/ +U08 getFPGAConcentrateCapStatus( void ) +{ + return ( fpgaSensorReadings.fpgaGPIO & CONCENTRATE_CAP_SWITCH_MASK ); +} + /**@}*/