Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r9e5ee62245eb2a73b167eabd6c274a71a76a7b0e -rc20562aef9d0b7487f16aeaa0568f1d92ca844ed
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 9e5ee62245eb2a73b167eabd6c274a71a76a7b0e)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision c20562aef9d0b7487f16aeaa0568f1d92ca844ed)
@@ -107,6 +107,9 @@
 
 #define PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE     1               ///< Tolerance for processor clock speed check against FPGA clock.
 
+#define MAX_FPGA_COMM_FAILURES_WINDOW_MS (1 * SEC_PER_MIN * MS_PER_SECOND) ///< ///< FPGA comm failures window
+#define MAX_FPGA_COMM_FAILURES           3                       ///< FPGA maximum comm failures per MAX_FPGA_COMM_FAILURES_WINDOW_MS
+
 // FPGA header struct.
 #pragma pack(push,1)
 typedef struct
@@ -328,7 +331,6 @@
 // ********** private data **********
 
 static FPGA_STATE_T fpgaState = FPGA_STATE_START;                   ///< FPGA current state.
-static U32 fpgaCommRetryCount = 0;                                  ///< FPGA communication retry count.
 static U32 fpgaReceiptCounter = 0;                                  ///< FPGA receipt completed counter.
 static U32 fpgaTransmitCounter = 0;                                 ///< FPGA transmit completed counter.
 static BOOL fpgaWriteCommandInProgress = FALSE;                     ///< Flag indicates whether a FPGA write command is in progress.
@@ -379,6 +381,8 @@
 static void consumeUnexpectedData( void );
 static void monitorFPGAPowerStatus( void );
 
+static BOOL checkFPGACommFailure( void );
+
 /*********************************************************************//**
  * @brief
  * The initFPGA function initializes the FPGA module.
@@ -497,6 +501,10 @@
 
     // Initialize the persistent alarm for FPGA power out
     initPersistentAlarm( ALARM_ID_DG_FPGA_POWER_OUT_TIMEOUT, FPGA_POWER_OUT_TIMEOUT_MS, FPGA_POWER_OUT_TIMEOUT_MS );
+
+    // initialize FPGA clock speed error time windowed count
+    initTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES, MAX_FPGA_COMM_FAILURES_WINDOW_MS);
+
 }
 
 /*********************************************************************//**
@@ -607,15 +615,12 @@
     }
 
     // if retries for commands exceeds limit or FPGA reports comm error, fault
-    if ( ( fpgaCommRetryCount > MAX_COMM_ERROR_RETRIES )
 #ifdef _RELEASE_
-         || ( fpgaSensorReadings.fpgaIOErrorCntProcessor > MAX_COMM_ERROR_RETRIES ) )
-#else
-         )
-#endif
+    if ( fpgaSensorReadings.fpgaIOErrorCntProcessor > MAX_COMM_ERROR_RETRIES )
     {
-        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, fpgaCommRetryCount, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
     }
+#endif
 
     // reset comm flags after processing incoming responses
     resetFPGACommFlags();
@@ -719,24 +724,23 @@
             // does the FPGA response CRC check out?
             if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
             {
-                fpgaCommRetryCount = 0;
                 // capture the read values
                 memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else
             {
-                fpgaCommRetryCount++;
+                checkFPGACommFailure();
             }
         }
         else  // header read was NAK'd
         {
-            fpgaCommRetryCount++;
+                checkFPGACommFailure();
         }
     }
     else // no response to read command
     {
-        fpgaCommRetryCount++;
+        checkFPGACommFailure();
     }
 
     // There should not be any data received at this time
@@ -811,12 +815,15 @@
  *************************************************************************/
 static FPGA_STATE_T handleFPGAReceiveAllSensorsState( void )
 {
+    static int CRCCounter = 0;
+    static int NAKCounter = 0;
+
     FPGA_STATE_T result = FPGA_STATE_WRITE_ALL_ACTUATORS;
 
     // check bulk write command success
     if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[ 0 ] != FPGA_WRITE_CMD_ACK ) )
     {
-        fpgaCommRetryCount++;
+        checkFPGACommFailure();
     }
 
     // if bulk read command is ACK'd, collect the readings
@@ -828,28 +835,36 @@
             U32 rspSize = FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize;
             U32 crcPos = rspSize;
             U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
+            U08 address1 = fpgaReadResponseBuffer[1];   //wjb
+            U08 address2 = fpgaReadResponseBuffer[2];   //wjb
+            U32 loadCell = getFPGALoadCellA1();
 
+            if (fpgaReadResponseBuffer[1] != 0)
+                CRCCounter++;
+
+            if (fpgaReadResponseBuffer[1] != 0xaa)
+                NAKCounter++;
+
             // does the FPGA response CRC check out?
             if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
             {
-                fpgaCommRetryCount = 0;
                 // capture the read values
                 memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], fpgaReadByteSize );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else // bad CRC
             {
-                fpgaCommRetryCount++;
-            }
+                checkFPGACommFailure();
+           }
         }
         else // read command was NAK'd
         {
-            fpgaCommRetryCount++;
+            checkFPGACommFailure();
         }
     }
     else // no response to read command
     {
-        fpgaCommRetryCount++;
+        checkFPGACommFailure();
     }
 
     // There should not be any data received at this time
@@ -902,7 +917,11 @@
  *************************************************************************/
 void execFPGAClockSpeedTest( void )
 {
+
 #ifndef DEBUG_ENABLED
+    static U16 currentFPGATimerCount_ms = 0;
+    static U32 currentTimerCount_ms = 0;
+
     U16 const newFPGATimerCount_ms = getFPGATimerCount();
     U32 const newTimerCount_ms = getMSTimerCount();
     U32 const diffFPGATimerCount = (U32)u16DiffWithWrap( currentFPGATimerCount_ms, newFPGATimerCount_ms );
@@ -2686,4 +2705,26 @@
     return fpgaSensorReadings.fpgaPowerSupply2;
 }
 
+/*********************************************************************//**
+ * @brief
+ * The checkFPGACommFailure function increments the FPGA comm failure
+ * windowed timer and returns whether or not the number of failures in
+ * the window have been reached.
+ * @details Inputs: none
+ * @details Outputs: none
+ * @return TRUE if windowed count exceeded, else false.
+ *************************************************************************/
+BOOL checkFPGACommFailure( void )
+{
+    BOOL status = false;
+
+    if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES ) )
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
+        status = TRUE;
+    }
+
+    return status;
+
+}
 /**@}*/