Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -rb29639b235a979e1fa5b25cf246c6a42fb4397f0 -rdcd360fb4dc37db2dcbeb7fb14fb327fe68235f4
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision b29639b235a979e1fa5b25cf246c6a42fb4397f0)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision dcd360fb4dc37db2dcbeb7fb14fb327fe68235f4)
@@ -6,13 +6,13 @@
 * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
 * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
 *
-* @file FPGA.c
+* @file    FPGA.c
 *
-* @author (last) H. Nguyen
-* @date (last) 21-Oct-2021
+* @author  (last)      Dara Navaei
+* @date    (last)      09-Nov-2021
 *
-* @author (original) Dara Navaei
-* @date (original) 05-Nov-2019
+* @author  (original)  Dara Navaei
+* @date    (original)  05-Nov-2019
 *
 ***************************************************************************/
 
@@ -82,8 +82,8 @@
 #define FPGA_FLUIDLEAK_STATE_MASK       0x0004                  ///< Bit mask for fluid leak detector.
 
 #define FLUID_DOOR_SWITCH_MASK          0x08                    ///< Fluid door switch bit mask.
-#define DIALYSATE_CAP_SWITCH_MASK       0x10                    ///< Dialysate cap switch bit mask.
-#define CONCENTRATE_CAP_SWITCH_MASK     0x1A                    ///< Concentrate cap switch bit mask.
+#define CONCENTRATE_CAP_SWITCH_MASK     0x10                    ///< Concentrate cap switch bit mask
+#define DIALYSATE_CAP_SWITCH_MASK       0x20                    ///< Dialysate cap switch bit mask..
 #define FPGA_POWER_OUT_TIMEOUT_MS       ( 2 * MS_PER_SECOND )   ///< FPGA power out timeout in milliseconds.
 #define FPGA_GPIO_POWER_STATUS_PIN      7                       ///< FPGA GPIO power status pin
 
@@ -186,14 +186,13 @@
     U16 fpgaFanIn3Pulse;                    ///< Reg 400. Fan inlet 3 pulse time in 2.5 resolution
     U16 fpgaFanOut3Pulse;                   ///< Reg 402. Fan outlet 3 pulse time in 2.5 resolution
     U16 fpgaTimerCount_ms;                  ///< Reg 404. Internal FPGA timer count in ms.
-    U16 fpgaVccIntVoltage;                  ///< Req 406. Internal FPGA Vcc Int voltage
-    U16 fpgaVccAuxVoltage;                  ///< Req 408. Internal FPGA Vcc Aux voltage
-    U16 fpgaVpvnVoltage;                    ///< Req 410. Internal FPGA VPVN voltage
-    U16 fpgaRoPumpFeedBack;                 ///< Req 412. Internal FPGA RO pump feedback register
-    U16 fpgaDrainPumpSpeedMeasure;          ///< Req 414. Drain pump speed measurement
-    U16 fpgaDrainPumpCurrent;               ///< Req 416. Drain pump electrical current measurement
+    U16 fpgaADCVccInt;                      ///< Reg 406. Internal FPGA Vcc Voltage.
+    U16 fpgaADCVccAux;                      ///< Reg 408. Internal FPGA Vcc auxiliary voltage.
+    U16 fpgaADCVPVN;                        ///< Reg 410. Internal FPGA VPVN voltage.
+    U16 fpgaOpenRegister;                   ///< Reg 412. Open register.
+    U16 fpgaDrainPumpSpeedFeedback;         ///< Reg 414. Drain pump speed feedback.
+    U16 fpgaDrainPumpCurrentFeedback;       ///< Reg 416. Drain pump current feedback.
     U16 fpgaDialysateFlowRate;              ///< Req 418. Dialysate flow rate measurement
-
 } DG_FPGA_SENSORS_T;
 
 typedef struct