Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -rc38c6d64b5f4df1fe08e2daabb37d3a7a483a4be -rf1cb4be5fb8201cec188589e683c8bf20d895ec0
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision c38c6d64b5f4df1fe08e2daabb37d3a7a483a4be)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision f1cb4be5fb8201cec188589e683c8bf20d895ec0)
@@ -376,10 +376,6 @@
     memset( &fpgaWriteResponseBuffer, 0, FPGA_WRITE_RSP_BUFFER_LEN );
     memset( &fpgaReadResponseBuffer, 0, FPGA_READ_RSP_BUFFER_LEN );
 
-    // Assume the read byte size is set for V3 since V3 contains less number of bytes.
-    // Once the V3 or DVT build switch is set resize the number of bytes to read.
-    fpgaReadByteSize = FPGA_SIZE_OF_V3_READ_BYTES;
-
     // enable interrupt notifications for FPGA serial port
     sciEnableNotification( scilinREG, SCI_OE_INT | SCI_FE_INT );
 
@@ -549,7 +545,7 @@
     fpgaReadByteSize = sizeof( DG_FPGA_SENSORS_T );
 
 #ifndef _RELEASE_
-    if( ( SW_CONFIG_ENABLE_VALUE == getSoftwareConfigStatus( SW_CONFIG_ENABLE_V3_SYSTEM ) ) && ( getCurrentOperationMode() != DG_MODE_INIT ) )
+    if( ( SW_CONFIG_ENABLE_VALUE == getSoftwareConfigStatus( SW_CONFIG_ENABLE_V3_SYSTEM ) ) || ( DG_MODE_INIT == getCurrentOperationMode() ) )
     {
         fpgaReadByteSize = FPGA_SIZE_OF_V3_READ_BYTES;
     }
@@ -774,7 +770,7 @@
 
     // prep DMA for sending the bulk read cmd and receiving its response
     setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN );
-    setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize /*sizeof( DG_FPGA_SENSORS_T )*/ + FPGA_CRC_LEN );
+    setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize + FPGA_CRC_LEN );
 
     // set fpga comm flags for bulk write cmd and follow-up bulk read command
     fpgaWriteCommandInProgress = TRUE;
@@ -810,7 +806,7 @@
         // did FPGA Ack the read command?
         if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK )
         {
-            U32 rspSize = FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize; //sizeof( DG_FPGA_SENSORS_T );
+            U32 rspSize = FPGA_READ_RSP_HDR_LEN + fpgaReadByteSize;
             U32 crcPos = rspSize;
             U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
 
@@ -819,7 +815,7 @@
             {
                 fpgaCommRetryCount = 0;
                 // capture the read values
-                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], fpgaReadByteSize /*sizeof( DG_FPGA_SENSORS_T )*/ );
+                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], fpgaReadByteSize );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else // bad CRC
@@ -854,32 +850,25 @@
 {
     SELF_TEST_STATUS_T result;
 
-    // check FPGA reported correct ID
-    if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
+    // TODO the FPGA self test has been implemented in DEN-13460.
+    /*if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
     {
         // Check FPGA compatibility w/ firmware
-        if ( fpgaHeader.fpgaRevMajor > MIN_DG_FPGA_MAJOR )
+        if ( DG_FPGA_COMPATIBILITY_REV == fpgaSensorReadings.fpgaCompatibilityRev )
         {
             result = SELF_TEST_STATUS_PASSED;
         }
         else
         {
-            if ( ( MIN_DG_FPGA_MAJOR == fpgaHeader.fpgaRevMajor ) && ( fpgaHeader.fpgaRevMinor >= MIN_DG_FPGA_MINOR ) )
-            {
-                result = SELF_TEST_STATUS_PASSED;
-            }
-            else
-            {
-                result = SELF_TEST_STATUS_FAILED;
-                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaRevMajor, (U32)fpgaHeader.fpgaRevMinor )
-            }
+            result = SELF_TEST_STATUS_FAILED;
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_POST_TEST_FAILED, (U32)DG_FPGA_COMPATIBILITY_REV, (U32)fpgaSensorReadings.fpgaCompatibilityRev )
         }
     }
     else
     {
         result = SELF_TEST_STATUS_FAILED;
         SET_ALARM_WITH_1_U32_DATA( ALARM_ID_DG_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaId )
-    }
+    }*/
 
     return result;
 }
@@ -1198,8 +1187,6 @@
     fpgaActuatorSetPoints.fpgaCP2StepSpeed = stepSpeed;
 }
 
-/****************************DVT Functions*******************************************/
-
 /*********************************************************************//**
  * @brief
  * The setFPGAAcidPumpControl function sets the DVT concentrate pump 1