Index: firmware/source/etpwm.c =================================================================== diff -u -r6d2d8f0267c57135554e5a1acaca9aef37f27949 -r8638b207699a3a48e3657e838e24ae838369c867 --- firmware/source/etpwm.c (.../etpwm.c) (revision 6d2d8f0267c57135554e5a1acaca9aef37f27949) +++ firmware/source/etpwm.c (.../etpwm.c) (revision 8638b207699a3a48e3657e838e24ae838369c867) @@ -82,7 +82,7 @@ etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG1->TBPRD = 25833U; + etpwmREG1->TBPRD = 6888U; /** - Setup the duty cycle for PWMA */ etpwmREG1->CMPA = 0U; @@ -107,7 +107,7 @@ | (uint16)((uint16)0u << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -272,7 +272,7 @@ etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U); /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG3->TBPRD = 25833U; + etpwmREG3->TBPRD = 6888U; /** - Setup the duty cycle for PWMA */ etpwmREG3->CMPA = 0U; @@ -297,7 +297,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U)); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -359,101 +359,6 @@ etpwmREG3->ETPS |= ((uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM4 */ - - /** - Sets high speed time-base clock prescale bits */ - etpwmREG4->TBCTL = (uint16)0U << 7U; - - /** - Sets time-base clock prescale bits */ - etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U); - - /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG4->TBPRD = 25833U; - - /** - Setup the duty cycle for PWMA */ - etpwmREG4->CMPA = 0U; - - /** - Setup the duty cycle for PWMB */ - etpwmREG4->CMPB = 0U; - - /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ - etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 4U)); - - /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ - etpwmREG4->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 8U)); - - /** - Mode setting for Dead Band Module - * -Select the input mode for Dead Band Module - * -Select the output mode for Dead Band Module - * -Select Polarity of the output PWMs - */ - etpwmREG4->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ - | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ - | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ - - /** - Set the rising edge delay */ - etpwmREG4->DBRED = 1U; - - /** - Set the falling edge delay */ - etpwmREG4->DBFED = 1U; - - /** - Enable the chopper module for ETPWMx - * -Sets the One shot pulse width in a chopper modulated wave - * -Sets the dutycycle for the subsequent pulse train - * -Sets the period for the subsequent pulse train - */ - etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ - | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ - | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ - - /** - Set trip source enable */ - etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ - | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ - - /** - Set interrupt enable */ - etpwmREG4->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable one-shot interrupt generation */ - | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ - - /** - Sets up the event for interrupt */ - etpwmREG4->ETSEL = (uint16)NO_EVENT; - - if ((etpwmREG4->ETSEL & 0x0007U) != 0U) - { - etpwmREG4->ETSEL |= 0x0008U; - } - /** - Setup the frequency of the interrupt generation */ - etpwmREG4->ETPS = 1U; - - /** - Sets up the ADC SOC interrupt */ - etpwmREG4->ETSEL |= (uint16)(0x0000U) - | (uint16)(0x0000U) - | (uint16)((uint16)DCAEVT1 << 8U) - | (uint16)((uint16)DCBEVT1 << 12U); - - /** - Sets up the ADC SOC period */ - etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U) - | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM6 */ /** - Sets high speed time-base clock prescale bits */ @@ -489,7 +394,7 @@ | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ + | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay */ | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ /** - Set the rising edge delay */ @@ -552,104 +457,8 @@ etpwmREG6->ETPS |= ((uint16)((uint16)1U << 8U) | (uint16)((uint16)1U << 12U)); - /** @b initialize @b ETPWM7 */ - /** - Sets high speed time-base clock prescale bits */ - etpwmREG7->TBCTL = (uint16)0U << 7U; - /** - Sets time-base clock prescale bits */ - etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U); - - /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ - etpwmREG7->TBPRD = 25833U; - - /** - Setup the duty cycle for PWMA */ - etpwmREG7->CMPA = 0U; - - /** - Setup the duty cycle for PWMB */ - etpwmREG7->CMPB = 0U; - - - /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */ - etpwmREG7->AQCTLA = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 4U)); - - /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */ - etpwmREG7->AQCTLB = ((uint16)((uint16)ActionQual_Set << 0U) - | (uint16)((uint16)ActionQual_Clear << 8U)); - - /** - Mode setting for Dead Band Module - * -Select the input mode for Dead Band Module - * -Select the output mode for Dead Band Module - * -Select Polarity of the output PWMs - */ - etpwmREG7->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB) */ - | (uint16)((uint16)0U << 3U) /* Enable/Disable EPWMxB invert */ - | (uint16)((uint16)0U << 2U) /* Enable/Disable EPWMxA invert */ - | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay */ - | (uint16)((uint16)0U << 0U); /* Enable/Disable Falling Edge Delay */ - - /** - Set the rising edge delay */ - etpwmREG7->DBRED = 1U; - - /** - Set the falling edge delay */ - etpwmREG7->DBFED = 1U; - - /** - Enable the chopper module for ETPWMx - * -Sets the One shot pulse width in a chopper modulated wave - * -Sets the dutycycle for the subsequent pulse train - * -Sets the period for the subsequent pulse train - */ - etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */ - | (uint16)((uint16)0U << 1U) /* One-shot Pulse Width */ - | (uint16)((uint16)3U << 8U) /* Chopping Clock Duty Cycle */ - | (uint16)((uint16)0U << 5U); /* Chopping Clock Frequency */ - - - /** - Set trip source enable */ - etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ - | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ - | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ - | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ - - /** - Set interrupt enable */ - etpwmREG7->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ - | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ - | 0x0000U /** - Enable/Disable one-shot interrupt generation */ - | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ - - /** - Sets up the event for interrupt */ - etpwmREG7->ETSEL = (uint16)NO_EVENT; - - if ((etpwmREG7->ETSEL & 0x0007U) != 0U) - { - etpwmREG7->ETSEL |= 0x0008U; - } - /** - Setup the frequency of the interrupt generation */ - etpwmREG7->ETPS = 1U; - - /** - Sets up the ADC SOC interrupt */ - etpwmREG7->ETSEL |= (uint16)(0x0000U) - | (uint16)(0x0000U) - | (uint16)((uint16)DCAEVT1 << 8U) - | (uint16)((uint16)DCBEVT1 << 12U); - - /** - Sets up the ADC SOC period */ - etpwmREG7->ETPS |= ((uint16)((uint16)1U << 8U) - | (uint16)((uint16)1U << 12U)); - - /* USER CODE BEGIN (2) */ /* USER CODE END */ }