Index: firmware/source/mibspi.c
===================================================================
diff -u -ra90f03eb56aaa492908cd2e7417da79f405d67d4 -re7f256098e5c23cc621af73b17160a247d40559c
--- firmware/source/mibspi.c	(.../mibspi.c)	(revision a90f03eb56aaa492908cd2e7417da79f405d67d4)
+++ firmware/source/mibspi.c	(.../mibspi.c)	(revision e7f256098e5c23cc621af73b17160a247d40559c)
@@ -475,9 +475,9 @@
     /** - MIBSPI1 Port direction */
     mibspiREG1->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
                     | (uint32)((uint32)1U << 1U)  /* SCS[1] */
-                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)1U << 3U)  /* SCS[3] */
-                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
                     | (uint32)((uint32)1U << 5U)  /* SCS[5] */
                     | (uint32)((uint32)0U << 8U)  /* ENA */
                     | (uint32)((uint32)1U << 9U)  /* CLK */
@@ -1436,7 +1436,7 @@
                     | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)1U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)1U << 3U)  /* SCS[3] */
-                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
                     | (uint32)((uint32)1U << 9U)  /* CLK */
                     | (uint32)((uint32)1U << 10U)  /* SIMO[0] */
                     | (uint32)((uint32)1U << 11U)  /* SOMI[0] */
@@ -1496,20 +1496,20 @@
                     | (uint32)((uint32)0U << 27U); /* SOMI[3] */
 
     /* MIBSPI5 set all pins to functional */
-    mibspiREG5->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+    mibspiREG5->PC0 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
                     | (uint32)((uint32)0U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)0U << 3U)  /* SCS[3] */
                     | (uint32)((uint32)0U << 8U)  /* ENA */
                     | (uint32)((uint32)0U << 9U)  /* CLK */
                     | (uint32)((uint32)0U << 10U)  /* SIMO[0] */
                     | (uint32)((uint32)0U << 11U)  /* SOMI[0] */
-                    | (uint32)((uint32)1U << 17U)  /* SIMO[1] */
-                    | (uint32)((uint32)1U << 18U)  /* SIMO[2] */
-                    | (uint32)((uint32)1U << 19U)  /* SIMO[3] */
-                    | (uint32)((uint32)1U << 25U)  /* SOMI[1] */
-                    | (uint32)((uint32)1U << 26U)  /* SOMI[2] */
-                    | (uint32)((uint32)1U << 27U); /* SOMI[3] */
+                    | (uint32)((uint32)0U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)0U << 18U)  /* SIMO[2] */
+                    | (uint32)((uint32)0U << 19U)  /* SIMO[3] */
+                    | (uint32)((uint32)0U << 25U)  /* SOMI[1] */
+                    | (uint32)((uint32)0U << 26U)  /* SOMI[2] */
+                    | (uint32)((uint32)0U << 27U); /* SOMI[3] */
 
   /** - Finally start MIBSPI5 */
     mibspiREG5->GCR1 = (mibspiREG5->GCR1 & 0xFEFFFFFFU) | 0x01000000U;