Index: firmware/source/mibspi.c =================================================================== diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -ra90f03eb56aaa492908cd2e7417da79f405d67d4 --- firmware/source/mibspi.c (.../mibspi.c) (revision eff7b1575f008f81b29ef906f6346fac6012d3ab) +++ firmware/source/mibspi.c (.../mibspi.c) (revision a90f03eb56aaa492908cd2e7417da79f405d67d4) @@ -64,8 +64,963 @@ /* USER CODE END */ + /** @b initialize @b MIBSPI1 */ + /** bring MIBSPI out of reset */ + mibspiREG1->GCR0 = 0U; + mibspiREG1->GCR0 = 1U; + /** enable MIBSPI1 multibuffered mode and enable buffer RAM */ + mibspiREG1->MIBSPIE = (mibspiREG1->MIBSPIE & 0xFFFFFFFEU) | 1U; + + /** MIBSPI1 master mode and clock configuration */ + mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ + | 1U); /* MASTER */ + + /** MIBSPI1 enable pin configuration */ + mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */ + + /** - Delays */ + mibspiREG1->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ + | (uint32)((uint32)0U << 16U) /* T2CDELAY */ + | (uint32)((uint32)0U << 8U) /* T2EDELAY */ + | (uint32)((uint32)0U << 0U); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG1->FMT0 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 1 */ + mibspiREG1->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 2 */ + mibspiREG1->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 3 */ + mibspiREG1->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Default Chip Select */ + mibspiREG1->DEF = (uint32)(0xFFU); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while ((mibspiREG1->FLG & 0x01000000U) != 0U) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U); + + /** - initialize transfer groups */ + mibspiREG1->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)0U << 8U); /* start buffer */ + + mibspiREG1->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)8U << 8U); /* start buffer */ + + mibspiREG1->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U) << 8U); /* start buffer */ + + mibspiREG1->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U) << 8U); /* start buffer */ + + mibspiREG1->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG1->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG1->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG1->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + + mibspiREG1->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U; + + mibspiREG1->LTGPEND = (mibspiREG1->LTGPEND & 0xFFFF00FFU) | (uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + + /** - initialize buffer ram */ + { + i = 0U; + +#if (8U > 0U) + { + +#if (8U > 1U) + + while (i < (8U-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU); /* chip select */ + + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U)-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U)-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U)-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U)-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG1->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG1->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFFFF0000U) + | (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** @b initialize @b MIBSPI1 @b Port */ + + /** - MIBSPI1 Port output values */ + mibspiREG1->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 25U); /* SOMI[1] */ + + /** - MIBSPI1 Port direction */ + mibspiREG1->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO[0] */ + | (uint32)((uint32)1U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 25U); /* SOMI[1] */ + + /** - MIBSPI1 Port open drain enable */ + mibspiREG1->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 25U); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown selection */ + mibspiREG1->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO[0] */ + | (uint32)((uint32)1U << 11U) /* SOMI[0] */ + | (uint32)((uint32)1U << 17U) /* SIMO[1] */ + | (uint32)((uint32)1U << 25U); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown enable*/ + mibspiREG1->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)0U << 17U) /* SIMO[1] */ + | (uint32)((uint32)0U << 25U); /* SOMI[1] */ + + /* MIBSPI1 set all pins to functional */ + mibspiREG1->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO[0] */ + | (uint32)((uint32)0U << 11U) /* SOMI[0] */ + | (uint32)((uint32)1U << 17U) /* SIMO[1] */ + | (uint32)((uint32)1U << 25U); /* SOMI[1] */ + + /** - Finally start MIBSPI1 */ + mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFEFFFFFFU) | 0x01000000U; + + + + /** @b initialize @b MIBSPI3 */ + + /** bring MIBSPI out of reset */ + mibspiREG3->GCR0 = 0U; + mibspiREG3->GCR0 = 1U; + + /** enable MIBSPI3 multibuffered mode and enable buffer RAM */ + mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U; + + /** MIBSPI3 master mode and clock configuration */ + mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U) /* CLOKMOD */ + | 1U); /* MASTER */ + + /** MIBSPI3 enable pin configuration */ + mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U); /* ENABLE HIGHZ */ + + /** - Delays */ + mibspiREG3->DELAY = (uint32)((uint32)0U << 24U) /* C2TDELAY */ + | (uint32)((uint32)0U << 16U) /* T2CDELAY */ + | (uint32)((uint32)0U << 8U) /* T2EDELAY */ + | (uint32)((uint32)0U << 0U); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG3->FMT0 = (uint32)((uint32)20U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)1U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)8U << 0U); /* data word length */ + + /** - Data Format 1 */ + mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 2 */ + mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Data Format 3 */ + mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U) /* wdelay */ + | (uint32)((uint32)0U << 23U) /* parity Polarity */ + | (uint32)((uint32)0U << 22U) /* parity enable */ + | (uint32)((uint32)0U << 21U) /* wait on enable */ + | (uint32)((uint32)0U << 20U) /* shift direction */ + | (uint32)((uint32)0U << 17U) /* clock polarity */ + | (uint32)((uint32)0U << 16U) /* clock phase */ + | (uint32)((uint32)102U << 8U) /* baudrate prescale */ + | (uint32)((uint32)16U << 0U); /* data word length */ + + /** - Default Chip Select */ + mibspiREG3->DEF = (uint32)(0xFFU); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while ((mibspiREG3->FLG & 0x01000000U) != 0U) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U); + + /** - initialize transfer groups */ + mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)0U << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)11U << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U) /* oneshot */ + | (uint32)((uint32)0U << 29U) /* pcurrent reset */ + | (uint32)((uint32)TRG_ALWAYS << 20U) /* trigger event */ + | (uint32)((uint32)TRG_DISABLED << 16U) /* trigger source */ + | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U); /* start buffer */ + + + mibspiREG3->TGCTRL[8U] = (uint32)(11U+0U+0U+0U+0U+0U+0U+0U) << 8U; + + mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U); + + /** - initialize buffer ram */ + { + i = 0U; + +#if (11U > 0U) + { + +#if (11U > 1U) + + while (i < (11U-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)1U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU); /* chip select */ + + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + +#if (0U > 0U) + { + +#if (0U > 1U) + + while (i < ((11U+0U+0U+0U+0U+0U+0U+0U)-1U)) + { + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 11U) /* lock transmission */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + + i++; + } +#endif + mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */ + | (uint16)((uint16)0U << 12U) /* chip select hold */ + | (uint16)((uint16)0U << 10U) /* enable WDELAY */ + | (uint16)((uint16)0U << 8U) /* data format */ + /*SAFETYMCUSW 334 S MR:10.5 "LDRA Tool issue" */ + | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG3->LVL = (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)0U << 6U) /* OVRNINT */ + | (uint32)((uint32)0U << 4U) /* BITERR */ + | (uint32)((uint32)0U << 3U) /* DESYNC */ + | (uint32)((uint32)0U << 2U) /* PARERR */ + | (uint32)((uint32)0U << 1U) /* TIMEOUT */ + | (uint32)((uint32)0U << 0U); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG3->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U) + | (uint32)((uint32)0U << 9U) /* TXINT */ + | (uint32)((uint32)0U << 8U) /* RXINT */ + | (uint32)((uint32)1U << 6U) /* OVRNINT */ + | (uint32)((uint32)1U << 4U) /* BITERR */ + | (uint32)((uint32)1U << 3U) /* DESYNC */ + | (uint32)((uint32)1U << 2U) /* PARERR */ + | (uint32)((uint32)1U << 1U) /* TIMEOUT */ + | (uint32)((uint32)1U << 0U); /* DLENERR */ + + /** @b initialize @b MIBSPI3 @b Port */ + + /** - MIBSPI3 Port output values */ + mibspiREG3->PC3 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + /** - MIBSPI3 Port direction */ + mibspiREG3->PC1 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + /** - MIBSPI3 Port open drain enable */ + mibspiREG3->PC6 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + + /** - MIBSPI3 Port pullup / pulldown selection */ + mibspiREG3->PC8 = (uint32)((uint32)1U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)1U << 2U) /* SCS[2] */ + | (uint32)((uint32)1U << 3U) /* SCS[3] */ + | (uint32)((uint32)1U << 4U) /* SCS[4] */ + | (uint32)((uint32)1U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)1U << 11U); /* SOMI */ + + + /** - MIBSPI3 Port pullup / pulldown enable*/ + mibspiREG3->PC7 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)0U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)0U << 9U) /* CLK */ + | (uint32)((uint32)0U << 10U) /* SIMO */ + | (uint32)((uint32)0U << 11U); /* SOMI */ + + + /* MIBSPI3 set all pins to functional */ + mibspiREG3->PC0 = (uint32)((uint32)0U << 0U) /* SCS[0] */ + | (uint32)((uint32)1U << 1U) /* SCS[1] */ + | (uint32)((uint32)0U << 2U) /* SCS[2] */ + | (uint32)((uint32)0U << 3U) /* SCS[3] */ + | (uint32)((uint32)0U << 4U) /* SCS[4] */ + | (uint32)((uint32)0U << 5U) /* SCS[5] */ + | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)1U << 9U) /* CLK */ + | (uint32)((uint32)1U << 10U) /* SIMO */ + | (uint32)((uint32)1U << 11U); /* SOMI */ + + /** - Finally start MIBSPI3 */ + mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U; + + + /** @b initialize @b MIBSPI5 */ /** bring MIBSPI out of reset */ @@ -481,7 +1436,7 @@ | (uint32)((uint32)1U << 1U) /* SCS[1] */ | (uint32)((uint32)1U << 2U) /* SCS[2] */ | (uint32)((uint32)1U << 3U) /* SCS[3] */ - | (uint32)((uint32)0U << 8U) /* ENA */ + | (uint32)((uint32)1U << 8U) /* ENA */ | (uint32)((uint32)1U << 9U) /* CLK */ | (uint32)((uint32)1U << 10U) /* SIMO[0] */ | (uint32)((uint32)1U << 11U) /* SOMI[0] */ @@ -545,7 +1500,7 @@ | (uint32)((uint32)0U << 1U) /* SCS[1] */ | (uint32)((uint32)0U << 2U) /* SCS[2] */ | (uint32)((uint32)0U << 3U) /* SCS[3] */ - | (uint32)((uint32)1U << 8U) /* ENA */ + | (uint32)((uint32)0U << 8U) /* ENA */ | (uint32)((uint32)0U << 9U) /* CLK */ | (uint32)((uint32)0U << 10U) /* SIMO[0] */ | (uint32)((uint32)0U << 11U) /* SOMI[0] */ @@ -857,7 +1812,159 @@ /* USER CODE END */ } +/** @fn void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : MIBSPI_SourceId_012 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR1 = MIBSPI1_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI1_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI1_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI1_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI1_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI1_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI1_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI1_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI1_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI1_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI1_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI1_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI1_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI1_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI1_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[0U] = MIBSPI1_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[1U] = MIBSPI1_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[2U] = MIBSPI1_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[3U] = MIBSPI1_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[4U] = MIBSPI1_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[5U] = MIBSPI1_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[6U] = MIBSPI1_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[7U] = MIBSPI1_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI1_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG1->GCR1; + config_reg->CONFIG_INT0 = mibspiREG1->INT0; + config_reg->CONFIG_LVL = mibspiREG1->LVL; + config_reg->CONFIG_PCFUN = mibspiREG1->PC0; + config_reg->CONFIG_PCDIR = mibspiREG1->PC1; + config_reg->CONFIG_PCPDR = mibspiREG1->PC6; + config_reg->CONFIG_PCDIS = mibspiREG1->PC7; + config_reg->CONFIG_PCPSL = mibspiREG1->PC8; + config_reg->CONFIG_DELAY = mibspiREG1->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG1->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG1->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG1->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG1->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG1->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG1->LTGPEND; + config_reg->CONFIG_TGCTRL[0U] = mibspiREG1->TGCTRL[0U]; + config_reg->CONFIG_TGCTRL[1U] = mibspiREG1->TGCTRL[1U]; + config_reg->CONFIG_TGCTRL[2U] = mibspiREG1->TGCTRL[2U]; + config_reg->CONFIG_TGCTRL[3U] = mibspiREG1->TGCTRL[3U]; + config_reg->CONFIG_TGCTRL[4U] = mibspiREG1->TGCTRL[4U]; + config_reg->CONFIG_TGCTRL[5U] = mibspiREG1->TGCTRL[5U]; + config_reg->CONFIG_TGCTRL[6U] = mibspiREG1->TGCTRL[6U]; + config_reg->CONFIG_TGCTRL[7U] = mibspiREG1->TGCTRL[7U]; + config_reg->CONFIG_UERRCTRL = mibspiREG1->UERRCTRL; + } +} +/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +* @brief Get the initial or current values of the configuration registers +* +* @param[in] *config_reg: pointer to the struct to which the initial or current +* value of the configuration registers need to be stored +* @param[in] type: whether initial or current value of the configuration registers need to be stored +* - InitialValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* - CurrentValue: initial value of the configuration registers will be stored +* in the struct pointed by config_reg +* +* This function will copy the initial or current value (depending on the parameter 'type') +* of the configuration registers to the struct pointed by config_reg +* +*/ +/* SourceId : MIBSPI_SourceId_013 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : HL_SR166 */ +void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) +{ + if (type == InitialValue) + { + config_reg->CONFIG_GCR1 = MIBSPI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI3_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI3_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI3_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI3_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI3_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI3_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI3_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI3_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI3_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI3_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI3_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI3_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI3_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI3_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[0U] = MIBSPI3_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[1U] = MIBSPI3_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[2U] = MIBSPI3_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[3U] = MIBSPI3_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[4U] = MIBSPI3_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[5U] = MIBSPI3_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[6U] = MIBSPI3_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[7U] = MIBSPI3_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_UERRCTRL = MIBSPI3_UERRCTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR1 = mibspiREG3->GCR1; + config_reg->CONFIG_INT0 = mibspiREG3->INT0; + config_reg->CONFIG_LVL = mibspiREG3->LVL; + config_reg->CONFIG_PCFUN = mibspiREG3->PC0; + config_reg->CONFIG_PCDIR = mibspiREG3->PC1; + config_reg->CONFIG_PCPDR = mibspiREG3->PC6; + config_reg->CONFIG_PCDIS = mibspiREG3->PC7; + config_reg->CONFIG_PCPSL = mibspiREG3->PC8; + config_reg->CONFIG_DELAY = mibspiREG3->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG3->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG3->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG3->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG3->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG3->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG3->LTGPEND; + config_reg->CONFIG_TGCTRL[0U] = mibspiREG3->TGCTRL[0U]; + config_reg->CONFIG_TGCTRL[1U] = mibspiREG3->TGCTRL[1U]; + config_reg->CONFIG_TGCTRL[2U] = mibspiREG3->TGCTRL[2U]; + config_reg->CONFIG_TGCTRL[3U] = mibspiREG3->TGCTRL[3U]; + config_reg->CONFIG_TGCTRL[4U] = mibspiREG3->TGCTRL[4U]; + config_reg->CONFIG_TGCTRL[5U] = mibspiREG3->TGCTRL[5U]; + config_reg->CONFIG_TGCTRL[6U] = mibspiREG3->TGCTRL[6U]; + config_reg->CONFIG_TGCTRL[7U] = mibspiREG3->TGCTRL[7U]; + config_reg->CONFIG_UERRCTRL = mibspiREG3->UERRCTRL; + } +} /** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type) * @brief Get the initial or current values of the configuration registers @@ -940,3 +2047,5 @@ + +