Index: firmware/source/sys_startup.c =================================================================== diff -u -r33c227865b5060922524162df4add41e4536a6d5 -r80f120f475bbd71c798c2a012633aab91cf0b5f0 --- firmware/source/sys_startup.c (.../sys_startup.c) (revision 33c227865b5060922524162df4add41e4536a6d5) +++ firmware/source/sys_startup.c (.../sys_startup.c) (revision 80f120f475bbd71c798c2a012633aab91cf0b5f0) @@ -1,4 +1,4 @@ -/** @file sys_startup.c +/** @file sys_startup.c * @brief Startup Source File * @date 11-Dec-2018 * @version 04.07.01 @@ -13,36 +13,36 @@ * which are relevant for the Startup. */ -/* -* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions +/* +* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com +* +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions * are met: * -* Redistributions of source code must retain the above copyright +* Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the +* notice, this list of conditions and the following disclaimer in the +* documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ @@ -99,7 +99,7 @@ /* DesignId : STARTUP_DesignId_001 */ /* Requirements : HL_SR508 */ void _c_int00(void) -{ +{ /* USER CODE BEGIN (5) */ /* USER CODE END */ @@ -120,26 +120,14 @@ * by its ECC logic for accesses to program flash or data RAM. */ _coreEnableEventBusExport_(); -/* USER CODE BEGIN (9) */ -/* USER CODE END */ - /* Enable response to ECC errors indicated by CPU for accesses to flash */ - flashWREG->FEDACCTRL1 = 0x000A060AU; - -/* USER CODE BEGIN (10) */ -/* USER CODE END */ - - /* Enable CPU ECC checking for ATCM (flash accesses) */ - _coreEnableFlashEcc_(); - - /* USER CODE BEGIN (11) */ /* USER CODE END */ /* Workaround for Errata CORTEXR4 66 */ _errata_CORTEXR4_66_(); - - /* Workaround for Errata CORTEXR4 57 */ + + /* Workaround for Errata CORTEXR4 57 */ _errata_CORTEXR4_57_(); /* Reset handler: the following instructions read from the system exception status register @@ -149,7 +137,7 @@ /* check for power-on reset condition */ /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ if ((SYS_EXCEPTION & POWERON_RESET) != 0U) - { + { /* USER CODE BEGIN (12) */ crcREG->PSA_SIGREGL1 = SYS_EXCEPTION; /* USER CODE END */ @@ -182,26 +170,26 @@ /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U) { - /* Reset caused due + /* Reset caused due * 1) windowed watchdog violation - Add user code here to handle watchdog violation. * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS */ /* Check the WatchDog Status register */ if(WATCHDOG_STATUS != 0U) { - /* Add user code here to handle watchdog violation. */ + /* Add user code here to handle watchdog violation. */ /* USER CODE BEGIN (17) */ /* USER CODE END */ - /* Clear the Watchdog reset flag in Exception Status register */ + /* Clear the Watchdog reset flag in Exception Status register */ SYS_EXCEPTION = WATCHDOG_RESET; - + /* USER CODE BEGIN (18) */ /* USER CODE END */ } else { - /* Clear the ICEPICK reset flag in Exception Status register */ + /* Clear the ICEPICK reset flag in Exception Status register */ SYS_EXCEPTION = ICEPICK_RESET; /* USER CODE BEGIN (19) */ /* USER CODE END */ @@ -229,7 +217,7 @@ { /* Reset caused due to software reset. Add user code to handle software reset. */ - + /* USER CODE BEGIN (22) */ /* USER CODE END */ } @@ -262,8 +250,8 @@ /*SAFETYMCUSW 26 S MR:NA "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ /*SAFETYMCUSW 28 D MR:NA "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ for(;;) - { - }/* Wait */ + { + }/* Wait */ /* USER CODE BEGIN (25) */ #endif /* USER CODE END */ @@ -274,66 +262,66 @@ /* Initialize System - Clock, Flash settings with Efuse self check */ systemInit(); - + /* Workaround for Errata PBIST#4 */ errata_PBIST_4(); - + /* Run a diagnostic check on the memory self-test controller. * This function chooses a RAM test algorithm and runs it on an on-chip ROM. * The memory self-test is expected to fail. The function ensures that the PBIST controller * is capable of detecting and indicating a memory self-test failure. */ - pbistSelfCheck(); - + pbistSelfCheck(); + /* Run PBIST on STC ROM */ pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP, ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast)); - + /* Wait for PBIST for STC ROM to be completed */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while(pbistIsTestCompleted() != TRUE) - { - }/* Wait */ - + { + }/* Wait */ + /* Check if PBIST on STC ROM passed the self-test */ if( pbistIsTestPassed() != TRUE) { /* PBIST and STC ROM failed the self-test. * Need custom handler to check the memory failure * and to take the appropriate next step. */ - + pbistFail(); - } - + } + /* Disable PBIST clocks and disable memory self-test mode */ pbistStop(); /* Run PBIST on PBIST ROM */ pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP, ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast)); - + /* Wait for PBIST for PBIST ROM to be completed */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while(pbistIsTestCompleted() != TRUE) - { - }/* Wait */ - + { + }/* Wait */ + /* Check if PBIST ROM passed the self-test */ if( pbistIsTestPassed() != TRUE) { /* PBIST and STC ROM failed the self-test. * Need custom handler to check the memory failure * and to take the appropriate next step. */ - + pbistFail(); - } - + } + /* Disable PBIST clocks and disable memory self-test mode */ - pbistStop(); + pbistStop(); /* USER CODE BEGIN (29) */ /* USER CODE END */ @@ -342,7 +330,7 @@ /* Disable RAM ECC before doing PBIST for Main RAM */ _coreDisableRamEcc_(); - + /* Run PBIST on CPU RAM. * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs. * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the @@ -357,13 +345,13 @@ /* Wait for PBIST for CPU RAM to be completed */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while(pbistIsTestCompleted() != TRUE) - { - }/* Wait */ + { + }/* Wait */ + - /* USER CODE BEGIN (33) */ /* USER CODE END */ - + /* Check if CPU RAM passed the self-test */ if( pbistIsTestPassed() != TRUE) { @@ -373,9 +361,9 @@ */ /* USER CODE BEGIN (34) */ /* USER CODE END */ - + pbistFail(); - + /* USER CODE BEGIN (35) */ /* USER CODE END */ } @@ -386,36 +374,16 @@ /* Disable PBIST clocks and disable memory self-test mode */ pbistStop(); - + /* USER CODE BEGIN (37) */ /* USER CODE END */ - - /* Initialize CPU RAM. - * This function uses the system module's hardware for auto-initialization of memories and their - * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. - * Hence the value 0x1 passed to the function. - * This function will initialize the entire CPU RAM and the corresponding ECC locations. - */ - memoryInit(0x1U); - -/* USER CODE BEGIN (38) */ -/* USER CODE END */ - - /* Enable ECC checking for TCRAM accesses. - * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. - */ - _coreEnableRamEcc_(); - -/* USER CODE BEGIN (39) */ -/* USER CODE END */ - /* Start PBIST on all dual-port memories */ /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Dual port Memories. PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. */ pbistRun( (uint32)0x00000000U /* EMAC RAM */ - | (uint32)0x00000000U /* USB RAM */ + | (uint32)0x00000000U /* USB RAM */ | (uint32)0x00000800U /* DMA RAM */ | (uint32)0x00000200U /* VIM RAM */ | (uint32)0x00000040U /* MIBSPI1 RAM */ @@ -436,28 +404,16 @@ /* USER CODE BEGIN (40) */ /* USER CODE END */ - - /* Test the CPU ECC mechanism for RAM accesses. - * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses - * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error - * in the ECC causes a data abort exception. The data abort handler is written to look for - * deliberately caused exception and to return the code execution to the instruction - * following the one that caused the abort. - */ - checkRAMECC(); - -/* USER CODE BEGIN (41) */ -/* USER CODE END */ /* USER CODE BEGIN (43) */ /* USER CODE END */ /* Wait for PBIST for CPU RAM to be completed */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while(pbistIsTestCompleted() != TRUE) - { - }/* Wait */ + { + }/* Wait */ + - /* USER CODE BEGIN (44) */ /* USER CODE END */ @@ -474,9 +430,9 @@ */ /* USER CODE BEGIN (46) */ /* USER CODE END */ - + pbistFail(); - + /* USER CODE BEGIN (47) */ /* USER CODE END */ } @@ -486,31 +442,31 @@ /* Disable PBIST clocks and disable memory self-test mode */ pbistStop(); - + /* USER CODE BEGIN (55) */ /* USER CODE END */ /* Release the MibSPI1 modules from local reset. * This will cause the MibSPI1 RAMs to get initialized along with the parity memory. */ mibspiREG1->GCR0 = 0x1U; - + /* Release the MibSPI3 modules from local reset. * This will cause the MibSPI3 RAMs to get initialized along with the parity memory. */ mibspiREG3->GCR0 = 0x1U; - + /* Release the MibSPI5 modules from local reset. * This will cause the MibSPI5 RAMs to get initialized along with the parity memory. */ mibspiREG5->GCR0 = 0x1U; - + /* USER CODE BEGIN (56) */ /* USER CODE END */ /* Enable parity on selected RAMs */ enableParity(); - + /* Initialize all on-chip SRAMs except for MibSPIx RAMs * The MibSPIx modules have their own auto-initialization mechanism which is triggered * as soon as the modules are brought out of local reset. @@ -535,62 +491,62 @@ /* Disable parity */ disableParity(); - + /* Test the parity protection mechanism for peripheral RAMs NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity. Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. */ /* USER CODE BEGIN (57) */ /* USER CODE END */ - + het1ParityCheck(); - + /* USER CODE BEGIN (58) */ /* USER CODE END */ htu1ParityCheck(); - + /* USER CODE BEGIN (59) */ /* USER CODE END */ het2ParityCheck(); - + /* USER CODE BEGIN (60) */ /* USER CODE END */ htu2ParityCheck(); - + /* USER CODE BEGIN (61) */ /* USER CODE END */ adc1ParityCheck(); - + /* USER CODE BEGIN (62) */ /* USER CODE END */ adc2ParityCheck(); - + /* USER CODE BEGIN (63) */ /* USER CODE END */ can1ParityCheck(); - + /* USER CODE BEGIN (64) */ /* USER CODE END */ can2ParityCheck(); - + /* USER CODE BEGIN (65) */ /* USER CODE END */ can3ParityCheck(); - + /* USER CODE BEGIN (66) */ /* USER CODE END */ vimParityCheck(); - + /* USER CODE BEGIN (67) */ /* USER CODE END */ @@ -602,45 +558,45 @@ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U) - { - }/* Wait */ + { + }/* Wait */ /* wait for MibSPI1 RAM to complete initialization */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U) - { - }/* Wait */ - /* wait for MibSPI3 RAM to complete initialization */ + { + }/* Wait */ + /* wait for MibSPI3 RAM to complete initialization */ /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U) - { - }/* Wait */ + { + }/* Wait */ /* wait for MibSPI5 RAM to complete initialization */ /* USER CODE BEGIN (69) */ /* USER CODE END */ mibspi1ParityCheck(); - + /* USER CODE BEGIN (70) */ /* USER CODE END */ mibspi3ParityCheck(); - + /* USER CODE BEGIN (71) */ /* USER CODE END */ - + mibspi5ParityCheck(); + - /* USER CODE BEGIN (72) */ /* USER CODE END */ + - /* USER CODE BEGIN (73) */ /* USER CODE END */ /* Initialize VIM table */ - vimInit(); + vimInit(); /* USER CODE BEGIN (74) */ // shuffle IRQ priorities per design requirements @@ -661,7 +617,7 @@ __TI_auto_init(); /* USER CODE BEGIN (75) */ /* USER CODE END */ - + /* call the application */ /*SAFETYMCUSW 296 S MR:8.6 "Startup code(library functions at block scope)" */ /*SAFETYMCUSW 326 S MR:8.2 "Startup code(Declaration for main in library)" */ @@ -688,7 +644,7 @@ /* USER CODE END */ while(1) { - + } /* USER CODE BEGIN (80) */ /* USER CODE END */