Index: firmware/App/Controllers/DrainPump.c
===================================================================
diff -u -r5a61bccd959265c00e5276ba23391198ca82b6dd -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Controllers/DrainPump.c	(.../DrainPump.c)	(revision 5a61bccd959265c00e5276ba23391198ca82b6dd)
+++ firmware/App/Controllers/DrainPump.c	(.../DrainPump.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -66,10 +66,14 @@
     NUM_OF_DRAIN_PUMP_SELF_TEST_STATES
 } DRAIN_PUMP_SELF_TEST_STATE_T;
 
+// pin assignment for pump enable
+#define DRAIN_PUMP_ENABLE_SPI3_PORT_MASK    0x00000020  // (CS5 - re-purposed as input GPIO)
+// drain pump enable macros
+#define SET_DRAIN_PUMP_ENABLE()             {mibspiREG3->PC3 |= DRAIN_PUMP_ENABLE_SPI3_PORT_MASK;}
+#define CLR_DRAIN_PUMP_ENABLE()             {mibspiREG3->PC3 &= ~DRAIN_PUMP_ENABLE_SPI3_PORT_MASK;}
+
 // TODO - test code - remove later
-// pin assignments for pump test DIP switch 2
 #define DRAIN_PUMP_TEST2_SPI1_PORT_MASK     0x00000004  // (CS2 - re-purposed as input GPIO)
-// dialIn pump stop and direction macros
 #define GET_DIP_SW2_TEST()                  ( ( mibspiREG1->PC2 & DRAIN_PUMP_TEST2_SPI1_PORT_MASK ) != 0 )
 
 // ********** private data **********
@@ -222,12 +226,15 @@
     // TODO - test code - remove later
     if ( GET_DIP_SW2_TEST() )
     {
+        setFPGAValveStates( 0x014F ); // TODO - test code - remove later
         setDrainPumpTargetSpeed( 1000 );
     }
 
     // if we've been given a pressure, transition to control to target state
     if ( getTargetDrainPumpSpeed() > 0 )
     {
+        // set drain pump enable pin
+        SET_DRAIN_PUMP_ENABLE();
         // set drain pump DAC
         drainPumpDACSet = drainPumpDAC;
         setFPGADrainPumpSpeed( drainPumpDACSet );
@@ -269,6 +276,8 @@
     if ( !GET_DIP_SW2_TEST() )
     {
         signalDrainPumpHardStop();
+        setFPGAValveStates( 0x015F ); // TODO - test code - remove later
+        result = DRAIN_PUMP_OFF_STATE;
     }
 
     return result;
@@ -288,7 +297,8 @@
     isDrainPumpOn = FALSE;
     drainPumpDAC = 0;
     drainPumpDACSet = 0;
-    setDrainPumpTargetSpeed( drainPumpDACSet );
+    setFPGADrainPumpSpeed( drainPumpDACSet );
+    CLR_DRAIN_PUMP_ENABLE();
 }
 
 /*********************************************************************//**
@@ -315,14 +325,14 @@
 
 /*********************************************************************//**
  * @brief
- * The getTargetDrainPumpPressure function gets the current target Drain pump \n
- * pressure.
+ * The getTargetDrainPumpSpeed function gets the current target Drain pump \n
+ * speed.
  * @details
- * Inputs : targetDrainPumpPressure
+ * Inputs : targetDrainPumpSpeed
  * Outputs : none
  * @return the current target drain pump speed.
  *************************************************************************/
-U32 getTargetDrainPumpPressure( void )
+U32 getTargetDrainPumpSpeed( void )
 {
     U32 result = targetDrainPumpSpeed.data;
 
Index: firmware/App/Controllers/Pressures.c
===================================================================
diff -u -r65cca9d3650f1da299e0c0c682bc557439a407f2 -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Controllers/Pressures.c	(.../Pressures.c)	(revision 65cca9d3650f1da299e0c0c682bc557439a407f2)
+++ firmware/App/Controllers/Pressures.c	(.../Pressures.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -18,6 +18,7 @@
 #include "AlarmMgmt.h"
 #include "FPGA.h"
 #include "InternalADC.h"
+#include "LoadCell.h"  // TODO - test - remove later
 #include "OperationModes.h"
 #include "SystemCommMessages.h"
 #include "TaskPriority.h"
@@ -253,6 +254,17 @@
 
         broadcastPressureSensorsData( roIn, roOut, drainIn, drainOut );
         pressuresDataPublicationTimerCounter = 0;
+                #ifdef DEBUG_ENABLED
+                {
+                    // TODO - temporary debug code - remove later
+                    F32  lc1 = getLoadCellFilteredWeight(LOAD_CELL_A1);
+                    F32  lc2 = getLoadCellFilteredWeight(LOAD_CELL_B1);
+                    char debugPresStr[ 256 ];
+
+                    sprintf( debugPresStr, "RO: %5d, %5d,  Drain: %5d, %5d,  Loads: %6d, %6d\n", (S32)roIn, (S32)roOut, (S32)drainIn, (S32)drainOut, (S32)lc1, (S32)lc2 );
+                    sendDebugData( (U08*)debugPresStr, strlen(debugPresStr) );
+                }
+                #endif
     }
 }
 
Index: firmware/App/Controllers/ROPump.c
===================================================================
diff -u -r416a8fba5774e6cd64c69513e082afbd79f75ccf -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Controllers/ROPump.c	(.../ROPump.c)	(revision 416a8fba5774e6cd64c69513e082afbd79f75ccf)
+++ firmware/App/Controllers/ROPump.c	(.../ROPump.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -46,7 +46,7 @@
 
 #define ROP_CONTROL_INTERVAL                ( MS_PER_SECOND / TASK_GENERAL_INTERVAL )   ///< interval (ms/task time) at which the RO pump is controlled
 #define ROP_P_COEFFICIENT                   0.005               ///< P term for RO pump control
-#define ROP_I_COEFFICIENT                   0.00015             ///< I term for RO pump control
+#define ROP_I_COEFFICIENT                   0.00025             ///< I term for RO pump control
 
 #define ROP_PSI_TO_PWM_DC(p)                ( 0.2 + ( (F32)((p) - 100) * 0.01 ) )  ///< conversion factor from target PSI to PWM duty cycle estimate   TODO - this is a place holder for real conversion
 
@@ -250,12 +250,13 @@
     // TODO - test code - remove later
     if ( GET_DIP_SW0_TEST() )
     {
-        setROPumpTargetPressure( 130, PUMP_CONTROL_MODE_CLOSED_LOOP );
+        setROPumpTargetPressure( 120, PUMP_CONTROL_MODE_CLOSED_LOOP );
     }
 
     // if we've been given a pressure, transition to control to target state
     if ( getTargetROPumpPressure() > 0 )
     {
+        roPumpControlModeSet = roPumpControlMode;
         // set initial PWM duty cycle
         roPumpPWMDutyCyclePctSet = roPumpPWMDutyCyclePct;
         setROPumpControlSignalPWM( roPumpPWMDutyCyclePctSet );
@@ -303,6 +304,7 @@
     if ( !GET_DIP_SW0_TEST() )
     {
         signalROPumpHardStop();
+        result = RO_PUMP_OFF_STATE;
     }
 
     return result;
Index: firmware/App/Drivers/CPLD.c
===================================================================
diff -u -rea562263f55f20589a8512da8c00be33a8f239b5 -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Drivers/CPLD.c	(.../CPLD.c)	(revision ea562263f55f20589a8512da8c00be33a8f239b5)
+++ firmware/App/Drivers/CPLD.c	(.../CPLD.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -26,6 +26,9 @@
 #define OFF_REQUEST_GIO_PORT_PIN    0U
 #define WD_PET_GIO_PORT_PIN         1U
 #define WD_EXP_GIO_PORT_PIN         2U
+#define LAMP_GRN_SPI5_PORT_MASK     0x00000200  // (CLK(100) - re-purposed as output GPIO)
+#define LAMP_BLU_SPI5_PORT_MASK     0x00010000  // (SIMO[0](99) - re-purposed as output GPIO)
+#define LAMP_RED_SPI5_PORT_MASK     0x01000000  // (SOMI[0](98) - re-purposed as output GPIO)
 
 // CPLD pin I/O macros
 #define GET_WD_EXP()       ( PIN_SIGNAL_STATE_T )( gioGetBit( gioPORTB, WD_EXP_GIO_PORT_PIN ) )
@@ -35,6 +38,13 @@
 
 #define CLR_WD_PET()       gioSetBit( gioPORTB, WD_PET_GIO_PORT_PIN, PIN_SIGNAL_LOW )
 
+#define SET_GREEN()        {mibspiREG5->PC3 |= LAMP_GRN_SPI5_PORT_MASK;}
+#define CLR_GREEN()        {mibspiREG5->PC3 &= ~LAMP_GRN_SPI5_PORT_MASK;}
+#define SET_BLUE()         {mibspiREG5->PC3 |= LAMP_BLU_SPI5_PORT_MASK;}
+#define CLR_BLUE()         {mibspiREG5->PC3 &= ~LAMP_BLU_SPI5_PORT_MASK;}
+#define SET_RED()          {mibspiREG5->PC3 |= LAMP_RED_SPI5_PORT_MASK;}
+#define CLR_RED()          {mibspiREG5->PC3 &= ~LAMP_RED_SPI5_PORT_MASK;}
+
 #ifdef RM46_EVAL_BOARD_TARGET
     // for RM46 eval board, user button B uses the MIBSPI1_nCS[4] pin, so need to re-purpose that pin as GPIO to see the button
     #define USER_BUTTON_MASK            0x00000010  // (nCS[4]
@@ -78,6 +88,11 @@
 {
     // initialize watchdog pet output low (inactive)
     CLR_WD_PET();
+
+    // initialize alarm lamp color LED outputs low (off)
+    CLR_GREEN();
+    CLR_RED();
+    CLR_BLUE();
 }
 
 /*************************************************************************
@@ -111,3 +126,68 @@
     return level;
 }
 
+/*************************************************************************
+ * @brief setCPLDLampGreen
+ * The setCPLDLampGreen function sets the alarm lamp green signal to CPLD \n
+ * to given level.
+ * @details
+ * Inputs : none
+ * Outputs : alarm lamp green signal set to given level.
+ * @param level : LOW or HIGH
+ * @return none
+ *************************************************************************/
+void setCPLDLampGreen( PIN_SIGNAL_STATE_T level )
+{
+    if ( level == PIN_SIGNAL_HIGH )
+    {
+        SET_GREEN();
+    }
+    else
+    {
+        CLR_GREEN();
+    }
+}
+
+/*************************************************************************
+ * @brief setCPLDLampBlue
+ * The setCPLDLampBlue function sets the alarm lamp blue signal to CPLD \n
+ * to given level.
+ * @details
+ * Inputs : none
+ * Outputs : alarm lamp blue signal set to given level.
+ * @param level : LOW or HIGH
+ * @return none
+ *************************************************************************/
+void setCPLDLampBlue( PIN_SIGNAL_STATE_T level )
+{
+    if ( level == PIN_SIGNAL_HIGH )
+    {
+        SET_BLUE();
+    }
+    else
+    {
+        CLR_BLUE();
+    }
+}
+
+/*************************************************************************
+ * @brief setCPLDLampRed
+ * The setCPLDLampRed function sets the alarm lamp red signal to CPLD \n
+ * to given level.
+ * @details
+ * Inputs : none
+ * Outputs : alarm lamp red signal set to given level.
+ * @param level : LOW or HIGH
+ * @return none
+ *************************************************************************/
+void setCPLDLampRed( PIN_SIGNAL_STATE_T level )
+{
+    if ( level == PIN_SIGNAL_HIGH )
+    {
+        SET_RED();
+    }
+    else
+    {
+        CLR_RED();
+    }
+}
Index: firmware/App/Drivers/CPLD.h
===================================================================
diff -u -rb64c49fdcf2b6d95e61e63f8e258c4e600935bbd -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Drivers/CPLD.h	(.../CPLD.h)	(revision b64c49fdcf2b6d95e61e63f8e258c4e600935bbd)
+++ firmware/App/Drivers/CPLD.h	(.../CPLD.h)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -26,6 +26,10 @@
 void toggleCPLDWatchdog( void );
 PIN_SIGNAL_STATE_T getCPLDWatchdogExpired( void );
 
+void setCPLDLampGreen( PIN_SIGNAL_STATE_T level );
+void setCPLDLampBlue( PIN_SIGNAL_STATE_T level );
+void setCPLDLampRed( PIN_SIGNAL_STATE_T level );
+
 #ifdef RM46_EVAL_BOARD_TARGET
     PIN_SIGNAL_STATE_T getUserButtonState( void );
     void setUserLED( BOOL on );
Index: firmware/App/Drivers/SafetyShutdown.c
===================================================================
diff -u -rb64c49fdcf2b6d95e61e63f8e258c4e600935bbd -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Drivers/SafetyShutdown.c	(.../SafetyShutdown.c)	(revision b64c49fdcf2b6d95e61e63f8e258c4e600935bbd)
+++ firmware/App/Drivers/SafetyShutdown.c	(.../SafetyShutdown.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -14,19 +14,17 @@
  *
  **************************************************************************/
 
-#include "gio.h"
+#include "mibspi.h"
 
 #include "SafetyShutdown.h"
 
 // ********** private definitions **********
 
-// GIO port A pin assignments for pins connected to CPLD
-#define SAFETY_GIO_PORT_PIN         3U
+// pin I/O macros
+#define SAFETY_SPI1_PORT_MASK       0x00000010  // (CS[4] - re-purposed as output GPIO)
+#define SET_SAFETY_SHUTDOWN()       {mibspiREG1->PC3 |= SAFETY_SPI1_PORT_MASK;}
+#define CLR_SAFETY_SHUTDOWN()       {mibspiREG1->PC3 &= ~SAFETY_SPI1_PORT_MASK;}
 
-// CPLD pin I/O macros
-#define SET_SAFETY_SHUTDOWN()       gioSetBit( gioPORTB, SAFETY_GIO_PORT_PIN, PIN_SIGNAL_HIGH )
-#define CLR_SAFETY_SHUTDOWN()       gioSetBit( gioPORTB, SAFETY_GIO_PORT_PIN, PIN_SIGNAL_LOW )
-
 /*************************************************************************
  * @brief initSafetyShutdown
  * The initSafetyShutdown function initializes the Buttons module.
Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r16dfbeeca1bcf1d2115c2f7549999fdaae0700e9 -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 16dfbeeca1bcf1d2115c2f7549999fdaae0700e9)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -218,6 +218,7 @@
     memset( &fpgaHeader, 0, sizeof(FPGA_HEADER_T) );
     memset( &fpgaSensorReadings, 0, sizeof(DG_FPGA_SENSORS_T) );
     memset( &fpgaActuatorSetPoints, 0, sizeof(FPGA_ACTUATORS_T) );
+    fpgaActuatorSetPoints.fpgaValveStates = 0x015F;  // TODO - temporary init per Blaine while testing - remove later.
 
     // initialize fpga comm buffers
     memset( &fpgaWriteCmdBuffer, 0, FPGA_WRITE_CMD_BUFFER_LEN );
Index: firmware/App/Tasks/TaskGeneral.c
===================================================================
diff -u -r5ff39fd6948ae3656b4035c85325bd8fca0a37f3 -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Tasks/TaskGeneral.c	(.../TaskGeneral.c)	(revision 5ff39fd6948ae3656b4035c85325bd8fca0a37f3)
+++ firmware/App/Tasks/TaskGeneral.c	(.../TaskGeneral.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -17,6 +17,7 @@
 #include "gio.h"
 #include "lin.h"
 
+#include "DrainPump.h"
 #include "OperationModes.h"
 #include "Reservoirs.h"
 #include "ROPump.h"
@@ -47,6 +48,9 @@
     // manage RO pump
     execROPumpController();
 
+    // manage drain pump
+    execDrainPumpController();
+
     // manage time-based reservoir tasks
     execReservoirs();
 
Index: firmware/App/Tasks/TaskPriority.c
===================================================================
diff -u -r68fc03b5a22f14190146fc9069f022c109682b63 -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/App/Tasks/TaskPriority.c	(.../TaskPriority.c)	(revision 68fc03b5a22f14190146fc9069f022c109682b63)
+++ firmware/App/Tasks/TaskPriority.c	(.../TaskPriority.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -41,7 +41,7 @@
     execInternalADC();
 
     // monitor pressures
-    initPressures();
+    execPressures();
 
     // load cells monitor
     execLoadCell();
Index: firmware/DG.dil
===================================================================
diff -u -r416a8fba5774e6cd64c69513e082afbd79f75ccf -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/DG.dil	(.../DG.dil)	(revision 416a8fba5774e6cd64c69513e082afbd79f75ccf)
+++ firmware/DG.dil	(.../DG.dil)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -1,4 +1,4 @@
-# RM46L852PGE 04/07/20 10:08:26
+# RM46L852PGE 04/10/20 10:43:10
 # 
 ARCH=RM46L852PGE
 # 
@@ -1769,8 +1769,8 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED
 DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1
@@ -1820,7 +1820,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1003.252
 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED
 DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1003.252
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1003.252
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2
@@ -2347,7 +2347,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2
 DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_USE_CS_ENCODE.VALUE=0
@@ -2472,8 +2472,8 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS
 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0
@@ -2525,8 +2525,8 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0
@@ -7125,7 +7125,7 @@
 DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0
-DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=1
 DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0
 DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0
 DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0
@@ -7141,7 +7141,7 @@
 DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0
-DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=1
+DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.DMA_FIDXD_31.VALUE=0
@@ -7209,7 +7209,7 @@
 DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1
 DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0
-DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0
 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_25.VALUE=0
 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_17.VALUE=0
@@ -7223,7 +7223,7 @@
 DRIVER.PINMUX.VAR.DMA_INTBTCEN_10.VALUE=1
 DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0
-DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=1
 DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0
@@ -7544,7 +7544,7 @@
 DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=1
+DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=3
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_27_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMW_24_VALUE.VALUE=0x0001
@@ -7746,7 +7746,7 @@
 DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=2
+DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=1
 DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0
 DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0
@@ -7757,7 +7757,7 @@
 DRIVER.PINMUX.VAR.MUX100_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_30_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_22_SELECT.VALUE=1
-DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_14_SELECT.VALUE=2
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMW_20_VALUE.VALUE=0x0001
@@ -8185,7 +8185,7 @@
 DRIVER.PINMUX.VAR.EMIF.VALUE=0
 DRIVER.PINMUX.VAR.MUX41_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX33_OPTION0.VALUE=1
-DRIVER.PINMUX.VAR.MUX25_OPTION0.VALUE=1
+DRIVER.PINMUX.VAR.MUX25_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX17_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX3_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.DMA_CP0_ISADDR_29.VALUE=0
@@ -8197,7 +8197,7 @@
 DRIVER.PINMUX.VAR.ETPWM_TZ1.VALUE=ASYNC
 DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0
-DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=1
 DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=1
 DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0
 DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT
@@ -8299,7 +8299,7 @@
 DRIVER.PINMUX.VAR.MUX10_OPTION2.VALUE=1
 DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=1
 DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=1
 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001
@@ -8487,7 +8487,7 @@
 DRIVER.PINMUX.VAR.DMA_TRIG_12.VALUE=HARDWARE_TRIGGER
 DRIVER.PINMUX.VAR.MUX40_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX32_OPTION0.VALUE=1
-DRIVER.PINMUX.VAR.MUX24_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX24_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX16_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX2_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.DMA_ADDMW_25.VALUE=CONSTANT
@@ -8496,7 +8496,7 @@
 DRIVER.PINMUX.VAR.DMA_TRIG_13.VALUE=HARDWARE_TRIGGER
 DRIVER.PINMUX.VAR.MUX40_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX32_OPTION1.VALUE=0
-DRIVER.PINMUX.VAR.MUX24_OPTION1.VALUE=1
+DRIVER.PINMUX.VAR.MUX24_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX16_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX2_OPTION5.VALUE=0
 DRIVER.PINMUX.VAR.DMA_ADDMW_26.VALUE=CONSTANT
@@ -8856,7 +8856,7 @@
 DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT
-DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_ETPWM3B"
+DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_ETPWM2B | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_ETPWM3B"
 DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT
@@ -8881,7 +8881,7 @@
 DRIVER.PINMUX.VAR.DMA_EIDXS_12.VALUE=0
 DRIVER.PINMUX.VAR.DMA_CHANNEL_2.VALUE=CHANNEL0
 DRIVER.PINMUX.VAR.ALT_ADC_B.VALUE=0
-DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_PIN_39_SCITX | PINMUX_PIN_40_HET1_19 | PINMUX_PIN_41_HET1_15"
+DRIVER.PINMUX.VAR.PINMUX8.VALUE="PINMUX_PIN_39_SCITX | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_MIBSPI1NCS_4"
 DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0
@@ -8892,7 +8892,7 @@
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0
 DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0
-DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_PIN_54_HET1_31 | PINMUX_PIN_55_MIBSPI3NCS_0"
+DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_PIN_54_MIBSPI3NCS_5 | PINMUX_PIN_55_MIBSPI3NCS_0"
 DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0
@@ -9440,7 +9440,7 @@
 DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000000.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=500004.839
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
@@ -9509,7 +9509,7 @@
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=1000000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=500000
 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=38.709
 DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000
@@ -9537,7 +9537,7 @@
 DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=103334
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=51667
 DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000
@@ -9604,7 +9604,7 @@
 DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=1000000.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=500004.839
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00
 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0
@@ -9636,7 +9636,7 @@
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=103334
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=51667
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000
@@ -9752,7 +9752,7 @@
 DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=250002.419
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=1000000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=500000
 DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1
Index: firmware/include/etpwm.h
===================================================================
diff -u -r416a8fba5774e6cd64c69513e082afbd79f75ccf -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/include/etpwm.h	(.../etpwm.h)	(revision 416a8fba5774e6cd64c69513e082afbd79f75ccf)
+++ firmware/include/etpwm.h	(.../etpwm.h)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -494,7 +494,7 @@
 
 #define ETPWM2_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM2_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM2_TBPRD_CONFIGVALUE          103334U
+#define ETPWM2_TBPRD_CONFIGVALUE          51667U
 #define ETPWM2_CMPCTL_CONFIGVALUE         0x00000000U
 #define ETPWM2_CMPA_CONFIGVALUE           0U
 #define ETPWM2_CMPB_CONFIGVALUE           0U
Index: firmware/include/mibspi.h
===================================================================
diff -u -r416a8fba5774e6cd64c69513e082afbd79f75ccf -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/include/mibspi.h	(.../mibspi.h)	(revision 416a8fba5774e6cd64c69513e082afbd79f75ccf)
+++ firmware/include/mibspi.h	(.../mibspi.h)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -193,7 +193,7 @@
 #define MIBSPI1_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 
 #define MIBSPI1_PCFUN_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) |  (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U))
-#define MIBSPI1_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) |  (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
+#define MIBSPI1_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) |  (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
 #define MIBSPI1_PCPDR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) |  (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
 #define MIBSPI1_PCDIS_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) |  (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
 #define MIBSPI1_PCPSL_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) |  (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U))
@@ -255,7 +255,7 @@
 #define MIBSPI5_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 #define MIBSPI5_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 
-#define MIBSPI5_PCFUN_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U))
+#define MIBSPI5_PCFUN_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
 #define MIBSPI5_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
 #define MIBSPI5_PCPDR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
 #define MIBSPI5_PCDIS_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
Index: firmware/source/etpwm.c
===================================================================
diff -u -r416a8fba5774e6cd64c69513e082afbd79f75ccf -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/source/etpwm.c	(.../etpwm.c)	(revision 416a8fba5774e6cd64c69513e082afbd79f75ccf)
+++ firmware/source/etpwm.c	(.../etpwm.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -177,7 +177,7 @@
     etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG2->TBPRD = 103334U;
+    etpwmREG2->TBPRD = 51667U;
 
     /** - Setup the duty cycle for PWMA */
     etpwmREG2->CMPA = 0U;
Index: firmware/source/mibspi.c
===================================================================
diff -u -r416a8fba5774e6cd64c69513e082afbd79f75ccf -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/source/mibspi.c	(.../mibspi.c)	(revision 416a8fba5774e6cd64c69513e082afbd79f75ccf)
+++ firmware/source/mibspi.c	(.../mibspi.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -477,7 +477,7 @@
                     | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)1U << 3U)  /* SCS[3] */
-                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
                     | (uint32)((uint32)1U << 5U)  /* SCS[5] */
                     | (uint32)((uint32)0U << 8U)  /* ENA */
                     | (uint32)((uint32)1U << 9U)  /* CLK */
@@ -1496,20 +1496,20 @@
                     | (uint32)((uint32)0U << 27U); /* SOMI[3] */
 
     /* MIBSPI5 set all pins to functional */
-    mibspiREG5->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+    mibspiREG5->PC0 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
                     | (uint32)((uint32)0U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)0U << 3U)  /* SCS[3] */
                     | (uint32)((uint32)0U << 8U)  /* ENA */
                     | (uint32)((uint32)0U << 9U)  /* CLK */
                     | (uint32)((uint32)0U << 10U)  /* SIMO[0] */
                     | (uint32)((uint32)0U << 11U)  /* SOMI[0] */
-                    | (uint32)((uint32)1U << 17U)  /* SIMO[1] */
-                    | (uint32)((uint32)1U << 18U)  /* SIMO[2] */
-                    | (uint32)((uint32)1U << 19U)  /* SIMO[3] */
-                    | (uint32)((uint32)1U << 25U)  /* SOMI[1] */
-                    | (uint32)((uint32)1U << 26U)  /* SOMI[2] */
-                    | (uint32)((uint32)1U << 27U); /* SOMI[3] */
+                    | (uint32)((uint32)0U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)0U << 18U)  /* SIMO[2] */
+                    | (uint32)((uint32)0U << 19U)  /* SIMO[3] */
+                    | (uint32)((uint32)0U << 25U)  /* SOMI[1] */
+                    | (uint32)((uint32)0U << 26U)  /* SOMI[2] */
+                    | (uint32)((uint32)0U << 27U); /* SOMI[3] */
 
   /** - Finally start MIBSPI5 */
     mibspiREG5->GCR1 = (mibspiREG5->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
Index: firmware/source/pinmux.c
===================================================================
diff -u -r6d2d8f0267c57135554e5a1acaca9aef37f27949 -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/source/pinmux.c	(.../pinmux.c)	(revision 6d2d8f0267c57135554e5a1acaca9aef37f27949)
+++ firmware/source/pinmux.c	(.../pinmux.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -178,15 +178,15 @@
     
     pinMuxReg->PINMMR4 =    PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03;
     
-    pinMuxReg->PINMMR5 =    PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_ETPWM3B;
+    pinMuxReg->PINMMR5 =    PINMUX_PIN_25_ETPWM2B | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_ETPWM3B;
     
     pinMuxReg->PINMMR6 =    PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A;
     
     pinMuxReg->PINMMR7 =    PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_SCIRX;
     
-    pinMuxReg->PINMMR8 =    PINMUX_PIN_39_SCITX | PINMUX_PIN_40_HET1_19 | PINMUX_PIN_41_HET1_15;
+    pinMuxReg->PINMMR8 =    PINMUX_PIN_39_SCITX | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_MIBSPI1NCS_4;
     
-    pinMuxReg->PINMMR9 =  ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_HET1_31 | PINMUX_PIN_55_MIBSPI3NCS_0;
+    pinMuxReg->PINMMR9 =  ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_MIBSPI3NCS_5 | PINMUX_PIN_55_MIBSPI3NCS_0;
     
     pinMuxReg->PINMMR10 =   PINMUX_PIN_86_AD1EVT;
     
Index: firmware/source/sys_main.c
===================================================================
diff -u -r68fc03b5a22f14190146fc9069f022c109682b63 -r216bd924f989182e648ee5f33f4c91c43ac438ac
--- firmware/source/sys_main.c	(.../sys_main.c)	(revision 68fc03b5a22f14190146fc9069f022c109682b63)
+++ firmware/source/sys_main.c	(.../sys_main.c)	(revision 216bd924f989182e648ee5f33f4c91c43ac438ac)
@@ -64,6 +64,7 @@
 #include "AlarmMgmt.h"
 #include "CommBuffers.h"
 #include "CPLD.h"
+#include "DrainPump.h"
 #include "FPGA.h"
 #include "InternalADC.h"
 #include "MsgQueues.h"
@@ -138,6 +139,7 @@
         etpwmSetCmpA( etpwmREG3, 0 );
         etpwmSetCmpA( etpwmREG6, 0 );
         etpwmSetCmpB( etpwmREG6, 0 );
+        etpwmStartTBCLK();
     canInit();      // CAN1 = CAN, re-purposing CAN2 and CAN3 Rx and Tx pins as GPIO
     sciInit();      // SCI1 used for PC serial interface, SCI2 used for FPGA serial interface
     dmaEnable();    // enable DMA
@@ -162,6 +164,7 @@
     initInternalADC();
     initPressures();
     initROPump();
+    initDrainPump();
     initRTC();
     initCommBuffers();
     initMsgQueues();