Index: firmware/.cproject
===================================================================
diff -u -r3d211bbf5607fb42f003d074caa58f75069774e9 -r33c227865b5060922524162df4add41e4536a6d5
--- firmware/.cproject	(.../.cproject)	(revision 3d211bbf5607fb42f003d074caa58f75069774e9)
+++ firmware/.cproject	(.../.cproject)	(revision 33c227865b5060922524162df4add41e4536a6d5)
@@ -13,7 +13,7 @@
 				</extensions>
 			</storageModule>
 			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
-				<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.1939553624" name="Debug" parent="com.ti.ccstudio.buildDefinitions.TMS470.Debug" postannouncebuildStep="AlarmEnum Check" postbuildStep="${PROJECT_ROOT}/checkAlarms.sh" preannouncebuildStep="AlarmEnum Check" prebuildStep="${PROJECT_ROOT}/checkAlarms.sh">
+				<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.1939553624" name="Debug" parent="com.ti.ccstudio.buildDefinitions.TMS470.Debug" postannouncebuildStep="AlarmEnum Check &amp; Bin Creation" postbuildStep="&quot;${CCE_INSTALL_ROOT}/utils/tiobj2bin/tiobj2bin&quot; &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; &quot;${CG_TOOL_ROOT}/bin/armofd&quot; &quot;${CG_TOOL_ROOT}/bin/armhex&quot; &quot;${CCE_INSTALL_ROOT}/utils/tiobj2bin/mkhex4bin&quot;;&quot;${PROJECT_ROOT}/checkAlarms.sh&quot;;" preannouncebuildStep="AlarmEnum Check" prebuildStep="${PROJECT_ROOT}/checkAlarms.sh">
 					<folderInfo id="com.ti.ccstudio.buildDefinitions.TMS470.Debug.1939553624." name="/" resourcePath="">
 						<toolChain id="com.ti.ccstudio.buildDefinitions.TMS470_18.12.exe.DebugToolchain.1323095594" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.12.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.TMS470_18.12.exe.linkerDebug.107982249">
 							<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.145859360" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
Index: firmware/.launches/DG.launch
===================================================================
diff -u
--- firmware/.launches/DG.launch	(revision 0)
+++ firmware/.launches/DG.launch	(revision 33c227865b5060922524162df4add41e4536a6d5)
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.ti.ccstudio.debug.launchType.device.debugging">
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_DEBUGGER_PROPERTIES./home/fw/workspace_dg_develop/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot; ?&gt;&#10;&lt;PropertyValues&gt;&#10;&#10;  &lt;property id=&quot;ConnectOnStartup&quot;&gt;&#10;    &lt;curValue&gt;1&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;EnableInstalledBreakpoint&quot;&gt;&#10;    &lt;curValue&gt;1&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;IgnoreSoftLaunchFailures&quot;&gt;&#10;    &lt;curValue&gt;0&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;FlashEraseSelection&quot;&gt;&#10;    &lt;curValue&gt;Necessary Sectors Only (for Program Load)&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;&lt;/PropertyValues&gt;&#10;"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_DEBUGGER_PROPERTIES./home/fw/wsdg/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot; ?&gt;&#10;&lt;PropertyValues&gt;&#10;&#10;  &lt;property id=&quot;VerifyAfterProgramLoad&quot;&gt;&#10;    &lt;curValue&gt;Fast verification&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;ConnectOnStartup&quot;&gt;&#10;    &lt;curValue&gt;1&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;EnableInstalledBreakpoint&quot;&gt;&#10;    &lt;curValue&gt;1&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;IgnoreSoftLaunchFailures&quot;&gt;&#10;    &lt;curValue&gt;0&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;FlashEraseSelection&quot;&gt;&#10;    &lt;curValue&gt;Necessary Sectors Only (for Program Load)&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;FlashAutoECCSetting&quot;&gt;&#10;    &lt;curValue&gt;0&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;FlashResetOnConnect&quot;&gt;&#10;    &lt;curValue&gt;1&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;FlashVerifySetting&quot;&gt;&#10;    &lt;curValue&gt;None&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;&lt;/PropertyValues&gt;&#10;"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_DEBUGGER_PROPERTIES./home/fw/wsdg_dev/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot; ?&gt;&#10;&lt;PropertyValues&gt;&#10;&#10;  &lt;property id=&quot;ConnectOnStartup&quot;&gt;&#10;    &lt;curValue&gt;1&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;EnableInstalledBreakpoint&quot;&gt;&#10;    &lt;curValue&gt;1&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;  &lt;property id=&quot;IgnoreSoftLaunchFailures&quot;&gt;&#10;    &lt;curValue&gt;0&lt;/curValue&gt;&#10;  &lt;/property&gt;&#10;&#10;&lt;/PropertyValues&gt;&#10;"/>
+<setAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_HIDE_CONFIG_ELEMENT_TYPES">
+<setEntry value="BOARD"/>
+<setEntry value="BYPASSED_CPU"/>
+<setEntry value="BYPASSED_ROUTER"/>
+<setEntry value="CONNECTION"/>
+<setEntry value="DEVICE"/>
+<setEntry value="NON_DEBUG_CPU"/>
+<setEntry value="NO_DRIVER"/>
+<setEntry value="ROUTER"/>
+<setEntry value="SUBPATH"/>
+<setEntry value="SYSTEM"/>
+</setAttribute>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROGRAM./home/fw/workspace_dg/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="${build_artifact:DG}"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROGRAM./home/fw/workspace_dg_develop/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="${build_artifact:DG}"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROGRAM./home/fw/wsdg/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="${build_artifact:DG}"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROGRAM./home/fw/wsdg_dev/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="${build_artifact:DG}"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROJECT./home/fw/workspace_dg/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="DG"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROJECT./home/fw/workspace_dg_develop/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="DG"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROJECT./home/fw/wsdg/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="DG"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_PROJECT./home/fw/wsdg_dev/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="DG"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.ATTR_TARGET_CONFIG" value="${target_config_active_default:DG}"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM./home/fw/workspace_dg_develop/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="/home/fw/workspace_dg_develop/dgfirmware/firmware/Debug/DG.out"/>
+<stringAttribute key="com.ti.ccstudio.debug.debugModel.MRU_PROGRAM./home/fw/wsdg/dgfirmware/firmware/targetConfigs/RM46L852.ccxml.Texas Instruments XDS110 USB Debug Probe/CortexR4" value="/home/fw/wsdg/dgfirmware/firmware/Debug/DG.out"/>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+<listEntry value="/DG"/>
+</listAttribute>
+<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+<listEntry value="4"/>
+</listAttribute>
+<stringAttribute key="org.eclipse.debug.core.source_locator_id" value="com.ti.ccstudio.debug.sourceLocator"/>
+<stringAttribute key="org.eclipse.debug.core.source_locator_memento" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;sourceLookupDirector&gt;&#10;&lt;sourceContainers duplicates=&quot;false&quot;&gt;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#10;&amp;lt;default/&amp;gt;&amp;#10;&quot; typeId=&quot;org.eclipse.debug.core.containerType.default&quot;/&gt;&#10;&lt;container memento=&quot;&amp;lt;?xml version=&amp;quot;1.0&amp;quot; encoding=&amp;quot;UTF-8&amp;quot; standalone=&amp;quot;no&amp;quot;?&amp;gt;&amp;#10;&amp;lt;cpuSpecificContainer cpuName=&amp;quot;Texas Instruments XDS110 USB Debug Probe/CortexR4&amp;quot;&amp;gt;&amp;#10;&amp;lt;childContainerEntry childMemento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#10;&amp;amp;lt;project name=&amp;amp;quot;DG&amp;amp;quot; referencedProjects=&amp;amp;quot;true&amp;amp;quot;/&amp;amp;gt;&amp;amp;#10;&amp;quot; childType=&amp;quot;org.eclipse.debug.core.containerType.project&amp;quot;/&amp;gt;&amp;#10;&amp;lt;childContainerEntry childMemento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#10;&amp;amp;lt;default/&amp;amp;gt;&amp;amp;#10;&amp;quot; childType=&amp;quot;org.eclipse.debug.core.containerType.default&amp;quot;/&amp;gt;&amp;#10;&amp;lt;childContainerEntry childMemento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#10;&amp;amp;lt;productsSource/&amp;amp;gt;&amp;amp;#10;&amp;quot; childType=&amp;quot;com.ti.ccstudio.debug.containerType.products.source&amp;quot;/&amp;gt;&amp;#10;&amp;lt;childContainerEntry childMemento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#10;&amp;amp;lt;deviceLibrarySource/&amp;amp;gt;&amp;amp;#10;&amp;quot; childType=&amp;quot;com.ti.ccstudio.debug.containerType.device.library.source&amp;quot;/&amp;gt;&amp;#10;&amp;lt;childContainerEntry childMemento=&amp;quot;&amp;amp;lt;?xml version=&amp;amp;quot;1.0&amp;amp;quot; encoding=&amp;amp;quot;UTF-8&amp;amp;quot; standalone=&amp;amp;quot;no&amp;amp;quot;?&amp;amp;gt;&amp;amp;#10;&amp;amp;lt;librarySource/&amp;amp;gt;&amp;amp;#10;&amp;quot; childType=&amp;quot;com.ti.ccstudio.debug.containerType.library.source&amp;quot;/&amp;gt;&amp;#10;&amp;lt;/cpuSpecificContainer&amp;gt;&amp;#10;&quot; typeId=&quot;com.ti.ccstudio.debug.containerType.cpu.specific&quot;/&gt;&#10;&lt;/sourceContainers&gt;&#10;&lt;/sourceLookupDirector&gt;&#10;"/>
+<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;&#10;"/>
+</launchConfiguration>
Index: firmware/App/Services/SystemComm.c
===================================================================
diff -u -r3d211bbf5607fb42f003d074caa58f75069774e9 -r33c227865b5060922524162df4add41e4536a6d5
--- firmware/App/Services/SystemComm.c	(.../SystemComm.c)	(revision 3d211bbf5607fb42f003d074caa58f75069774e9)
+++ firmware/App/Services/SystemComm.c	(.../SystemComm.c)	(revision 33c227865b5060922524162df4add41e4536a6d5)
@@ -973,9 +973,9 @@
             handleSendDGServiceRecordToHD( message );
             break;
 
-        case MSG_ID_DG_SET_ENTER_BOOTLOADER:
-        case MSG_ID_DG_ENTER_BOOTLOADER_NOW:
-        case MSG_ID_DG_REBOOT_NOW:
+        case MSG_ID_FW_SET_ENTER_BOOTLOADER:
+        case MSG_ID_FW_ENTER_BOOTLOADER_NOW:
+        case MSG_ID_FW_REBOOT_NOW:
             handleRebootNowRequest( message );
             break;
 
Index: firmware/App/Services/SystemCommMessages.h
===================================================================
diff -u -r164e1a3ffca18c703676bc7f57f5903c76050600 -r33c227865b5060922524162df4add41e4536a6d5
--- firmware/App/Services/SystemCommMessages.h	(.../SystemCommMessages.h)	(revision 164e1a3ffca18c703676bc7f57f5903c76050600)
+++ firmware/App/Services/SystemCommMessages.h	(.../SystemCommMessages.h)	(revision 33c227865b5060922524162df4add41e4536a6d5)
@@ -535,6 +535,11 @@
 // MSG_ID_DG_CHEM_DISINFECT_ACID_OVERRIDE
 void handleTestChemDisinfectAcidOverride( MESSAGE_T* message );
 
+// MSG_ID_FW_SET_ENTER_BOOTLOADER
+// MSG_ID_FW_ENTER_BOOTLOADER_NOW
+// MSG_ID_FW_REBOOT_NOW
+void handleRebootNowRequest( MESSAGE_T *message );
+
 /**@}*/
 
 #endif
Index: firmware/source/sys_startup.c
===================================================================
diff -u -r2830e6300c40e331b274511fa9183937810cc190 -r33c227865b5060922524162df4add41e4536a6d5
--- firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 2830e6300c40e331b274511fa9183937810cc190)
+++ firmware/source/sys_startup.c	(.../sys_startup.c)	(revision 33c227865b5060922524162df4add41e4536a6d5)
@@ -1,4 +1,4 @@
-/** @file sys_startup.c 
+/** @file sys_startup.c
 *   @brief Startup Source File
 *   @date 11-Dec-2018
 *   @version 04.07.01
@@ -13,36 +13,36 @@
 *   which are relevant for the Startup.
 */
 
-/* 
-* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
-* 
-* 
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+/*
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
+*
+*
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
 *
-*    Redistributions of source code must retain the above copyright 
+*    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
-*    notice, this list of conditions and the following disclaimer in the 
-*    documentation and/or other materials provided with the   
+*    notice, this list of conditions and the following disclaimer in the
+*    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
-*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
-*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
-*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
@@ -99,7 +99,7 @@
 /* DesignId : STARTUP_DesignId_001 */
 /* Requirements : HL_SR508 */
 void _c_int00(void)
-{    
+{
 /* USER CODE BEGIN (5) */
 /* USER CODE END */
 
@@ -131,15 +131,15 @@
 
     /* Enable CPU ECC checking for ATCM (flash accesses) */
     _coreEnableFlashEcc_();
-	
 
+
 /* USER CODE BEGIN (11) */
 /* USER CODE END */
 
         /* Workaround for Errata CORTEXR4 66 */
         _errata_CORTEXR4_66_();
-    
-        /* Workaround for Errata CORTEXR4 57 */ 
+
+        /* Workaround for Errata CORTEXR4 57 */
         _errata_CORTEXR4_57_();
 
     /* Reset handler: the following instructions read from the system exception status register
@@ -149,7 +149,7 @@
     /* check for power-on reset condition */
     /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
     if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
-    {		
+    {
 /* USER CODE BEGIN (12) */
         crcREG->PSA_SIGREGL1 = SYS_EXCEPTION;
 /* USER CODE END */
@@ -182,26 +182,26 @@
     /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */
     else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
     {
-        /* Reset caused due 
+        /* Reset caused due
          *  1) windowed watchdog violation - Add user code here to handle watchdog violation.
          *  2) ICEPICK Reset - After loading code via CCS / System Reset through CCS
          */
         /* Check the WatchDog Status register */
         if(WATCHDOG_STATUS != 0U)
         {
-            /* Add user code here to handle watchdog violation. */ 
+            /* Add user code here to handle watchdog violation. */
 /* USER CODE BEGIN (17) */
 /* USER CODE END */
 
-            /* Clear the Watchdog reset flag in Exception Status register */ 
+            /* Clear the Watchdog reset flag in Exception Status register */
             SYS_EXCEPTION = WATCHDOG_RESET;
-        
+
 /* USER CODE BEGIN (18) */
 /* USER CODE END */
         }
         else
         {
-            /* Clear the ICEPICK reset flag in Exception Status register */ 
+            /* Clear the ICEPICK reset flag in Exception Status register */
             SYS_EXCEPTION = ICEPICK_RESET;
 /* USER CODE BEGIN (19) */
 /* USER CODE END */
@@ -229,7 +229,7 @@
     {
         /* Reset caused due to software reset.
         Add user code to handle software reset. */
-		
+
 /* USER CODE BEGIN (22) */
 /* USER CODE END */
 	}
@@ -253,14 +253,19 @@
     if ((esmREG->SR1[2]) != 0U)
     {
 /* USER CODE BEGIN (24) */
+/* USER CODE BEGIN (24) */
+        const uint32_t testVal = (esmREG->SR1[2]);
+        esmREG->EKR = 0x5;
+#if 1
 /* USER CODE END */
     /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
     /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */
         for(;;)
-        { 
-        }/* Wait */                 
+        {
+        }/* Wait */
 /* USER CODE BEGIN (25) */
+#endif
 /* USER CODE END */
     }
 
@@ -269,66 +274,66 @@
 
     /* Initialize System - Clock, Flash settings with Efuse self check */
     systemInit();
-    
+
     /* Workaround for Errata PBIST#4 */
     errata_PBIST_4();
-	
+
     /* Run a diagnostic check on the memory self-test controller.
      * This function chooses a RAM test algorithm and runs it on an on-chip ROM.
      * The memory self-test is expected to fail. The function ensures that the PBIST controller
      * is capable of detecting and indicating a memory self-test failure.
      */
-    pbistSelfCheck();	
-	
+    pbistSelfCheck();
+
 	/* Run PBIST on STC ROM */
     pbistRun((uint32)STC_ROM_PBIST_RAM_GROUP,
              ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
-    
+
     /* Wait for PBIST for STC ROM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    { 
-    }/* Wait */ 
-    
+    {
+    }/* Wait */
+
     /* Check if PBIST on STC ROM passed the self-test */
     if( pbistIsTestPassed() != TRUE)
     {
         /* PBIST and STC ROM failed the self-test.
          * Need custom handler to check the memory failure
          * and to take the appropriate next step.
          */
-         
+
         pbistFail();
 
-    }   
-	
+    }
+
     /* Disable PBIST clocks and disable memory self-test mode */
     pbistStop();
 
 	/* Run PBIST on PBIST ROM */
     pbistRun((uint32)PBIST_ROM_PBIST_RAM_GROUP,
              ((uint32)PBIST_TripleReadSlow | (uint32)PBIST_TripleReadFast));
-    
+
     /* Wait for PBIST for PBIST ROM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    { 
-    }/* Wait */ 
-    
+    {
+    }/* Wait */
+
     /* Check if PBIST ROM passed the self-test */
     if( pbistIsTestPassed() != TRUE)
     {
         /* PBIST and STC ROM failed the self-test.
          * Need custom handler to check the memory failure
          * and to take the appropriate next step.
          */
-         
+
         pbistFail();
 
-    } 
-	
+    }
+
     /* Disable PBIST clocks and disable memory self-test mode */
-    pbistStop();	
+    pbistStop();
 /* USER CODE BEGIN (29) */
 /* USER CODE END */
 
@@ -337,7 +342,7 @@
 
     /* Disable RAM ECC before doing PBIST for Main RAM */
     _coreDisableRamEcc_();
-    
+
     /* Run PBIST on CPU RAM.
      * The PBIST controller needs to be configured separately for single-port and dual-port SRAMs.
      * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the
@@ -352,13 +357,13 @@
     /* Wait for PBIST for CPU RAM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    { 
-    }/* Wait */                 
-    
+    {
+    }/* Wait */
 
+
 /* USER CODE BEGIN (33) */
 /* USER CODE END */
-    
+
     /* Check if CPU RAM passed the self-test */
     if( pbistIsTestPassed() != TRUE)
     {
@@ -368,9 +373,9 @@
          */
 /* USER CODE BEGIN (34) */
 /* USER CODE END */
-         
+
         pbistFail();
-        
+
 /* USER CODE BEGIN (35) */
 /* USER CODE END */
     }
@@ -381,7 +386,7 @@
     /* Disable PBIST clocks and disable memory self-test mode */
     pbistStop();
 
-    
+
 /* USER CODE BEGIN (37) */
 /* USER CODE END */
 
@@ -396,7 +401,7 @@
 
 /* USER CODE BEGIN (38) */
 /* USER CODE END */
-    
+
     /* Enable ECC checking for TCRAM accesses.
      * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
      */
@@ -410,7 +415,7 @@
        PBIST test performed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
      */
     pbistRun(  (uint32)0x00000000U    /* EMAC RAM */
-             | (uint32)0x00000000U    /* USB RAM */  
+             | (uint32)0x00000000U    /* USB RAM */
              | (uint32)0x00000800U    /* DMA RAM */
              | (uint32)0x00000200U    /* VIM RAM */
              | (uint32)0x00000040U    /* MIBSPI1 RAM */
@@ -449,10 +454,10 @@
     /* Wait for PBIST for CPU RAM to be completed */
     /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while(pbistIsTestCompleted() != TRUE)
-    { 
-    }/* Wait */                 
-    
+    {
+    }/* Wait */
 
+
 /* USER CODE BEGIN (44) */
 /* USER CODE END */
 
@@ -469,9 +474,9 @@
          */
 /* USER CODE BEGIN (46) */
 /* USER CODE END */
-         
+
         pbistFail();
-        
+
 /* USER CODE BEGIN (47) */
 /* USER CODE END */
     }
@@ -481,31 +486,31 @@
 
     /* Disable PBIST clocks and disable memory self-test mode */
     pbistStop();
-    
+
 /* USER CODE BEGIN (55) */
 /* USER CODE END */
 
     /* Release the MibSPI1 modules from local reset.
      * This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
      */
      mibspiREG1->GCR0 = 0x1U;
-     
+
     /* Release the MibSPI3 modules from local reset.
      * This will cause the MibSPI3 RAMs to get initialized along with the parity memory.
      */
     mibspiREG3->GCR0 = 0x1U;
-    
+
     /* Release the MibSPI5 modules from local reset.
      * This will cause the MibSPI5 RAMs to get initialized along with the parity memory.
      */
     mibspiREG5->GCR0 = 0x1U;
-    
+
 /* USER CODE BEGIN (56) */
 /* USER CODE END */
 
     /* Enable parity on selected RAMs */
     enableParity();
-    
+
     /* Initialize all on-chip SRAMs except for MibSPIx RAMs
      * The MibSPIx modules have their own auto-initialization mechanism which is triggered
      * as soon as the modules are brought out of local reset.
@@ -530,62 +535,62 @@
 
     /* Disable parity */
     disableParity();
-    
+
     /* Test the parity protection mechanism for peripheral RAMs
        NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories with parity.
                  Parity Self check is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
     */
 
 /* USER CODE BEGIN (57) */
 /* USER CODE END */
-     
+
     het1ParityCheck();
-    
+
 /* USER CODE BEGIN (58) */
 /* USER CODE END */
 
     htu1ParityCheck();
-    
+
 /* USER CODE BEGIN (59) */
 /* USER CODE END */
 
     het2ParityCheck();
-    
+
 /* USER CODE BEGIN (60) */
 /* USER CODE END */
 
     htu2ParityCheck();
-    
+
 /* USER CODE BEGIN (61) */
 /* USER CODE END */
 
     adc1ParityCheck();
-    
+
 /* USER CODE BEGIN (62) */
 /* USER CODE END */
 
     adc2ParityCheck();
-    
+
 /* USER CODE BEGIN (63) */
 /* USER CODE END */
 
     can1ParityCheck();
-    
+
 /* USER CODE BEGIN (64) */
 /* USER CODE END */
 
     can2ParityCheck();
-    
+
 /* USER CODE BEGIN (65) */
 /* USER CODE END */
 
     can3ParityCheck();
-    
+
 /* USER CODE BEGIN (66) */
 /* USER CODE END */
 
     vimParityCheck();
-    
+
 /* USER CODE BEGIN (67) */
 /* USER CODE END */
 
@@ -597,45 +602,45 @@
 
 /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
-    { 
-    }/* Wait */                 
+    {
+    }/* Wait */
     /* wait for MibSPI1 RAM to complete initialization */
 /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while ((mibspiREG3->FLG & 0x01000000U) == 0x01000000U)
-    { 
-    }/* Wait */                 
-    /* wait for MibSPI3 RAM to complete initialization */ 
+    {
+    }/* Wait */
+    /* wait for MibSPI3 RAM to complete initialization */
 /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
     while ((mibspiREG5->FLG & 0x01000000U) == 0x01000000U)
-    { 
-    }/* Wait */                 
+    {
+    }/* Wait */
     /* wait for MibSPI5 RAM to complete initialization */
 
 /* USER CODE BEGIN (69) */
 /* USER CODE END */
 
     mibspi1ParityCheck();
-    
+
 /* USER CODE BEGIN (70) */
 /* USER CODE END */
 
     mibspi3ParityCheck();
-    
+
 /* USER CODE BEGIN (71) */
 /* USER CODE END */
-    
+
     mibspi5ParityCheck();
-    
 
+
 /* USER CODE BEGIN (72) */
 /* USER CODE END */
-    
 
+
 /* USER CODE BEGIN (73) */
 /* USER CODE END */
 
     /* Initialize VIM table */
-    vimInit();    
+    vimInit();
 
 /* USER CODE BEGIN (74) */
     // shuffle IRQ priorities per design requirements
@@ -656,7 +661,7 @@
     __TI_auto_init();
 /* USER CODE BEGIN (75) */
 /* USER CODE END */
-    
+
     /* call the application */
 /*SAFETYMCUSW 296 S MR:8.6 <APPROVED> "Startup code(library functions at block scope)" */
 /*SAFETYMCUSW 326 S MR:8.2 <APPROVED> "Startup code(Declaration for main in library)" */
@@ -683,7 +688,7 @@
 /* USER CODE END */
 	while(1)
 	{
-		
+
 	}
 /* USER CODE BEGIN (80) */
 /* USER CODE END */