Index: firmware/DG.dil
===================================================================
diff -u -r6d2d8f0267c57135554e5a1acaca9aef37f27949 -ra90f03eb56aaa492908cd2e7417da79f405d67d4
--- firmware/DG.dil	(.../DG.dil)	(revision 6d2d8f0267c57135554e5a1acaca9aef37f27949)
+++ firmware/DG.dil	(.../DG.dil)	(revision a90f03eb56aaa492908cd2e7417da79f405d67d4)
@@ -1,4 +1,4 @@
-# RM46L852PGE 02/21/20 10:09:21
+# RM46L852PGE 02/27/20 09:42:29
 # 
 ARCH=RM46L852PGE
 # 
@@ -2477,7 +2477,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS
 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF
Index: firmware/include/mibspi.h
===================================================================
diff -u -r6d2d8f0267c57135554e5a1acaca9aef37f27949 -ra90f03eb56aaa492908cd2e7417da79f405d67d4
--- firmware/include/mibspi.h	(.../mibspi.h)	(revision 6d2d8f0267c57135554e5a1acaca9aef37f27949)
+++ firmware/include/mibspi.h	(.../mibspi.h)	(revision a90f03eb56aaa492908cd2e7417da79f405d67d4)
@@ -224,7 +224,7 @@
 #define MIBSPI3_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)1U << 6U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 0U))
 #define MIBSPI3_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 
-#define MIBSPI3_PCFUN_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+#define MIBSPI3_PCFUN_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
 #define MIBSPI3_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
 #define MIBSPI3_PCPDR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
 #define MIBSPI3_PCDIS_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
Index: firmware/source/mibspi.c
===================================================================
diff -u -r6d2d8f0267c57135554e5a1acaca9aef37f27949 -ra90f03eb56aaa492908cd2e7417da79f405d67d4
--- firmware/source/mibspi.c	(.../mibspi.c)	(revision 6d2d8f0267c57135554e5a1acaca9aef37f27949)
+++ firmware/source/mibspi.c	(.../mibspi.c)	(revision a90f03eb56aaa492908cd2e7417da79f405d67d4)
@@ -1006,7 +1006,7 @@
 
     /* MIBSPI3 set all pins to functional */
     mibspiREG3->PC0 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
-                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)0U << 3U)  /* SCS[3] */
                     | (uint32)((uint32)0U << 4U)  /* SCS[4] */