Index: firmware/App/Modes/ModeInitPOST.c =================================================================== diff -u -r8467f8ff09e382e0991f14d02683080dc811e24e -rb57b5341e4dfe3a7b17cd333bfcfac9036d11e85 --- firmware/App/Modes/ModeInitPOST.c (.../ModeInitPOST.c) (revision 8467f8ff09e382e0991f14d02683080dc811e24e) +++ firmware/App/Modes/ModeInitPOST.c (.../ModeInitPOST.c) (revision b57b5341e4dfe3a7b17cd333bfcfac9036d11e85) @@ -21,6 +21,7 @@ #include "Fans.h" #include "FPGA.h" #include "Heaters.h" +#include "Integrity.h" #include "LoadCell.h" #include "ModeInitPOST.h" #include "NVDataMgmt.h" @@ -92,7 +93,7 @@ switch ( postState ) { case DG_POST_STATE_START: - postState = DG_POST_STATE_FPGA; + postState = DG_POST_STATE_FW_INTEGRITY; #ifdef SKIP_POST postState = DG_POST_STATE_COMPLETED; #endif @@ -102,6 +103,11 @@ #endif break; + case DG_POST_STATE_FW_INTEGRITY: + testStatus = execIntegrityTest(); + postState = handlePOSTStatus( testStatus ); + break; + case DG_POST_STATE_FPGA: testStatus = execFPGATest(); postState = handlePOSTStatus( testStatus ); Index: firmware/App/Services/AlarmMgmt.h =================================================================== diff -u -rbdf2072247c8779596c6bcf418c5a7ae4d9f9848 -rb57b5341e4dfe3a7b17cd333bfcfac9036d11e85 --- firmware/App/Services/AlarmMgmt.h (.../AlarmMgmt.h) (revision bdf2072247c8779596c6bcf418c5a7ae4d9f9848) +++ firmware/App/Services/AlarmMgmt.h (.../AlarmMgmt.h) (revision b57b5341e4dfe3a7b17cd333bfcfac9036d11e85) @@ -171,6 +171,7 @@ SW_FAULT_ID_INVALID_CONDUCTIVITY_SENSOR_ID, // 90 SW_FAULT_ID_INVALID_PRESSURE_SENSOR_ID, SW_FAULT_ID_INVALID_TASK, + SW_FAULT_ID_INVALID_CRC_ALGO, NUM_OF_SW_FAULT_IDS } SW_FAULT_ID_T; Index: firmware/App/Services/Integrity.c =================================================================== diff -u --- firmware/App/Services/Integrity.c (revision 0) +++ firmware/App/Services/Integrity.c (revision b57b5341e4dfe3a7b17cd333bfcfac9036d11e85) @@ -0,0 +1,95 @@ +/************************************************************************** +* +* Copyright (c) 2021 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file Integrity.c +* +* @author (last) Quang Nguyen +* @date (last) 11-May-2021 +* +* @author (last) Quang Nguyen +* @date (last) 11-May-2021 +* +***************************************************************************/ + +#include + +#include "Integrity.h" +#include "Utilities.h" + +/** + * @addtogroup Integrity + * @{ + */ + +// ********** private definitions ********** + +#define CRC_TABLE_STARTING_ADDR 0x20 ///< The starting address of CRC table for firmware image. + +// ********** private data ********** + +static BOOL checkCrc( CRC_RECORD const * const recPtr ); + +/*********************************************************************//** + * @brief + * The initIntegrity function initializes the Integrity module. + * @details Inputs: none + * @details Outputs: Integrity module initialized + * @return none + *************************************************************************/ +void initIntegrity( void ) +{ +} + +/*********************************************************************//** + * @brief + * The execIntegrityTest function executes the integrity check for firmware image. + * @details Inputs: firmware image CRC table + * @details Outputs: none + * @return Firmware image integrity self-test status + *************************************************************************/ +SELF_TEST_STATUS_T execIntegrityTest( void ) +{ + CRC_TABLE const * const crcTablePtr = (CRC_TABLE *)CRC_TABLE_STARTING_ADDR; + BOOL integrityStatus = TRUE; + U32 i; + + for ( i = 0; i < crcTablePtr->num_recs; ++i ) + { + integrityStatus &= checkCrc( &crcTablePtr->recs[i] ); + } + + return ( TRUE == integrityStatus ) ? SELF_TEST_STATUS_PASSED : SELF_TEST_STATUS_FAILED; +} + +/*********************************************************************//** + * @brief + * The checkCrc function computes the CRC on given memory section and CRC + * algorithm. Then it compares with calculated CRC created by linker. + * @details Inputs: none + * @details Outputs: none + * @param recPtr CRC record data pointer + * @return TRUE if two CRCs are matched, otherwise FALSE + *************************************************************************/ +static BOOL checkCrc( CRC_RECORD const * const recPtr ) +{ + U32 crcCalculated = 0; + + switch ( recPtr->crc_alg_ID ) + { + case CRC32_C: + crcCalculated = crc32( (U08 *)recPtr->addr, recPtr->size ); + break; + + default: + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_SOFTWARE_FAULT, SW_FAULT_ID_INVALID_CRC_ALGO, recPtr->crc_alg_ID ) + break; + } + + return ( (U32)recPtr->crc_value == crcCalculated ) ? TRUE : FALSE; +} + +/**@}*/ Index: firmware/App/Services/Integrity.h =================================================================== diff -u --- firmware/App/Services/Integrity.h (revision 0) +++ firmware/App/Services/Integrity.h (revision b57b5341e4dfe3a7b17cd333bfcfac9036d11e85) @@ -0,0 +1,40 @@ +/************************************************************************** +* +* Copyright (c) 2021 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file Integrity.h +* +* @author (last) Quang Nguyen +* @date (last) 11-May-2021 +* +* @author (last) Quang Nguyen +* @date (last) 11-May-2021 +* +***************************************************************************/ + +#ifndef __INTEGRITY_H__ +#define __INTEGRITY_H__ + +#include "DGCommon.h" + +/** + * @defgroup Integrity Integrity + * @brief Integrity module checks for firmware integrity through crc table generated by TI linker. + * + * @addtogroup Integrity + * @{ + */ + +// ********** public definitions ********** + +// ********** public function prototypes ********** + +void initIntegrity( void ); +SELF_TEST_STATUS_T execIntegrityTest( void ); + +/**@}*/ + +#endif Index: firmware/source/sys_link.cmd =================================================================== diff -u -r0953a2a6940f9f096fa98cc1e8a5578deab4d8ef -rb57b5341e4dfe3a7b17cd333bfcfac9036d11e85 --- firmware/source/sys_link.cmd (.../sys_link.cmd) (revision 0953a2a6940f9f096fa98cc1e8a5578deab4d8ef) +++ firmware/source/sys_link.cmd (.../sys_link.cmd) (revision b57b5341e4dfe3a7b17cd333bfcfac9036d11e85) @@ -55,7 +55,8 @@ MEMORY { VECTORS (X) : origin=0x00000000 length=0x00000020 - FLASH0 (RX) : origin=0x00000020 length=0x0013FFE0 + CRCMEM (RX) : origin=0x00000020 length=0x000001E0 + FLASH0 (RX) : origin=0x00000200 length=0x0013FE00 STACKS (RW) : origin=0x08000000 length=0x00004c00 RAM (RW) : origin=0x08004c00 length=0x0002b400 @@ -71,17 +72,18 @@ SECTIONS { - .intvecs : {} > VECTORS - .text : {} > FLASH0 - .const : {} > FLASH0 - .cinit : {} > FLASH0 - .pinit : {} > FLASH0 + .intvecs : {} > VECTORS, crc_table( _crc_table, algorithm=CRC32_C ) + .text : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .const : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .cinit : {} > FLASH0, crc_table( _crc_table, algorithm=CRC32_C ) + .pinit : {} > FLASH0 .bss : {} > RAM .data : {} > RAM .sysmem : {} > RAM /* USER CODE BEGIN (4) */ + .TI.crctab : {} > CRCMEM /* USER CODE END */ }