Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r30bf93016955d5eb5c4053645d5b2065f20be911 -rc44d6f39df2b76d453754ffea6597f48c9cfab6f
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 30bf93016955d5eb5c4053645d5b2065f20be911)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision c44d6f39df2b76d453754ffea6597f48c9cfab6f)
@@ -107,8 +107,9 @@
 
 #define PROCESSOR_FPGA_CLOCK_DIFF_TOLERANCE     1               ///< Tolerance for processor clock speed check against FPGA clock.
 
-#define MAX_FPGA_COMM_FAILURES_WINDOW_MS (1 * SEC_PER_MIN * MS_PER_SECOND) ///< ///< FPGA comm failures window
+#define MAX_FPGA_COMM_FAILURES_WINDOW_MS ( 1 * SEC_PER_MIN * MS_PER_SECOND ) ///< ///< FPGA comm failures window
 #define MAX_FPGA_COMM_FAILURES           3                       ///< FPGA maximum comm failures per MAX_FPGA_COMM_FAILURES_WINDOW_MS
+#define MIN_POWER_ON_TIME_FOR_COMM_FAILS ( 1 * MS_PER_SECOND )   ///< Allow FPGA comm errors for first second after power-up
 
 // FPGA header struct.
 #pragma pack(push,1)
@@ -2709,10 +2710,13 @@
 {
     BOOL status = false;
 
-    if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES ) )
+    if ( getMSTimerCount() > MIN_POWER_ON_TIME_FOR_COMM_FAILS )
     {
-        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
-        status = TRUE;
+        if ( TRUE == incTimeWindowedCount( TIME_WINDOWED_COUNT_FPGA_COMM_FAILURES ) )
+        {
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_FPGA_COMM_TIMEOUT, MAX_FPGA_COMM_FAILURES, (U32)fpgaSensorReadings.fpgaIOErrorCntProcessor )
+            status = TRUE;
+        }
     }
 
     return status;