Index: firmware/App/Controllers/Switches.c
===================================================================
diff -u -r264d5853c97ab9550878609c9302e87464078734 -rd0b30928bfbb1f3b2b13ffbcf17d4e6ff4bf4f7c
--- firmware/App/Controllers/Switches.c	(.../Switches.c)	(revision 264d5853c97ab9550878609c9302e87464078734)
+++ firmware/App/Controllers/Switches.c	(.../Switches.c)	(revision d0b30928bfbb1f3b2b13ffbcf17d4e6ff4bf4f7c)
@@ -95,11 +95,11 @@
         switch ( i )
         {
             case CONCENTRATE_CAP:
-                currentSwitchStatus = ( getFPGAConcentrateCapStatus() != 0 ? STATE_OPEN : STATE_CLOSED );
+                currentSwitchStatus = getFPGAConcentrateCapStatus();
                 break;
 
             case DIALYSATE_CAP:
-                currentSwitchStatus = ( getFPGADialysateCapStatus() != 0 ? STATE_OPEN : STATE_CLOSED );
+                currentSwitchStatus = getFPGADialysateCapStatus();
                 break;
 
             // NOTE: the default case was removed since this switch case is executed using a for loop so the default
Index: firmware/App/DGCommon.h
===================================================================
diff -u -r264d5853c97ab9550878609c9302e87464078734 -rd0b30928bfbb1f3b2b13ffbcf17d4e6ff4bf4f7c
--- firmware/App/DGCommon.h	(.../DGCommon.h)	(revision 264d5853c97ab9550878609c9302e87464078734)
+++ firmware/App/DGCommon.h	(.../DGCommon.h)	(revision d0b30928bfbb1f3b2b13ffbcf17d4e6ff4bf4f7c)
@@ -25,7 +25,7 @@
 #define DG_VERSION_MAJOR        0
 #define DG_VERSION_MINOR        6
 #define DG_VERSION_MICRO        0
-#define DG_VERSION_BUILD        19
+#define DG_VERSION_BUILD        140
 
 // ********** build switches **********
 
@@ -55,6 +55,7 @@
     #define IGNORE_CONC_PUMP_IN_HEAT_DISINFECT  1          // Not needed
 //    #define NEW_FMD_FLOW_SENSOR             1            // Not needed
     #define DISABLE_HEATERS_EFFICIENCY      1
+
     #define DISABLE_DISINFECT_CONDUCTIVITY 1           // Implement
  //   #define DISABLE_CONC_PUMPS             1
     #define DISABLE_CAP_SWITCHES            1           // Implement
@@ -94,6 +95,7 @@
     U08 fpgaMajor;                          ///< DG FPGA major revision
     U08 fpgaMinor;                          ///< DG FPGA minor revision
     U08 fpgaLab;                            ///< DG FPGA lab revision
+    U32 compatibilityRev;                   ///< DG compatibility revision
 } DG_VERSIONS_T;
 #pragma pack(pop)
 
Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -r264d5853c97ab9550878609c9302e87464078734 -rd0b30928bfbb1f3b2b13ffbcf17d4e6ff4bf4f7c
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision 264d5853c97ab9550878609c9302e87464078734)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision d0b30928bfbb1f3b2b13ffbcf17d4e6ff4bf4f7c)
@@ -82,7 +82,7 @@
 #define FPGA_FLUIDLEAK_STATE_MASK       0x0004                  ///< Bit mask for fluid leak detector.
 
 #define CONCENTRATE_CAP_SWITCH_MASK     0x10                    ///< Concentrate cap switch bit mask
-#define DIALYSATE_CAP_SWITCH_MASK       0x20                    ///< Dialysate cap switch bit mask..
+#define DIALYSATE_CAP_SWITCH_MASK       0x20                    ///< Dialysate cap switch bit mask.
 #define FPGA_POWER_OUT_TIMEOUT_MS       ( 2 * MS_PER_SECOND )   ///< FPGA power out timeout in milliseconds.
 #define FPGA_GPIO_POWER_STATUS_PIN      7                       ///< FPGA GPIO power status pin
 
@@ -185,6 +185,7 @@
     U16 fpgaFanIn3Pulse;                    ///< Reg 400. Fan inlet 3 pulse time in 2.5 resolution
     U16 fpgaFanOut3Pulse;                   ///< Reg 402. Fan outlet 3 pulse time in 2.5 resolution
     U16 fpgaTimerCount_ms;                  ///< Reg 404. Internal FPGA timer count in ms.
+
     U16 fpgaADCVccInt;                      ///< Reg 406. Internal FPGA Vcc Voltage.
     U16 fpgaADCVccAux;                      ///< Reg 408. Internal FPGA Vcc auxiliary voltage.
     U16 fpgaADCVPVN;                        ///< Reg 410. Internal FPGA VPVN voltage.