Fisheye: Tag f068446fdb7889d320ddb6ffbd58f347ce0501e7 refers to a dead (removed) revision in file `.gitignore'.
Fisheye: No comparison available.  Pass `N' to diff?
Fisheye: Tag f068446fdb7889d320ddb6ffbd58f347ce0501e7 refers to a dead (removed) revision in file `.project'.
Fisheye: No comparison available.  Pass `N' to diff?
Index: firmware/.cproject
===================================================================
diff -u -r068955e84bbce746f57f39b1c666337e1d832f56 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/.cproject	(.../.cproject)	(revision 068955e84bbce746f57f39b1c666337e1d832f56)
+++ firmware/.cproject	(.../.cproject)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -41,6 +41,8 @@
 								<option id="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.DIAG_WRAP.810761604" name="Wrap diagnostic messages (--diag_wrap)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.DIAG_WRAP" useByScannerDiscovery="false" value="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.DIAG_WRAP.off" valueType="enumerated"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.INCLUDE_PATH.1133210616" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.TMS470_18.12.compilerID.INCLUDE_PATH" valueType="includePath">
 									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/App}"/>
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/Common}"/>
+									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/FWCommon}"/>
 									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/App/Tasks}"/>
 									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/App/Modes}"/>
 									<listOptionValue builtIn="false" value="${workspace_loc:/${ProjName}/App/Drivers}"/>
Index: firmware/.settings/org.eclipse.core.resources.prefs
===================================================================
diff -u -r068955e84bbce746f57f39b1c666337e1d832f56 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/.settings/org.eclipse.core.resources.prefs	(.../org.eclipse.core.resources.prefs)	(revision 068955e84bbce746f57f39b1c666337e1d832f56)
+++ firmware/.settings/org.eclipse.core.resources.prefs	(.../org.eclipse.core.resources.prefs)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -11,6 +11,8 @@
 encoding//Debug/App/Services/subdir_vars.mk=UTF-8
 encoding//Debug/App/Tasks/subdir_rules.mk=UTF-8
 encoding//Debug/App/Tasks/subdir_vars.mk=UTF-8
+encoding//Debug/FWCommon/subdir_rules.mk=UTF-8
+encoding//Debug/FWCommon/subdir_vars.mk=UTF-8
 encoding//Debug/makefile=UTF-8
 encoding//Debug/objects.mk=UTF-8
 encoding//Debug/source/subdir_rules.mk=UTF-8
Fisheye: Tag f068446fdb7889d320ddb6ffbd58f347ce0501e7 refers to a dead (removed) revision in file `firmware/App/Common.h'.
Fisheye: No comparison available.  Pass `N' to diff?
Fisheye: Tag f068446fdb7889d320ddb6ffbd58f347ce0501e7 refers to a dead (removed) revision in file `firmware/App/Controllers/AlarmLamp.c'.
Fisheye: No comparison available.  Pass `N' to diff?
Fisheye: Tag f068446fdb7889d320ddb6ffbd58f347ce0501e7 refers to a dead (removed) revision in file `firmware/App/Controllers/AlarmLamp.h'.
Fisheye: No comparison available.  Pass `N' to diff?
Index: firmware/App/Drivers/CPLD.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Drivers/CPLD.c	(.../CPLD.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Drivers/CPLD.c	(.../CPLD.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  **************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include "gio.h"
 #include "mibspi.h"
 
Index: firmware/App/Drivers/Comm.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Drivers/Comm.c	(.../Comm.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Drivers/Comm.c	(.../Comm.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -24,7 +24,72 @@
 
 #define DMA_CH_STATUS_BIT(ch)       ((U32)1U << (ch))
 
+// ********** private data **********
+
+static volatile BOOL canXmitsInProgress = FALSE;
+static volatile BOOL uartXmitsInProgress = FALSE;
+
 /*************************************************************************
+ * @brief signalCANXmitsInitiated
+ * The signalCANXmitsInitiated function sets the CAN transmits in \n
+ * progress flag.
+ * @details
+ * Inputs : none
+ * Outputs : canXmitsInProgress
+ * @param none
+ * @return none
+ *************************************************************************/
+void signalCANXmitsInitiated( void )
+{
+    canXmitsInProgress = TRUE;
+}
+
+/*************************************************************************
+ * @brief signalCANXmitsCompleted
+ * The signalCANXmitsCompleted function resets the CAN transmits in \n
+ * progress flag.
+ * @details
+ * Inputs : none
+ * Outputs : canXmitsInProgress
+ * @param none
+ * @return none
+ *************************************************************************/
+void signalCANXmitsCompleted( void )
+{
+    canXmitsInProgress = FALSE;
+}
+
+/*************************************************************************
+ * @brief signalSCI1XmitsInitiated
+ * The signalSCI1XmitsInitiated function sets the SCI1 transmits in \n
+ * progress flag.
+ * @details
+ * Inputs : none
+ * Outputs : uartXmitsInProgress
+ * @param none
+ * @return none
+ *************************************************************************/
+void signalSCI1XmitsInitiated( void )
+{
+    uartXmitsInProgress = TRUE;
+}
+
+/*************************************************************************
+ * @brief signalSCI1XmitsCompleted
+ * The signalSCI1XmitsCompleted function resets the SCI1 transmits in \n
+ * progress flag.
+ * @details
+ * Inputs : none
+ * Outputs : uartXmitsInProgress
+ * @param none
+ * @return none
+ *************************************************************************/
+void signalSCI1XmitsCompleted( void )
+{
+    uartXmitsInProgress = FALSE;
+}
+
+/*************************************************************************
  * @brief setSCI1DMAReceiveInterrupt
  * The setSCI1DMAReceiveInterrupt function enables DMA receive interrupts \n
  * for the SCI1 peripheral.
@@ -145,6 +210,38 @@
 }
 
 /*************************************************************************
+ * @brief clearSCI1CommErrors
+ * The clearSCI1CommErrors function clears framing and/or overrun error flags \
+ * for the SCI1 peripheral.
+ * @details
+ * Inputs : none
+ * Outputs : SCI1 error flags cleared.
+ * @param none
+ * @return none
+ *************************************************************************/
+void clearSCI1CommErrors( void )
+{
+    sciReceiveByte( sciREG );
+    sciREG->FLR |= ( SCI_FE_INT | SCI_OE_INT );
+}
+
+/*************************************************************************
+ * @brief clearSCI2CommErrors
+ * The clearSCI2CommErrors function clears framing and/or overrun error flags \n
+ * for the SCI2 peripheral.
+ * @details
+ * Inputs : none
+ * Outputs : SCI2 error flags cleared.
+ * @param none
+ * @return none
+ *************************************************************************/
+void clearSCI2CommErrors( void )
+{
+    sciReceiveByte( scilinREG );
+    scilinREG->FLR |= ( SCI_FE_INT | SCI_OE_INT );
+}
+
+/*************************************************************************
  * @brief isSCI1DMATransmitInProgress
  * The isSCI2DMATransmitInProgress function determines whether a DMA transmit \n
  * is in progress on the SCI1 peripheral.
@@ -160,7 +257,7 @@
     BOOL dmaTransmitterBusy = ( ( dmaREG->PEND & DMA_CH_STATUS_BIT(DMA_CH3) ) != 0U ? TRUE : FALSE );
 
 
-    return ( ( transmitterBusy == TRUE ) || ( dmaTransmitterBusy == TRUE ) ? TRUE : FALSE );
+    return ( ( TRUE == uartXmitsInProgress ) || ( transmitterBusy == TRUE ) || ( dmaTransmitterBusy == TRUE ) ? TRUE : FALSE );
 }
 
 /*************************************************************************
@@ -193,7 +290,7 @@
  *************************************************************************/
 BOOL isCAN1TransmitInProgress( void )
 {
-    BOOL result = ( ( canREG1->TXRQx[0] != 0 ) || ( canREG1->TXRQx[1] != 0 ) ? TRUE : FALSE );
+    BOOL result = ( ( TRUE == canXmitsInProgress ) || ( canREG1->TXRQx[ 0 ] != 0 ) || ( canREG1->TXRQx[ 1 ] != 0 ) ? TRUE : FALSE );
 
     return result;
 }
Index: firmware/App/Drivers/Comm.h
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Drivers/Comm.h	(.../Comm.h)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Drivers/Comm.h	(.../Comm.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -26,6 +26,11 @@
 
 // ********** public function prototypes **********
 
+void signalCANXmitsInitiated( void );
+void signalCANXmitsCompleted( void );
+void signalSCI1XmitsInitiated( void );
+void signalSCI1XmitsCompleted( void );
+
 void setSCI1DMAReceiveInterrupt( void );
 void setSCI1DMATransmitInterrupt( void );
 void clearSCI1DMAReceiveInterrupt( void );
@@ -35,6 +40,9 @@
 void clearSCI2DMAReceiveInterrupt( void );
 void clearSCI2DMATransmitInterrupt( void );
 
+void clearSCI1CommErrors( void );
+void clearSCI2CommErrors( void );
+
 BOOL isSCI1DMATransmitInProgress( void );
 BOOL isSCI2DMATransmitInProgress( void );
 
Index: firmware/App/Drivers/InternalADC.c
===================================================================
diff -u
--- firmware/App/Drivers/InternalADC.c	(revision 0)
+++ firmware/App/Drivers/InternalADC.c	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -0,0 +1,183 @@
+/**************************************************************************
+ *
+ *  Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+ *
+ *  THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+ *  WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+ *
+ *  @file InternalADC.c
+ *
+ *  @date 08-Nov-2019
+ *  @author S. Nash
+ *
+ *  @brief Driver for the internal ADC peripheral.
+ *
+ **************************************************************************/
+
+#include "adc.h"
+
+#include "InternalADC.h"
+
+// ********** private definitions **********
+
+#define MAX_ADC_CHANNELS                24      // ADC supports up to 24 channels
+#define SIZE_OF_ROLLING_AVG             16      // samples in rolling average calculations
+#define ROLLING_AVG_SHIFT_DIVIDER       4       // rolling average shift divider
+
+const INT_ADC_CHANNEL_T adcChannelNum2ChannelId[ MAX_ADC_CHANNELS ] =
+{
+    INT_ADC_DIAL_IN_PUMP_SPEED,         // 0
+    INT_ADC_NOT_USED,                   // 1
+    INT_ADC_NOT_USED,                   // 2
+    INT_ADC_NOT_USED,                   // 3
+    INT_ADC_NOT_USED,                   // 4
+    INT_ADC_NOT_USED,                   // 5
+    INT_ADC_NOT_USED,                   // 6
+    INT_ADC_DIAL_IN_PUMP_MOTOR_CURRENT, // 7
+    INT_ADC_NOT_USED,                   // 8
+    INT_ADC_NOT_USED,                   // 9
+    INT_ADC_NOT_USED,                   // 10
+    INT_ADC_NOT_USED,                   // 11
+    INT_ADC_NOT_USED,                   // 12
+    INT_ADC_NOT_USED,                   // 13
+    INT_ADC_NOT_USED,                   // 14
+    INT_ADC_NOT_USED,                   // 15
+    INT_ADC_BLOOD_PUMP_SPEED,           // 16
+    INT_ADC_BLOOD_PUMP_MOTOR_CURRENT,   // 17
+    INT_ADC_DIAL_OUT_PUMP_SPEED,        // 18
+    INT_ADC_DIAL_OUT_PUMP_MOTOR_CURRENT,// 19
+    INT_ADC_NOT_USED,                   // 20
+    INT_ADC_NOT_USED,                   // 21
+    INT_ADC_NOT_USED,                   // 22
+    INT_ADC_NOT_USED                    // 23
+};
+
+// ********** private data **********
+
+static adcData_t adcRawReadings[ NUM_OF_INT_ADC_CHANNELS ];               // buffer holds latest adc channel readings
+static U32 adcRawReadingsCount = 0;                                       // readings count for raw readings buffer
+
+static U16 adcReadings[ NUM_OF_INT_ADC_CHANNELS ][ SIZE_OF_ROLLING_AVG ]; // holds samples for each channel for a rolling average
+static U32 adcReadingsIdx[ NUM_OF_INT_ADC_CHANNELS ];                     // index for next reading in each rolling average array
+static U32 adcReadingsTotals[ NUM_OF_INT_ADC_CHANNELS ];                  // rolling total for each channel - used to calc average
+static U32 adcReadingsAvgs[ NUM_OF_INT_ADC_CHANNELS ];                    // rolling average for each channel
+
+// ********** private function prototypes **********
+
+
+
+/*************************************************************************
+ * @brief initInternalADC
+ * The initInternalADC function initializes the InternalADC module.
+ * @details
+ * Inputs : none
+ * Outputs : InternalADC module is initialized.
+ * @param none
+ * @return none
+ *************************************************************************/
+void initInternalADC( void )
+{
+    U32 c,r;
+
+    // zero all adc values and stats
+    adcRawReadingsCount = 0;
+    for ( c = 0; c < NUM_OF_INT_ADC_CHANNELS; c++ )
+    {
+        adcRawReadings[ c ].id = 0;
+        adcRawReadings[ c ].value = 0;
+        adcReadingsIdx[ c ] = 0;
+        adcReadingsTotals[ c ] = 0;
+        adcReadingsAvgs[ c ] = 0;
+        for ( r = 0; r < SIZE_OF_ROLLING_AVG; r++ )
+        {
+            adcReadings[ c ][ r ] = 0;
+        }
+    }
+
+    // enable interrupt when all channels converted
+    adcEnableNotification( adcREG1, adcGROUP1 );
+}
+
+/*************************************************************************
+ * @brief adcNotification
+ * The adcNotification function handles an ADC conversion complete interrupt. \n
+ * All channel readings in the FIFO are retrieved.
+ * @details
+ * Inputs : ADC FIFO
+ * Outputs : adcRawReadingsCount, adcRawReadings[]
+ * @param adc : pointer to the ADC1 controller
+ * @param group : ADC channel group ID
+ * @return none
+ *************************************************************************/
+void adcNotification( adcBASE_t *adc, uint32 group )
+{
+   if ( adcGROUP1 == group )
+    {
+        adcRawReadingsCount = adcGetData( adcREG1, adcGROUP1, adcRawReadings );
+    }
+}
+
+/*************************************************************************
+ * @brief execInternalADC
+ * The execInternalADC function processes the last set of raw ADC channel \n
+ * readings and kicks off the next conversion of ADC channels.
+ * @details
+ * Inputs : adcRawReadingsCount, adcRawReadings[]
+ * Outputs : adcReadings[][], adcReadingsIdx[], adcReadingsTotals[], adcReadingsAvgs[]
+ * @param adc : pointer to the ADC1 controller
+ * @param group : ADC channel group ID
+ * @return none
+ *************************************************************************/
+void execInternalADC( void )
+{
+    U32 i;
+
+    if ( adcRawReadingsCount < NUM_OF_INT_ADC_CHANNELS )
+    {
+        // process readings from last conversion
+        for ( i = 0; i < adcRawReadingsCount; i++ )
+        {
+            U32 ch = adcChannelNum2ChannelId[ adcRawReadings[ i ].id ];
+
+            adcReadingsTotals[ ch ] -= adcReadings[ ch ][ adcReadingsIdx[ ch ] ];
+            adcReadings[ ch ][ adcReadingsIdx[ ch ] ] = adcRawReadings[i].value;
+            adcReadingsTotals[ ch ] += adcRawReadings[ i ].value;
+            adcReadingsAvgs[ ch ] = adcReadingsTotals[ ch ] >> ROLLING_AVG_SHIFT_DIVIDER;
+            adcReadingsIdx[ ch ] = INC_WRAP( adcReadingsIdx[ ch ], 0, SIZE_OF_ROLLING_AVG - 1 );
+        }
+    }
+    else
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_INT_ADC_DATA_OVERRUN, adcRawReadingsCount )
+    }
+
+    // start an adc channel group conversion
+    adcStartConversion( adcREG1, adcGROUP1 );
+}
+
+/*************************************************************************
+ * @brief getIntADCReading
+ * The getIntADCReading function gets the latest average reading for a given \n
+ * channel.
+ * @details
+ * Inputs : adcReadingsAvgs[]
+ * Outputs : none
+ * @param channel : adc channel to retrieve a reading for
+ * @return average reading for the given channel
+ *************************************************************************/
+U16 getIntADCReading( INT_ADC_CHANNEL_T channel )
+{
+    U16 result = 0;
+
+    if ( channel < NUM_OF_INT_ADC_CHANNELS )
+    {
+        result = adcReadingsAvgs[ channel ];
+    }
+    else
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_INT_ADC_INVALID_CHANNEL_REQUESTED, channel )
+    }
+
+    return result;
+}
+
Index: firmware/App/Drivers/InternalADC.h
===================================================================
diff -u
--- firmware/App/Drivers/InternalADC.h	(revision 0)
+++ firmware/App/Drivers/InternalADC.h	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -0,0 +1,46 @@
+/**************************************************************************
+ *
+ *  Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+ *
+ *  THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+ *  WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+ *
+ *  @file Comm.h
+ *
+ *  @date 08-Nov-2019
+ *  @author S. Nash
+ *
+ *  @brief Header file for internal ADC driver module.
+ *
+ **************************************************************************/
+
+#ifndef __INT_ADC_H__
+#define __INT_ADC_H__
+
+#include "Common.h"
+
+// ********** public definitions **********
+
+#define INT_ADC_BITS_PER_CHANNEL        12
+#define INT_ADC_FULL_SCALE_BITS         4096
+#define INT_ADC_REF_V                   3.3
+
+typedef enum Int_ADC_Channels
+{
+    INT_ADC_NOT_USED = 0,   // TODO - replace with DG channels
+    INT_ADC_BLOOD_PUMP_SPEED,
+    INT_ADC_BLOOD_PUMP_MOTOR_CURRENT,
+    INT_ADC_DIAL_IN_PUMP_SPEED,
+    INT_ADC_DIAL_IN_PUMP_MOTOR_CURRENT,
+    INT_ADC_DIAL_OUT_PUMP_SPEED,
+    INT_ADC_DIAL_OUT_PUMP_MOTOR_CURRENT,
+    NUM_OF_INT_ADC_CHANNELS
+} INT_ADC_CHANNEL_T;
+
+// ********** public function prototypes **********
+
+void initInternalADC( void );
+void execInternalADC( void );
+U16 getIntADCReading( INT_ADC_CHANNEL_T channel );
+
+#endif
Index: firmware/App/Modes/ModeDisinfect.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Modes/ModeDisinfect.c	(.../ModeDisinfect.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Modes/ModeDisinfect.c	(.../ModeDisinfect.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  **************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include <ModeDisinfect.h>
 #include "Common.h"
 #include "OperationModes.h"
@@ -47,8 +46,6 @@
  *************************************************************************/
 void transitionToDisinfectMode( void )
 {
-    // temporary test code - alarm lamp medium alarm
-    requestAlarmLampPattern( LAMP_PATTERN_MED_ALARM );
 }
 
 /*************************************************************************
Index: firmware/App/Modes/ModeFault.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Modes/ModeFault.c	(.../ModeFault.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Modes/ModeFault.c	(.../ModeFault.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  **************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include "Common.h"
 #include "OperationModes.h"
 #include "ModeFault.h"
@@ -47,8 +46,6 @@
  *************************************************************************/
 void transitionToFaultMode( void )
 {
-    // temporary test code - solid red alarm lamp
-    requestAlarmLampPattern( LAMP_PATTERN_FAULT );
 }
 
 /*************************************************************************
Index: firmware/App/Modes/ModeFlush.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Modes/ModeFlush.c	(.../ModeFlush.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Modes/ModeFlush.c	(.../ModeFlush.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  *************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include <ModeFlush.h>
 #include "Common.h"
 #include "OperationModes.h"
@@ -48,8 +47,6 @@
 *************************************************************************/
 void transitionToFlushMode( void )
 {
-   // temporary test code - alarm lamp low alarm
-    requestAlarmLampPattern( LAMP_PATTERN_LOW_ALARM );
 }
 
 /*************************************************************************
Index: firmware/App/Modes/ModeInitPOST.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Modes/ModeInitPOST.c	(.../ModeInitPOST.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Modes/ModeInitPOST.c	(.../ModeInitPOST.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  **************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include "Common.h"
 #include "CPLD.h"
 #include "FPGA.h"
@@ -27,7 +26,6 @@
 typedef enum POST_States
 {
     POST_STATE_START = 0,
-    POST_STATE_ALARM_LAMP,
     POST_STATE_FPGA,
     POST_STATE_WATCHDOG,
     POST_STATE_COMPLETED,
@@ -75,7 +73,6 @@
  *************************************************************************/
 void transitionToInitAndPOSTMode( void )
 {
-    requestAlarmLampPattern( LAMP_PATTERN_MANUAL );
 }
 
 /*************************************************************************
@@ -95,14 +92,9 @@
     switch ( postState )
     {
         case POST_STATE_START:
-            postState = POST_STATE_COMPLETED;
+            postState = POST_STATE_COMPLETED;  //POST_STATE_FPGA;
             break;
 
-        case POST_STATE_ALARM_LAMP:
-            testStatus = execAlarmLampTest();
-            postState = handlePOSTStatus( testStatus );
-            break;
-
         case POST_STATE_FPGA:
             testStatus = execFPGATest();
             postState = handlePOSTStatus( testStatus );
Index: firmware/App/Modes/ModePostTreat.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Modes/ModePostTreat.c	(.../ModePostTreat.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Modes/ModePostTreat.c	(.../ModePostTreat.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  **************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include "Common.h"
 #include "OperationModes.h"
 #include "ModePostTreat.h"
@@ -48,8 +47,6 @@
  *************************************************************************/
 void transitionToPostTreatmentMode( void )
 {
-    // temporary test code - alarm lamp high alarm
-    requestAlarmLampPattern( LAMP_PATTERN_HIGH_ALARM );
 }
 
 /*************************************************************************
Index: firmware/App/Modes/ModeStandby.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Modes/ModeStandby.c	(.../ModeStandby.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Modes/ModeStandby.c	(.../ModeStandby.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  **************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include "Common.h"
 #include "OperationModes.h"
 #include "ModeStandby.h"
@@ -48,12 +47,6 @@
  *************************************************************************/
 void transitionToStandbyMode( void )
 {
-    // temporary test code - alarm lamp OK
-    requestAlarmLampPattern( LAMP_PATTERN_OK );
-
-    // set User LED to off
-
-    setUserLED(FALSE);
 }
 
 /*************************************************************************
Index: firmware/App/Services/AlarmMgmt.c
===================================================================
diff -u
--- firmware/App/Services/AlarmMgmt.c	(revision 0)
+++ firmware/App/Services/AlarmMgmt.c	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -0,0 +1,312 @@
+/**********************************************************************//**
+ *
+ *  Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+ *
+ *  THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+ *  WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+ *
+ *  @file Timers.c
+ *
+ *  @date 07-Nov-2019
+ *  @author S. Nash
+ *
+ *  @brief Alarm Management service module.  Provides general alarm management \n
+ *  functionality including support functions for triggering and clearing \n
+ *  specific alarms.
+ *
+ **************************************************************************/
+
+#include "AlarmMgmt.h"
+#include "OperationModes.h"
+#include "SystemCommMessages.h"
+#include "TaskGeneral.h"
+#include "Timers.h"
+
+/**
+ *  @addtogroup AlarmManagement
+ *  @{
+ */
+
+// ********** private definitions **********
+
+/// A blank alarm data record for alarms that do not include alarm data when triggered.
+const ALARM_DATA_T blankAlarmData = { ALARM_DATA_TYPE_NONE, 0 };
+
+// ********** private data **********
+
+/// table - current state of each alarm
+DATA_ARRAY_DECL( BOOL, AlarmStates, NUM_OF_ALARM_IDS, alarmIsActive );
+
+// ********** private function prototypes **********
+
+static void activateAlarm( ALARM_ID_T alarm );
+
+static DATA_ARRAY_GET_PROTOTYPE( BOOL, getAlarmActive, alarmID );
+
+/*************************************************************************
+ * @brief initAlarmMgmt
+ * The initAlarmMgmt function initializes the AlarmMgmt module.
+ * @details
+ * Inputs : none
+ * Outputs : AlarmMgmt module initialized.
+ * @param none
+ * @return none
+ *************************************************************************/
+void initAlarmMgmt( void )
+{
+    ALARM_ID_T a;
+
+    // initialize alarm states and start time stamps
+    for ( a = ALARM_ID_NO_ALARM; a < NUM_OF_ALARM_IDS; a++ )
+    {
+        alarmIsActive[ a ].data = FALSE;
+        alarmIsActive[ a ].ovData = FALSE;
+        alarmIsActive[ a ].ovInitData = TRUE;
+        alarmIsActive[ a ].override = OVERRIDE_RESET;
+    }
+}
+
+/*************************************************************************
+ * @brief execAlarmMgmt
+ * The execAlarmMgmt function executes the alarm management functions to be \n
+ * done periodically.
+ * @details
+ * Inputs :
+ * Outputs :
+ * @param none
+ * @return none
+ *************************************************************************/
+void execAlarmMgmt( void )
+{
+    // TODO - any alarm audio or LED/lamp management for DG?
+}
+
+/*************************************************************************
+ * @brief activateAlarm
+ * The activateAlarm function activates a given alarm.
+ * @details
+ * Inputs : none
+ * Outputs : alarmIsActive[]
+ * @param alarm : ID of alarm to activate
+ * @return none
+ *************************************************************************/
+static void activateAlarm( ALARM_ID_T alarm )
+{
+    // verify given alarm
+    if ( ( alarm > ALARM_ID_NO_ALARM ) && ( alarm < NUM_OF_ALARM_IDS ) )
+    {
+        // no need to do anything if alarm is already active
+        if ( FALSE == getAlarmActive( alarm ) )
+        {
+            // activate alarm
+            alarmIsActive[ alarm ].data = TRUE;
+#ifdef DEBUG_ENABLED
+            {
+                // TODO - temporary debug code - remove later
+                char debugStr[ 256 ];
+                sprintf( debugStr, "ALARM triggered:%5d \n", alarm );
+                sendDebugData( (U08*)debugStr, strlen(debugStr) );
+            }
+#endif
+        }
+    }
+    else
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_INVALID_ALARM_TO_ACTIVATE, alarm )
+    }
+}
+
+/*************************************************************************
+ * @brief activateAlarmNoData
+ * The activateAlarmNoData function activates a given alarm.  Also, an alarm \n
+ * message is broadcast to the rest of the system.  This function will \n
+ * include given data in the broadcast message for logging.
+ * @details
+ * Inputs : none
+ * Outputs : alarm triggered message sent, alarm activated
+ * @param alarm : ID of alarm to activate
+ * @param alarmData : supporting data to include in alarm msg
+ * @return none
+ *************************************************************************/
+void activateAlarmNoData( ALARM_ID_T alarm )
+{
+    // broadcast alarm and data if alarm not already active
+    if ( FALSE == alarmIsActive[ alarm ].data )
+    {
+        broadcastAlarmTriggered( (U16)alarm, blankAlarmData, blankAlarmData );
+    }
+    activateAlarm( alarm );
+}
+
+/*************************************************************************
+ * @brief activateAlarm1Data
+ * The activateAlarm1Data function activates a given alarm.  Also, an alarm \n
+ * message is broadcast to the rest of the system.  This function will \n
+ * include given data in the broadcast message for logging.
+ * @details
+ * Inputs : none
+ * Outputs : alarm triggered message sent, alarm activated
+ * @param alarm : ID of alarm to activate
+ * @param alarmData : supporting data to include in alarm msg
+ * @return none
+ *************************************************************************/
+void activateAlarm1Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData )
+{
+    // broadcast alarm and data if alarm not already active
+    if ( FALSE == alarmIsActive[ alarm ].data )
+    {
+        broadcastAlarmTriggered( (U16)alarm, alarmData, blankAlarmData );
+    }
+    activateAlarm( alarm );
+}
+
+/*************************************************************************
+ * @brief activateAlarm1Data
+ * The activateAlarm2Data function activates a given alarm.  Also, an alarm \n
+ * message is broadcast to the rest of the system.  This function will \n
+ * include two given data in the broadcast message for logging.
+ * @details
+ * Inputs : none
+ * Outputs : alarm triggered message sent, alarm activated
+ * @param alarm : ID of alarm to activate
+ * @param alarmData1 : supporting data to include in alarm msg
+ * @param alarmData2 : supporting data to include in alarm msg
+ * @return none
+ *************************************************************************/
+void activateAlarm2Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData1, ALARM_DATA_T alarmData2 )
+{
+    // broadcast alarm and data if alarm not already active
+    if ( FALSE == alarmIsActive[ alarm ].data )
+    {
+        broadcastAlarmTriggered( (U16)alarm, alarmData1, alarmData2 );
+    }
+    activateAlarm( alarm );
+}
+
+/*************************************************************************
+ * @brief clearAlarm
+ * The clearAlarm function clears a given alarm if it is recoverable.  Also \n
+ * an alarm message is broadcast to the rest of the system.
+ * @details
+ * Inputs : none
+ * Outputs : AlarmStatusTable[]
+ * @param alarm : ID of alarm to clear
+ * @return none
+ *************************************************************************/
+void clearAlarm( ALARM_ID_T alarm )
+{
+    // verify given alarm
+    if ( ( alarm > ALARM_ID_NO_ALARM ) && ( alarm < NUM_OF_ALARM_IDS ) )
+    {
+        // clear alarm and broadcast alarm clear if not already cleared
+        if ( TRUE == alarmIsActive[ alarm ].data )
+        {
+            broadcastAlarmCleared( alarm );
+            alarmIsActive[ alarm ].data = FALSE;
+        }
+    }
+    else
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_ALARM_MGMT_INVALID_ALARM_TO_CLEAR, alarm )
+    }
+}
+
+/*************************************************************************
+ * @brief isAlarmActive
+ * The isAlarmActive function determines whether a given alarm is currently \n
+ * active.
+ * @details
+ * Inputs : alarmIsActive[]
+ * Outputs : none
+ * @param alarmID : ID of alarm to check
+ * @return TRUE if given alarm is active, FALSE if not
+ *************************************************************************/
+BOOL isAlarmActive( ALARM_ID_T alarm )
+{
+    BOOL result = getAlarmActive( alarm );
+
+    return result;
+}
+
+/*************************************************************************
+ * @brief getAlarmActive
+ * The getAlarmActive function gets the active state of a given alarm.
+ * @details
+ * Inputs : alarmIsActive[]
+ * Outputs : none
+ * @param alarmID : ID of alarm to check
+ * @return TRUE if given alarm is active, FALSE if not
+ *************************************************************************/
+static DATA_ARRAY_GET( BOOL, getAlarmActive, alarmID, NUM_OF_ALARM_IDS-1, alarmIsActive, TRUE )
+
+/**@}*/
+
+
+/*************************************************************************
+ *                       TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/*************************************************************************
+ * @brief
+ * The testSetAlarmStateOverride function overrides the state of the \n
+ * alarm active state for a given alarm with the alarm management with \n
+ * a given active state.
+ * @details
+ * Inputs : none
+ * Outputs : alarm activated or cleared
+ * @param alarmID : ID of alarm to activate or clear
+ * @param value : override state for the given alarm ID (1=activate, 0=clear)
+ * @return TRUE if override successful, FALSE if not
+ *************************************************************************/
+BOOL testSetAlarmStateOverride( U32 alarmID, U32 state )
+{
+    BOOL result = FALSE;
+
+    if ( alarmID < NUM_OF_ALARM_IDS )
+    {
+        if ( TRUE == isTestingActivated() )
+        {
+            if ( TRUE == state )
+            {
+                activateAlarmNoData( (ALARM_ID_T)alarmID );
+            }
+            else
+            {
+                clearAlarm( (ALARM_ID_T)alarmID );
+            }
+            result = TRUE;
+        }
+    }
+
+    return result;
+}
+
+/*************************************************************************
+ * @brief
+ * The testResetAlarmStateOverride function resets the override of the \n
+ * state of the active state for a given alarm with the alarm management.
+ * @details
+ * Inputs : none
+ * Outputs : alarm cleared
+ * @param alarmID : ID of alarm to clear
+ * @return TRUE if alarm clear successful, FALSE if not
+ *************************************************************************/
+BOOL testResetAlarmStateOverride( U32 alarmID )
+{
+    BOOL result = FALSE;
+
+    if ( alarmID < NUM_OF_ALARM_IDS )
+    {
+        if ( TRUE == isTestingActivated() )
+        {
+            result = TRUE;
+            clearAlarm( (ALARM_ID_T)alarmID );
+        }
+    }
+
+    return result;
+}
+
+
+
Index: firmware/App/Services/AlarmMgmt.h
===================================================================
diff -u
--- firmware/App/Services/AlarmMgmt.h	(revision 0)
+++ firmware/App/Services/AlarmMgmt.h	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -0,0 +1,144 @@
+/**********************************************************************//**
+ *
+ *  Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+ *
+ *  THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+ *  WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+ *
+ *  @file AlarmMgmt.h
+ *
+ *  @date 07-Nov-2019
+ *  @author S. Nash
+ *
+ *  @brief header file for Alarm Management service module.
+ *
+ **************************************************************************/
+
+#ifndef __ALARM_MGMT_H__
+#define __ALARM_MGMT_H__
+
+#include "Common.h"
+
+/**
+ *  @defgroup AlarmManagement AlarmManagement
+ *  @brief Alarm Management service module.  Provides general alarm management \n
+ *  functionality including support functions for triggering and clearing \n
+ *  specific alarms.
+ *
+ *  @addtogroup AlarmManagement
+ *  @{
+ */
+
+// ********** public definitions **********
+
+#include "AlarmDefs.h"
+
+/// Alarm data types list.
+typedef enum Alarm_Data_Types
+{
+    ALARM_DATA_TYPE_NONE = 0,                                       ///< No data given.
+    ALARM_DATA_TYPE_U32 = 1,                                        ///< Alarm data is unsigned 32-bit integer type.
+    ALARM_DATA_TYPE_S32 = 2,                                        ///< Alarm data is signed 32-bit integer type.
+    ALARM_DATA_TYPE_F32 = 3,                                        ///< Alarm data is 32-bit floating point type.
+    ALARM_DATA_TYPE_BOOL = 4,                                       ///< Alarm data is 32-bit boolean type.
+    NUM_OF_ALARM_DATA_TYPES                                         ///< Total number of alarm data types.
+} ALARM_DATA_TYPES_T;
+
+#pragma pack(push,4)
+/// Record structure for unsigned integer alarm data.
+typedef struct
+{
+    U32 data;                       ///< Alarm data of unsigned integer type.
+} ALARM_DATA_U32_T;
+
+/// Record structure for signed integer alarm data.
+typedef struct
+{
+    S32 data;                       ///< Alarm data of signed integer type.
+} ALARM_DATA_S32_T;
+
+/// Record structure for floating point alarm data.
+typedef struct
+{
+    F32 data;                       ///< Alarm data of floating point type.
+} ALARM_DATA_F32_T;
+
+/// Record structure for boolean alarm data.
+typedef struct
+{
+    BOOL data;                      ///< Alarm data of boolean type.
+} ALARM_DATA_BOOL_T;
+
+/// Record structure for alarm data of any supported type.
+typedef union
+{
+    ALARM_DATA_U32_T    uInt;       ///< Alarm data of unsigned integer type.
+    ALARM_DATA_S32_T    sInt;       ///< Alarm data of signed integer type.
+    ALARM_DATA_F32_T    flt;        ///< Alarm data of floating point type.
+    ALARM_DATA_BOOL_T   bln;        ///< Alarm data of boolean type.
+} ALARM_DATAS_T;
+
+/// Record structure for alarm data including the data type to aid in interpretation.
+typedef struct
+{
+    ALARM_DATA_TYPES_T  dataType;   ///< The type of alarm data provided.
+    ALARM_DATAS_T       data;       ///< The alarm data of specified type.
+} ALARM_DATA_T;
+#pragma pack(pop)
+
+// Listing of specific software faults for logging purposes.
+typedef enum
+{
+    SW_FAULT_ID_NONE = 0,
+    SW_FAULT_ID_INT_ADC_DATA_OVERRUN,
+    SW_FAULT_ID_INT_ADC_INVALID_CHANNEL_REQUESTED,
+    SW_FAULT_ID_MODE_INIT_POST_INVALID_POST_STATE,
+    SW_FAULT_ID_OP_MODES_ILLEGAL_MODE_TRANSITION_REQUESTED,
+    SW_FAULT_ID_OP_MODES_INVALID_MODE_STATE,
+    SW_FAULT_ID_OP_MODES_INVALID_MODE_REQUESTED,
+    SW_FAULT_ID_OP_MODES_INVALID_MODE_TO_TRANSITION_TO,
+    SW_FAULT_ID_ALARM_MGMT_INVALID_ALARM_TO_ACTIVATE,
+    SW_FAULT_ID_ALARM_MGMT_INVALID_ALARM_TO_CLEAR,
+    SW_FAULT_ID_COMM_BUFFERS_ADD_TOO_MUCH_DATA,
+    SW_FAULT_ID_COMM_BUFFERS_ADD_INVALID_BUFFER,
+    SW_FAULT_ID_COMM_BUFFERS_GET_INVALID_BUFFER,
+    SW_FAULT_ID_COMM_BUFFERS_PEEK_INVALID_BUFFER,
+    SW_FAULT_ID_COMM_BUFFERS_COUNT_INVALID_BUFFER,
+    SW_FAULT_ID_FPGA_INVALID_IN_STATE,
+    SW_FAULT_ID_FPGA_INVALID_OUT_STATE,
+    SW_FAULT_ID_FPGA_WRITE_CMD_TOO_MUCH_DATA,
+    SW_FAULT_ID_FPGA_WRITE_RSP_TOO_MUCH_DATA,
+    SW_FAULT_ID_FPGA_READ_CMD_TOO_MUCH_DATA,
+    SW_FAULT_ID_FPGA_READ_RSP_TOO_MUCH_DATA,
+    SW_FAULT_ID_MSG_QUEUES_ADD_QUEUE_FULL,
+    SW_FAULT_ID_MSG_QUEUES_ADD_INVALID_QUEUE,
+    SW_FAULT_ID_MSG_QUEUES_GET_INVALID_QUEUE,
+    SW_FAULT_ID_MSG_QUEUES_IS_EMPTY_INVALID_QUEUE,
+    SW_FAULT_ID_MSG_QUEUES_IS_FULL_INVALID_QUEUE,
+    SW_FAULT_ID_WATCHDOG_INVALID_SELF_TEST_STATE,
+    SW_FAULT_ID_RTC_EXEC_INVALID_STATE,
+    SW_FAULT_ID_RTC_SELF_TEST_INVALID_STATE,
+    SW_FAULT_ID_RTC_TRANSACTION_SERVICE_INVALID_STATE,
+    SW_FAULT_ID_MSG_PENDING_ACK_LIST_FULL,
+    SW_FAULT_ID_PI_CTRL_INVALID_CONTROLLER,
+    SW_FAULT_ID_PI_CTRL_INVALID_SIGNAL,
+    NUM_OF_SW_FAULT_IDS
+} SW_FAULT_ID_T;
+
+// ********** public function prototypes **********
+
+void initAlarmMgmt( void );
+void execAlarmMgmt( void );
+
+void activateAlarmNoData( ALARM_ID_T alarm );
+void activateAlarm1Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData );
+void activateAlarm2Data( ALARM_ID_T alarm, ALARM_DATA_T alarmData1, ALARM_DATA_T alarmData2 );
+void clearAlarm( ALARM_ID_T alarm );
+BOOL isAlarmActive( ALARM_ID_T alarm );
+
+/**@}*/
+
+BOOL testSetAlarmStateOverride( U32 alarmID, BOOL value );
+BOOL testResetAlarmStateOverride( U32 alarmID );
+
+#endif
Index: firmware/App/Services/CommBuffers.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/CommBuffers.c	(.../CommBuffers.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/CommBuffers.c	(.../CommBuffers.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -32,9 +32,10 @@
 
 // ********** private data **********
 
-static U32 commBufferByteCount[NUM_OF_COMM_BUFFERS][DOUBLE_BUFFERS];             // for each buffer, how many bytes does it contain?  (also index to next available)
-static U32 activeDoubleBuffer[NUM_OF_COMM_BUFFERS];                              // for each buffer, which double buffer is being fed right now?
-static U08 commBuffers[NUM_OF_COMM_BUFFERS][DOUBLE_BUFFERS][COMM_BUFFER_LENGTH]; // each is double buffered to avoid thread contention
+static volatile U32 commBufferByteCount[ NUM_OF_COMM_BUFFERS ][ DOUBLE_BUFFERS ];      // for each buffer, how many bytes does it contain?  (also index to next available)
+static volatile U32 activeDoubleBuffer[ NUM_OF_COMM_BUFFERS ];                         // for each buffer, which double buffer is being fed right now?
+static U08 commBuffers[ NUM_OF_COMM_BUFFERS ][ DOUBLE_BUFFERS ][ COMM_BUFFER_LENGTH ]; // each is double buffered to avoid thread contention
+static volatile BOOL bufferGetLock[ NUM_OF_COMM_BUFFERS ];                             // prevent getter from accessing active buffer while add in progress
 
 // ********** private function prototypes **********
 
@@ -57,13 +58,13 @@
     // reset and zero out all buffers
     for ( b = 0; b < NUM_OF_COMM_BUFFERS; b++ )
     {
-        activeDoubleBuffer[b] = 0;
+        activeDoubleBuffer[ b ] = 0;
         for ( d = 0; d < DOUBLE_BUFFERS; d++ )
         {
-            commBufferByteCount[b][d] = 0;
+            commBufferByteCount[ b ][ d ] = 0;
             for ( i = 0; i < COMM_BUFFER_LENGTH; i++ )
             {
-                commBuffers[b][d][i] = 0;
+                commBuffers[ b ][ d ][ i ] = 0;
             }
         }
     }
@@ -87,44 +88,51 @@
 BOOL addToCommBuffer( COMM_BUFFER_T buffer, U08* data, U32 len )
 {
     BOOL result = FALSE;
-    U32  activeBuffer = activeDoubleBuffer[buffer];
 
     // verify given buffer
     if ( buffer < NUM_OF_COMM_BUFFERS )
     {
+        U32 activeBuffer;
         U32 currentActiveBufCount;  // where to start adding new data to buffer (after existing data)
 
         // add requires brief thread protection because there may be multiple sources for transmits trying to add data to a buffer.
         _disable_IRQ();
+//        _disable_FIQ();
+        bufferGetLock[ buffer ] = TRUE;
 
-        currentActiveBufCount = commBufferByteCount[buffer][activeBuffer];
+        activeBuffer = activeDoubleBuffer[ buffer ];
+        currentActiveBufCount = commBufferByteCount[ buffer ][ activeBuffer ];
 
         // check to make sure buffer is not too full to service this add
         if ( len <= ( COMM_BUFFER_LENGTH - currentActiveBufCount ) )
         {
             U08 *buffPtr;  // buffer destination for added data
 
-            // adjust buffer count per this data add (also reserves space to add data before releasing thread protection)
-            commBufferByteCount[buffer][activeBuffer] += len;
-            // release thread protection
-            _enable_IRQ();
             // set destination pointer to end of active buffer data
-            buffPtr = &commBuffers[buffer][activeBuffer][currentActiveBufCount];
+            buffPtr = &commBuffers[ buffer ][ activeBuffer ][ currentActiveBufCount ];
             // copy source data to destination buffer
             memcpy( buffPtr, data, len );
+            // adjust buffer count per this data add (also reserves space to add data before releasing thread protection)
+            commBufferByteCount[ buffer ][ activeBuffer ] += len;
+            // release thread protection
+            bufferGetLock[ buffer ] = FALSE;
+//            _enable_FIQ();
+            _enable_IRQ();
             // data successfully added to buffer
             result = TRUE;
         }
         else // buffer too full to add this much data
         {
             // release thread protection
+            bufferGetLock[ buffer ] = FALSE;
+//            _enable_FIQ();
             _enable_IRQ();
-            // TODO - s/w fault?
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_ADD_TOO_MUCH_DATA, len )
         }
     }
     else // invalid buffer given
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_ADD_INVALID_BUFFER, buffer )
     }
 
     return result;
@@ -155,12 +163,14 @@
     // verify given buffer
     if ( buffer < NUM_OF_COMM_BUFFERS )
     {
-        // verify size of get
+//        _disable_IRQ();
+//        _disable_FIQ();
+        // verify requested # of bytes to get are in the buffer
         if ( ( len <= ( COMM_BUFFER_LENGTH * DOUBLE_BUFFERS ) ) && ( len <= numberOfBytesInCommBuffer( buffer ) ) )
         {
-            U32 activeBuffer = activeDoubleBuffer[buffer];
+            U32 activeBuffer = activeDoubleBuffer[ buffer ];
             U32 inactiveBuffer = ( activeBuffer == 0 ? 1 : 0 );
-            U32 bytesInInactiveBuffer = commBufferByteCount[buffer][inactiveBuffer];
+            U32 bytesInInactiveBuffer = commBufferByteCount[ buffer ][ inactiveBuffer ];
             U32 sizeOfFirstConsumption = MIN( len, bytesInInactiveBuffer );
 
             // see what we can get from inactive buffer
@@ -178,14 +188,12 @@
                 result += remNumOfBytes;
             }
         }
-        else // invalid peek size given
-        {
-            // TODO - s/w fault
-        }
+//        _enable_FIQ();
+//        _enable_IRQ();
     }
     else // invalid buffer given
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_GET_INVALID_BUFFER, buffer )
     }
 
     return result;
@@ -214,36 +222,32 @@
     // verify given buffer
     if ( buffer < NUM_OF_COMM_BUFFERS )
     {
-        // verify size of peek
+        // verify requested # of bytes to peek are in the buffer
         if ( ( len <= ( COMM_BUFFER_LENGTH * DOUBLE_BUFFERS ) ) && ( len <= numberOfBytesInCommBuffer( buffer ) ) )
         {
-            U32 activeBuffer = activeDoubleBuffer[buffer];
+            U32 activeBuffer = activeDoubleBuffer[ buffer ];
             U32 inactiveBuffer = ( activeBuffer == 0 ? 1 : 0 );
-            U32 bytesInInactiveBuffer = commBufferByteCount[buffer][inactiveBuffer];
+            U32 bytesInInactiveBuffer = commBufferByteCount[ buffer ][ inactiveBuffer ];
 
             if ( len <= bytesInInactiveBuffer )
             {
-                memcpy( data, &commBuffers[buffer][inactiveBuffer][0], len );
+                memcpy( data, &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], len );
                 numOfBytesPeeked = len;
             }
             else // will need to get the rest from active buffer
             {
                 U32 remNumOfBytes = len - bytesInInactiveBuffer;
                 U08 *remPtr = data + bytesInInactiveBuffer;
 
-                memcpy( data, &commBuffers[buffer][inactiveBuffer][0], bytesInInactiveBuffer );
-                memcpy( remPtr, &commBuffers[buffer][activeBuffer][0], remNumOfBytes );
+                memcpy( data, &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], bytesInInactiveBuffer );
+                memcpy( remPtr, &commBuffers[ buffer ][ activeBuffer ][ 0 ], remNumOfBytes );
                 numOfBytesPeeked = bytesInInactiveBuffer + remNumOfBytes;
             }
         }
-        else // invalid peek size given
-        {
-            // TODO - s/w fault
-        }
     }
     else // invalid buffer given
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_PEEK_INVALID_BUFFER, buffer )
     }
 
     return numOfBytesPeeked;
@@ -267,11 +271,21 @@
     // verify given buffer
     if ( buffer < NUM_OF_COMM_BUFFERS )
     {
-        result = commBufferByteCount[buffer][0] + commBufferByteCount[buffer][1];
+        U32 activeBuffer = activeDoubleBuffer[ buffer ];
+        U32 inactiveBuffer = GET_TOGGLE( activeBuffer, 0, 1 );
+
+        if ( FALSE == bufferGetLock[ buffer ] )
+        {
+            result = commBufferByteCount[ buffer ][ inactiveBuffer ] + commBufferByteCount[ buffer ][ activeBuffer ];
+        }
+        else
+        {
+            result = commBufferByteCount[ buffer ][ inactiveBuffer ];
+        }
     }
     else // invalid buffer
     {
-        // TODO - s/w fault.
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_COMM_BUFFERS_COUNT_INVALID_BUFFER, buffer )
     }
 
     return result;
@@ -291,13 +305,13 @@
  *************************************************************************/
 static U32 switchDoubleBuffer( COMM_BUFFER_T buffer )
 {
-    U32 activeBuffer = activeDoubleBuffer[buffer];
+    U32 activeBuffer = activeDoubleBuffer[ buffer ];
     U32 inactiveBuffer = ( activeBuffer == 0 ? 1 : 0 );
 
     // ensure inactive buffer is reset before making active
-    commBufferByteCount[buffer][inactiveBuffer] = 0;
+    commBufferByteCount[ buffer ][ inactiveBuffer ] = 0;
     // switch buffers
-    activeDoubleBuffer[buffer] = inactiveBuffer;
+    activeDoubleBuffer[ buffer ] = inactiveBuffer;
 
     // return the new active buffer (was just inactive)
     return inactiveBuffer;
@@ -318,21 +332,21 @@
  *************************************************************************/
 static void getDataFromInactiveBuffer( COMM_BUFFER_T buffer, U08 *data, U32 len )
 {
-    U32 activeBuffer = activeDoubleBuffer[buffer];
+    U32 activeBuffer = activeDoubleBuffer[ buffer ];
     U32 inactiveBuffer = ( activeBuffer == 0 ? 1 : 0 );
-    U32 bytesInInactiveBuffer = commBufferByteCount[buffer][inactiveBuffer];
+    U32 bytesInInactiveBuffer = commBufferByteCount[ buffer ][ inactiveBuffer ];
 
     // get the requested data from inactive buffer
-    memcpy( data, &commBuffers[buffer][inactiveBuffer][0], len );
+    memcpy( data, &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], len );
 
     if ( len < bytesInInactiveBuffer )
     {
-        U08 *endPtr = (&commBuffers[buffer][inactiveBuffer][0] + len);
+        U08 *endPtr = (&commBuffers[ buffer ][ inactiveBuffer ][ 0 ] + len);
 
         // move un-consumed data in inactive buffer to start of inactive buffer
-        memcpy( &commBuffers[buffer][inactiveBuffer][0], endPtr, (bytesInInactiveBuffer - len) );
+        memcpy( &commBuffers[ buffer ][ inactiveBuffer ][ 0 ], endPtr, ( bytesInInactiveBuffer - len ) );
         // reduce byte count for inactive buffer by # of bytes consumed
-        commBufferByteCount[buffer][inactiveBuffer] -= len;
+        commBufferByteCount[ buffer ][ inactiveBuffer ] -= len;
     }
     else
     {
Index: firmware/App/Services/CommBuffers.h
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/CommBuffers.h	(.../CommBuffers.h)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/CommBuffers.h	(.../CommBuffers.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -24,12 +24,16 @@
 typedef enum Comm_Buffers
 {
     COMM_BUFFER_NOT_USED = 0,           // CAN message boxes start at 1
+    COMM_BUFFER_IN_CAN_HD_ALARM,
     COMM_BUFFER_OUT_CAN_DG_ALARM,
+    COMM_BUFFER_IN_CAN_UI_ALARM,
     COMM_BUFFER_IN_CAN_HD_2_DG,
     COMM_BUFFER_OUT_CAN_DG_2_HD,
+    COMM_BUFFER_IN_CAN_HD_BROADCAST,
     COMM_BUFFER_OUT_CAN_DG_BROADCAST,
-    COMM_BUFFER_IN_CAN_PC_2_DG,
-    COMM_BUFFER_OUT_CAN_DG_2_PC,
+    COMM_BUFFER_IN_CAN_UI_BROADCAST,
+    COMM_BUFFER_IN_CAN_PC,
+    COMM_BUFFER_OUT_CAN_PC,
     COMM_BUFFER_IN_UART_PC,
     COMM_BUFFER_OUT_UART_PC,
     NUM_OF_COMM_BUFFERS
Index: firmware/App/Services/FPGA.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/FPGA.c	(.../FPGA.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -42,6 +42,10 @@
 #define FPGA_PAGE_SIZE                  256
 #define FPGA_EXPECTED_ID                0x59
 
+#define FPGA_HEADER_START_ADDR          256     // update these after re-arranging w/ Randy
+#define FPGA_BULK_READ_START_ADDR       262
+#define FPGA_BULK_WRITE_START_ADDR      2
+
 #define FPGA_WRITE_CMD_BUFFER_LEN       (FPGA_PAGE_SIZE+8)
 #define FPGA_READ_CMD_BUFFER_LEN        8
 #define FPGA_WRITE_RSP_BUFFER_LEN       8
@@ -50,15 +54,14 @@
 #define FPGA_WRITE_CMD_CODE             0x55
 #define FPGA_READ_CMD_CODE              0x5A
 #define FPGA_WRITE_CMD_ACK              0xA5
-#define FPGA_WRITE_CMD_NAK              0xAE
 #define FPGA_READ_CMD_ACK               0xAA
-#define FPGA_READ_CMD_NAK               0xAF
+#define FPGA_CMD_NAK                    0xEE
 
 #define FPGA_CRC_LEN                    2
 #define FPGA_WRITE_CMD_HDR_LEN          4
 #define FPGA_READ_CMD_HDR_LEN           4
-#define FPGA_WRITE_RSP_HDR_LEN          1
-#define FPGA_READ_RSP_HDR_LEN           1
+#define FPGA_WRITE_RSP_HDR_LEN          3
+#define FPGA_READ_RSP_HDR_LEN           3
 
 #define SCI2_RECEIVE_DMA_REQUEST        28
 #define SCI2_TRANSMIT_DMA_REQUEST       29
@@ -71,27 +74,43 @@
 {
     U08 fpgaId;
     U08 fpgaRev;
-    U08 fpgaDiag;
-    U08 gap1;
-    U16 fpgaStatus;
     U16 fpgaControl;
-} FPGA_HEADER_T;
+    U16 fpgaStatus;
+} FPGA_HEADER_T;    // read only on FPGA
 
-typedef struct
+typedef struct  // TODO - add all sensor readings to this structure per FPGA register map
 {
-    U16 bloodLeak;
-    U32 adc1b;
-    U32 adc2b;
-    U32 dialysateTemp1;
-    U32 venousPressure;
-    U32 arterialPressure;
-    U32 adc1a;
-    U32 adc2a;
-    U32 dialysateTemp2;
+    U08 bloodFlowMeterDataPktCount;
+    U08 bloodFlowMeterSlowPktCounts;
+    U08 bloodFlowMeterDeviceStatus;
+    U08 bloodFlowMeterResponse;
+    F32 bloodFlowLast;
+    U08 dialysateFlowMeterDataPktCount;
+    U08 dialysateFlowMeterSlowPckCounts;
+    U08 dialysateFlowMeterDeviceStatus;
+    U08 dialysateFlowMeterResponse;
+    F32 dialysateFlowLast;
+    U08 bloodFlowMeterErrorCount;
+    U08 dialysateFlowMeterErrorCount;
+    U16 bloodOcclusionData;
+    U08 bloodOcclusionReadCount;
+    U08 bloodOcclusionErrorCount;
+    U16 dialysateInOcclusionData;
+    U08 dialysateInOcclusionReadCount;
+    U08 dialysateInOcclusionErrorCount;
+    U16 dialysateOutOcclusionData;
+    U08 dialysateOutOcclusionReadCount;
+    U08 dialysateOutOcclusionErrorCount;
+    U16 arterialPressureData;
+    U08 arterialPressureReadCount;
+    U08 arterialPressureErrorCount;
+    U16 dialysateTempPrimaryData;
+    U16 dialysateTempBackupData;
 } FPGA_SENSORS_T;
 
-typedef struct
+typedef struct  // TODO - add all actuator set points to this structure per FPGA register map
 {
+    U08 bloodValveSetState;
 } FPGA_ACTUATORS_T;
 #pragma pack(pop)
 
@@ -110,10 +129,10 @@
 static BOOL fpgaReadCommandResponseReceived = FALSE;
 
 // FPGA comm buffers
-static U08 fpgaWriteCmdBuffer[FPGA_WRITE_CMD_BUFFER_LEN];
-static U08 fpgaReadCmdBuffer[FPGA_READ_CMD_BUFFER_LEN];
-static U08 fpgaWriteResponseBuffer[FPGA_WRITE_RSP_BUFFER_LEN];
-static U08 fpgaReadResponseBuffer[FPGA_READ_RSP_BUFFER_LEN];
+static U08 fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_BUFFER_LEN ];
+static U08 fpgaReadCmdBuffer[ FPGA_READ_CMD_BUFFER_LEN ];
+static U08 fpgaWriteResponseBuffer[ FPGA_WRITE_RSP_BUFFER_LEN ];
+static U08 fpgaReadResponseBuffer[ FPGA_READ_RSP_BUFFER_LEN ];
 
 // DMA control records
 static g_dmaCTRL fpgaDMAWriteControlRecord;
@@ -363,7 +382,7 @@
         default:
             if ( fpgaState >= NUM_OF_FPGA_STATES )
             {
-                // TODO - s/w fault
+                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_IN_STATE, fpgaState )
             }
             else
             {
@@ -413,7 +432,7 @@
         default:
             if ( fpgaState >= NUM_OF_FPGA_STATES )
             {
-                // TODO - s/w fault
+                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_INVALID_OUT_STATE, fpgaState )
             }
             else
             {
@@ -439,13 +458,13 @@
     U16 crc;
 
     // construct read command to read 3 registers starting at address 0
-    fpgaReadCmdBuffer[0] = FPGA_READ_CMD_CODE;
-    fpgaReadCmdBuffer[1] = 0x00;    // start at FPGA address 0
-    fpgaReadCmdBuffer[2] = 0x00;
-    fpgaReadCmdBuffer[3] = sizeof(FPGA_HEADER_T);
+    fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
+    fpgaReadCmdBuffer[ 1 ] = 0x00;    // start at FPGA address 0
+    fpgaReadCmdBuffer[ 2 ] = 0x00;
+    fpgaReadCmdBuffer[ 3 ] = sizeof(FPGA_HEADER_T);
     crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
-    fpgaReadCmdBuffer[4] = GET_LSB_OF_WORD( crc );
-    fpgaReadCmdBuffer[5] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
     // prep DMA for sending the read cmd and receiving the response
     fpgaReadCommandInProgress = TRUE;
     setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_HEADER_T) + FPGA_CRC_LEN );
@@ -474,19 +493,18 @@
     if ( TRUE == fpgaReadCommandResponseReceived )
     {
         // did FPGA Ack the read command?
-        if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK )
+        if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK )
         {
             U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_HEADER_T);
             U32 crcPos = rspSize;
-            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos+1], fpgaReadResponseBuffer[crcPos] );
+            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
 
             // does the FPGA response CRC check out?
             if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
-//            if ( 1 ) // TODO - remove when FPGA CRCs are implemented
             {
                 fpgaCommRetryCount = 0;
                 // capture the read values
-                memcpy( &fpgaHeader, &fpgaReadResponseBuffer[1], sizeof(FPGA_HEADER_T) );
+                memcpy( &fpgaHeader, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_HEADER_T ) );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else
@@ -526,29 +544,28 @@
     U16 crc;
 
     // construct bulk write command to write actuator data registers starting at address 3  (TODO - change address later)
-    fpgaWriteCmdBuffer[0] = FPGA_WRITE_CMD_CODE;
-    fpgaWriteCmdBuffer[1] = 0x08;    // start at FPGA address 8
-    fpgaWriteCmdBuffer[2] = 0x00;
-    fpgaWriteCmdBuffer[3] = 1;  // TODO - replace 1 with sizeof(FPGA_ACTUATORS_T)
-//    memcpy( &(fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN]), &fpgaActuatorSetPoints, sizeof(FPGA_ACTUATORS_T) );
-    fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN] = 99; // TODO - remove and replace with memcpy above
-    crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN+1 ); // TODO - replace +1 with +sizeof(FPGA_ACTUATORS_T)
-    fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN+1] = GET_LSB_OF_WORD( crc ); // TODO - replace +1 with +sizeof(FPGA_ACTUATORS_T)
-    fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN+1+1] = GET_MSB_OF_WORD( crc ); // TODO - replace +1 with +sizeof(FPGA_ACTUATORS_T)
+    fpgaWriteCmdBuffer[ 0 ] = FPGA_WRITE_CMD_CODE;
+    fpgaWriteCmdBuffer[ 1 ] = 0x08;    // start at FPGA address 8
+    fpgaWriteCmdBuffer[ 2 ] = 0x00;
+    fpgaWriteCmdBuffer[ 3 ] = sizeof(FPGA_ACTUATORS_T);
+    memcpy( &( fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN ] ), &fpgaActuatorSetPoints, sizeof( FPGA_ACTUATORS_T ) );
+    crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) );
+    fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) ] = GET_MSB_OF_WORD( crc );
+    fpgaWriteCmdBuffer[ FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) + 1 ] = GET_LSB_OF_WORD( crc );
     // construct bulk read command to read sensor data registers starting at address 8
-    fpgaReadCmdBuffer[0] = FPGA_READ_CMD_CODE;
-    fpgaReadCmdBuffer[1] = 0x08;    // start at FPGA address 8
-    fpgaReadCmdBuffer[2] = 0x00;
-    fpgaReadCmdBuffer[3] = sizeof(FPGA_SENSORS_T);
+    fpgaReadCmdBuffer[ 0 ] = FPGA_READ_CMD_CODE;
+    fpgaReadCmdBuffer[ 1 ] = 0x08;    // start at FPGA address 0x108 (264)
+    fpgaReadCmdBuffer[ 2 ] = 0x01;
+    fpgaReadCmdBuffer[ 3 ] = sizeof(FPGA_SENSORS_T);
     crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN );
-    fpgaReadCmdBuffer[4] = GET_LSB_OF_WORD( crc );
-    fpgaReadCmdBuffer[5] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 4 ] = GET_MSB_OF_WORD( crc );
+    fpgaReadCmdBuffer[ 5 ] = GET_LSB_OF_WORD( crc );
     // prep DMA for sending the bulk write cmd and receiving its response
-    setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + 1 + FPGA_CRC_LEN );  // TODO s/b sizeof(FPGA_ACTUATORS_T) instead of 1
-    setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN );
+    setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + sizeof( FPGA_ACTUATORS_T ) + FPGA_CRC_LEN );
+    setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN + FPGA_CRC_LEN );
     // prep DMA for sending the bulk read cmd and receiving its response
     setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN );
-    setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T) + FPGA_CRC_LEN );
+    setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof( FPGA_SENSORS_T ) + FPGA_CRC_LEN );
     // set fpga comm flags for bulk write cmd and follow-up bulk read command
     fpgaWriteCommandInProgress = TRUE;
     fpgaBulkWriteAndReadInProgress = TRUE;
@@ -574,7 +591,7 @@
     FPGA_STATE_T result = FPGA_STATE_WRITE_ALL_ACTUATORS;
 
     // check bulk write command success
-    if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[0] != FPGA_WRITE_CMD_ACK ) )
+    if ( ( FALSE == fpgaWriteCommandResponseReceived ) || ( fpgaWriteResponseBuffer[ 0 ] != FPGA_WRITE_CMD_ACK ) )
     {
         fpgaCommRetryCount++;
     }
@@ -583,19 +600,18 @@
     if ( TRUE == fpgaReadCommandResponseReceived )
     {
         // did FPGA Ack the read command?
-        if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK )
+        if ( fpgaReadResponseBuffer[ 0 ] == FPGA_READ_CMD_ACK )
         {
             U32 rspSize = FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T);
             U32 crcPos = rspSize;
-            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[crcPos+1], fpgaReadResponseBuffer[crcPos] );
+            U16 crc = MAKE_WORD_OF_BYTES( fpgaReadResponseBuffer[ crcPos ], fpgaReadResponseBuffer[ crcPos + 1 ] );
 
             // does the FPGA response CRC check out?
             if ( crc == crc16( fpgaReadResponseBuffer, rspSize ) )
-//            if ( 1 ) // TODO - remove when FPGA CRCs are implemented
             {
                 fpgaCommRetryCount = 0;
                 // capture the read values
-                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[1], sizeof(FPGA_SENSORS_T) );
+                memcpy( &fpgaSensorReadings, &fpgaReadResponseBuffer[ FPGA_READ_RSP_HDR_LEN ], sizeof( FPGA_SENSORS_T ) );
                 result = FPGA_STATE_WRITE_ALL_ACTUATORS;
             }
             else // bad CRC
@@ -630,13 +646,22 @@
  *************************************************************************/
 SELF_TEST_STATUS_T execFPGATest( void )
 {
-    SELF_TEST_STATUS_T result = SELF_TEST_STATUS_FAILED;
+    SELF_TEST_STATUS_T result;
 
     // check FPGA reported correct ID
+#ifndef RM46_EVAL_BOARD_TARGET
     if ( FPGA_EXPECTED_ID == fpgaHeader.fpgaId )
+#else
+    if ( 1 )
+#endif
     {
         result = SELF_TEST_STATUS_PASSED;
     }
+    else
+    {
+        result = SELF_TEST_STATUS_FAILED;
+        SET_ALARM_WITH_1_U32_DATA( ALARM_ID_FPGA_POST_TEST_FAILED, (U32)fpgaHeader.fpgaId )
+    }
 
     return result;
 }
@@ -660,7 +685,7 @@
     }
     else
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_CMD_TOO_MUCH_DATA, bytes2Transmit )
     }
 }
 
@@ -700,7 +725,7 @@
     }
     else
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_WRITE_RSP_TOO_MUCH_DATA, bytes2Receive )
     }
 }
 
@@ -740,7 +765,7 @@
     }
     else
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_CMD_TOO_MUCH_DATA, bytes2Transmit )
     }
 }
 
@@ -780,7 +805,7 @@
     }
     else
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_FPGA_READ_RSP_TOO_MUCH_DATA, bytes2Receive )
     }
 }
 
@@ -832,51 +857,147 @@
 }
 
 /*************************************************************************
- * @brief getFPGADiag
- * The getFPGADiag function gets the version read from the diagnostic register \n
+ * @brief getFPGAStatus
+ * The getFPGAStatus function gets the version read from the diagnostic register \n
  * of the FPGA.
  * @details
  * Inputs : fpgaHeader
  * Outputs : none
  * @param none
- * @return fpgaDiag
+ * @return fpgaHeader.fpgaStatus
  *************************************************************************/
-U08 getFPGADiag( void )
+U16 getFPGAStatus( void )
 {
-    return fpgaHeader.fpgaDiag;
+    return fpgaHeader.fpgaStatus;
 }
 
 /*************************************************************************
- * @brief getFPGAStatus
- * The getFPGAStatus function gets the version read from the diagnostic register \n
- * of the FPGA.
+ * @brief getFPGADiag
+ * The getFPGADiag function sets the diagnostic register of the FPGA.
  * @details
  * Inputs : fpgaHeader
  * Outputs : none
+ * @param ctrl : value to write to diagnostic register
+ * @return none
+ *************************************************************************/
+void setFPGAControl( U16 ctrl )
+{
+    fpgaHeader.fpgaControl = ctrl;
+}
+
+/*************************************************************************
+ * @brief getFPGABloodFlow
+ * The getFPGABloodFlow function gets the latest blood flow reading.
+ * @details
+ * Inputs : fpgaSensorReadings
+ * Outputs : none
  * @param none
- * @return fpgaDiag
+ * @return last blood flow reading
  *************************************************************************/
-U16 getFPGAStatus( void )
+F32 getFPGABloodFlow( void )
 {
-    return fpgaHeader.fpgaStatus;
+    return fpgaSensorReadings.bloodFlowLast;
 }
 
 /*************************************************************************
- * @brief getFPGADiag
- * The getFPGADiag function gets the version read from the diagnostic register \n
- * of the FPGA.
+ * @brief getFPGADialysateFlow
+ * The getFPGADialysateFlow function gets the latest dialysate flow reading.
  * @details
- * Inputs : fpgaHeader
+ * Inputs : fpgaSensorReadings
  * Outputs : none
  * @param none
- * @return fpgaDiag
+ * @return last dialysate flow reading
  *************************************************************************/
-void setFPGAControl( U16 ctrl )
+F32 getFPGADialysateFlow( void )
 {
-    fpgaHeader.fpgaControl = ctrl;
+    return fpgaSensorReadings.dialysateFlowLast;
 }
 
 /*************************************************************************
+ * @brief getFPGABloodPumpOcclusion
+ * The getFPGABloodPumpOcclusion function gets the latest blood occlusion reading.
+ * @details
+ * Inputs : fpgaSensorReadings
+ * Outputs : none
+ * @param none
+ * @return last blood occlusion reading
+ *************************************************************************/
+U16 getFPGABloodPumpOcclusion( void )
+{
+    return fpgaSensorReadings.bloodOcclusionData;
+}
+
+/*************************************************************************
+ * @brief getFPGADialInPumpOcclusion
+ * The getFPGADialInPumpOcclusion function gets the latest dialysate \n
+ * inlet occlusion reading.
+ * @details
+ * Inputs : fpgaSensorReadings
+ * Outputs : none
+ * @param none
+ * @return last dialysate inlet occlusion reading
+ *************************************************************************/
+U16 getFPGADialInPumpOcclusion( void )
+{
+#ifdef DEBUG_ENABLED
+//    {
+//        // TODO - temporary debug code - remove later
+//        char debugOccStr[ 60 ];
+//        S32  dat = fpgaSensorReadings.dialysateInOcclusionData;
+//        S32  rct = fpgaSensorReadings.dialysateInOcclusionReadCount;
+//        S32  ect = fpgaSensorReadings.dialysateInOcclusionErrorCount;
+//
+//        sprintf( debugOccStr, "Data %5d    Reads %5d   Errors %5d\n", dat, rct, ect );
+//        sendDebugData( (U08*)debugOccStr, strlen(debugOccStr) );
+//    }
+#endif
+    return fpgaSensorReadings.dialysateInOcclusionData;
+}
+
+/*************************************************************************
+ * @brief getFPGADialOutPumpOcclusion
+ * The getFPGADialOutPumpOcclusion function gets the latest dialysate \n
+ * outlet occlusion reading.
+ * @details
+ * Inputs : fpgaSensorReadings
+ * Outputs : none
+ * @param none
+ * @return last dialysate outlet occlusion reading
+ *************************************************************************/
+U16 getFPGADialOutPumpOcclusion( void )
+{
+    return fpgaSensorReadings.dialysateOutOcclusionData;
+}
+
+/*************************************************************************
+ * @brief getFPGAArterialPressure
+ * The getFPGAArterialPressure function gets the latest arterial pressure reading.
+ * @details
+ * Inputs : fpgaSensorReadings
+ * Outputs : none
+ * @param none
+ * @return last arterial pressure reading
+ *************************************************************************/
+U16 getFPGAArterialPressure( void )
+{
+    return fpgaSensorReadings.arterialPressureData;
+}
+
+/*************************************************************************
+ * @brief getFPGAVenousPressure
+ * The getFPGAVenousPressure function gets the venous arterial pressure reading.
+ * @details
+ * Inputs : fpgaSensorReadings
+ * Outputs : none
+ * @param none
+ * @return last venous pressure reading
+ *************************************************************************/
+U16 getFPGAVenousPressure( void )
+{
+    return 0;  // TODO - return reading when available
+}
+
+/*************************************************************************
  * @brief consumeUnexpectedData
  * The consumeUnexpectedData function checks to see if a byte is sitting in \n
  * the SCI2 received data register.
@@ -891,7 +1012,7 @@
     // clear any errors
     sciRxError( scilinREG );
     // if a byte is pending read, read it
-    if ( 0 != sciIsRxReady( scilinREG ) )
+    if ( sciIsRxReady( scilinREG ) != 0 )
     {
         sciReceiveByte( scilinREG );
     }
Index: firmware/App/Services/FPGA.h
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/FPGA.h	(.../FPGA.h)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/FPGA.h	(.../FPGA.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -34,5 +34,12 @@
 
 U16 getFPGAStatus( void );
 void setFPGAControl( U16 ctrl );
+F32 getFPGABloodFlow( void );
+F32 getFPGADialysateFlow( void );
+U16 getFPGAArterialPressure( void );
+U16 getFPGAVenousPressure( void );
+U16 getFPGABloodPumpOcclusion( void );
+U16 getFPGADialInPumpOcclusion( void );
+U16 getFPGADialOutPumpOcclusion( void );
 
 #endif
Index: firmware/App/Services/Interrupts.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/Interrupts.c	(.../Interrupts.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/Interrupts.c	(.../Interrupts.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -19,24 +19,50 @@
 #include "sci.h"
 #include "sys_dma.h"
 
+#include "Common.h"
+
+#include "AlarmMgmt.h"
 #include "Comm.h"
 #include "Interrupts.h"
 #include "FPGA.h"
 #include "SystemComm.h"
+#ifdef DEBUG_ENABLED
+    #include "SystemCommMessages.h"
+#endif
 
 // ********** private definitions **********
 
 
 // ********** private data **********
 
-static U32 frameErrorCnt = 0;
-static U32 overrunErrorCnt = 0;
+static U32 sci1FrameErrorCnt = 0;
+static U32 sci1OverrunErrorCnt = 0;
+static U32 sci2FrameErrorCnt = 0;
+static U32 sci2OverrunErrorCnt = 0;
 
+static U32 can1PassiveCnt = 0;
+static U32 can1WarningCnt = 0;
+static U32 can1BusOffCnt = 0;
+static U32 can1ParityCnt = 0;
 
 // ********** private function prototypes **********
 
 
 /*************************************************************************
+ * @brief phantomInterrupt
+ * The phantomInterrupt function handles phantom interrupts.
+ * @details
+ * Inputs : none
+ * Outputs : phantom interrupt handled.
+ * @param none
+ * @return none
+ *************************************************************************/
+void phantomInterrupt(void)
+{
+    // TODO - what to do with phantom interrupts?
+}
+
+/*************************************************************************
  * @brief canMessageNotification
  * The canMessageNotification function handles CAN message notifications.
  * @details
@@ -48,10 +74,77 @@
  *************************************************************************/
 void canMessageNotification(canBASE_t *node, uint32 messageBox)
 {
-    handleCANMsgInterrupt( (CAN_MESSAGE_BOX_T)messageBox );
+    if ( node == canREG1 )
+    {
+        handleCANMsgInterrupt( (CAN_MESSAGE_BOX_T)messageBox );
+    }
 }
 
 /*************************************************************************
+ * @brief canErrorNotification
+ * The canErrorNotification function handles CAN error notifications.
+ * @details
+ * Inputs : none
+ * Outputs : CAN error notification handled.
+ * @param node : which CAN controller
+ * @param notification : canLEVEL_PASSIVE    (0x20) : When RX- or TX error counter are between 32 and 63 \n
+ *                       canLEVEL_WARNING    (0x40) : When RX- or TX error counter are between 64 and 127 \n
+ *                       canLEVEL_BUS_OFF    (0x80) : When RX- or TX error counter are between 128 and 255 \n
+ *                       canLEVEL_PARITY_ERR (0x100): When parity error detected on CAN RAM read access
+ * @return none
+ *************************************************************************/
+void canErrorNotification(canBASE_t *node, uint32 notification)
+{
+#ifdef DEBUG_ENABLED
+    // TODO - temporary debug code - remove later
+    char debugStr[ 256 ];
+#endif
+    if ( node == canREG1 )
+    {
+        if ( notification & canLEVEL_PARITY_ERR )
+        {
+            can1ParityCnt++;
+#ifdef DEBUG_ENABLED
+        // TODO - temporary debug code - remove later
+        sprintf( debugStr, "CAN parity error:%5d \n", can1ParityCnt );
+        sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
+        else if ( notification & canLEVEL_BUS_OFF )
+        {
+            can1BusOffCnt++;
+#ifdef DEBUG_ENABLED
+        // TODO - temporary debug code - remove later
+        sprintf( debugStr, "CAN bus off error:%5d \n", can1BusOffCnt );
+        sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
+        else if ( notification & canLEVEL_WARNING )
+        {
+            can1WarningCnt++;
+#ifdef DEBUG_ENABLED
+        // TODO - temporary debug code - remove later
+        sprintf( debugStr, "CAN bus warning:%5d \n", can1WarningCnt );
+        sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
+        else if ( notification & canLEVEL_PASSIVE )
+        {
+            can1PassiveCnt++;
+#ifdef DEBUG_ENABLED
+        // TODO - temporary debug code - remove later
+        sprintf( debugStr, "CAN passive warning:%5d \n", can1PassiveCnt );
+        sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
+        else
+        {
+            // ignore - other bits undefined
+        }
+    }
+}
+
+/*************************************************************************
  * @brief sciNotification
  * The sciNotification function handles UART communication error interrupts. \n
  * Frame and Over-run errors are handled.
@@ -64,16 +157,64 @@
  *************************************************************************/
 void sciNotification(sciBASE_t *sci, uint32 flags)
 {
-    if ( ( flags & SCI_FE_INT ) != 0 )
+#ifdef DEBUG_ENABLED
+    // TODO - temporary debug code - remove later
+    char debugStr[ 256 ];
+#endif
+    if ( sci == sciREG )
     {
-        frameErrorCnt++;
-        // TODO - clear and try to do something to recover (+ max retries = comm fault)
+        if ( ( flags & SCI_FE_INT ) != 0 )
+        {
+            sci1FrameErrorCnt++;
+            clearSCI1CommErrors();
+            // TODO - try to do something to recover (+ max retries = comm fault)
+#ifdef DEBUG_ENABLED
+            // TODO - temporary debug code - remove later
+            sprintf( debugStr, "Debug UART frame error:%5d \n", sci1FrameErrorCnt );
+            sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
+        if ( ( flags & SCI_OE_INT ) != 0 )
+        {
+            sci1OverrunErrorCnt++;
+            clearSCI1CommErrors();
+            // TODO - try to do something to recover (+ max retries = comm fault)
+#ifdef DEBUG_ENABLED
+            // TODO - temporary debug code - remove later
+            sprintf( debugStr, "Debug UART overrun error:%5d \n", sci1OverrunErrorCnt );
+            sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
     }
-    if ( ( flags & SCI_OE_INT ) != 0 )
+    else if ( sci == scilinREG )
     {
-        overrunErrorCnt++;
-        // TODO - clear and try to do something to recover (+ max retries = comm fault)
+        if ( ( flags & SCI_FE_INT ) != 0 )
+        {
+            sci2FrameErrorCnt++;
+            clearSCI2CommErrors();
+            // TODO - try to do something to recover (+ max retries = comm fault)
+#ifdef DEBUG_ENABLED
+            // TODO - temporary debug code - remove later
+            sprintf( debugStr, "FPGA UART frame error:%5d \n", sci2FrameErrorCnt );
+            sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
+        if ( ( flags & SCI_OE_INT ) != 0 )
+        {
+            sci2OverrunErrorCnt++;
+            clearSCI2CommErrors();
+            // TODO - try to do something to recover (+ max retries = comm fault)
+#ifdef DEBUG_ENABLED
+            // TODO - temporary debug code - remove later
+            sprintf( debugStr, "FPGA UART overrun error:%5d \n", sci2OverrunErrorCnt );
+            sendDebugData( (U08*)debugStr, strlen(debugStr) );
+#endif
+        }
     }
+    else
+    {
+        // TODO - ignore? - should not be any other SCI peripherals
+    }
 }
 
 /*************************************************************************
Index: firmware/App/Services/MsgQueues.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/MsgQueues.c	(.../MsgQueues.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/MsgQueues.c	(.../MsgQueues.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -26,10 +26,10 @@
 
 // ********** private data **********
 
-static U32 msgQueueCounts[NUM_OF_MSG_QUEUES];
-static U32 msgQueueStarts[NUM_OF_MSG_QUEUES];
-static U32 msgQueueNexts[NUM_OF_MSG_QUEUES];
-static MESSAGE_WRAPPER_T msgQueues[NUM_OF_MSG_QUEUES][MAX_MSG_QUEUE_SIZE];
+static U32 msgQueueCounts[ NUM_OF_MSG_QUEUES ];
+static U32 msgQueueStarts[ NUM_OF_MSG_QUEUES ];
+static U32 msgQueueNexts[ NUM_OF_MSG_QUEUES ];
+static MESSAGE_WRAPPER_T msgQueues[ NUM_OF_MSG_QUEUES ][ MAX_MSG_QUEUE_SIZE ];
 
 // ********** private function prototypes **********
 
@@ -49,12 +49,12 @@
     // reset message queues
     for ( q = 0; q < NUM_OF_MSG_QUEUES; q++ )
     {
-        msgQueueCounts[q] = 0;
-        msgQueueStarts[q] = 0;
-        msgQueueNexts[q] = 0;
+        msgQueueCounts[ q ] = 0;
+        msgQueueStarts[ q ] = 0;
+        msgQueueNexts[ q ] = 0;
         for ( m = 0; m < MAX_MSG_QUEUE_SIZE; m++ )
         {
-            blankMessageInWrapper( &msgQueues[q][m] );
+            blankMessageInWrapper( &msgQueues[ q ][ m ] );
         }
     }
 }
@@ -81,20 +81,20 @@
         {
             result = TRUE;
             // add message to queue
-            msgQueues[queue][msgQueueNexts[queue]] = *msg;
+            msgQueues[ queue ][ msgQueueNexts[ queue ] ] = *msg;
             // increment next index to add to
-            msgQueueNexts[queue] = INC_WRAP(msgQueueNexts[queue],0,MAX_MSG_QUEUE_SIZE-1);
+            msgQueueNexts[ queue ] = INC_WRAP( msgQueueNexts[ queue ], 0, MAX_MSG_QUEUE_SIZE - 1 );
             // increment queue count
-            msgQueueCounts[queue]++;
+            msgQueueCounts[ queue ]++;
         }
         else // msg queue is full
         {
-            // TODO - s/w fault?
+            SET_ALARM_WITH_1_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_ADD_QUEUE_FULL )
         }
     }
     else // invalid message queue
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_ADD_INVALID_QUEUE, queue )
     }
 
     return result;
@@ -123,11 +123,11 @@
         {
             result = TRUE;
             // get message from queue
-            *msg = msgQueues[queue][msgQueueStarts[queue]];
+            *msg = msgQueues[ queue ][ msgQueueStarts[ queue ] ];
             // increment queue next index to get from
-            msgQueueStarts[queue] = INC_WRAP(msgQueueStarts[queue],0,MAX_MSG_QUEUE_SIZE-1);
+            msgQueueStarts[ queue ] = INC_WRAP( msgQueueStarts[ queue ], 0, MAX_MSG_QUEUE_SIZE - 1 );
             // decrement queue count
-            msgQueueCounts[queue]--;
+            msgQueueCounts[ queue ]--;
         }
         else // message queue is empty
         {
@@ -136,7 +136,7 @@
     }
     else // invalid message queue
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_GET_INVALID_QUEUE, queue )
     }
 
     return result;
@@ -158,14 +158,14 @@
     // verify given message queue
     if ( queue < NUM_OF_MSG_QUEUES )
     {
-        if ( msgQueueCounts[queue] == 0 )
+        if ( msgQueueCounts[ queue ] == 0 )
         {
             result = TRUE;
         }
     }
     else // invalid message queue
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_IS_EMPTY_INVALID_QUEUE, queue )
     }
 
     return result;
@@ -187,14 +187,14 @@
     // verify given message queue
     if ( queue < NUM_OF_MSG_QUEUES )
     {
-        if ( msgQueueCounts[queue] < MAX_MSG_QUEUE_SIZE )
+        if ( msgQueueCounts[ queue ] < MAX_MSG_QUEUE_SIZE )
         {
             result = FALSE;
         }
     }
     else // invalid message queue
     {
-        // TODO - s/w fault
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_MSG_QUEUES_IS_FULL_INVALID_QUEUE, queue )
     }
 
     return result;
@@ -220,9 +220,6 @@
     {
         *msgContent++ = 0x0;
     }
-
-    // set msg ID out of bounds in case blank message goes somewhere
-    message->hdr.msgID = 0xFFFF;
 }
 
 /*************************************************************************
Index: firmware/App/Services/MsgQueues.h
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/MsgQueues.h	(.../MsgQueues.h)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/MsgQueues.h	(.../MsgQueues.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -21,7 +21,7 @@
 
 // ********** public definitions **********
 
-#define MAX_MSG_CARGO_SIZE          100         // bytes
+#define MAX_MSG_PAYLOAD_SIZE          100         // bytes
 
 typedef enum Msg_Queues
 {
@@ -32,14 +32,17 @@
 #pragma pack(push,1)
 typedef struct
 {
+#ifndef ACK_NOT_IMPLEMENTED
+    S16 seqNo;                                  // sequence # (and ACK required bit) of message
+#endif
     U16 msgID;                                  // ID of message
-    U08 payloadLen;                               // length of cargo in bytes
+    U08 payloadLen;                             // length of payload in bytes
 } MESSAGE_HEADER_T;
 
 typedef struct
 {
     MESSAGE_HEADER_T hdr;                       // message header
-    U08              payload[MAX_MSG_CARGO_SIZE]; // message cargo
+    U08              payload[ MAX_MSG_PAYLOAD_SIZE ]; // message payload
 } MESSAGE_T;
 
 typedef struct
Index: firmware/App/Services/PIControllers.c
===================================================================
diff -u
--- firmware/App/Services/PIControllers.c	(revision 0)
+++ firmware/App/Services/PIControllers.c	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -0,0 +1,267 @@
+/**********************************************************************//**
+ *
+ *  Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+ *
+ *  THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+ *  WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+ *
+ *  @file PIControllers.c
+ *
+ *  @date 18-Dec-2019
+ *  @author L. Baloa
+ *
+ *  @brief PIControllers source file.
+ *
+ **************************************************************************/
+
+#ifndef _VECTORCAST_
+    #include "math.h"
+#endif
+
+#include "SystemCommMessages.h"
+#include "PIControllers.h"
+
+/**
+ *  @addtogroup PIControllers
+ *  @{
+ */
+
+// ********** private definitions **********
+
+/// minimum integral coefficient - cannot be zero.
+#define MIN_KI                      NEARLY_ZERO
+
+/// record for PI controller.
+typedef struct {
+    // -- PI's parameters --
+    F32 Kp;                         ///< Proportional Value.
+    F32 Ki;                         ///< Integral Value.
+    F32 uMax;                       ///< Maximum control signal.
+    F32 uMin;                       ///< Minimum control signal.
+    // -- PI's signals --
+    F32 referenceSignal;            ///< reference signal.
+    F32 measuredSignal;             ///< measured signal.
+    F32 errorSignal;                ///< reference - measured signal.
+    F32 errorSumBeforeWindUp;       ///< error signal before windup correction.
+    F32 errorSum;                   ///< error integral after windup correction.
+    F32 controlSignal;              ///< actual control signal.
+} PI_CONTROLLER_T;
+
+#define SET_CONTROLLER( c, id )     ((c) = &piControllers[id])          ///< macro to set a local controller pointer to a given piController.
+
+// ********** private data **********
+
+/// PI Controllers -- initial configurations.
+static PI_CONTROLLER_T piControllers[ NUM_OF_PI_CONTROLLERS_IDS ] =
+{   // Kp   Ki  uMax  uMin  ref meas  err  esw esum ctrl
+    { 0.0, 0.0,  1.0,  0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 },  // PI_CONTROLLER_ID_ULTRAFILTRATION
+    { 0.0, 0.0, 0.90, 0.10, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 },  // PI_CONTROLLER_ID_BLOOD_FLOW
+    { 0.0, 0.0, 0.90, 0.10, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 }   // PI_CONTROLLER_ID_DIALYSATE_FLOW
+};
+
+/**@}*/
+
+/*********************************************************************//**
+ * @brief
+ * Initialize controller before operation. Make sure to call it before
+ * first call to runController function.
+ *
+ * @param controllerID - ID filter number
+ * @param initialControlSignal - Value of the output on the first iteration
+ * @param kP - Coefficient for proportional.
+ * @param kI - Coefficient for integral.
+ * @param controlMin - Minimum control output.
+ * @param controlMax - Maximum control output.
+ *
+ * @return none
+ *************************************************************************/
+void initializePIController( PI_CONTROLLER_ID_T controllerID, F32 initialControlSignal,
+                             F32 kP, F32 kI, F32 controlMin, F32 controlMax )
+{
+    PI_CONTROLLER_T *controller;
+
+    if ( controllerID < NUM_OF_PI_CONTROLLERS_IDS )
+    {
+        SET_CONTROLLER( controller, controllerID );
+
+        controller->Kp = kP;
+        if ( fabs( kI ) > MIN_KI )      // ensure kI is not zero
+        {
+            controller->Ki = kI;
+        }
+        else
+        {
+            controller->Ki = ( kI < 0.0 ? MIN_KI * -1.0 : MIN_KI );
+        }
+        controller->uMin = controlMin;
+        controller->uMax = controlMax;
+        resetPIController( controllerID, initialControlSignal );
+    }
+    else
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_PI_CTRL_INVALID_CONTROLLER, (U32)controllerID )
+    }
+}
+
+/*********************************************************************//**
+ * @brief
+ * Reset controller before new set point. Make sure to call it before first
+ * call to runController function.
+ *
+ * @param controllerID - ID filter number
+ * @param initialControlSignal - Value of the output on the first iteration
+ *
+ * @return none
+ *************************************************************************/
+void resetPIController( PI_CONTROLLER_ID_T controllerID, F32 initialControlSignal )
+{
+    PI_CONTROLLER_T *controller;
+
+    if ( controllerID < NUM_OF_PI_CONTROLLERS_IDS )
+    {
+        SET_CONTROLLER( controller, controllerID );
+        controller->controlSignal = RANGE( initialControlSignal, controller->uMin, controller->uMax );
+        controller->referenceSignal = 0.0;
+        controller->errorSignal = 0.0;
+        controller->errorSum = controller->controlSignal / controller->Ki;
+        controller->errorSumBeforeWindUp = controller->errorSum;
+        controller->measuredSignal = 0.0;
+    }
+    else
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_PI_CTRL_INVALID_CONTROLLER, (U32)controllerID )
+    }
+}
+
+/*********************************************************************//**
+ * @brief
+ * Call this function whenever a new measured signal sampled is acquired.
+ *
+ * @param controllerID - ID filter number
+ * @param referenceSignal - reference signal value
+ * @param measuredSignal - latest measured sample
+ *
+ * @return value of the control signal
+ *************************************************************************/
+F32 runPIController(PI_CONTROLLER_ID_T controllerID, F32 referenceSignal, F32 measuredSignal)
+{
+    PI_CONTROLLER_T *controller;
+    F32 result = 0.0;
+
+    if ( controllerID < NUM_OF_PI_CONTROLLERS_IDS )
+    {
+        F32 controlSignalBeforeWindup;
+        F32 windupError;
+
+        SET_CONTROLLER( controller, controllerID );
+
+        controller->referenceSignal = referenceSignal;
+        controller->measuredSignal = measuredSignal;
+        // calculate error signal
+        controller->errorSignal = fabs( referenceSignal ) - ( referenceSignal < 0.0 ? ( measuredSignal * -1.0 ) : measuredSignal );
+        controller->errorSum += controller->errorSignal;
+        // anti-windup
+        controller->errorSumBeforeWindUp = controller->errorSum;
+        // calculate control signal
+        controlSignalBeforeWindup = ( controller->Kp * controller->errorSignal ) + ( controller->Ki * controller->errorSum );
+        controller->controlSignal = RANGE( controlSignalBeforeWindup, controller->uMin, controller->uMax );
+        // handle anti-windup for i term
+        windupError = controlSignalBeforeWindup - controller->controlSignal;
+        if ( fabs( windupError ) > NEARLY_ZERO )
+        {
+            controller->errorSum -= ( windupError / controller->Ki );
+        }
+        result = controller->controlSignal;
+//#ifdef DEBUG_ENABLED
+//    {
+//        // TODO - temporary debug code - remove later
+//        char debugFlowStr[ 100 ];
+//        S32  nums = (S32)(measuredSignal);
+//        S32  decs = (S32)(fabs(measuredSignal-(S32)(measuredSignal))*100.0);
+//        S32  nume = (S32)controller->errorSignal;
+//        S32  dece = (S32)(fabs(controller->errorSignal-(S32)controller->errorSignal)*100.0);
+//        S32  numes = (S32)controller->errorSum;
+//        S32  deces = (S32)((controller->errorSum-(S32)(controller->errorSum))*100.0);
+//        S32  nump = (S32)controller->controlSignal;
+//        S32  decp = (S32)((controller->controlSignal-(S32)controller->controlSignal)*10000.0);
+//
+//        sprintf( debugFlowStr, "%6d.%02d  %6d.%02d  %10d.%02d  %3d.%04d\n", nums, decs, nume, dece, numes, deces, nump, decp );
+//        sendDebugData( (U08*)debugFlowStr, strlen(debugFlowStr) );
+//    }
+//#endif
+    }
+    else
+    {
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_PI_CTRL_INVALID_CONTROLLER, (U32)controllerID )
+    }
+
+    return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * Returns the latest requested signal sample.
+ *
+ * @param controllerID - ID filter number
+ * @param signalID -  signal sample ID request
+ *
+ * @return latest sample requested
+ *************************************************************************/
+F32 getPIControllerSignals( PI_CONTROLLER_ID_T controllerID, PI_CONTROLLER_SIGNALS_ID signalID )
+{
+    PI_CONTROLLER_T *controller;
+    F32 output = 0.0;
+
+    if ( controllerID < NUM_OF_PI_CONTROLLERS_IDS )
+    {
+        SET_CONTROLLER( controller, controllerID );
+
+        switch( signalID )
+        {
+            case CONTROLLER_SIGNAL_REFERENCE:
+                output = controller->referenceSignal;
+                break;
+
+            case CONTROLLER_SIGNAL_MEASURED:
+                output = controller->measuredSignal;
+                break;
+
+            case CONTROLLER_SIGNAL_ERROR:
+                output = controller->errorSignal;
+                break;
+
+            case CONTROLLER_SIGNAL_ERROR_SUM:
+                output = controller->errorSumBeforeWindUp;
+                break;
+
+            case CONTROLLER_SIGNAL_ERROR_SUM_AFTER_WINDUP:
+                output = controller->errorSum;
+                break;
+
+            case CONTROLLER_SIGNAL_PROPORTIONAL_OUTPUT:
+                output = controller->Kp * controller->errorSignal;
+                break;
+
+            case CONTROLLER_SIGNAL_INTEGRAL_OUTPUT:
+                output = controller->Ki * controller->errorSum;
+                break;
+
+            case CONTROLLER_SIGNAL_CONTROL:
+                output = controller->controlSignal;
+                break;
+
+            default:
+                SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_PI_CTRL_INVALID_SIGNAL, (U32)signalID )
+                break;
+        } // end of switch
+    }
+    else
+    {   // invalid controller given
+        SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_PI_CTRL_INVALID_CONTROLLER, (U32)controllerID )
+    }
+
+    return output;
+}
+
+/**@}*/
+
Index: firmware/App/Services/PIControllers.h
===================================================================
diff -u
--- firmware/App/Services/PIControllers.h	(revision 0)
+++ firmware/App/Services/PIControllers.h	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -0,0 +1,66 @@
+/**********************************************************************//**
+ *
+ *  Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved.
+ *
+ *  THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN
+ *  WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER.
+ *
+ *  @file PIControllers.h
+ *
+ *  @date 12-Dec-2019
+ *  @author L. Baloa
+ *
+ *  @brief Header file for the PI controllers service (PIControllers.c).
+ *
+ **************************************************************************/
+
+#ifndef __PICONTROLLERS_H__
+#define __PICONTROLLERS_H__
+
+#include "Common.h"
+
+/**
+ *  @defgroup PIControllers PIControllers
+ *  @brief PIControllers service module.  Provides PI controllers for various actuators..
+ *
+ *  @addtogroup PIControllers
+ *  @{
+ */
+
+// ********** public definitions **********
+
+/// Enumeration of PI controllers
+typedef enum ControllerList
+{
+    PI_CONTROLLER_ID_ULTRAFILTRATION = 0,           ///< Load cell controller for dialysate outlet pump.
+    PI_CONTROLLER_ID_BLOOD_FLOW,                    ///< Flow controller for blood pump.
+    PI_CONTROLLER_ID_DIALYSATE_FLOW,                ///< Flow controller for dialysate inlet pump.
+    NUM_OF_PI_CONTROLLERS_IDS                       ///< Number of PI controllers.
+} PI_CONTROLLER_ID_T;
+
+/// Enumeration of PI controller signals
+typedef enum ControllerSignals
+{
+    CONTROLLER_SIGNAL_REFERENCE = 0,                ///< Reference value.
+    CONTROLLER_SIGNAL_MEASURED,                     ///< Measured value.
+    CONTROLLER_SIGNAL_ERROR,                        ///< Error value.
+    CONTROLLER_SIGNAL_ERROR_SUM,                    ///< Error sum before anti-windup.
+    CONTROLLER_SIGNAL_ERROR_SUM_AFTER_WINDUP,       ///< Error sum after anti-windup.
+    CONTROLLER_SIGNAL_PROPORTIONAL_OUTPUT,          ///< P portion of controller output signal.
+    CONTROLLER_SIGNAL_INTEGRAL_OUTPUT,              ///< I portion of controller output signal.
+    CONTROLLER_SIGNAL_CONTROL,                      ///< Controller output signal.
+    NUM_OF_CONTROLLER_SIGNAL                        ///< Number of PI controller signals.
+} PI_CONTROLLER_SIGNALS_ID;
+
+// ********** public function prototypes **********
+
+void initializePIController( PI_CONTROLLER_ID_T controllerID, F32 initialControlSignal,
+                             F32 kP, F32 kI, F32 controlMin, F32 controlMax );
+void resetPIController( PI_CONTROLLER_ID_T controllerID, F32 initialControlSignal );
+F32 runPIController( PI_CONTROLLER_ID_T controllerID, F32 referenceSignal, F32 measuredSignal );
+F32 getPIControllerSignals( PI_CONTROLLER_ID_T controllerID, PI_CONTROLLER_SIGNALS_ID signalID );
+
+/**@}*/
+
+#endif
+
Index: firmware/App/Services/SystemComm.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/SystemComm.c	(.../SystemComm.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/SystemComm.c	(.../SystemComm.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -25,9 +25,9 @@
 #include "SystemComm.h"
 #include "Comm.h"
 #include "Interrupts.h"
-#include "MsgQueues.h"
-#include "SystemCommMessages.h"
+#include "Timers.h"
 #include "Utilities.h"
+#include "SystemCommMessages.h"
 
 #ifdef RM46_EVAL_BOARD_TARGET
     #include "CPLD.h"
@@ -36,53 +36,99 @@
 // ********** private definitions **********
 
 #define NUM_OF_CAN_OUT_BUFFERS          5       // # of CAN buffers for transmit
-#define NUM_OF_CAN_IN_BUFFERS           3       // # of CAN buffers for receiving
-#define NUM_OF_MSG_IN_BUFFERS           4       // # of Msg buffers for receiving
+#define NUM_OF_CAN_IN_BUFFERS           7       // # of CAN buffers for receiving
+#define NUM_OF_MSG_IN_BUFFERS           8       // # of Msg buffers for receiving - 1 is UART
 
 #define SCI1_RECEIVE_DMA_REQUEST        30
 #define SCI1_TRANSMIT_DMA_REQUEST       31
 
+#define HD_COMM_TIMEOUT_IN_MS           2000
+
+#define MAX_COMM_CRC_FAILURES           5
+#define MAX_COMM_CRC_FAILURE_WINDOW_MS  (10 * SEC_PER_MIN * MS_PER_SECOND)
+
+#define MSG_NOT_ACKED_TIMEOUT_MS    ( MS_PER_SECOND * 1 )
+#define MSG_NOT_ACKED_MAX_RETRIES   3
+#define PENDING_ACK_LIST_SIZE       25
+
+#pragma pack(push,1)
+
+typedef struct
+{
+    BOOL used;
+    U16  seqNo;
+    U16  retries;
+    U32  timeStamp;
+    COMM_BUFFER_T channel;
+    U32  msgSize;
+    U08  msg[ MAX_ACK_MSG_SIZE ];
+} PENDING_ACK_RECORD_T;
+
+#pragma pack(pop)
+
 // ********** private data **********
 
 const COMM_BUFFER_T CAN_OUT_BUFFERS[ NUM_OF_CAN_OUT_BUFFERS ] =
 {
-     COMM_BUFFER_OUT_CAN_DG_ALARM,
-     COMM_BUFFER_OUT_CAN_DG_2_HD,
-     COMM_BUFFER_OUT_CAN_DG_BROADCAST,
-     COMM_BUFFER_OUT_CAN_DG_2_PC,
-     COMM_BUFFER_OUT_UART_PC
+    COMM_BUFFER_OUT_CAN_DG_ALARM,
+    COMM_BUFFER_OUT_CAN_DG_2_HD,
+    COMM_BUFFER_OUT_CAN_DG_BROADCAST,
+    COMM_BUFFER_OUT_CAN_PC
 };
 
 const COMM_BUFFER_T MSG_IN_BUFFERS[ NUM_OF_MSG_IN_BUFFERS ] =
 {
-     COMM_BUFFER_IN_CAN_HD_2_DG,
-     COMM_BUFFER_IN_CAN_PC_2_DG,
-     COMM_BUFFER_IN_UART_PC
+    COMM_BUFFER_IN_CAN_HD_ALARM,
+    COMM_BUFFER_IN_CAN_UI_ALARM,
+    COMM_BUFFER_IN_CAN_HD_2_DG,
+    COMM_BUFFER_IN_CAN_HD_BROADCAST,
+    COMM_BUFFER_IN_CAN_UI_BROADCAST,
+    COMM_BUFFER_IN_CAN_PC,
+    COMM_BUFFER_IN_UART_PC
 };
 
-static U08 pcXmitPacket[ PC_MESSAGE_PACKET_SIZE ] = { 0, 0, 0, 0, 0, 0, 0, 0 };// = { 1,2,3,4,5,6,7,8};
+static U08 pcXmitPacket[ PC_MESSAGE_PACKET_SIZE ] = { 0, 0, 0, 0, 0, 0, 0, 0 };
 static U08 pcRecvPacket[ PC_MESSAGE_PACKET_SIZE ] = { 0, 0, 0, 0, 0, 0, 0, 0 };
 
+#ifndef ACK_NOT_IMPLEMENTED
+static PENDING_ACK_RECORD_T pendingAckList[ PENDING_ACK_LIST_SIZE ];    // list of outgoing messages that are awaiting an ACK
+#endif
+
 // DMA control records
-static g_dmaCTRL pcDMAXmitControlRecord;
-static g_dmaCTRL pcDMARecvControlRecord;
+static g_dmaCTRL pcDMAXmitControlRecord;                // DMA transmit control record (UART-debug)
+static g_dmaCTRL pcDMARecvControlRecord;                // DMA receive control record (UART-debug)
 
+static volatile BOOL hdIsCommunicating = FALSE;         // has HD sent a message since last check
+static volatile U32 timeOfLastHDCheckIn = 0;            // last time we received an HD broadcast
+
+static U32 badCRCTimeStamps[ MAX_COMM_CRC_FAILURES ];   // time of last five bad message CRCs (wrapping list)
+static U32 badCRCListIdx = 0;                           // where next bad message CRC time stamp will go in list
+static U32 badCRCListCount = 0;                         // # of bad CRCs in the list
+
 // ********** private function prototypes **********
 
 static void initUARTAndDMA( void );
 static BOOL isCANBoxForXmit( CAN_MESSAGE_BOX_T srcCANBox );
 static BOOL isCANBoxForRecv( CAN_MESSAGE_BOX_T srcCANBox );
 
 static COMM_BUFFER_T findNextHighestPriorityCANPacketToTransmit( void );
-static void transmitNextCANPacket( void );
-static void transmitNextUARTPacket( void );
+static U32 transmitNextCANPacket( void );
+static U32 transmitNextUARTPacket( void );
 
 static void processIncomingData( void );
-static U32 parseMessageFromBuffer( U08 *data, U32 len );
+static S32 parseMessageFromBuffer( U08 *data, U32 len );
 static void consumeBufferPaddingBeforeSync( COMM_BUFFER_T buffer );
 static void processReceivedMessages( void );
 static void processReceivedMessage( MESSAGE_T *message );
 
+static void checkForCommTimeouts( void );
+static void checkTooManyBadMsgCRCs( void );
+
+#ifndef ACK_NOT_IMPLEMENTED
+static BOOL matchACKtoPendingACKList( S16 seqNo );
+static void checkPendingACKList( void );
+#endif
+
 /*************************************************************************
  * @brief initSystemComm
  * The initSystemComm function initializes the SystemComm module.
@@ -94,16 +140,46 @@
  *************************************************************************/
 void initSystemComm( void )
 {
+    U32 i;
+
     // initialize UART and DMA for PC communication
     initUARTAndDMA();
 
-    // TODO - remove this test code that sends a packet
-//    dmaSetCtrlPacket( DMA_CH3, pcDMAXmitControlRecord );
-//    dmaSetChEnable( DMA_CH3, DMA_HW );
-//    setSCI1DMATransmitInterrupt();
+    // initialize bad message CRC list
+    for ( i = 0; i < MAX_COMM_CRC_FAILURES; i++ )
+    {
+        badCRCTimeStamps[ i ] = 0;
+    }
+
+#ifndef ACK_NOT_IMPLEMENTED
+    // initialize pending ACK list
+    for ( i = 0; i < PENDING_ACK_LIST_SIZE; i++ )
+    {
+        pendingAckList[ i ].used = FALSE;
+    }
+#endif
 }
 
 /*************************************************************************
+ * @brief
+ * The isHDCommunicating function determines whether the HD is communicating \n
+ * with the DG.
+ * @details
+ * Inputs : hdIsCommunicating
+ * Outputs : none
+ * @param none
+ * @return TRUE if HD has broadcast since last call, FALSE if not
+ *************************************************************************/
+BOOL isHDCommunicating( void )
+{
+    BOOL result = hdIsCommunicating;
+
+    hdIsCommunicating = FALSE;
+
+    return result;
+}
+
+/*************************************************************************
  * @brief execSystemCommRx
  * The execSystemCommRx function manages received data from other sub-systems.
  * @details
@@ -119,6 +195,14 @@
 
     // process received messages in the queue
     processReceivedMessages();
+
+    // check for sub-system comm timeouts
+    checkForCommTimeouts();
+
+#ifndef ACK_NOT_IMPLEMENTED
+    // check ACK list for messages that need to be re-sent because they haven't been ACK'd
+    checkPendingACKList();
+#endif
 }
 
 /*************************************************************************
@@ -163,18 +247,35 @@
     // message interrupt is for a transmit message box?
     if ( TRUE == isCANBoxForXmit( srcCANBox ) )
     {
-        transmitNextCANPacket();
+        U32 bytesXmitted = transmitNextCANPacket();
+
+        if ( 0 == bytesXmitted )
+        {
+            signalCANXmitsCompleted();
+        }
     }
     else if ( TRUE == isCANBoxForRecv( srcCANBox ) )
     {
-        U08 data[CAN_MESSAGE_PAYLOAD_SIZE];
+        U08 data[ CAN_MESSAGE_PAYLOAD_SIZE ];
 
         // get CAN packet received on given CAN message box
         if ( FALSE != canIsRxMessageArrived( canREG1, srcCANBox ) )
         {
-            canGetData( canREG1, srcCANBox, data );
-            // add CAN packet to appropriate comm buffer based on the message box it came in on (s/b same #)
-            addToCommBuffer( srcCANBox, data, CAN_MESSAGE_PAYLOAD_SIZE );
+            U32 result = canGetData( canREG1, srcCANBox, data );
+
+            // if packet retrieved, add to buffer
+            if ( result != 0 )
+            {
+//#ifdef DEBUG_ENABLED
+//                if ( srcCANBox == COMM_BUFFER_IN_CAN_PC )
+//                {
+//                    memcpy( &dbgRcvFromDialin[dbgRcvFromDialinIdx], data, CAN_MESSAGE_PAYLOAD_SIZE);
+//                    dbgRcvFromDialinIdx += CAN_MESSAGE_PAYLOAD_SIZE;
+//                }
+//#endif
+                // add CAN packet to appropriate comm buffer based on the message box it came in on (s/b same #)
+                addToCommBuffer( srcCANBox, data, CAN_MESSAGE_PAYLOAD_SIZE );
+            }
         }
     }
     else
@@ -216,7 +317,12 @@
  *************************************************************************/
 void handleUARTMsgXmitPacketInterrupt( void )
 {
-    transmitNextUARTPacket();
+    U32 bytesXmitted = transmitNextUARTPacket();
+
+    if ( 0 == bytesXmitted )
+    {
+        signalSCI1XmitsCompleted();
+    }
 }
 
 /*************************************************************************
@@ -300,7 +406,7 @@
 
     for ( i = 0; i < NUM_OF_CAN_OUT_BUFFERS; i++ )
     {
-        if ( CAN_OUT_BUFFERS[i] == srcCANBox )
+        if ( CAN_OUT_BUFFERS[ i ] == srcCANBox )
         {
             result = TRUE;
             break;
@@ -327,7 +433,7 @@
 
     for ( i = 0; i < NUM_OF_CAN_IN_BUFFERS; i++ )
     {
-        if ( MSG_IN_BUFFERS[i] == srcCANBox )
+        if ( MSG_IN_BUFFERS[ i ] == srcCANBox )
         {
             result = TRUE;
             break;
@@ -362,9 +468,9 @@
     // search for next priority CAN packet to transmit
     for ( i = 0; i < NUM_OF_CAN_OUT_BUFFERS; i++ )
     {
-        if ( numberOfBytesInCommBuffer( CAN_OUT_BUFFERS[i] ) >= CAN_MESSAGE_PAYLOAD_SIZE )
+        if ( numberOfBytesInCommBuffer( CAN_OUT_BUFFERS[ i ] ) >= CAN_MESSAGE_PAYLOAD_SIZE )
         {
-            result = CAN_OUT_BUFFERS[i];
+            result = CAN_OUT_BUFFERS[ i ];
             break; // found highest priority packet to transmit - we're done
         }
     }
@@ -380,25 +486,42 @@
  * Inputs : Output CAN Comm Buffers
  * Outputs : CAN packet transmit initiated.
  * @param msg : none
- * @return none
+ * @return # of bytes transmitted
  *************************************************************************/
-static void transmitNextCANPacket( void )
+static U32 transmitNextCANPacket( void )
 {
+    U32 result = 0;
     COMM_BUFFER_T buffer = findNextHighestPriorityCANPacketToTransmit();
 
     // if a buffer is found with a packet to transmit, get packet from buffer and transmit it
     if ( buffer != COMM_BUFFER_NOT_USED )
     {
-        U08 data[CAN_MESSAGE_PAYLOAD_SIZE];
+        U08 data[ CAN_MESSAGE_PAYLOAD_SIZE ];
         U32 dataSize = getFromCommBuffer( buffer, data, CAN_MESSAGE_PAYLOAD_SIZE );
         CAN_MESSAGE_BOX_T mBox = buffer;  // CAN message boxes and comm buffers are aligned
 
         // if there's another CAN packet to send, send it
         if ( dataSize == CAN_MESSAGE_PAYLOAD_SIZE )
         {
-            canTransmit( canREG1, mBox, data );
+            signalCANXmitsInitiated();
+            if ( 0 != canTransmit( canREG1, mBox, data ) )
+            {
+                result = CAN_MESSAGE_PAYLOAD_SIZE;
+            }
+            else
+            {
+                signalCANXmitsCompleted();
+                // TODO - shouldn't get here, but let's see if we do
+                SET_ALARM_WITH_1_U32_DATA( ALARM_ID_SOFTWARE_FAULT, (U32)mBox )
+            }
         }
+        else
+        {   // TODO - shouldn't get here - just testing - set first data to new s/w fault enum later
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, (U32)buffer, (U32)dataSize )
+        }
     }
+
+    return result;
 }
 
 /*************************************************************************
@@ -409,19 +532,30 @@
  * Inputs : Output UART Comm Buffer(s)
  * Outputs : UART DMA transmit initiated.
  * @param msg : none
- * @return none
+ * @return # of bytes transmitted
  *************************************************************************/
-static void transmitNextUARTPacket( void )
+static U32 transmitNextUARTPacket( void )
 {
-    U32 dataSize = getFromCommBuffer( COMM_BUFFER_OUT_UART_PC, pcXmitPacket, PC_MESSAGE_PACKET_SIZE );
+    U32 result = 0;
+    U32 dataPend = numberOfBytesInCommBuffer( COMM_BUFFER_OUT_UART_PC );
+    U32 dataSize;
 
-    // if there's another UART packet to send, send it
-    if ( dataSize == PC_MESSAGE_PACKET_SIZE )
+    if ( dataPend >= PC_MESSAGE_PACKET_SIZE )
     {
-        dmaSetCtrlPacket( DMA_CH3, pcDMAXmitControlRecord );
-        dmaSetChEnable( DMA_CH3, DMA_HW );
-        setSCI1DMATransmitInterrupt();
+        dataSize = getFromCommBuffer( COMM_BUFFER_OUT_UART_PC, pcXmitPacket, PC_MESSAGE_PACKET_SIZE );
+
+        // if there's another UART packet to send, send it
+        if ( dataSize == PC_MESSAGE_PACKET_SIZE )
+        {
+            signalSCI1XmitsInitiated();
+            dmaSetCtrlPacket( DMA_CH3, pcDMAXmitControlRecord );
+            dmaSetChEnable( DMA_CH3, DMA_HW );
+            setSCI1DMATransmitInterrupt();
+            result = PC_MESSAGE_PACKET_SIZE;
+        }
     }
+
+    return result;
 }
 
 
@@ -442,8 +576,9 @@
  *************************************************************************/
 static void processIncomingData( void )
 {
-    U08 data[sizeof(MESSAGE_WRAPPER_T)+1];
+    U08 data[ 512 ];  // message work space
     U32 i;
+    BOOL badCRCDetected = FALSE;
 
     // queue any received messages
     for ( i = 0; i < NUM_OF_MSG_IN_BUFFERS; i++ )
@@ -458,42 +593,57 @@
             messagesInBuffer = FALSE;
 
             // since messages can have 8-byte alignment padding left unconsumed by last get, get padding out of buffer
-            consumeBufferPaddingBeforeSync( MSG_IN_BUFFERS[i] );
+            consumeBufferPaddingBeforeSync( MSG_IN_BUFFERS[ i ] );
             // do we have enough bytes in buffer for smallest message?
-            numOfBytesInBuffer = numberOfBytesInCommBuffer( MSG_IN_BUFFERS[i] );
+            numOfBytesInBuffer = numberOfBytesInCommBuffer( MSG_IN_BUFFERS[ i ] );
             if ( numOfBytesInBuffer >= MESSAGE_OVERHEAD_SIZE )
             {   // peek at minimum of all bytes available or max message size (+1 for sync byte)
-                U32 bytesPeeked = peekFromCommBuffer( MSG_IN_BUFFERS[i], data, MIN(numOfBytesInBuffer,sizeof(MESSAGE_WRAPPER_T)+1) );
-                U32 msgSize = parseMessageFromBuffer( data, bytesPeeked );
+                U32 bytesPeeked = peekFromCommBuffer( MSG_IN_BUFFERS[ i ], data, MIN( numOfBytesInBuffer, sizeof( MESSAGE_WRAPPER_T ) + 1 ) );
+                S32 msgSize = parseMessageFromBuffer( data, bytesPeeked );
 
-                if ( msgSize > 0 )
+                if ( msgSize > 0 ) // valid, complete message found?
                 {
+                    MESSAGE_WRAPPER_T rcvMsg;
+                    U08 *dataPtr = data+1; // skip over sync byte
+
                     // consume message (+sync byte)
-                    msgSize = getFromCommBuffer( MSG_IN_BUFFERS[i], data, msgSize+1 );
-                    // if message data is at least minimum size, convert received message data to a message and add to message queue
-                    if ( msgSize > MESSAGE_OVERHEAD_SIZE )
+                    msgSize = getFromCommBuffer( MSG_IN_BUFFERS[ i ], data, msgSize + 1 );
+                    // convert received message data to a message and add to message queue
+                    messagesInBuffer = TRUE;  // keep processing this buffer
+                    // blank the new message record
+                    blankMessageInWrapper( &rcvMsg );
+                    // copy message header portion of message data to the new message
+                    memcpy( &(rcvMsg.msg.hdr), dataPtr, sizeof(MESSAGE_HEADER_T) );
+                    dataPtr += sizeof(MESSAGE_HEADER_T);
+                    // copy message payload portion of message data to the new message
+                    memcpy( &(rcvMsg.msg.payload), dataPtr, rcvMsg.msg.hdr.payloadLen );
+                    dataPtr += rcvMsg.msg.hdr.payloadLen;
+                    // copy CRC portion of message data to the new message
+                    rcvMsg.crc = *dataPtr;
+                    // add new message to queue for later processing
+                    addToMsgQueue( MSG_Q_IN, &rcvMsg );
+                    // if message from HD broadcast channel, update HD comm status
+                    if ( COMM_BUFFER_IN_CAN_HD_BROADCAST == i )
                     {
-                        MESSAGE_WRAPPER_T rcvMsg;
-                        U08 *dataPtr = data+1; // skip over sync byte
-
-                        messagesInBuffer = TRUE;
-                        // blank the new message record
-                        blankMessageInWrapper( &rcvMsg );
-                        // copy message header portion of message data to the new message
-                        memcpy( &(rcvMsg.msg.hdr), dataPtr, sizeof(MESSAGE_HEADER_T) );
-                        dataPtr += sizeof(MESSAGE_HEADER_T);
-                        // copy message cargo portion of message data to the new message
-                        memcpy( &(rcvMsg.msg.payload), dataPtr, rcvMsg.msg.hdr.payloadLen );
-                        dataPtr += rcvMsg.msg.hdr.payloadLen;
-                        // copy CRC portion of message data to the new message
-                        rcvMsg.crc = *dataPtr;
-                        // add new message to queue for later processing
-                        addToMsgQueue( MSG_Q_IN, &rcvMsg );
-                    } // message is at least as large as minimum size
+                        hdIsCommunicating = TRUE;
+                        timeOfLastHDCheckIn = getMSTimerCount();
+                    }
+                }
+                else if ( -1 == msgSize ) // candidate message with bad CRC found?
+                {
+                    badCRCDetected = TRUE;
+                    getFromCommBuffer( MSG_IN_BUFFERS[ i ], data, 1 );  // consume sync byte so we can re-sync
+                    messagesInBuffer = TRUE;  // keep processing this buffer
                 } // looks like there is a complete message in the comm buffer
             } // enough data left in comm buffer to possibly be a complete message
         } // while loop to get all complete messages for each comm buffer
     } // for loop to check all comm buffers for messages
+
+    // if any bad CRCs detected, see if too many
+    if ( TRUE == badCRCDetected )
+    {
+        checkTooManyBadMsgCRCs();
+    }
 }
 
 /*************************************************************************
@@ -536,35 +686,42 @@
  * Outputs : none
  * @param data : pointer to byte array to search for a message
  * @param len : # of bytes in the data to search
- * @return size of message if found, zero if no complete message found.
+ * @return size of message if found, zero if no complete message found, \n
+ * -1 if message found but CRC fails.
  *************************************************************************/
-static U32 parseMessageFromBuffer( U08 *data, U32 len )
+static S32 parseMessageFromBuffer( U08 *data, U32 len )
 {
     U32 i;
-    U32 cargoSize;
+    U32 payloadSize;
     U32 msgSize;
-    U32 result = 0;
+    S32 result = 0;
 
     for ( i = 0; i < len; i++ )
     {
         // find sync byte
-        if ( MESSAGE_SYNC_BYTE == data[i] )
+        if ( MESSAGE_SYNC_BYTE == data[ i ] )
         {
             U32 pos = i + 1;  // skip past sync byte implemented
             U32 remSize = len - pos;
 
             // if a minimum sized msg would fit in remaining, continue
             if ( remSize >= MESSAGE_OVERHEAD_SIZE )
             {
-                cargoSize = data[pos+sizeof(U16)];
-                msgSize = MESSAGE_OVERHEAD_SIZE + cargoSize;
+                payloadSize = data[ pos + sizeof(MESSAGE_HEADER_T) - sizeof(U08) ];
+                msgSize = MESSAGE_OVERHEAD_SIZE + payloadSize;
                 // we now know the size of the message - we can now know if full message is contained in buffer
                 if ( msgSize <= remSize )
-                {
-                    result = msgSize; // we found a complete message of this size
+                {   // check CRC to make sure it's a valid message
+                    if ( data[i+msgSize] == crc8( &data[pos], msgSize - 1 ) )
+                    {
+                        result = msgSize; // we found a complete, valid message of this size
+                    }
+                    else  // CRC failed
+                    {
+                        result = -1; // we found a complete, invalid message
+                    }
                 }
             }
-
             break;
         }
     }
@@ -592,42 +749,218 @@
         // see if any messages received
         isThereMsgRcvd = getFromMsgQueue( MSG_Q_IN, &message );
         if ( TRUE == isThereMsgRcvd )
-        {
-            // TODO - check CRC before processing a message and if it fails we will...
+        {   // CRC should be good because we checked it during parsing before adding to queue - but check it again for good measure
             if ( message.crc == crc8( (U08*)(&message), sizeof(MESSAGE_HEADER_T) + message.msg.hdr.payloadLen ) )
             {
-                processReceivedMessage( &message.msg );
+#ifndef ACK_NOT_IMPLEMENTED
+                // if ACK, mark pending message ACK'd
+                if ( MSG_ID_ACK == message.msg.hdr.msgID )
+                {
+                    matchACKtoPendingACKList( message.msg.hdr.seqNo );
+                }
+                else
+#endif
+                {
+#ifndef ACK_NOT_IMPLEMENTED
+                    // if received message requires ACK, queue one up
+                    if ( message.msg.hdr.seqNo < 0 )
+                    {
+                        sendACKMsg( &message.msg );
+                    }
+                    else
+#endif
+                    {   // otherwise, process the received message
+                        processReceivedMessage( &message.msg );
+                    }
+                }
             }
             else // CRC failed
             {
-                // TODO - probably wouldn't want to fault on this.  ignore?
+                checkTooManyBadMsgCRCs();
             }
         }
     }
+}
 
-    // TODO - process UART (script) messages too
+/*************************************************************************
+ * @brief checkForCommTimeouts
+ * The checkForCommTimeouts function checks for sub-system communication \n
+ * timeout errors.
+ * @details
+ * Inputs : timeOfLastDGCheckIn, timeOfLastUICheckIn
+ * Outputs : possibly a comm t/o alarm
+ * @param none
+ * @return none
+ *************************************************************************/
+static void checkForCommTimeouts( void )
+{
+    if ( TRUE == didTimeout( timeOfLastHDCheckIn, HD_COMM_TIMEOUT_IN_MS ) )
+    {
+        //activateAlarmNoData( ALARM_ID_HD_COMM_TIMEOUT );  // TODO - add this alarm
+    }
 }
 
 /*************************************************************************
+ * @brief checkTooManyBadMsgCRCs
+ * The checkTooManyBadMsgCRCs function checks for too many bad message CRCs \n
+ * within a set period of time.  Assumed function is being called when a new \n
+ * bad CRC is detected so a new bad CRC will be added to the list.
+ * @details
+ * Inputs : badCRCTimeStamps[], badCRCListIdx, badCRCListCount
+ * Outputs : possibly a "too many bad CRCs" alarm
+ * @return none
+ *************************************************************************/
+static void checkTooManyBadMsgCRCs( void )
+{
+    U32 listTimeInMS;
+
+    // replace oldest bad CRC in list with this new one
+    badCRCTimeStamps[ badCRCListIdx ] = getMSTimerCount();
+    // move list index to next position (may wrap)
+    badCRCListIdx = INC_WRAP( badCRCListIdx, 0, MAX_COMM_CRC_FAILURES - 1 );
+    // update list count
+    badCRCListCount = INC_CAP( badCRCListCount, MAX_COMM_CRC_FAILURES );
+    // check if too many bad CRCs in window of time
+    listTimeInMS = calcTimeSince( badCRCTimeStamps[ badCRCListIdx ] );
+    if ( ( badCRCListCount >= MAX_COMM_CRC_FAILURES ) && ( listTimeInMS <= MAX_COMM_CRC_FAILURE_WINDOW_MS ) )
+    {
+#ifndef DISABLE_CRC_ERROR
+        activateAlarmNoData( ALARM_ID_COMM_TOO_MANY_BAD_CRCS );
+#endif
+    }
+}
+
+#ifndef ACK_NOT_IMPLEMENTED
+/*************************************************************************
+ * @brief addMsgToPendingACKList
+ * The addMsgToPendingACKList function adds a given message to the pending \n
+ * ACK list.  Messages in this list will require receipt of an ACK message \n
+ * for this particular message within a limited time.
+ * @details
+ * Inputs : pendingAckList[]
+ * Outputs : pendingAckList[]
+ * @param msg : pointer to msg within the message data
+ * @param msgData : pointer to message data to add to pending ACK list
+ * @param len : # of bytes of message data
+ * @return TRUE if message added successfully, FALSE if not
+ *************************************************************************/
+BOOL addMsgToPendingACKList( MESSAGE_T *msg, COMM_BUFFER_T channel, U08 *msgData, U32 len )
+{
+    BOOL result = FALSE;
+    U32  i;
+
+    // find first open slot in pending ACK list and add given msg data to it
+    for ( i = 0; i < PENDING_ACK_LIST_SIZE; i++ )
+    {
+        _disable_IRQ();  // slot selection needs interrupt protection
+        if ( FALSE == pendingAckList[ i ].used )
+        {
+            S16 seqNo = msg->hdr.seqNo * -1;  // remove ACK bit from seq #
+
+            pendingAckList[ i ].used = TRUE;
+            _enable_IRQ();
+            pendingAckList[ i ].seqNo = seqNo;
+            pendingAckList[ i ].channel = channel;
+            pendingAckList[ i ].timeStamp = getMSTimerCount();
+            pendingAckList[ i ].retries = MSG_NOT_ACKED_MAX_RETRIES;
+            pendingAckList[ i ].msgSize = len;
+            memcpy( pendingAckList[ i ].msg, msgData, len );
+            result = TRUE;
+            break;
+        }
+        else
+        {
+            _enable_IRQ();
+        }
+    }
+
+    return result;
+}
+
+/*************************************************************************
+ * @brief matchACKtoPendingACKList
+ * The matchACKtoPendingACKList function searches the pending ACK list to \n
+ * see if the sequence # from a received ACK msg matches any.  If found, \n
+ * the list entry is removed.
+ * @details
+ * Inputs : pendingAckList[]
+ * Outputs : pendingAckList[]
+ * @param seqNo : sequence # to match to an entry in the list
+ * @return TRUE if a match was found, FALSE if not
+ *************************************************************************/
+static BOOL matchACKtoPendingACKList( S16 seqNo )
+{
+    BOOL result = FALSE;
+    U32  i;
+
+    // find match
+    for ( i = 0; i < PENDING_ACK_LIST_SIZE; i++ )
+    {
+        if ( ( TRUE == pendingAckList[ i ].used ) && ( pendingAckList[ i ].seqNo == seqNo ) )
+        {   // remove message pending ACK from list
+            pendingAckList[ i ].used = FALSE;
+            result = TRUE;
+            break;
+        }
+    }
+
+    return result;
+}
+
+/*************************************************************************
+ * @brief checkPendingACKList
+ * The checkPendingACKList function searches the pending ACK list to \n
+ * see if any have expired.  Any such messages will be queued for retransmission \n
+ * and if max retries reached a fault is triggered.
+ * @details
+ * Inputs : pendingAckList[]
+ * Outputs : pendingAckList[]
+ * @param none
+ * @return none
+ *************************************************************************/
+static void checkPendingACKList( void )
+{
+    U32  i;
+
+    // find expired messages pending ACK
+    for ( i = 0; i < PENDING_ACK_LIST_SIZE; i++ )
+    {
+        if ( ( TRUE == pendingAckList[ i ].used ) && ( TRUE == didTimeout( pendingAckList[ i ].timeStamp, MSG_NOT_ACKED_TIMEOUT_MS ) ) )
+        {
+            if ( pendingAckList[ i ].retries > 0 )
+            {   // re-queue message for transmit
+                pendingAckList[ i ].retries--;
+                pendingAckList[ i ].timeStamp = getMSTimerCount();
+                addToCommBuffer( pendingAckList[ i ].channel, pendingAckList[ i ].msg, pendingAckList[ i ].msgSize );
+            }
+            else
+            {
+                U16 msgID;
+
+                memcpy( &msgID, &pendingAckList[ i ].msg[ sizeof( U08 ) + sizeof( U16) ], sizeof( U16 ) );
+                SET_ALARM_WITH_1_U32_DATA( ALARM_ID_CAN_MESSAGE_NOT_ACKED, (U32)msgID );
+            }
+        }
+    }
+}
+#endif
+
+/*************************************************************************
  * @brief processReceivedMessage
  * The processReceivedMessage function processes a given message.
  * @details
  * Inputs : none
  * Outputs : message processed
- * @param msg :
+ * @param message : pointer to message to process
  * @return none
  *************************************************************************/
 static void processReceivedMessage( MESSAGE_T *message )
 {
     U16 msgID = message->hdr.msgID;
 
+    // handle any messages from other sub-systems
     switch ( msgID )
     {
-
-        case MSD_ID_DG_FILL_START_STOP:
-            handleDGFillStartStopMessages( message );
-            break;
-
         case MSG_ID_TESTER_LOGIN_REQUEST:
             handleTesterLogInRequest( message );
             break;
@@ -638,25 +971,30 @@
     }
 
     // handle any test messages if tester has logged in successfully
-    if ( ( msgID > MSG_ID_FIRST_TESTER_MESSAGE ) && ( TRUE == isTestingActivated() ) )
+    if ( ( msgID > MSG_ID_FIRST_TESTER_MESSAGE ) && ( msgID <= END_OF_MSG_IDS ) && ( TRUE == isTestingActivated() ) )
     {
         switch ( msgID )
         {
-            case MSG_ID_HD_MESSAGE:
-                handleTestHDMessageRequest( message );
+            case MSG_ID_DG_MESSAGE:
+                handleTestDGMessageRequest( message );
                 break;
 
-            case MSG_ID_ALARM_LAMP_PATTERN_OVERRIDE:
-                handleTestAlarmLampPatternOverrideRequest( message );
-                break;
-
             case MSG_ID_WATCHDOG_TASK_CHECKIN_OVERRIDE:
                 handleTestWatchdogCheckInStateOverrideRequest( message );
                 break;
 
+            case MSG_ID_ALARM_STATE_OVERRIDE:
+                handleTestAlarmStateOverrideRequest( message );
+                break;
+
+            case MSG_ID_SET_RTC_DATE_TIME:
+                handleSetRTCTimestamp( message );
+                break;
+
             default:
                 // TODO - unrecognized message ID received - ignore
                 break;
         }
     }
 }
+
Index: firmware/App/Services/SystemComm.h
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/SystemComm.h	(.../SystemComm.h)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/SystemComm.h	(.../SystemComm.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -19,6 +19,7 @@
 
 #include "Common.h"
 #include "CommBuffers.h"
+#include "MsgQueues.h"
 
 // ********** public definitions **********
 
@@ -27,8 +28,14 @@
 #define CAN_MESSAGE_PAYLOAD_SIZE    8
 #define PC_MESSAGE_PACKET_SIZE      8
 
-typedef COMM_BUFFER_T   CAN_MESSAGE_BOX_T;       // the first 10 comm buffers align with the 10 active CAN message boxes
+#define MSG_ID_ACK                  0xFFFF
+#define MSG_ACK_BIT                 0x8000
+#define MAX_MSG_SEQ_NO              0x7FFF
+#define MIN_MSG_SEQ_NO              0x0001
+#define MAX_ACK_MSG_SIZE            ( sizeof( MESSAGE_WRAPPER_T ) + 1 + CAN_MESSAGE_PAYLOAD_SIZE )  // must hold full (wrapped) message + sync + any CAN padding
 
+typedef COMM_BUFFER_T   CAN_MESSAGE_BOX_T;       // the first 12 comm buffers align with the 12 active CAN message boxes
+
 // ********** public function prototypes **********
 
 void initSystemComm( void );
@@ -37,5 +44,9 @@
 void handleCANMsgInterrupt( CAN_MESSAGE_BOX_T srcCANBox );
 void handleUARTMsgRecvPacketInterrupt( void );
 void handleUARTMsgXmitPacketInterrupt( void );
+BOOL isHDCommunicating( void );
+#ifndef ACK_NOT_IMPLEMENTED
+BOOL addMsgToPendingACKList( MESSAGE_T *msg, COMM_BUFFER_T channel, U08 *msgData, U32 len );
+#endif
 
 #endif
Index: firmware/App/Services/SystemCommMessages.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/SystemCommMessages.c	(.../SystemCommMessages.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/SystemCommMessages.c	(.../SystemCommMessages.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -19,65 +19,134 @@
 #include <string.h>     // for memcpy()
 
 #include "Common.h"
-#include "AlarmLamp.h"
 #include "MsgQueues.h"
 #include "WatchdogMgmt.h"
 #include "SystemCommMessages.h"
-#include "SystemComm.h"
-#include "CPLD.h"
-#include "OperationModes.h"
 #include "Utilities.h"
+#include "SystemComm.h"
+#include "RTC.h"
 
 // ********** private definitions **********
 
+#define ACK_REQUIRED                    TRUE
+#define ACK_NOT_REQUIRED                FALSE
+
 #pragma pack(push,1)
 
 typedef struct
 {
     U08 confirmed;                              // 1 = confirmed, 0 = rejected/timed out
 } OFF_BUTTON_MESSAGE_FROM_UI_PAYLOAD_T;
 
+typedef struct
+{
+    U32 alarmState;                             // 0 = no alarms, 1 = low priority, 2 = medium priority, 3 = high priority
+    U32 alarmTop;                               // ID of top active alarm
+    U32 escalatesIn;                            // seconds
+    U32 silenceExpiresIn;                       // seconds
+    U16 alarmsFlags;                            // bit flags: 1 = true, 0 = false for each bit
+} ALARM_COMP_STATUS_PAYLOAD_T;
+
+typedef struct
+{
+    U32 setPoint;
+    F32 measFlow;
+    F32 measRotorSpd;
+    F32 measPumpSpd;
+    F32 measMCSpd;
+    F32 measMCCurr;
+    F32 pwmDC;
+} PERISTALTIC_PUMP_STATUS_PAYLOAD_T;
+
+typedef struct
+{
+    F32 arterialPressure;
+    F32 venousPressure;
+    F32 bldPumpOcclusion;
+    F32 diPumpOcclusion;
+    F32 doPumpOcclusion;
+} PRESSURE_OCCLUSION_DATA_T;
+
+typedef struct
+{
+    U32 treatmentTimePrescribedinSec;
+    U32 treatmentTimeElapsedinSec;
+    U32 treatmentTimeRemaininginSec;
+} TREATMENT_TIME_DATA_T;
+
+typedef struct
+{
+    F32 res1PrimaryLoadCell;
+    F32 res1BackupLoadCell;
+    F32 res2PrimaryLoadCell;
+    F32 res2BackupLoadCell;
+} LOAD_CELL_READINGS_PAYLOAD_T;
+
 #pragma pack(pop)
 
 // ********** private data **********
 
 static BOOL testerLoggedIn = FALSE;
+static volatile U16 nextSeqNo = 1;
 
 // ********** private function prototypes **********
 
-static U32 serializeMessage( MESSAGE_T msg, U08 *data );
+static U32 serializeMessage( MESSAGE_T msg, COMM_BUFFER_T buffer, BOOL ackReq );
 static BOOL sendTestAckResponseMsg( MSG_ID_T msgID, BOOL ack );
 
 /*************************************************************************
  * @brief serializeMessage
  * The serializeMessage function serializes a given message into a given \n
- * array of bytes.  A sync byte is inserted at the beginning of the message \n
- * and an 8-bit CRC is appended to the end of the message. The given array \n
- * must be large enough to hold the message + 1 sync byte and 1 CRC byte and \n
- * up to 7 CAN padding bytes.
+ * array of bytes.  A sequence # is added to the message here and the ACK \n
+ * bit of the sequence # is set if ACK is required per parameter.  A sync byte \n
+ * is inserted at the beginning of the message and an 8-bit CRC is appended to \n
+ * the end of the message. The message is queued for transmission in the given buffer.
  * @details
  * Inputs : none
- * Outputs : given data array populated with serialized message data.
+ * Outputs : given data array populated with serialized message data and queued for transmit.
  * @param msg : message to serialize
- * @param data : byte array to populate with message data
+ * @param buffer : outgoing buffer that message should be queued in
+ * @param ackReq : is an acknowledgement from receiver required?
  * @return size (in bytes) of serialized message populated in given data array.
  *************************************************************************/
-static U32 serializeMessage( MESSAGE_T msg, U08 *data )
+static U32 serializeMessage( MESSAGE_T msg, COMM_BUFFER_T buffer, BOOL ackReq )
 {
+    BOOL result = 0;
+    BOOL error = FALSE;
     U32 msgSize = 0;
     U32 sizeMod, sizePad;
     U32 i;
-    U08 crc = crc8( (U08*)(&msg), sizeof( MESSAGE_HEADER_T ) + msg.hdr.payloadLen );
+    U08 crc;
+    U08 data[ MAX_ACK_MSG_SIZE ];  // byte array to populate with message data
 
     // prefix data with message sync byte
-    data[msgSize++] = MESSAGE_SYNC_BYTE;
+    data[ msgSize++ ] = MESSAGE_SYNC_BYTE;
 
+    // set sequence # and ACK bit (unless this is an ACK to a received message)
+#ifndef ACK_NOT_IMPLEMENTED
+    if ( msg.hdr.msgID != MSG_ID_ACK )
+    {
+        // thread protect next sequence # access & increment
+        _disable_IRQ();
+            msg.hdr.seqNo = nextSeqNo;
+            nextSeqNo = INC_WRAP( nextSeqNo, MIN_MSG_SEQ_NO, MAX_MSG_SEQ_NO );
+        _enable_IRQ();
+        if ( TRUE == ackReq )
+        {
+            msg.hdr.seqNo *= -1;
+        }
+    }
+#endif
+
+    // calculate message CRC
+    crc = crc8( (U08*)(&msg), sizeof( MESSAGE_HEADER_T ) + msg.hdr.payloadLen );
+
     // serialize message header data
-    memcpy( &data[msgSize], &(msg.hdr), sizeof(MESSAGE_HEADER_T) );
-    msgSize += sizeof(MESSAGE_HEADER_T);
+    memcpy( &data[ msgSize ], &( msg.hdr ), sizeof( MESSAGE_HEADER_T ) );
+    msgSize += sizeof( MESSAGE_HEADER_T );
 
     // serialize message payload (only used bytes per payloadLen field)
-    memcpy( &data[msgSize], &(msg.payload), msg.hdr.payloadLen );
+    memcpy( &data[ msgSize ], &( msg.payload ), msg.hdr.payloadLen );
     msgSize += msg.hdr.payloadLen;
 
     // add 8-bit CRC
@@ -88,58 +157,198 @@
     sizePad = ( sizeMod == 0 ? 0 : CAN_MESSAGE_PAYLOAD_SIZE - sizeMod );
     for ( i = 0; i < sizePad; i++ )
     {
-        data[msgSize++] = 0;
+        data[ msgSize++ ] = 0;
     }
 
-    return msgSize;
+#ifndef ACK_NOT_IMPLEMENTED
+    // if ACK required, add to pending ACK list
+    if ( TRUE == ackReq )
+    {
+        if ( FALSE == addMsgToPendingACKList( &msg, buffer, data, msgSize ) )
+        {
+            error = TRUE;
+            SET_ALARM_WITH_1_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_MSG_PENDING_ACK_LIST_FULL )
+        }
+    }
+#endif
+
+    if ( FALSE == error )
+    {
+        // add serialized message data to appropriate out-going comm buffer
+        result = addToCommBuffer( buffer, data, msgSize );
+    }
+
+    return result;
 }
 
+#ifndef ACK_NOT_IMPLEMENTED
+/*************************************************************************
+ * @brief sendACKMsg
+ * The sendACKMsg function constructs and queues for transmit an ACK message \n
+ * for a given received message.
+ * @details
+ * Inputs : none
+ * Outputs : ACK message queued for transmit on broadcast CAN channel.
+ * @param message : message to send an ACK for
+ * @return TRUE if ACK message queued successfully, FALSE if not
+ *************************************************************************/
+BOOL sendACKMsg( MESSAGE_T *message )
+{
+    BOOL result;
+    MESSAGE_T msg;
+
+    // create a message record
+    blankMessage( &msg );
+    // send ACK back with same seq. #, but w/o ACK bit
+    msg.hdr.seqNo = message->hdr.seqNo * -1;
+    // ACK messages always have this ID
+    msg.hdr.msgID = MSG_ID_ACK;
+    // ACK messages always have no payload
+    msg.hdr.payloadLen = 0;
+
+    // serialize and queue the message for transmit on broadcast channel
+    result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_DG_BROADCAST, ACK_NOT_REQUIRED );
+
+    return result;
+}
+#endif
+
 // ***********************************************************************
 // ********************* MSG_ID_OFF_BUTTON_PRESS *************************
 // ***********************************************************************
 
+/*************************************************************************
+ * @brief broadcastAlarmTriggered
+ * The broadcastAlarmTriggered function constructs an alarm triggered msg to \n
+ * be broadcast and queues the msg for transmit on the appropriate CAN channel.
+ * @details
+ * Inputs : none
+ * Outputs : alarm triggered msg constructed and queued.
+ * @param alarm : ID of alarm triggered
+ * @param almData1 : 1st data associated with alarm
+ * @param almData2 : 2nd data associated with alarm
+ * @return TRUE if msg successfully queued for transmit, FALSE if not
+ *************************************************************************/
+BOOL broadcastAlarmTriggered( U16 alarm, ALARM_DATA_T almData1, ALARM_DATA_T almData2 )
+{
+    BOOL result;
+    MESSAGE_T msg;
+    U08 *payloadPtr = msg.payload;
 
+    // create a message record
+    blankMessage( &msg );
+    msg.hdr.msgID = MSG_ID_ALARM_TRIGGERED;
+    msg.hdr.payloadLen = sizeof( U16 ) + sizeof( ALARM_DATA_T ) + sizeof( ALARM_DATA_T );
 
+    memcpy( payloadPtr, &alarm, sizeof( U16 ) );
+    payloadPtr += sizeof( U16 );
+    memcpy( payloadPtr, &almData1, sizeof( ALARM_DATA_T ) );
+    payloadPtr += sizeof( ALARM_DATA_T );
+    memcpy( payloadPtr, &almData2, sizeof( ALARM_DATA_T ) );
+
+    // serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+    result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_DG_ALARM, ACK_REQUIRED );
+
+    return result;
+}
+
 /*************************************************************************
- * @brief handleDGFillStartStopMessages
- * The handleDGFillStartStopMessages function handles a response to the
- * start and stop messages thru the CAN bus.
+ * @brief broadcastAlarmCleared
+ * The broadcastAlarmCleared function constructs an alarm cleared msg to be \n
+ * broadcast and queues the msg for transmit on the appropriate CAN channel.
  * @details
  * Inputs : none
- * Outputs : message handled
- * @param message : a pointer to the message to handle
- * @return none
+ * Outputs : alarm cleared msg constructed and queued.
+ * @param alarm : ID of alarm cleared
+ * @return TRUE if msg successfully queued for transmit, FALSE if not
  *************************************************************************/
-void handleDGFillStartStopMessages( MESSAGE_T *message )
+BOOL broadcastAlarmCleared( U16 alarm )
 {
-    # define STOP  0
-    # define START 1
+    BOOL result;
+    MESSAGE_T msg;
+    U08 *payloadPtr = msg.payload;
 
-    #ifdef RM46_EVAL_BOARD_TARGET
-      toggleUserLED();
-    #endif
+    // create a message record
+    blankMessage( &msg );
+    msg.hdr.msgID = MSG_ID_ALARM_CLEARED;
+    msg.hdr.payloadLen = sizeof( U16 );
 
-    // If we start therapy
-    if (message->payload[0] == START && getCurrentOperationMode() == MODE_STAN)
-    {
-        requestNewOperationMode(MODE_FILL);
-        sendTestAckResponseMsg((MSG_ID_T)message->hdr.msgID, TRUE);
-    } // We can only stop fill if we are in fill mode
-    else if (message->payload[0] == STOP && getCurrentOperationMode() == MODE_FILL)
-    {
-        requestNewOperationMode(MODE_STAN);
-        sendTestAckResponseMsg((MSG_ID_T)message->hdr.msgID, TRUE);
-    }
-    else
-    {
-        // TODO: Print to log that either start was called when t he machine was not
-        // in standby or that stop was called when the machine was not in fill
-        sendTestAckResponseMsg((MSG_ID_T)message->hdr.msgID, FALSE);
-    }
+    memcpy( payloadPtr, &alarm, sizeof( U16 ) );
+
+    // serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+    result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_DG_ALARM, ACK_REQUIRED );
+
+    return result;
 }
 
+/*************************************************************************
+ * @brief broadcastRTCEpoch
+ * The broadcastRTCEpoch function constructs an epoch  msg to \n
+ * be broadcast and queues the msg for transmit on the appropriate CAN channel.
+ * @details
+ * Inputs : none
+ * Outputs : RTC time and date in epoch
+ * @param epoch : Current time and date in epoch
+ * @return TRUE if msg successfully queued for transmit, FALSE if not
+ *************************************************************************/
+BOOL broadcastRTCEpoch( U32 epoch )
+{
+    BOOL result;
+    MESSAGE_T msg;
+    U08 *payloadPtr = msg.payload;
 
+    // create a message record
+    blankMessage( &msg );
+    msg.hdr.msgID = MSG_ID_RTC_EPOCH;
+    msg.hdr.payloadLen = sizeof( U32 );
+
+    memcpy( payloadPtr, &epoch, sizeof( U32 ) );
+
+    // serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+//    result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_HD_BROADCAST, ACK_NOT_REQUIRED );
+    result = TRUE;  // TODO - don't want DG broadcasting its time
+
+    return result;
+}
+
 /*************************************************************************
+ * @brief
+ * The broadcastTreatmentTime function constructs a treatment time msg to \n
+ * be broadcast and queues the msg for transmit on the appropriate CAN channel.
+ * @details
+ * Inputs : none
+ * Outputs : treatment time data msg constructed and queued
+ * @param secsTotTreatment : Total treatment time prescribed (in seconds).
+ * @param secsElapsed : Treatment time elapsed (in seconds).
+ * @param secsRemaining : Treatment time remaining (in seconds).
+ * @return TRUE if msg successfully queued for transmit, FALSE if not
+ *************************************************************************/
+BOOL broadcastTreatmentTime( U32 secsTotTreatment, U32 secsElapsed, U32 secsRemaining )
+{
+    BOOL result;
+    MESSAGE_T msg;
+    U08 *payloadPtr = msg.payload;
+    TREATMENT_TIME_DATA_T payload;
+
+    // create a message record
+    blankMessage( &msg );
+    msg.hdr.msgID = MSG_ID_TREATMENT_TIME;
+    msg.hdr.payloadLen = sizeof( TREATMENT_TIME_DATA_T );
+
+    payload.treatmentTimePrescribedinSec = secsTotTreatment;
+    payload.treatmentTimeElapsedinSec = secsElapsed;
+    payload.treatmentTimeRemaininginSec = secsRemaining;
+
+    memcpy( payloadPtr, &payload, sizeof( TREATMENT_TIME_DATA_T ) );
+
+    // serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+    result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_DG_BROADCAST, ACK_NOT_REQUIRED );
+
+    return result;
+}
+
+
+/*************************************************************************
  *                       TEST SUPPORT FUNCTIONS
  *************************************************************************/
 
@@ -157,21 +366,9 @@
 BOOL sendDebugData( U08 *dbgData, U32 len )
 {
     BOOL result;
-    MESSAGE_T msg;
-    U32 msgSize;
-    U08  data[sizeof(MESSAGE_WRAPPER_T) + 1 + CAN_MESSAGE_PAYLOAD_SIZE];  // must hold full (wrapped) message + sync + any CAN padding
 
-    // create a message record
-    blankMessage( &msg );
-    msg.hdr.msgID = 2;
-    msg.hdr.payloadLen = len;
-    memcpy( msg.payload, dbgData, len );
-
-    // serialize the message (w/ sync, CRC, and appropriate CAN padding)
-    msgSize = serializeMessage( msg, data );
-
     // add serialized message data to appropriate comm buffer
-    result = addToCommBuffer( COMM_BUFFER_OUT_UART_PC, data, msgSize );
+    result = addToCommBuffer( COMM_BUFFER_OUT_UART_PC, dbgData, len );
 
     return result;
 }
@@ -188,8 +385,7 @@
  *************************************************************************/
 BOOL isTestingActivated( void )
 {
-    //TODO: Disable all login related functions
-    return TRUE;
+    return testerLoggedIn;
 }
 
 /*************************************************************************
@@ -208,21 +404,16 @@
 {
     BOOL result;
     MESSAGE_T msg;
-    U32 msgSize;
-    U08  data[PC_MESSAGE_PACKET_SIZE];
 
     // create a message record
     blankMessage( &msg );
     msg.hdr.msgID = msgID;
-    msg.hdr.payloadLen = 1;
-    msg.payload[0] = (U08)ack;
+    msg.hdr.payloadLen = sizeof( U08 );
+    msg.payload[ 0 ] = (U08)ack;
 
-    // serialize the message (w/ sync, CRC, and appropriate CAN padding)
-    msgSize = serializeMessage( msg, data );
+    // serialize the message (w/ sync, CRC, and appropriate CAN padding) and add serialized message data to appropriate comm buffer
+    result = serializeMessage( msg, COMM_BUFFER_OUT_CAN_PC, ACK_NOT_REQUIRED );
 
-    // add serialized message data to appropriate comm buffer
-    result = addToCommBuffer( COMM_BUFFER_OUT_CAN_DG_2_HD, data, msgSize );
-
     return result;
 }
 
@@ -240,7 +431,7 @@
 {
     // verify pass code
     // TODO - placeholder - how do we want to authenticate tester?
-    if ( ( 3 == message->hdr.payloadLen ) && ( 0x31 == message->payload[0] ) && ( 0x32 == message->payload[1] ) && ( 0x33 == message->payload[2] ) )
+    if ( ( 3 == message->hdr.payloadLen ) && ( 0x31 == message->payload[ 0 ] ) && ( 0x32 == message->payload[ 1 ] ) && ( 0x33 == message->payload[ 2 ] ) )
     {
         testerLoggedIn = TRUE;
     }
@@ -253,94 +444,83 @@
 }
 
 /*************************************************************************
- * @brief handleTestHDMessageRequest
- * The handleTestHDMessageRequest function handles a request to add an \n
- * HD message to the received message queue.
+ * @brief
+ * The handleTestDGMessageRequest function handles a request to add a \n
+ * DG message to the received message queue.
  * @details
  * Inputs : none
  * Outputs : message handled
  * @param message : a pointer to the message to handle
  * @return none
  *************************************************************************/
-void handleTestHDMessageRequest( MESSAGE_T *message )
+void handleTestDGMessageRequest( MESSAGE_T *message )
 {
-    MESSAGE_WRAPPER_T hdMessage;
+    MESSAGE_WRAPPER_T dgMessage;
     U32 msgLen = (U32)(message->hdr.payloadLen);
-    U08 *msgBytes = (U08*)(&(hdMessage));
+    U08 *msgBytes = (U08*)(&(dgMessage));
     BOOL result;
 
     memcpy( msgBytes, message->payload, msgLen );
 
     // add HD message to received message queue
-    result = addToMsgQueue( MSG_Q_IN, &hdMessage );
+    result = addToMsgQueue( MSG_Q_IN, &dgMessage );
 
     // respond to request
     sendTestAckResponseMsg( (MSG_ID_T)message->hdr.msgID, result );
 }
 
 /*************************************************************************
- * @brief handleTestAlarmLampPatternOverrideRequest
- * The handleTestAlarmLampPatternOverrideRequest function handles a request to \n
- * override the alarm lamp pattern.
+ * @brief handleTestWatchdogCheckInStateOverrideRequest
+ * The handleTestWatchdogCheckInStateOverrideRequest function handles a \n
+ * request to override the check-in status of a given task.
  * @details
  * Inputs : none
  * Outputs : message handled
  * @param message : a pointer to the message to handle
  * @return none
  *************************************************************************/
-void handleTestAlarmLampPatternOverrideRequest( MESSAGE_T *message )
-{
-    TEST_OVERRIDE_PAYLOAD_T payload;
-    BOOL result = FALSE;
+DATA_ARRAY_OVERRIDE_HANDLER_FUNC_U32( BOOL, handleTestWatchdogCheckInStateOverrideRequest, testSetWatchdogTaskCheckInOverride, testResetWatchdogTaskCheckInOverride )
 
-    // verify payload length
-    if ( sizeof(TEST_OVERRIDE_PAYLOAD_T) == message->hdr.payloadLen )
-    {
-        memcpy( &payload, message->payload, sizeof(TEST_OVERRIDE_PAYLOAD_T) );
+/*************************************************************************
+ * @brief handleTestAlarmStateOverrideRequest
+ * The handleTestAlarmStateOverrideRequest function handles a request to \n
+ * override the active status of a given alarm.
+ * @details
+ * Inputs : none
+ * Outputs : message handled
+ * @param message : a pointer to the message to handle
+ * @return none
+ *************************************************************************/
+DATA_ARRAY_OVERRIDE_HANDLER_FUNC_U32( BOOL, handleTestAlarmStateOverrideRequest, testSetAlarmStateOverride, testResetAlarmStateOverride )
 
-        if ( FALSE == payload.reset )
-        {
-            result = testSetCurrentLampPatternOverride( (LAMP_PATTERN_T)(payload.state) );
-        }
-        else
-        {
-            result = testResetCurrentLampPatternOverride();
-        }
-    }
-    // respond to request
-    sendTestAckResponseMsg( (MSG_ID_T)message->hdr.msgID, result );
-}
-
 /*************************************************************************
- * @brief handleTestAlarmLampPatternOverrideRequest
- * The handleTestAlarmLampPatternOverrideRequest function handles a request to \n
- * override the alarm lamp pattern.
+ * @brief handleSetRTCTimestamp
+ * The handleSetRTCTimestamp function handles a request to write time and
+ * date to RTC
  * @details
  * Inputs : none
  * Outputs : message handled
  * @param message : a pointer to the message to handle
  * @return none
  *************************************************************************/
-void handleTestWatchdogCheckInStateOverrideRequest( MESSAGE_T *message )
+void handleSetRTCTimestamp( MESSAGE_T *message )
 {
-    TEST_OVERRIDE_ARRAY_PAYLOAD_T payload;
-    BOOL result = FALSE;
+    BOOL result;
+    U08 seconds = message->payload[0];
+    U08 minutes = message->payload[1];
+    U08 hours   = message->payload[2];
+    U08 days    = message->payload[3];
+    U08 months  = message->payload[4];
+    U32 years;
+    memcpy(&years, &message->payload[5], sizeof(U32));
 
-    // verify payload length
-    if ( sizeof(TEST_OVERRIDE_ARRAY_PAYLOAD_T) == message->hdr.payloadLen )
-    {
-        memcpy( &payload, message->payload, sizeof(TEST_OVERRIDE_ARRAY_PAYLOAD_T) );
+    // TODO: Change setRTCTimestamp to return a boolean for this
+    result = TRUE;
 
-        if ( FALSE == payload.reset )
-        {
-            result = testSetWatchdogTaskCheckInOverride( payload.index, (BOOL)(payload.state) );
-        }
-        else
-        {
-            result = testResetWatchdogTaskCheckInOverride( payload.index );
-        }
-    }
+    setRTCTimestamp( seconds, minutes, hours, days, months, years );
+
     // respond to request
     sendTestAckResponseMsg( (MSG_ID_T)message->hdr.msgID, result );
 }
 
+
Index: firmware/App/Services/SystemCommMessages.h
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/SystemCommMessages.h	(.../SystemCommMessages.h)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/SystemCommMessages.h	(.../SystemCommMessages.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -23,23 +23,48 @@
 // ********** public definitions **********
 
 typedef enum Msg_IDs
-{
+{   // normal CAN messages
     MSG_ID_UNUSED = 0,
-    MSD_ID_DG_FILL_START_STOP = 0x2000,
-    MSG_ID_FIRST_TESTER_MESSAGE = 0xA000,
+    MSG_ID_OFF_BUTTON_PRESS,                    // 1
+    MSG_ID_ALARM_STATUS,                        // 2
+    MSG_ID_ALARM_TRIGGERED,                     // 3
+    MSG_ID_ALARM_CLEARED,                       // 4
+    MSG_ID_BLOOD_FLOW_DATA,                     // 5
+    MSG_ID_DG_CHECK_IN,                         // 6
+    MSG_ID_UI_CHECK_IN,                         // 7
+    MSG_ID_DIALYSATE_FLOW_DATA,                 // 8
+    MSG_ID_PRESSURE_OCCLUSION_DATA,             // 9
+    MSG_ID_RTC_EPOCH,                           // 10
+    MSG_ID_DIALYSATE_OUT_FLOW_DATA,             // 11
+    MSG_ID_LOAD_CELL_READINGS,                  // 12
+    MSG_ID_TREATMENT_TIME,                      // 13
+
+    // service/test CAN messages
+
+    MSG_ID_FIRST_TESTER_MESSAGE = 0xA000,                       // 0xA000
     MSG_ID_TESTER_LOGIN_REQUEST = MSG_ID_FIRST_TESTER_MESSAGE,
-    MSG_ID_HD_MESSAGE,
-    MSG_ID_ALARM_LAMP_PATTERN_OVERRIDE,
-    MSG_ID_WATCHDOG_TASK_CHECKIN_OVERRIDE,
-    NUM_OF_MSG_IDS
+    MSG_ID_DG_MESSAGE,                                          // 0xA001
+    MSG_ID_WATCHDOG_TASK_CHECKIN_OVERRIDE,                      // 0xA002
+    MSG_ID_ALARM_STATE_OVERRIDE,                                // 0xA003
+    MSG_ID_SET_RTC_DATE_TIME,                                   // 0xA004
+    END_OF_MSG_IDS
 } MSG_ID_T;
 
 // ********** public function prototypes **********
 
-// MSG_ID_OFF_BUTTON_PRESS
-BOOL sendOffButtonMsgToUI( void );
-void handleDGFillStartStopMessages( MESSAGE_T *message );
+#ifndef ACK_NOT_IMPLEMENTED
+// ACK MSG
+BOOL sendACKMsg( MESSAGE_T *message );
+#endif
 
+// MSG_ID_ALARM_TRIGGERED
+BOOL broadcastAlarmTriggered( U16 alarm, ALARM_DATA_T almData1, ALARM_DATA_T almData2 );
+// MSG_ID_ALARM_CLEARED
+BOOL broadcastAlarmCleared( U16 alarm );
+
+// MSG_ID_RTC_EPOCH
+BOOL broadcastRTCEpoch( U32 epoch );  // TODO - probably don't want DG to broadcast these
+
 // *********** public test support message functions **********
 
 // DEBUG OUTPUT
@@ -49,16 +74,17 @@
 void handleTesterLogInRequest( MESSAGE_T *message );
 BOOL isTestingActivated( void );
 
-// MSG_ID_HD_MESSAGE
-void handleTestHDMessageRequest( MESSAGE_T *message );
+// MSG_ID_DG_MESSAGE
+void handleTestDGMessageRequest( MESSAGE_T *message );
 
-// MSG_ID_OFF_BUTTON_STATE_OVERRIDE
-void handleTestOffButtonStateOverrideRequest( MESSAGE_T *message );
-
-// MSG_ID_ALARM_LAMP_PATTERN_OVERRIDE
-void handleTestAlarmLampPatternOverrideRequest( MESSAGE_T *message );
-
 // MSG_ID_WATCHDOG_TASK_CHECKIN_OVERRIDE:
 void handleTestWatchdogCheckInStateOverrideRequest( MESSAGE_T *message );
 
+// MSG_ID_ALARM_STATE_OVERRIDE
+void handleTestAlarmStateOverrideRequest( MESSAGE_T *message );
+
+// MSG_ID_SET_RTC_TIMESTAMP
+void handleSetRTCTimestamp( MESSAGE_T *message );
+
 #endif
+
Index: firmware/App/Services/Timers.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/Timers.c	(.../Timers.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/Timers.c	(.../Timers.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -23,7 +23,7 @@
 static U32 msTimerCount = 0;
 
 /*************************************************************************
- * @brief initTimers
+ * @brief
  * The initTimers function initializes the Timers module.
  * @details
  * Inputs : none
@@ -37,7 +37,7 @@
 }
 
 /*************************************************************************
- * @brief incMSTimerCount
+ * @brief
  * The incMSTimerCount function increments the ms timer count.
  * @details
  * Inputs : none
@@ -51,7 +51,7 @@
 }
 
 /*************************************************************************
- * @brief getMSTimerCount
+ * @brief
  * The getMSTimerCount function returns the current ms timer count.
  * @details
  * Inputs : msTimerCount
@@ -65,7 +65,7 @@
 }
 
 /*************************************************************************
- * @brief didTimeout
+ * @brief
  * The didTimeout function determines whether a timeout has occurred between \n
  * a given start count and a given timeout period (in ms).
  * @details
@@ -101,3 +101,60 @@
 
     return result;
 }
+
+/*************************************************************************
+ * @brief
+ * The calcTimeSince function calculates the time (in ms) from a given start \n
+ * time until now.
+ * @details
+ * Inputs : msTimerCount
+ * Outputs : none
+ * @param startMSCount : the ms count at the start of the period
+ * @return ms since given start time
+ *************************************************************************/
+U32 calcTimeSince( U32 startMSCount )
+{
+    U32 result;
+    U32 currMSCount = msTimerCount;
+
+    // no wrap
+    if ( currMSCount >= startMSCount )
+    {
+        result = currMSCount - startMSCount;
+    }
+    else
+    {
+        result = ( 0xFFFFFFFF - startMSCount ) + currMSCount + 1;
+    }
+
+    return result;
+}
+
+/*************************************************************************
+ * @brief
+ * The calcTimeBetween function calculates the time (in ms) from a given start \n
+ * time until a given end time.
+ * @details
+ * Inputs : none
+ * Outputs : none
+ * @param startMSCount : the ms count at the start of the period
+ * @param endMSCount : the ms count at the end of the period
+ * @return ms between two given times
+ *************************************************************************/
+U32 calcTimeBetween( U32 startMSCount, U32 endMSCount )
+{
+    U32 result;
+
+    // no wrap
+    if ( endMSCount >= startMSCount )
+    {
+        result = endMSCount - startMSCount;
+    }
+    else
+    {
+        result = ( 0xFFFFFFFF - startMSCount ) + endMSCount + 1;
+    }
+
+    return result;
+}
+
Index: firmware/App/Services/Timers.h
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/Timers.h	(.../Timers.h)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/Timers.h	(.../Timers.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -25,5 +25,7 @@
 void incMSTimerCount( void );
 U32 getMSTimerCount( void );
 BOOL didTimeout( U32 startMSCount, U32 timeoutPeriod );
+U32 calcTimeSince( U32 startMSCount );
+U32 calcTimeBetween( U32 startMSCount, U32 endMSCount );
 
 #endif
Index: firmware/App/Services/Utilities.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/Utilities.c	(.../Utilities.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/Utilities.c	(.../Utilities.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -27,42 +27,41 @@
 
 const U16 crc16_table[] =
 {
-      0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
-      0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
-      0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
-      0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
-      0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
-      0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
-      0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
-      0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
-      0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
-      0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
-      0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
-      0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
-      0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
-      0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
-      0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
-      0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
-      0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
-      0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
-      0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
-      0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
-      0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
-      0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
-      0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
-      0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
-      0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
-      0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
-      0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
-      0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
-      0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
-      0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
-      0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
-      0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
+    0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
+    0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
+    0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
+    0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
+    0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
+    0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
+    0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
+    0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
+    0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
+    0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
+    0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
+    0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
+    0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
+    0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
+    0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
+    0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
+    0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
+    0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
+    0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
+    0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
+    0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
+    0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+    0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
+    0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
+    0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
+    0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
+    0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
+    0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
+    0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
+    0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
+    0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
+    0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
 };
 
-const U08 crc8_table[] =
-{
+const U08 crc8_table[] = {
       0,  49,  98,  83, 196, 245, 166, 151, 185, 136, 219, 234, 125,  76,  31,  46,
      67, 114,  33,  16, 135, 182, 229, 212, 250, 203, 152, 169,  62,  15,  92, 109,
     134, 183, 228, 213,  66, 115,  32,  17,  63,  14,  93, 108, 251, 202, 153, 168,
@@ -81,9 +80,6 @@
     130, 179, 224, 209,  70, 119,  36,  21,  59,  10,  89, 104, 255, 206, 157, 172
 };
 
-// ********** private function prototypes **********
-
-
 /*************************************************************************
  * @brief crc16
  * The crc16 function calculates a 16-bit CRC for a given range of bytes \n
Index: firmware/App/Services/WatchdogMgmt.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Services/WatchdogMgmt.c	(.../WatchdogMgmt.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Services/WatchdogMgmt.c	(.../WatchdogMgmt.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -16,31 +16,34 @@
 
 #include "Common.h"
 #include "CPLD.h"
+#include "SafetyShutdown.h"
 #include "SystemCommMessages.h"
 #include "Timers.h"
 #include "WatchdogMgmt.h"
 
 // ********** private definitions **********
 
 #define MIN_WATCHDOG_PET_INTERVAL_MS        45
+#define WATCHDOG_POST_TIMEOUT_MS            100
+#define WATCHDOG_RECOVERY_TIME_MS           250
 
 typedef enum Button_Self_Test_States
 {
     WATCHDOG_SELF_TEST_STATE_START = 0,
     WATCHDOG_SELF_TEST_STATE_IN_PROGRESS,
+    WATCHDOG_SELF_TEST_STATE_RECOVER,
     WATCHDOG_SELF_TEST_STATE_COMPLETE,
     NUM_OF_WATCHDOG_SELF_TEST_STATES
 } WATCHDOG_SELF_TEST_STATE_T;
 
-#define WATCHDOG_POST_TIMEOUT_MS            100 // ms
-
 // ********** private data **********
 
 static U32  lastWatchdogPetTime = 0;
 
 DATA_ARRAY_DECL( BOOL, TaskCheckIns, NUM_OF_TASKS, watchdogTaskCheckedIn );
 
 static WATCHDOG_SELF_TEST_STATE_T watchdogSelfTestState = WATCHDOG_SELF_TEST_STATE_START;
+static SELF_TEST_STATUS_T         watchdogSelfTestStatus;
 static U32 watchdogSelfTestTimerCount = 0;
 
 // ********** private function prototypes **********
@@ -65,14 +68,15 @@
 
     lastWatchdogPetTime = 0;
     watchdogSelfTestState = WATCHDOG_SELF_TEST_STATE_START;
+    watchdogSelfTestStatus = SELF_TEST_STATUS_IN_PROGRESS;
     watchdogSelfTestTimerCount = 0;
     // initialize task check-ins to false
     for ( i = 0; i < NUM_OF_TASKS; i++ )
     {
-        watchdogTaskCheckedIn[i].data = FALSE;
-        watchdogTaskCheckedIn[i].ovData = FALSE;
-        watchdogTaskCheckedIn[i].ovInitData = FALSE;
-        watchdogTaskCheckedIn[i].override = OVERRIDE_RESET;
+        watchdogTaskCheckedIn[ i ].data = FALSE;
+        watchdogTaskCheckedIn[ i ].ovData = FALSE;
+        watchdogTaskCheckedIn[ i ].ovInitData = FALSE;
+        watchdogTaskCheckedIn[ i ].override = OVERRIDE_RESET;
     }
 }
 
@@ -105,7 +109,14 @@
     // check to see if watchdog has expired
     if ( getCPLDWatchdogExpired() == PIN_SIGNAL_HIGH )
     {
-        // TODO - watchdog expired fault
+        // ignore expired watchdog until after watchdog POST
+        if ( WATCHDOG_SELF_TEST_STATE_COMPLETE == watchdogSelfTestState )
+        {
+#ifndef DEBUG_ENABLED
+            activateSafetyShutdown();   // TODO - restore these - commented out now so that we don't get WD error with breakpoints while debugging
+            activateAlarmNoData( ALARM_ID_WATCHDOG_EXPIRED );
+#endif
+        }
     }
 }
 
@@ -123,7 +134,7 @@
 {
     if ( task < NUM_OF_TASKS )
     {
-        watchdogTaskCheckedIn[task].data = TRUE;
+        watchdogTaskCheckedIn[ task ].data = TRUE;
     }
 }
 
@@ -156,24 +167,34 @@
             }
             if ( getCPLDWatchdogExpired() == PIN_SIGNAL_HIGH )
             {
-                result = SELF_TEST_STATUS_PASSED;
+                watchdogSelfTestStatus = SELF_TEST_STATUS_PASSED;
             }
             else
             {
-                result = SELF_TEST_STATUS_FAILED;
-                // TODO - trigger watchdog POST failure
+                activateAlarmNoData( ALARM_ID_WATCHDOG_POST_TEST_FAILED );
+                watchdogSelfTestStatus = SELF_TEST_STATUS_FAILED;
             }
-            watchdogSelfTestState = WATCHDOG_SELF_TEST_STATE_COMPLETE;
+            watchdogSelfTestTimerCount = getMSTimerCount();
+            watchdogSelfTestState = WATCHDOG_SELF_TEST_STATE_RECOVER;
             break;
 
+        case WATCHDOG_SELF_TEST_STATE_RECOVER:
+            if ( TRUE == didTimeout( watchdogSelfTestTimerCount, WATCHDOG_RECOVERY_TIME_MS ) )
+            {
+                result = watchdogSelfTestStatus;
+                watchdogSelfTestState = WATCHDOG_SELF_TEST_STATE_COMPLETE;
+            }
+            break;
+
         case WATCHDOG_SELF_TEST_STATE_COMPLETE:
             // if we get called in this state, assume we're doing self test again
+            watchdogSelfTestStatus = SELF_TEST_STATUS_IN_PROGRESS;
             watchdogSelfTestState = WATCHDOG_SELF_TEST_STATE_START;
             break;
 
         default:
             result = SELF_TEST_STATUS_FAILED;
-            // TODO - s/w fault
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_WATCHDOG_INVALID_SELF_TEST_STATE, watchdogSelfTestState )
             break;
     }
 
@@ -196,7 +217,7 @@
     // initialize task check-ins to false
     for ( i = 0; i < NUM_OF_TASKS; i++ )
     {
-        watchdogTaskCheckedIn[i].data = FALSE;
+        watchdogTaskCheckedIn[ i ].data = FALSE;
     }
 }
 
Index: firmware/App/Tasks/TaskGeneral.c
===================================================================
diff -u -ra303cd4258157a8fbcbd8af4dd2bbaadec1a736c -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/App/Tasks/TaskGeneral.c	(.../TaskGeneral.c)	(revision a303cd4258157a8fbcbd8af4dd2bbaadec1a736c)
+++ firmware/App/Tasks/TaskGeneral.c	(.../TaskGeneral.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,7 +14,6 @@
  *
  **************************************************************************/
 
-#include <Controllers/AlarmLamp.h>
 #include "gio.h"
 #include "lin.h"
 
@@ -24,12 +23,6 @@
 #include "WatchdogMgmt.h"
 #include "TaskGeneral.h"
 
-#ifdef RM46_EVAL_BOARD_TARGET
-    #include "CPLD.h"
-    #include "SystemCommMessages.h"
-    static BOOL lastUserPress = FALSE;
-#endif
-
 /*************************************************************************
  * @brief taskGeneral
  * The taskGeneral function handles the scheduled General Task interrupt.\n
@@ -52,24 +45,6 @@
     // run operation mode state machine
     execOperationModes();
 
-    // control alarm lamp
-    execAlarmLamp();
-
-#ifdef RM46_EVAL_BOARD_TARGET
-    if ( getUserButtonState() == PIN_SIGNAL_LOW )
-    {
-        if ( lastUserPress == FALSE )
-        {
-            lastUserPress = TRUE;
-            setUserLED( FALSE );
-        }
-    }
-    else
-    {
-        lastUserPress = FALSE;
-    }
-#endif
-
     // manage data to be transmitted to other sub-systems
     execSystemCommTx();
 
Fisheye: Tag f068446fdb7889d320ddb6ffbd58f347ce0501e7 refers to a dead (removed) revision in file `firmware/App/TestSupport.h'.
Fisheye: No comparison available.  Pass `N' to diff?
Index: firmware/DG.dil
===================================================================
diff -u -r88b7f489c8da945997f1516600a30032393f5088 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/DG.dil	(.../DG.dil)	(revision 88b7f489c8da945997f1516600a30032393f5088)
+++ firmware/DG.dil	(.../DG.dil)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -1,4 +1,4 @@
-# RM46L852PGE 12/03/19 13:09:15
+# RM46L852PGE 02/01/20 13:33:21
 # 
 ARCH=RM46L852PGE
 # 
@@ -60,7 +60,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=FIQ
 DRIVER.SYSTEM.VAR.SAFETY_INIT_MIBSPI2_RAMPARITYCHECK_ENA.VALUE=0
 DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=0
-DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=206.670
 DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=220.00
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81
@@ -80,7 +80,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ
-DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=FIQ
 DRIVER.SYSTEM.VAR.SAFETY_INIT_CCM_SELFCHECK_ENA.VALUE=0
 DRIVER.SYSTEM.VAR.PMM_MEM_PD2_STATE_AVAIL.VALUE=1
 DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0
@@ -139,7 +139,7 @@
 DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=110.0
-DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08001200
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08002400
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109
@@ -179,7 +179,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=0
-DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=103.335
 DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0
@@ -358,7 +358,7 @@
 DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=etpwm6TripZoneInterrupt
-DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000200
 DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3
 DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=0
@@ -373,7 +373,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=0
-DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=FIQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1
@@ -407,7 +407,7 @@
 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.SAFETY_INIT_PBIST_SP_SELECTED.VALUE=0
-DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08001300
+DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08003400
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt
@@ -420,7 +420,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0
-DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ
 DRIVER.SYSTEM.VAR.PMM_LOGIC_PD3_STATE.VALUE=1
 DRIVER.SYSTEM.VAR.SAFETY_INIT_EFUSE_SELFCHECK_ENA.VALUE=1
@@ -435,7 +435,7 @@
 DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11
 DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0
-DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08001500
+DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08003800
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0
@@ -549,14 +549,14 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt
-DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00001000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1300
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=rtiCompare3Interrupt
-DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00001500
+DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00003800
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC
 DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true
 DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4
@@ -604,7 +604,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=0
-DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1
@@ -628,7 +628,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt
 DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0
 DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1
-DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002eb00
+DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0002c800
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0802ffff
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0
@@ -651,8 +651,8 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ
-DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=1
-DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=165
 DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0
 DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080
@@ -793,7 +793,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29
 DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1
 DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00140000
-DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00001000
 DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0
@@ -859,7 +859,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.SAFETY_INIT_HTU1_DP_PBISTCHECK_ENA.VALUE=0x00002000
 DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1
-DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x0008
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt
@@ -925,7 +925,7 @@
 DRIVER.SYSTEM.VAR.SAFETY_INIT_DMA_DP_PBISTCHECK_ENA.VALUE=0x00000800
 DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=0
 DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0
-DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08001400
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08003600
 DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08001000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=DEVICE_NONSHAREABLE
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=0
@@ -1109,7 +1109,7 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ
 DRIVER.SYSTEM.VAR.SAFETY_INIT_FTU_DP_PBISTCHECK_ENA.VALUE=0x00000000
 DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0
-DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=0
+DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x0013FFE0
 DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00180000
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16
@@ -1134,7 +1134,7 @@
 DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=1
 DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF
 DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00
-DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08001100
+DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08001400
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x0300
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt
 DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000010000
@@ -1183,8 +1183,8 @@
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt
 DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt
 DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=1
-DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100
-DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100
+DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000200
+DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000400
 DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4
 DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0
 DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef
@@ -1473,17 +1473,17 @@
 DRIVER.RTI.VAR.RTI_1_COMPARE_2_SOURCE.VALUE=0x00000100
 DRIVER.RTI.VAR.RTI_1_COMPARE_3_FREQ.VALUE=0.000100000
 DRIVER.RTI.VAR.RTI_1_FREQ.VALUE=103.335
-DRIVER.RTI.VAR.RTI_1_COMPARE_1_ACTUALTIME.VALUE=5.000
+DRIVER.RTI.VAR.RTI_1_COMPARE_1_ACTUALTIME.VALUE=10.000
 DRIVER.RTI.VAR.RTI_1_COUNTER_1_UC_COMPARE.VALUE=9
-DRIVER.RTI.VAR.RTI_1_COMPARE_1_TIME.VALUE=5.000
+DRIVER.RTI.VAR.RTI_1_COMPARE_1_TIME.VALUE=10.0
 DRIVER.RTI.VAR.RTI_1_COMPARE_3_UPDATE.VALUE=516675
 DRIVER.RTI.VAR.RTI_1_CONTINUE_ON_SUSPEND_ENABLE.VALUE=0x00000000
 DRIVER.RTI.VAR.RTI_1_COMPARE_1_INPUT_FREQ.VALUE=10.333500000
 DRIVER.RTI.VAR.RTI_1_COMPARE_0_SOURCE.VALUE=0x00000000
 DRIVER.RTI.VAR.RTI_1_COMPARE_2_TIME.VALUE=8.000
 DRIVER.RTI.VAR.RTI_1_COMPARE_0_ACTUALTIME.VALUE=1.000
 DRIVER.RTI.VAR.RTI_1_COUNTER_0_UC_COMPARE.VALUE=9
-DRIVER.RTI.VAR.RTI_1_COMPARE_1_UPDATE.VALUE=51668
+DRIVER.RTI.VAR.RTI_1_COMPARE_1_UPDATE.VALUE=103335
 DRIVER.RTI.VAR.RTI_1_COMPARE_3_TIME.VALUE=50.0
 DRIVER.RTI.VAR.RTI_1_COUNTER_0_NTU_SOURCE.VALUE=0
 DRIVER.RTI.VAR.RTI_1_COMPARE_0_INPUT_FREQ.VALUE=10.333500000
@@ -1508,7 +1508,7 @@
 DRIVER.RTI.VAR.RTI_1_NTU_3_FREQ.VALUE=220.000
 DRIVER.RTI.VAR.RTI_1_COMPARE_0.VALUE=10334
 DRIVER.RTI.VAR.RTI_1_COMPARE_2_ACTUALTIME.VALUE=8.000
-DRIVER.RTI.VAR.RTI_1_COMPARE_1.VALUE=51668
+DRIVER.RTI.VAR.RTI_1_COMPARE_1.VALUE=103335
 DRIVER.RTI.VAR.RTI_1_COMPARE_2.VALUE=82668
 DRIVER.RTI.VAR.RTI_1_COMPARE_3.VALUE=516675
 DRIVER.RTI.VAR.RTI_1_COUNTER_0_NTU_FREQ.VALUE=0.000
@@ -1527,8 +1527,8 @@
 DRIVER.GIO.VAR.GIO_PORT0_BIT2_POL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT6_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT2_PSL.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT6_DIR.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT2_DOUT.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_DIR.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_DOUT.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT0_BIT3_LVL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT4_PDR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT3_POL.VALUE=0
@@ -1554,7 +1554,7 @@
 DRIVER.GIO.VAR.GIO_PORT0_BIT7_PDR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT6_POL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT0_DOUT.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT6_PSL.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PSL.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULL.VALUE=2
 DRIVER.GIO.VAR.GIO_PORT0_BIT4_DOUT.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT7_LVL.VALUE=0
@@ -1567,23 +1567,23 @@
 DRIVER.GIO.VAR.GIO_PORT0_BIT2_PULL.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT1_BIT1_PULDIS.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT5_DOUT.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT1_BIT0_ENA.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT0_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT5_PULDIS.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT0_DIR.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT1_BIT2_DOUT.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULL.VALUE=1
-DRIVER.GIO.VAR.GIO_PORT1_BIT1_ENA.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT1_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT6_DOUT.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT1_DIR.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT1_BIT6_PULDIS.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT1_BIT2_ENA.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT2_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT2_DIR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT0_PDR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULL.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT0_BIT3_PULDIS.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT3_DOUT.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT4_PULL.VALUE=1
-DRIVER.GIO.VAR.GIO_PORT1_BIT3_ENA.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT1_BIT3_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT7_DOUT.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT3_DIR.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT1_BIT0_LVL.VALUE=0
@@ -1606,7 +1606,7 @@
 DRIVER.GIO.VAR.GIO_PORT1_BIT5_DIR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT2_LVL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT1_PULDIS.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT0_ENA.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT0_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT3_PDR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT2_POL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT0_DIR.VALUE=0
@@ -1615,13 +1615,13 @@
 DRIVER.GIO.VAR.GIO_PORT1_BIT6_DIR.VALUE=0
 DRIVER.GIO.VAR.GIO_BASE.VALUE=0xFFF7BC00
 DRIVER.GIO.VAR.GIO_PORT1_BIT3_LVL.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT1_ENA.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT1_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT4_PDR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT3_POL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULL.VALUE=2
 DRIVER.GIO.VAR.GIO_PORT0_BIT1_DIR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT5_DOUT.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=1
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT7_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULDIS.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT3_PSL.VALUE=0
@@ -1630,9 +1630,9 @@
 DRIVER.GIO.VAR.GIO_PORT0_BIT2_ENA.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT5_PDR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT1_BIT4_POL.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT0_BIT0_DOUT.VALUE=0
-DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=0
+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=1
 DRIVER.GIO.VAR.GIO_PORT1_BIT4_PSL.VALUE=0
 DRIVER.GIO.VAR.GIO_PORT0_BIT0_PDR.VALUE=0
 DRIVER.GIO.VAR.GIO_PORTB_ENABLE.VALUE=1
@@ -1846,7 +1846,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF
 DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0
@@ -1855,17 +1855,17 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3
+DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_NONE
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4
 DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1
@@ -1914,7 +1914,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1003.252
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1003.252
 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0
@@ -1932,7 +1932,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=20
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=9.677
@@ -1960,7 +1960,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6
+DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_NONE
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18
@@ -1988,7 +1988,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_USE_CS_ENCODE.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_TG4_CS_ENCODE.VALUE=0xFF
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0
@@ -2086,10 +2086,10 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16
 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2
+DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_NONE
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD_LASTBUF.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818
 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4
@@ -2151,8 +2151,8 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3
 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED
 DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2
@@ -2162,20 +2162,20 @@
 DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4
 DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000
-DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF
 DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5
+DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_NONE
 DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0
@@ -2248,13 +2248,13 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2
 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6
 DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS
 DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4
 DRIVER.MIBSPI.VAR.MIBSPI1_TG0_CS_ENCODE.VALUE=0xFF
@@ -2311,7 +2311,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1
-DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1
+DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_NONE
 DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED
@@ -2336,7 +2336,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED
 DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=11
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF
@@ -2411,7 +2411,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005
 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4
+DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_NONE
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0
@@ -2431,15 +2431,15 @@
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000
 DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED
-DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF
 DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED
 DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0
@@ -2477,7 +2477,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS
 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF
@@ -2511,7 +2511,7 @@
 DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=19.355
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7
+DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_NONE
 DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0
@@ -2558,18 +2558,18 @@
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=102
-DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16
+DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=8
 DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1003.252
 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=102
 DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16
-DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0
+DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=1
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0
-DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0
+DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_1
 DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16
 DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0
 DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16
@@ -2590,7 +2590,7 @@
 DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0
 DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0
 DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2
-DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=0
 DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0
 DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0
 DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0
@@ -2912,7 +2912,7 @@
 DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1003.252
 DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0
 DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1003.252
-DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=0
 DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1
 DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2
 DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1003.252
@@ -2958,7 +2958,7 @@
 DRIVER.SPI.VAR.SPI5_PORT_BIT27_DOUT.VALUE=0
 DRIVER.SPI.VAR.SPI5_PORT_BIT19_DOUT.VALUE=0
 DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1
-DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=0
 DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2
 DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0
 DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0
@@ -2977,7 +2977,7 @@
 DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16
 DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1
 DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2
-DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=0
 DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0
 DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0
 DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0
@@ -3265,7 +3265,7 @@
 DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0
 DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0
 DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0
-DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1
+DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=0
 DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0
 DRIVER.SPI.VAR.SPI1_PORT_BIT5_FUN.VALUE=1
 DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0
@@ -3299,8 +3299,8 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000
@@ -3310,7 +3310,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005
 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8
@@ -3414,10 +3414,10 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000200
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000
@@ -3433,7 +3433,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00002000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00
@@ -3459,7 +3459,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32
 DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24
 DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16
-DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000002
 DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8
@@ -3588,7 +3588,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2
-DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000040
 DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=9
 DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8
@@ -3610,7 +3610,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000800
 DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51
@@ -3758,7 +3758,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0
@@ -3767,7 +3767,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54
 DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46
 DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38
-DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000800
 DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=9
 DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8
@@ -3779,7 +3779,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0
@@ -3852,7 +3852,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_TQ.VALUE=222.577
-DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7
 DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000
@@ -3898,7 +3898,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF
@@ -3910,7 +3910,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF
-DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_3_MESSAGE_64_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_56_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_48_RTR.VALUE=0x00000000
@@ -3919,7 +3919,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=0x200
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=0x403
 DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8
@@ -3952,7 +3952,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_30_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_14_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000010
 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75
@@ -4001,7 +4001,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1
 DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000800
 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1
 DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58
@@ -4019,7 +4019,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000
@@ -4086,7 +4086,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_28_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000001
-DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=18
+DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF
@@ -4104,7 +4104,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x000007FF
+DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF
 DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000
@@ -4114,7 +4114,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_6_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21
 DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13
-DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000200
 DRIVER.CAN.VAR.CAN_2_MESSAGE_40_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_32_EOB.VALUE=0x00000000
@@ -4158,7 +4158,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF
@@ -4250,7 +4250,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x80000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1
@@ -4267,7 +4267,7 @@
 DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=77.778
 DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=1
 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000001
 DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005
@@ -4318,7 +4318,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_25_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_17_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00004000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8
@@ -4358,7 +4358,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33
 DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25
 DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17
-DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000004
 DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_50_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000
@@ -4384,7 +4384,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_1_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=0x002
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=0x1
 DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8
@@ -4396,7 +4396,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0
@@ -4440,8 +4440,8 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_34_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_26_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_18_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=0x008
-DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=103
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=0x2
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8
@@ -4503,16 +4503,16 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11
 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=0x010
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=0x4
 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8
@@ -4574,13 +4574,13 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_35_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_27_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_19_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=0x080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=0x8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8
-DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=996.758
+DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000
 DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_64_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000
@@ -4609,7 +4609,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000400
+DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000800
 DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=1
 DRIVER.CAN.VAR.CAN_2_MESSAGE_31_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_23_RTR.VALUE=0x00000000
@@ -4645,14 +4645,14 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF
-DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21
 DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13
 DRIVER.CAN.VAR.CAN_3_MESSAGE_11_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=0x402
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=0x10
 DRIVER.CAN.VAR.CAN_1_MESSAGE_3_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8
@@ -4721,7 +4721,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=0x403
+DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=0x40
 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8
@@ -4760,7 +4760,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47
 DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00001000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_61_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000
@@ -4782,7 +4782,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31
 DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23
 DRIVER.CAN.VAR.CAN_3_MESSAGE_20_RTR.VALUE=0x00000000
@@ -4791,7 +4791,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1
-DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=0x40
+DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=0x80
 DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000
@@ -4843,7 +4843,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40
 DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32
 DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24
@@ -4853,7 +4853,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_45_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_37_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_29_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=0x80
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=0x200
 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8
@@ -4928,7 +4928,7 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=0x100
+DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=0x402
 DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_SJW.VALUE=3
@@ -4963,19 +4963,19 @@
 DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF
-DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_1_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58
-DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000020
 DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8
-DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=1000
+DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_6_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000
@@ -4988,7 +4988,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=1
-DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000800
+DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50
 DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42
 DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34
@@ -5177,7 +5177,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_23_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_15_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000400
 DRIVER.CAN.VAR.CAN_1_MESSAGE_7_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_SJW.VALUE=2
 DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8
@@ -5204,7 +5204,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x80000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_3_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2
@@ -5213,7 +5213,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000080
-DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=66.667
 DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0
@@ -5324,8 +5324,8 @@
 DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=1
 DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000080
+DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0
@@ -5341,7 +5341,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_57_RTR.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_49_RTR.VALUE=0x00000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000008
 DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8
@@ -5429,7 +5429,7 @@
 DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_EOB.VALUE=0x00000000
 DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000
-DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000080
 DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000
 DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF
@@ -5474,7 +5474,7 @@
 DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20
 DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12
 DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7
-DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000100
 DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8
 DRIVER.CAN.VAR.CAN_2_MESSAGE_59_EOB.VALUE=0x00000000
@@ -5498,7 +5498,7 @@
 DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0
 DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF
-DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0
+DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=1
 DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF
 DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59
 DRIVER.CAN.VAR.CAN_3_MESSAGE_50_RTR.VALUE=0x00000000
@@ -5553,12 +5553,12 @@
 DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
-DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=6
 DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=2
-DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=6
 DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=3.271
 DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0
 DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000
@@ -5575,21 +5575,21 @@
 DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=387.08
 DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=2
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00040000
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_BND.VALUE=2
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=2
+DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=0
 DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULDIS.VALUE=0
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00
-DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300
+DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000020
+DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=503.22
+DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=3.271
 DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT
@@ -5615,15 +5615,15 @@
 DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000
 DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=300.00
 DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16
-DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=2
+DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=0
 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULDIS.VALUE=0
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=387.08
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00010000
+DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=503.22
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_PORT_BIT0_PSL.VALUE=1
@@ -5642,7 +5642,7 @@
 DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000
 DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8
 DRIVER.ADC.VAR.ADC1_PORT_BIT0_DOUT.VALUE=0
-DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000
+DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=241.932
 DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT
 DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16
 DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000
@@ -5658,7 +5658,7 @@
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005
-DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=96.77
+DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=251.61
 DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000
@@ -5673,7 +5673,7 @@
 DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=32
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000
 DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000
@@ -5682,8 +5682,8 @@
 DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT
 DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=387.08
-DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32
-DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8
+DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=58
+DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=0
 DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000
 DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000
@@ -5701,9 +5701,9 @@
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8
+DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=3
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00080000
 DRIVER.ADC.VAR.ADC2_PORT_BIT0_DOUT.VALUE=0
 DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00
 DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
@@ -5726,25 +5726,25 @@
 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0
 DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300
-DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=3.271
+DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=0
 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2
-DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16
+DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=0
 DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300
 DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0
-DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=387.08
+DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=503.22
 DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000
 DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT
-DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000
-DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=22.887252
+DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=503.22
 DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
 DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1
-DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00
+DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=503.22
 DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16
 DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000
@@ -5754,25 +5754,25 @@
 DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00020000
 DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00
+DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=250
 DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000080
 DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00
 DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
-DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000
+DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000001
 DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00
 DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000
-DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0
+DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=6
 DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1
 DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
@@ -5796,7 +5796,7 @@
 DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=9
+DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=25
 DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=387.08
 DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0
 DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULL.VALUE=2
@@ -5809,7 +5809,7 @@
 DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000
-DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=387.08
+DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=503.22
 DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000
 DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000
 DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000
@@ -5896,7 +5896,7 @@
 DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000
 DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=103296
 DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000
-DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1
+DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=2
 DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0
 DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000
@@ -6379,7 +6379,7 @@
 DRIVER.HET.VAR.HET2_PWM7_DUTY_LVL.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_EDGE0_BOTH.VALUE=0
 DRIVER.HET.VAR.HET1_BIT30_DIR.VALUE=0x00000000
-DRIVER.HET.VAR.HET1_BIT22_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_DIR.VALUE=0x00400000
 DRIVER.HET.VAR.HET1_BIT14_DIR.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_INT_X0.VALUE=0x00000000
 DRIVER.HET.VAR.HET2_EDGE2_POLARITY.VALUE=0
@@ -6455,7 +6455,7 @@
 DRIVER.HET.VAR.HET1_BIT21_PDR.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_BIT13_PDR.VALUE=0x00000000
 DRIVER.HET.VAR.HET2_PWM2_PERIOD_LVL.VALUE=0x00000000
-DRIVER.HET.VAR.HET2_BIT0_DIR.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_DIR.VALUE=0x00000001
 DRIVER.HET.VAR.HET1_PWM3_DUTY_PRESCALER.VALUE=51968
 DRIVER.HET.VAR.HET2_CAP3_POLARITY.VALUE=0
 DRIVER.HET.VAR.HET2_BIT0_PULDIS.VALUE=0x00000000
@@ -6547,7 +6547,7 @@
 DRIVER.HET.VAR.HET2_BIT0_PDR.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_PWM4_PERIOD.VALUE=1000.000
 DRIVER.HET.VAR.HET1_BIT30_PSL.VALUE=0x00000000
-DRIVER.HET.VAR.HET1_BIT22_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET1_BIT22_PSL.VALUE=0x00400000
 DRIVER.HET.VAR.HET1_BIT14_PSL.VALUE=0x00000000
 DRIVER.HET.VAR.HET2_EDGE1_LVL.VALUE=0x00000000
 DRIVER.HET.VAR.HET2_PWM7_PERIOD_LVL.VALUE=0x00000000
@@ -6596,7 +6596,7 @@
 DRIVER.HET.VAR.HET1_PWM4_DUTY_LVL.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_BIT30_PULL.VALUE=1
 DRIVER.HET.VAR.HET1_BIT27_DIR.VALUE=0x00000000
-DRIVER.HET.VAR.HET1_BIT22_PULL.VALUE=1
+DRIVER.HET.VAR.HET1_BIT22_PULL.VALUE=2
 DRIVER.HET.VAR.HET1_BIT19_DIR.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_BIT14_PULL.VALUE=1
 DRIVER.HET.VAR.HET2_EDGE2_INTENA.VALUE=0x00000000
@@ -6613,7 +6613,7 @@
 DRIVER.HET.VAR.HET2_BIT14_ANDSHARE.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_BIT2_PULDIS.VALUE=0x00000000
 DRIVER.HET.VAR.HET2_PWM5_PERIOD.VALUE=1000.000
-DRIVER.HET.VAR.HET2_BIT0_PSL.VALUE=0x00000000
+DRIVER.HET.VAR.HET2_BIT0_PSL.VALUE=0x00000001
 DRIVER.HET.VAR.HET1_PWM5_PIN_SELECT.VALUE=17
 DRIVER.HET.VAR.HET1_BIT25_PDR.VALUE=0x00000000
 DRIVER.HET.VAR.HET1_BIT17_PDR.VALUE=0x00000000
@@ -7125,7 +7125,7 @@
 DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0
-DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=1
 DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0
 DRIVER.PINMUX.VAR.DMA_FIDXD_30.VALUE=0
 DRIVER.PINMUX.VAR.DMA_FIDXD_22.VALUE=0
@@ -7207,7 +7207,7 @@
 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_24.VALUE=0
 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_16.VALUE=0
 DRIVER.PINMUX.VAR.DMA_INTLFSEN_12.VALUE=1
-DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.DMA_FIDXD_29.VALUE=0
@@ -7253,7 +7253,7 @@
 DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0
 DRIVER.PINMUX.VAR.DMA_INTBTCEN_14.VALUE=1
 DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=1
 DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0
@@ -7272,7 +7272,7 @@
 DRIVER.PINMUX.VAR.DMA_ENABLEINT_4.VALUE=1
 DRIVER.PINMUX.VAR.PINMUX10.VALUE=PINMUX_PIN_86_AD1EVT
 DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=2
 DRIVER.PINMUX.VAR.DMA_PRITY_11.VALUE=FIXED
 DRIVER.PINMUX.VAR.DMA_CHPR_10_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_PRITY_1_VALUE.VALUE=0x0001
@@ -7297,15 +7297,15 @@
 DRIVER.PINMUX.VAR.DMA_PRITY_16.VALUE=FIXED
 DRIVER.PINMUX.VAR.PINMUX33.VALUE="PINMUX_PIN_36_HET1_04 | PINMUX_PIN_51_MIBSPI3SOMI | PINMUX_PIN_52_MIBSPI3SIMO | PINMUX_PIN_53_MIBSPI3CLK"
 DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_PIN_118_HET1_10 | PINMUX_PIN_124_HET1_12"
-DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_HET1_18 | PINMUX_PIN_141_HET1_20"
+DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_ETPWM6A | PINMUX_PIN_141_HET1_20"
 DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_PIN_125_HET1_14 | PINMUX_PIN_126_GIOB_0"
 DRIVER.PINMUX.VAR.DMA_ADDMR_26_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_CHANNEL_20_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMR_18_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_CHANNEL_12_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_10_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.PINMUX35.VALUE=0
-DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_PIN_32_MIBSPI5NCS_0
+DRIVER.PINMUX.VAR.PINMUX27.VALUE=PINMUX_PIN_32_ETPWM4A
 DRIVER.PINMUX.VAR.PINMUX19.VALUE=PINMUX_PIN_127_HET1_30
 DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0
@@ -7407,7 +7407,7 @@
 DRIVER.PINMUX.VAR.DMA_FIDXS_7.VALUE=0
 DRIVER.PINMUX.VAR.DMA_AIM_7.VALUE=ENABLED
 DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0
-DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=1
 DRIVER.PINMUX.VAR.DMA_FIDXS_8.VALUE=0
 DRIVER.PINMUX.VAR.DMA_AIM_8.VALUE=ENABLED
 DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0
@@ -7424,7 +7424,7 @@
 DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0
-DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0
@@ -7497,7 +7497,7 @@
 DRIVER.PINMUX.VAR.DMA_TTYPE_16.VALUE=FRAME_TRANSFER
 DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_16.VALUE=0
 DRIVER.PINMUX.VAR.DMA_STADD_2.VALUE=0
-DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.DMA_TTYPE_25.VALUE=FRAME_TRANSFER
 DRIVER.PINMUX.VAR.DMA_CP0_IDADDR_25.VALUE=0
@@ -7651,7 +7651,7 @@
 DRIVER.PINMUX.VAR.MUX74_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX66_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX58_OPTION4.VALUE=0
-DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX5_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.DMA_ADDMW_3.VALUE=CONSTANT
 DRIVER.PINMUX.VAR.MUX58_OPTION5.VALUE=0
 DRIVER.PINMUX.VAR.MUX5_OPTION1.VALUE=0
@@ -7670,7 +7670,7 @@
 DRIVER.PINMUX.VAR.MUX51_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX43_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX35_OPTION0.VALUE=0
-DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX27_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX19_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX5_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.DMA_ADDMW_7.VALUE=CONSTANT
@@ -7694,7 +7694,7 @@
 DRIVER.PINMUX.VAR.MUX19_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.MUX17_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_99_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_8_SELECT.VALUE=2
 DRIVER.PINMUX.VAR.DMA_ADDMR_27_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_CHANNEL_21_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMR_19_VALUE.VALUE=0x0001
@@ -7714,7 +7714,7 @@
 DRIVER.PINMUX.VAR.MUX43_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX35_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX27_OPTION4.VALUE=0
-DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=0
+DRIVER.PINMUX.VAR.MUX19_OPTION4.VALUE=1
 DRIVER.PINMUX.VAR.DMA_INTEN_13.VALUE=1
 DRIVER.PINMUX.VAR.DMA_INTFTCEN_7.VALUE=1
 DRIVER.PINMUX.VAR.MUX51_OPTION5.VALUE=0
@@ -7746,7 +7746,7 @@
 DRIVER.PINMUX.VAR.PIN_MUX_53_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_45_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_37_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_29_SELECT.VALUE=1
 DRIVER.PINMUX.VAR.DMA_TTYPE_7_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.MUX20_OPTION3.VALUE=0
 DRIVER.PINMUX.VAR.MUX12_OPTION3.VALUE=0
@@ -7945,13 +7945,13 @@
 DRIVER.PINMUX.VAR.MUX50_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX42_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX34_OPTION0.VALUE=0
-DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX26_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.MUX18_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX4_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.DMA_IFT_COUNT_7.VALUE=0
 DRIVER.PINMUX.VAR.DMA_BYP_13.VALUE=1
 DRIVER.PINMUX.VAR.DMA_INTBTCEN_3.VALUE=1
-DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX50_OPTION1.VALUE=1
 DRIVER.PINMUX.VAR.MUX42_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX34_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX26_OPTION1.VALUE=0
@@ -7967,7 +7967,7 @@
 DRIVER.PINMUX.VAR.MUX18_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_97_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_89_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_6_SELECT.VALUE=1
 DRIVER.PINMUX.VAR.DMA_ADDMR_31_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMR_23_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMR_15_VALUE.VALUE=0x0001
@@ -8015,12 +8015,12 @@
 DRIVER.PINMUX.VAR.DMA_PRITY_8.VALUE=FIXED
 DRIVER.PINMUX.VAR.MUX21_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.MUX13_CONFLICT.VALUE=0
-DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX11_OPTION2.VALUE=1
 DRIVER.PINMUX.VAR.PIN_MUX_51_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_43_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_35_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_27_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_19_SELECT.VALUE=4
 DRIVER.PINMUX.VAR.DMA_TTYPE_3_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_PRITY_9.VALUE=FIXED
 DRIVER.PINMUX.VAR.MUX11_OPTION3.VALUE=0
@@ -8198,7 +8198,7 @@
 DRIVER.PINMUX.VAR.MUX41_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX33_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX25_OPTION1.VALUE=0
-DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=0
+DRIVER.PINMUX.VAR.MUX17_OPTION1.VALUE=1
 DRIVER.PINMUX.VAR.MUX3_OPTION5.VALUE=0
 DRIVER.PINMUX.VAR.DMA_ADDMR_30.VALUE=CONSTANT
 DRIVER.PINMUX.VAR.DMA_EIDXD_26.VALUE=0
@@ -8276,14 +8276,14 @@
 DRIVER.PINMUX.VAR.DMA_INTMP_12_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_CHPR_6_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_TRIG_2_VALUE.VALUE=0x0001
-DRIVER.PINMUX.VAR.GIOA.VALUE=0
+DRIVER.PINMUX.VAR.GIOA.VALUE=1
 DRIVER.PINMUX.VAR.DMA_ADDMR_28.VALUE=CONSTANT
 DRIVER.PINMUX.VAR.DMA_IET_COUNT_24.VALUE=0
 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_20.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_IET_COUNT_16.VALUE=0
 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_12.VALUE=8BIT
 DRIVER.PINMUX.VAR.GIOB.VALUE=0
-DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX10_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.DMA_ADDMR_29.VALUE=CONSTANT
 DRIVER.PINMUX.VAR.DMA_IET_COUNT_25.VALUE=0
 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_21.VALUE=8BIT
@@ -8300,7 +8300,7 @@
 DRIVER.PINMUX.VAR.PIN_MUX_41_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_33_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_25_SELECT.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_17_SELECT.VALUE=1
 DRIVER.PINMUX.VAR.DMA_WRITE_ELSIZE_31.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_IET_COUNT_27.VALUE=0
@@ -8350,15 +8350,15 @@
 DRIVER.PINMUX.VAR.DMA_BYP_9.VALUE=1
 DRIVER.PINMUX.VAR.MIBSPI1.VALUE=0
 DRIVER.PINMUX.VAR.MUX103_OPTION0.VALUE=0
-DRIVER.PINMUX.VAR.MIBSPI3.VALUE=0
+DRIVER.PINMUX.VAR.MIBSPI3.VALUE=1
 DRIVER.PINMUX.VAR.MUX103_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.OHCI0.VALUE=0
 DRIVER.PINMUX.VAR.MUX103_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.DMA_ADDMW_9_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_TRIG_7_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.MIBSPI5.VALUE=0
 DRIVER.PINMUX.VAR.DMM.VALUE=0
-DRIVER.PINMUX.VAR.W2FC.VALUE=0
+DRIVER.PINMUX.VAR.W2FC.VALUE=1
 DRIVER.PINMUX.VAR.OHCI1.VALUE=0
 DRIVER.PINMUX.VAR.MUX103_OPTION3.VALUE=0
 DRIVER.PINMUX.VAR.MUX103_OPTION4.VALUE=0
@@ -8384,7 +8384,7 @@
 DRIVER.PINMUX.VAR.MUX9_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.DMA_EIDXD_0.VALUE=0
 DRIVER.PINMUX.VAR.DMA_CHPR_10.VALUE=HIGH
-DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX9_OPTION2.VALUE=1
 DRIVER.PINMUX.VAR.PIN_MUX_101_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12_VALUE.VALUE=0x0001
@@ -8449,7 +8449,7 @@
 DRIVER.PINMUX.VAR.MUX55_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX47_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX39_OPTION4.VALUE=0
-DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX2_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.DMA_ADDMW_21.VALUE=CONSTANT
 DRIVER.PINMUX.VAR.DMA_ADDMW_13.VALUE=CONSTANT
 DRIVER.PINMUX.VAR.DMA_EIDXD_7.VALUE=0
@@ -8466,7 +8466,7 @@
 DRIVER.PINMUX.VAR.DMA_IET_COUNT_4.VALUE=0
 DRIVER.PINMUX.VAR.DMA_TRIG_10.VALUE=HARDWARE_TRIGGER
 DRIVER.PINMUX.VAR.MUX2_OPTION2.VALUE=0
-DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_9_SELECT.VALUE=2
 DRIVER.PINMUX.VAR.DMA_ADDMW_31.VALUE=CONSTANT
 DRIVER.PINMUX.VAR.DMA_CHANNEL_31_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMR_29_VALUE.VALUE=0x0001
@@ -8561,7 +8561,7 @@
 DRIVER.PINMUX.VAR.MUX12_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_31_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_23_SELECT.VALUE=1
-DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=0
+DRIVER.PINMUX.VAR.PIN_MUX_15_SELECT.VALUE=2
 DRIVER.PINMUX.VAR.DMA_ADDMW_30_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_25_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ADDMW_22_VALUE.VALUE=0x0001
@@ -8641,7 +8641,7 @@
 DRIVER.PINMUX.VAR.DMA_INTMP_5.VALUE=GROUP_A
 DRIVER.PINMUX.VAR.DMA_TRIG_3_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ACC_1.VALUE=ALL
-DRIVER.PINMUX.VAR.ETPWM.VALUE=0
+DRIVER.PINMUX.VAR.ETPWM.VALUE=1
 DRIVER.PINMUX.VAR.MUX102_OPTION3.VALUE=0
 DRIVER.PINMUX.VAR.DMA_INTMP_6.VALUE=GROUP_A
 DRIVER.PINMUX.VAR.DMA_ACC_2.VALUE=ALL
@@ -8685,7 +8685,7 @@
 DRIVER.PINMUX.VAR.MUX69_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX8_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX8_OPTION1.VALUE=0
-DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX8_OPTION2.VALUE=1
 DRIVER.PINMUX.VAR.DMA_BASE.VALUE=0xFFFFF000
 DRIVER.PINMUX.VAR.MUX8_OPTION3.VALUE=0
 DRIVER.PINMUX.VAR.MUX70_OPTION0.VALUE=0
@@ -8744,7 +8744,7 @@
 DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0
-DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0
+DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=1
 DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0
 DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0
@@ -8830,11 +8830,11 @@
 DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_MIBSPI3NCS_3 | PINMUX_PIN_4_MIBSPI3NCS_2"
 DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.DMA_INTLFSEN_7.VALUE=1
-DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_HET1_11"
+DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_MIBSPI3NCS_4"
 DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_10.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_INTLFSEN_8.VALUE=1
-DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5"
+DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_ETPWM1A"
 DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0
 DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0
@@ -8846,24 +8846,24 @@
 DRIVER.PINMUX.VAR.DMA_INTLFSEN_9.VALUE=1
 DRIVER.PINMUX.VAR.DMA_INTMP_5_VALUE.VALUE=0x0001
 DRIVER.PINMUX.VAR.DMA_ACC_1_VALUE.VALUE=0x0001
-DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_PIN_15_HET1_22 | PINMUX_PIN_16_GIOA_6"
+DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_PIN_15_W2FC_SE0O | PINMUX_PIN_16_GIOA_6"
 DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_20.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_12.VALUE=8BIT
 DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12
-DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03"
+DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_PIN_22_ETPWM2A | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03"
 DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0
 DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_21.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_13.VALUE=8BIT
-DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05"
+DRIVER.PINMUX.VAR.PINMUX5.VALUE="PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_HET1_05"
 DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_30.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_22.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_14.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_EIDXS_10.VALUE=0
 DRIVER.PINMUX.VAR.DMA_CHANNEL_0.VALUE=CHANNEL0
-DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09"
+DRIVER.PINMUX.VAR.PINMUX6.VALUE="PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A"
 DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_31.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_23.VALUE=8BIT
@@ -8892,7 +8892,7 @@
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_17.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_EIDXS_13.VALUE=0
 DRIVER.PINMUX.VAR.DMA_CHANNEL_3.VALUE=CHANNEL0
-DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_PIN_54_MIBSPI3NENA | PINMUX_PIN_55_MIBSPI3NCS_0"
+DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_PIN_54_MIBSPI3NCS_5 | PINMUX_PIN_55_MIBSPI3NCS_0"
 DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0
 DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0
@@ -8936,7 +8936,7 @@
 DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0
 DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0
-DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0
+DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=1
 DRIVER.PINMUX.VAR.DMA_READ_ELSIZE_29.VALUE=8BIT
 DRIVER.PINMUX.VAR.DMA_EIDXS_25.VALUE=0
 DRIVER.PINMUX.VAR.DMA_EIDXS_17.VALUE=0
@@ -9348,19 +9348,19 @@
 DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0
 DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100
-DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=1000
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=1000.000
-DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=50
-DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_SOCA_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_INPUT.VALUE=PWMA_RED_FED
 DRIVER.ETPWM.VAR.ETPWM7_BASE.VALUE=0xFCF79200
-DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=80.000
+DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=103.335
 DRIVER.ETPWM.VAR.ETPWM6_DCBEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM6_DCBEVT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCA.VALUE=0x0000
@@ -9369,61 +9369,61 @@
 DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0
 DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=1000
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
-DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY.VALUE=50
 DRIVER.ETPWM.VAR.ETPWM5_DCAEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_DCAEVT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=50.000
-DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_PWMB_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=503.218
 DRIVER.ETPWM.VAR.ETPWM3_CBC.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=80.000
+DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=103.335
 DRIVER.ETPWM.VAR.ETPWM1_FDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_OSHT4.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_OSHT5.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_OSHT6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_INPUT.VALUE=PWMA_RED_FED
@@ -9435,12 +9435,12 @@
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
@@ -9459,17 +9459,17 @@
 DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
 DRIVER.ETPWM.VAR.ETPWM6_FDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_RDELAY_SOURCE.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=50.000
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=38.709
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT
 DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=50
-DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED
 DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000
@@ -9481,37 +9481,37 @@
 DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3
 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000
 DRIVER.ETPWM.VAR.ETPWM4_DCAEVT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=80.000
+DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=103.335
 DRIVER.ETPWM.VAR.ETPWM3_TB_FREQUENCY.VALUE=110.000
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3
 DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50
-DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_OSHT3.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_OSHT4.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME_REG.VALUE=3
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_POLARITY.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
-DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=500.000
-DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=1000.000
-DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=50.000
-DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=250000
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_SOCA_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_OUT.VALUE=0
@@ -9522,12 +9522,12 @@
 DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_PWMA_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM7_OSHT1.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=50
-DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=1000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM7_OSHT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM7_CBC.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_OSHT3.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_CBC1.VALUE=0x0000
@@ -9537,40 +9537,40 @@
 DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=1000.000
-DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_CLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CBC6.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_INPUT.VALUE=PWMA_RED_FED
 DRIVER.ETPWM.VAR.ETPWM6_INTERRUPT_PERIOD.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_OUT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCA.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM1_BASE.VALUE=0xFCF78C00
 DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
-DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=80.000
-DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=103.335
+DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM6_SOCB_PERIOD.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=50.000
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=38.709
 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD_REG.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_DCAEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_DCAEVT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_OST.VALUE=0x0000
@@ -9579,15 +9579,15 @@
 DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCB.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_PWMA_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
-DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=500.000
-DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=1000
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=503.218
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM4_PWMA_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_POLARITY.VALUE=0
@@ -9604,7 +9604,7 @@
 DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00
 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0
@@ -9615,36 +9615,36 @@
 DRIVER.ETPWM.VAR.ETPWM7_TB_FREQUENCY.VALUE=110.000
 DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCA.VALUE=DCAEVT1
 DRIVER.ETPWM.VAR.ETPWM3_OSHT3.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=50.000
+DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=38.709
 DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCB.VALUE=DCBEVT1
-DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM3_OSHT4.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH.VALUE=100
 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY.VALUE=50
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM3_OSHT5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=80.000
+DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=103.335
 DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM4_OST.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=500.000
-DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=0.000
+DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=1000
-DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=25833
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000
 DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1
 DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT
 DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1
-DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000
@@ -9655,7 +9655,7 @@
 DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000
@@ -9664,53 +9664,53 @@
 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY_NEW.VALUE=50.0
 DRIVER.ETPWM.VAR.ETPWM4_PWMA_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY.VALUE=50
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_FDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_BASE.VALUE=0xFCF78E00
-DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=50.000
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=38.709
 DRIVER.ETPWM.VAR.ETPWM2_RDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY.VALUE=9.091
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=1000.000
-DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=996.758
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT
-DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM7_SOCA_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_OST.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_OUT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_INVERT.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=80.000
+DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=103.335
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_INVERT.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
 DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000
 DRIVER.ETPWM.VAR.ETPWM3_CLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000
@@ -9719,19 +9719,19 @@
 DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0
 DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=50.000
-DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=38.709
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=100
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=50
-DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000
 DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED
-DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00
 DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
@@ -9743,33 +9743,33 @@
 DRIVER.ETPWM.VAR.ETPWM1_DCAEVT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_OSHT3.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_OSHT4.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=102
 DRIVER.ETPWM.VAR.ETPWM4_OSHT5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM4_OSHT6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCA.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=1000.000
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=250002.419
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
 DRIVER.ETPWM.VAR.ETPWM2_INTERRUPT_PERIOD.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM2_FDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY.VALUE=9.091
-DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=50
-DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=52
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME_REG.VALUE=3
 DRIVER.ETPWM.VAR.ETPWM1_DCBEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD.VALUE=100.000
 DRIVER.ETPWM.VAR.ETPWM1_DCBEVT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=80.000
+DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=103.335
 DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCA.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCB.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV.VALUE=0
@@ -9786,10 +9786,10 @@
 DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=1000
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=250002.419
 DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000
@@ -9799,86 +9799,86 @@
 DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50
 DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM7_DCAEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTY.VALUE=50
 DRIVER.ETPWM.VAR.ETPWM7_DCAEVT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM5_CLKDIV_REG.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL
 DRIVER.ETPWM.VAR.ETPWM1_INTERRUPT_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCA.VALUE=DCAEVT1
 DRIVER.ETPWM.VAR.ETPWM5_SELECT_EVENT.VALUE=NO_EVENT
 DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCB.VALUE=DCBEVT1
 DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH.VALUE=100
-DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=1
+DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM6_PWMA_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY_NEW.VALUE=50.0
-DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM7_DCBEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_MODE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_DCBEVT2.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=100.000
-DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=77.418
+DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM7_CBC1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM5_TB_FREQUENCY.VALUE=110.000
 DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCA.VALUE=DCAEVT1
 DRIVER.ETPWM.VAR.ETPWM7_CBC2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCB.VALUE=DCBEVT1
 DRIVER.ETPWM.VAR.ETPWM7_CBC3.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=1000
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=102
 DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY.VALUE=50
 DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM7_CBC4.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=100.000
+DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM7_CBC5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM7_CBC6.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_POLARITY.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=50
+DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=52
 DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=25833
 DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091
 DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100
-DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=0.000
 DRIVER.ETPWM.VAR.ETPWM6_PWMB_ENA.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM5_OSHT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY_REG.VALUE=1
-DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM5_OSHT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_INPUT.VALUE=PWMA_RED_FED
-DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=996.758
 DRIVER.ETPWM.VAR.ETPWM5_OSHT3.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_OSHT4.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM2_SELECT_EVENT.VALUE=NO_EVENT
 DRIVER.ETPWM.VAR.ETPWM5_OSHT5.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTY.VALUE=50
 DRIVER.ETPWM.VAR.ETPWM5_OSHT6.VALUE=0x0000
-DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=100
+DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=77.418
 DRIVER.ETPWM.VAR.ETPWM6_CLKDIV.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=0
+DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0
-DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=1000.000
+DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=250000
 DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000
 DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM6_SOCA_PERIOD.VALUE=1
 DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000
 DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0
 DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0
-DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=500.000
+DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=0.000
 DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0
 DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0
 DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000
Index: firmware/DG.hcg
===================================================================
diff -u -raa2d2d9c54eda4fbc18a3cdcba48222cd4b4177f -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/DG.hcg	(.../DG.hcg)	(revision aa2d2d9c54eda4fbc18a3cdcba48222cd4b4177f)
+++ firmware/DG.hcg	(.../DG.hcg)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -243,16 +243,16 @@
       <HDRMIBSPI>
         <NAME>mibspi.h</NAME>
       </HDRMIBSPI>
+      <SRCMIBSPI>
+        <NAME>mibspi.c</NAME>
+      </SRCMIBSPI>
       <HDRSPI_R>
         <NAME>reg_spi.h</NAME>
       </HDRSPI_R>
       <HDRSPI>
         <NAME>spi.h</NAME>
       </HDRSPI>
       <SRCSPI/>
-      <SRCMIBSPI>
-        <NAME>mibspi.c</NAME>
-      </SRCMIBSPI>
       <HDRCAN_R>
         <NAME>reg_can.h</NAME>
       </HDRCAN_R>
@@ -268,7 +268,9 @@
       <HDRADC>
         <NAME>adc.h</NAME>
       </HDRADC>
-      <SRCADC/>
+      <SRCADC>
+        <NAME>adc.c</NAME>
+      </SRCADC>
       <HET1ASMHDR>
         <NAME/>
       </HET1ASMHDR>
@@ -400,7 +402,9 @@
       <HDRETPWM>
         <NAME>etpwm.h</NAME>
       </HDRETPWM>
-      <SRCETPWM/>
+      <SRCETPWM>
+        <NAME>etpwm.c</NAME>
+      </SRCETPWM>
       <HDRECAP_R>
         <NAME>reg_ecap.h</NAME>
       </HDRECAP_R>
@@ -570,7 +574,7 @@
         <PATH>include\adc.h</PATH>
       </HDRADC>
       <SRCADC>
-        <PATH/>
+        <PATH>source\adc.c</PATH>
       </SRCADC>
     </FILENAMES>
   </ADC>
@@ -762,7 +766,7 @@
         <PATH>include\etpwm.h</PATH>
       </HDRETPWM>
       <SRCETPWM>
-        <PATH/>
+        <PATH>source\etpwm.c</PATH>
       </SRCETPWM>
     </FILENAMES>
   </ETPWM>
Index: firmware/Debug/App/Drivers/subdir_rules.mk
===================================================================
diff -u -r3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/App/Drivers/subdir_rules.mk	(.../subdir_rules.mk)	(revision 3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1)
+++ firmware/Debug/App/Drivers/subdir_rules.mk	(.../subdir_rules.mk)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -6,7 +6,7 @@
 App/Drivers/%.obj: ../App/Drivers/%.c $(GEN_OPTS) | $(GEN_FILES)
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: ARM Compiler'
-	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/workspace/dgfirmware/firmware/App" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Modes" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Services" --include_path="/home/fw/workspace/dgfirmware/firmware" --include_path="/home/fw/workspace/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="App/Drivers/$(basename $(<F)).d_raw" --obj_directory="App/Drivers" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/wsdg/dgfirmware/firmware/App" --include_path="/home/fw/wsdg/dgfirmware/firmware/Common" --include_path="/home/fw/wsdg/dgfirmware/firmware/FWCommon" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Modes" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Services" --include_path="/home/fw/wsdg/dgfirmware/firmware" --include_path="/home/fw/wsdg/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="App/Drivers/$(basename $(<F)).d_raw" --obj_directory="App/Drivers" $(GEN_OPTS__FLAG) "$(shell echo $<)"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
Index: firmware/Debug/App/Drivers/subdir_vars.mk
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/App/Drivers/subdir_vars.mk	(.../subdir_vars.mk)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/Debug/App/Drivers/subdir_vars.mk	(.../subdir_vars.mk)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -6,31 +6,37 @@
 C_SRCS += \
 ../App/Drivers/CPLD.c \
 ../App/Drivers/Comm.c \
+../App/Drivers/InternalADC.c \
 ../App/Drivers/SafetyShutdown.c 
 
 C_DEPS += \
 ./App/Drivers/CPLD.d \
 ./App/Drivers/Comm.d \
+./App/Drivers/InternalADC.d \
 ./App/Drivers/SafetyShutdown.d 
 
 OBJS += \
 ./App/Drivers/CPLD.obj \
 ./App/Drivers/Comm.obj \
+./App/Drivers/InternalADC.obj \
 ./App/Drivers/SafetyShutdown.obj 
 
 OBJS__QUOTED += \
 "App/Drivers/CPLD.obj" \
 "App/Drivers/Comm.obj" \
+"App/Drivers/InternalADC.obj" \
 "App/Drivers/SafetyShutdown.obj" 
 
 C_DEPS__QUOTED += \
 "App/Drivers/CPLD.d" \
 "App/Drivers/Comm.d" \
+"App/Drivers/InternalADC.d" \
 "App/Drivers/SafetyShutdown.d" 
 
 C_SRCS__QUOTED += \
 "../App/Drivers/CPLD.c" \
 "../App/Drivers/Comm.c" \
+"../App/Drivers/InternalADC.c" \
 "../App/Drivers/SafetyShutdown.c" 
 
 
Index: firmware/Debug/App/Modes/subdir_rules.mk
===================================================================
diff -u -r3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/App/Modes/subdir_rules.mk	(.../subdir_rules.mk)	(revision 3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1)
+++ firmware/Debug/App/Modes/subdir_rules.mk	(.../subdir_rules.mk)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -6,7 +6,7 @@
 App/Modes/%.obj: ../App/Modes/%.c $(GEN_OPTS) | $(GEN_FILES)
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: ARM Compiler'
-	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/workspace/dgfirmware/firmware/App" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Modes" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Services" --include_path="/home/fw/workspace/dgfirmware/firmware" --include_path="/home/fw/workspace/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="App/Modes/$(basename $(<F)).d_raw" --obj_directory="App/Modes" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/wsdg/dgfirmware/firmware/App" --include_path="/home/fw/wsdg/dgfirmware/firmware/Common" --include_path="/home/fw/wsdg/dgfirmware/firmware/FWCommon" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Modes" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Services" --include_path="/home/fw/wsdg/dgfirmware/firmware" --include_path="/home/fw/wsdg/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="App/Modes/$(basename $(<F)).d_raw" --obj_directory="App/Modes" $(GEN_OPTS__FLAG) "$(shell echo $<)"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
Index: firmware/Debug/App/Tasks/subdir_rules.mk
===================================================================
diff -u -r3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/App/Tasks/subdir_rules.mk	(.../subdir_rules.mk)	(revision 3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1)
+++ firmware/Debug/App/Tasks/subdir_rules.mk	(.../subdir_rules.mk)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -6,7 +6,7 @@
 App/Tasks/%.obj: ../App/Tasks/%.c $(GEN_OPTS) | $(GEN_FILES)
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: ARM Compiler'
-	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/workspace/dgfirmware/firmware/App" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Modes" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Services" --include_path="/home/fw/workspace/dgfirmware/firmware" --include_path="/home/fw/workspace/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="App/Tasks/$(basename $(<F)).d_raw" --obj_directory="App/Tasks" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/wsdg/dgfirmware/firmware/App" --include_path="/home/fw/wsdg/dgfirmware/firmware/Common" --include_path="/home/fw/wsdg/dgfirmware/firmware/FWCommon" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Modes" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Services" --include_path="/home/fw/wsdg/dgfirmware/firmware" --include_path="/home/fw/wsdg/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="App/Tasks/$(basename $(<F)).d_raw" --obj_directory="App/Tasks" $(GEN_OPTS__FLAG) "$(shell echo $<)"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
Index: firmware/Debug/ccsObjs.opt
===================================================================
diff -u -rdcbd821e41803adc6e582d909207bc97f85ff939 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/ccsObjs.opt	(.../ccsObjs.opt)	(revision dcbd821e41803adc6e582d909207bc97f85ff939)
+++ firmware/Debug/ccsObjs.opt	(.../ccsObjs.opt)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -1 +1 @@
-"./irqDispatch_a.obj" "./irqDispatch_c.obj" "./App/Controllers/AlarmLamp.obj" "./App/Drivers/CPLD.obj" "./App/Drivers/Comm.obj" "./App/Drivers/SafetyShutdown.obj" "./App/Modes/ModeDisinfect.obj" "./App/Modes/ModeDrain.obj" "./App/Modes/ModeFault.obj" "./App/Modes/ModeFill.obj" "./App/Modes/ModeFlush.obj" "./App/Modes/ModeInitPOST.obj" "./App/Modes/ModePostTreat.obj" "./App/Modes/ModeService.obj" "./App/Modes/ModeStandby.obj" "./App/Modes/OperationModes.obj" "./App/Services/CommBuffers.obj" "./App/Services/FPGA.obj" "./App/Services/Interrupts.obj" "./App/Services/MsgQueues.obj" "./App/Services/SystemComm.obj" "./App/Services/SystemCommMessages.obj" "./App/Services/Timers.obj" "./App/Services/Utilities.obj" "./App/Services/WatchdogMgmt.obj" "./App/Tasks/TaskBG.obj" "./App/Tasks/TaskGeneral.obj" "./App/Tasks/TaskPriority.obj" "./App/Tasks/TaskTimer.obj" "./source/can.obj" "./source/crc.obj" "./source/dabort.obj" "./source/ecap.obj" "./source/emac.obj" "./source/eqep.obj" "./source/errata_SSWF021_45.obj" "./source/esm.obj" "./source/etpwm.obj" "./source/gio.obj" "./source/lin.obj" "./source/mdio.obj" "./source/mibspi.obj" "./source/notification.obj" "./source/phy_dp83640.obj" "./source/pinmux.obj" "./source/rti.obj" "./source/sci.obj" "./source/sys_core.obj" "./source/sys_dma.obj" "./source/sys_intvecs.obj" "./source/sys_main.obj" "./source/sys_mpu.obj" "./source/sys_pcr.obj" "./source/sys_phantom.obj" "./source/sys_pmm.obj" "./source/sys_pmu.obj" "./source/sys_selftest.obj" "./source/sys_startup.obj" "./source/sys_vim.obj" "./source/system.obj" "../source/sys_link.cmd" -lrtsv7R4_T_le_v3D16_eabi.lib 
\ No newline at end of file
+"./irqDispatch_a.obj" "./irqDispatch_c.obj" "./App/Drivers/CPLD.obj" "./App/Drivers/Comm.obj" "./App/Drivers/InternalADC.obj" "./App/Drivers/SafetyShutdown.obj" "./App/Modes/ModeDisinfect.obj" "./App/Modes/ModeDrain.obj" "./App/Modes/ModeFault.obj" "./App/Modes/ModeFill.obj" "./App/Modes/ModeFlush.obj" "./App/Modes/ModeInitPOST.obj" "./App/Modes/ModePostTreat.obj" "./App/Modes/ModeService.obj" "./App/Modes/ModeStandby.obj" "./App/Modes/OperationModes.obj" "./App/Services/AlarmMgmt.obj" "./App/Services/CommBuffers.obj" "./App/Services/FPGA.obj" "./App/Services/Interrupts.obj" "./App/Services/MsgQueues.obj" "./App/Services/PIControllers.obj" "./App/Services/SystemComm.obj" "./App/Services/SystemCommMessages.obj" "./App/Services/Timers.obj" "./App/Services/Utilities.obj" "./App/Services/WatchdogMgmt.obj" "./App/Tasks/TaskBG.obj" "./App/Tasks/TaskGeneral.obj" "./App/Tasks/TaskPriority.obj" "./App/Tasks/TaskTimer.obj" "./FWCommon/RTC.obj" "./source/adc.obj" "./source/can.obj" "./source/crc.obj" "./source/dabort.obj" "./source/ecap.obj" "./source/emac.obj" "./source/eqep.obj" "./source/errata_SSWF021_45.obj" "./source/esm.obj" "./source/etpwm.obj" "./source/gio.obj" "./source/lin.obj" "./source/mdio.obj" "./source/mibspi.obj" "./source/notification.obj" "./source/phy_dp83640.obj" "./source/pinmux.obj" "./source/rti.obj" "./source/sci.obj" "./source/sys_core.obj" "./source/sys_dma.obj" "./source/sys_intvecs.obj" "./source/sys_main.obj" "./source/sys_mpu.obj" "./source/sys_pcr.obj" "./source/sys_phantom.obj" "./source/sys_pmm.obj" "./source/sys_pmu.obj" "./source/sys_selftest.obj" "./source/sys_startup.obj" "./source/sys_vim.obj" "./source/system.obj" "../source/sys_link.cmd" -lrtsv7R4_T_le_v3D16_eabi.lib 
\ No newline at end of file
Index: firmware/Debug/makefile
===================================================================
diff -u -rdcbd821e41803adc6e582d909207bc97f85ff939 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/makefile	(.../makefile)	(revision dcbd821e41803adc6e582d909207bc97f85ff939)
+++ firmware/Debug/makefile	(.../makefile)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -10,9 +10,9 @@
 ORDERED_OBJS += \
 "./irqDispatch_a.obj" \
 "./irqDispatch_c.obj" \
-"./App/Controllers/AlarmLamp.obj" \
 "./App/Drivers/CPLD.obj" \
 "./App/Drivers/Comm.obj" \
+"./App/Drivers/InternalADC.obj" \
 "./App/Drivers/SafetyShutdown.obj" \
 "./App/Modes/ModeDisinfect.obj" \
 "./App/Modes/ModeDrain.obj" \
@@ -24,10 +24,12 @@
 "./App/Modes/ModeService.obj" \
 "./App/Modes/ModeStandby.obj" \
 "./App/Modes/OperationModes.obj" \
+"./App/Services/AlarmMgmt.obj" \
 "./App/Services/CommBuffers.obj" \
 "./App/Services/FPGA.obj" \
 "./App/Services/Interrupts.obj" \
 "./App/Services/MsgQueues.obj" \
+"./App/Services/PIControllers.obj" \
 "./App/Services/SystemComm.obj" \
 "./App/Services/SystemCommMessages.obj" \
 "./App/Services/Timers.obj" \
@@ -37,6 +39,8 @@
 "./App/Tasks/TaskGeneral.obj" \
 "./App/Tasks/TaskPriority.obj" \
 "./App/Tasks/TaskTimer.obj" \
+"./FWCommon/RTC.obj" \
+"./source/adc.obj" \
 "./source/can.obj" \
 "./source/crc.obj" \
 "./source/dabort.obj" \
@@ -80,18 +84,18 @@
 # All of the sources participating in the build are defined here
 -include sources.mk
 -include subdir_vars.mk
--include App/Controllers/subdir_vars.mk
 -include App/Drivers/subdir_vars.mk
 -include App/Modes/subdir_vars.mk
 -include App/Services/subdir_vars.mk
 -include App/Tasks/subdir_vars.mk
+-include FWCommon/subdir_vars.mk
 -include source/subdir_vars.mk
 -include subdir_rules.mk
--include App/Controllers/subdir_rules.mk
 -include App/Drivers/subdir_rules.mk
 -include App/Modes/subdir_rules.mk
 -include App/Services/subdir_rules.mk
 -include App/Tasks/subdir_rules.mk
+-include FWCommon/subdir_rules.mk
 -include source/subdir_rules.mk
 -include objects.mk
 
@@ -223,10 +227,10 @@
 # Other Targets
 clean:
 	-$(RM) $(BIN_OUTPUTS__QUOTED)$(EXE_OUTPUTS__QUOTED)
-	-$(RM) "irqDispatch_a.obj" "irqDispatch_c.obj" "App/Controllers/AlarmLamp.obj" "App/Drivers/CPLD.obj" "App/Drivers/Comm.obj" "App/Drivers/SafetyShutdown.obj" "App/Modes/ModeDisinfect.obj" "App/Modes/ModeDrain.obj" "App/Modes/ModeFault.obj" "App/Modes/ModeFill.obj" "App/Modes/ModeFlush.obj" "App/Modes/ModeInitPOST.obj" "App/Modes/ModePostTreat.obj" "App/Modes/ModeService.obj" "App/Modes/ModeStandby.obj" "App/Modes/OperationModes.obj" "App/Services/CommBuffers.obj" "App/Services/FPGA.obj" "App/Services/Interrupts.obj" "App/Services/MsgQueues.obj" "App/Services/SystemComm.obj" "App/Services/SystemCommMessages.obj" "App/Services/Timers.obj" "App/Services/Utilities.obj" "App/Services/WatchdogMgmt.obj" "App/Tasks/TaskBG.obj" "App/Tasks/TaskGeneral.obj" "App/Tasks/TaskPriority.obj" "App/Tasks/TaskTimer.obj" "source/can.obj" "source/crc.obj" "source/dabort.obj" "source/ecap.obj" "source/emac.obj" "source/eqep.obj" "source/errata_SSWF021_45.obj" "source/esm.obj" "source/etpwm.obj" "source/gio.obj" "source/lin.obj" 
-	-$(RM) "source/mdio.obj" "source/mibspi.obj" "source/notification.obj" "source/phy_dp83640.obj" "source/pinmux.obj" "source/rti.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_dma.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_pcr.obj" "source/sys_phantom.obj" "source/sys_pmm.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/sys_vim.obj" "source/system.obj" 
-	-$(RM) "irqDispatch_c.d" "App/Controllers/AlarmLamp.d" "App/Drivers/CPLD.d" "App/Drivers/Comm.d" "App/Drivers/SafetyShutdown.d" "App/Modes/ModeDisinfect.d" "App/Modes/ModeDrain.d" "App/Modes/ModeFault.d" "App/Modes/ModeFill.d" "App/Modes/ModeFlush.d" "App/Modes/ModeInitPOST.d" "App/Modes/ModePostTreat.d" "App/Modes/ModeService.d" "App/Modes/ModeStandby.d" "App/Modes/OperationModes.d" "App/Services/CommBuffers.d" "App/Services/FPGA.d" "App/Services/Interrupts.d" "App/Services/MsgQueues.d" "App/Services/SystemComm.d" "App/Services/SystemCommMessages.d" "App/Services/Timers.d" "App/Services/Utilities.d" "App/Services/WatchdogMgmt.d" "App/Tasks/TaskBG.d" "App/Tasks/TaskGeneral.d" "App/Tasks/TaskPriority.d" "App/Tasks/TaskTimer.d" "source/can.d" "source/crc.d" "source/ecap.d" "source/emac.d" "source/eqep.d" "source/errata_SSWF021_45.d" "source/esm.d" "source/etpwm.d" "source/gio.d" "source/lin.d" "source/mdio.d" "source/mibspi.d" "source/notification.d" "source/phy_dp83640.d" "source/pinmux.d" "source/rti.d" 
-	-$(RM) "source/sci.d" "source/sys_dma.d" "source/sys_main.d" "source/sys_pcr.d" "source/sys_phantom.d" "source/sys_pmm.d" "source/sys_selftest.d" "source/sys_startup.d" "source/sys_vim.d" "source/system.d" 
+	-$(RM) "irqDispatch_a.obj" "irqDispatch_c.obj" "App/Drivers/CPLD.obj" "App/Drivers/Comm.obj" "App/Drivers/InternalADC.obj" "App/Drivers/SafetyShutdown.obj" "App/Modes/ModeDisinfect.obj" "App/Modes/ModeDrain.obj" "App/Modes/ModeFault.obj" "App/Modes/ModeFill.obj" "App/Modes/ModeFlush.obj" "App/Modes/ModeInitPOST.obj" "App/Modes/ModePostTreat.obj" "App/Modes/ModeService.obj" "App/Modes/ModeStandby.obj" "App/Modes/OperationModes.obj" "App/Services/AlarmMgmt.obj" "App/Services/CommBuffers.obj" "App/Services/FPGA.obj" "App/Services/Interrupts.obj" "App/Services/MsgQueues.obj" "App/Services/PIControllers.obj" "App/Services/SystemComm.obj" "App/Services/SystemCommMessages.obj" "App/Services/Timers.obj" "App/Services/Utilities.obj" "App/Services/WatchdogMgmt.obj" "App/Tasks/TaskBG.obj" "App/Tasks/TaskGeneral.obj" "App/Tasks/TaskPriority.obj" "App/Tasks/TaskTimer.obj" "FWCommon/RTC.obj" "source/adc.obj" "source/can.obj" "source/crc.obj" "source/dabort.obj" "source/ecap.obj" "source/emac.obj" "source/eqep.obj" 
+	-$(RM) "source/errata_SSWF021_45.obj" "source/esm.obj" "source/etpwm.obj" "source/gio.obj" "source/lin.obj" "source/mdio.obj" "source/mibspi.obj" "source/notification.obj" "source/phy_dp83640.obj" "source/pinmux.obj" "source/rti.obj" "source/sci.obj" "source/sys_core.obj" "source/sys_dma.obj" "source/sys_intvecs.obj" "source/sys_main.obj" "source/sys_mpu.obj" "source/sys_pcr.obj" "source/sys_phantom.obj" "source/sys_pmm.obj" "source/sys_pmu.obj" "source/sys_selftest.obj" "source/sys_startup.obj" "source/sys_vim.obj" "source/system.obj" 
+	-$(RM) "irqDispatch_c.d" "App/Drivers/CPLD.d" "App/Drivers/Comm.d" "App/Drivers/InternalADC.d" "App/Drivers/SafetyShutdown.d" "App/Modes/ModeDisinfect.d" "App/Modes/ModeDrain.d" "App/Modes/ModeFault.d" "App/Modes/ModeFill.d" "App/Modes/ModeFlush.d" "App/Modes/ModeInitPOST.d" "App/Modes/ModePostTreat.d" "App/Modes/ModeService.d" "App/Modes/ModeStandby.d" "App/Modes/OperationModes.d" "App/Services/AlarmMgmt.d" "App/Services/CommBuffers.d" "App/Services/FPGA.d" "App/Services/Interrupts.d" "App/Services/MsgQueues.d" "App/Services/PIControllers.d" "App/Services/SystemComm.d" "App/Services/SystemCommMessages.d" "App/Services/Timers.d" "App/Services/Utilities.d" "App/Services/WatchdogMgmt.d" "App/Tasks/TaskBG.d" "App/Tasks/TaskGeneral.d" "App/Tasks/TaskPriority.d" "App/Tasks/TaskTimer.d" "FWCommon/RTC.d" "source/adc.d" "source/can.d" "source/crc.d" "source/ecap.d" "source/emac.d" "source/eqep.d" "source/errata_SSWF021_45.d" "source/esm.d" "source/etpwm.d" "source/gio.d" "source/lin.d" "source/mdio.d" 
+	-$(RM) "source/mibspi.d" "source/notification.d" "source/phy_dp83640.d" "source/pinmux.d" "source/rti.d" "source/sci.d" "source/sys_dma.d" "source/sys_main.d" "source/sys_pcr.d" "source/sys_phantom.d" "source/sys_pmm.d" "source/sys_selftest.d" "source/sys_startup.d" "source/sys_vim.d" "source/system.d" 
 	-$(RM) "irqDispatch_a.d" "source/dabort.d" "source/sys_core.d" "source/sys_intvecs.d" "source/sys_mpu.d" "source/sys_pmu.d" 
 	-@echo 'Finished clean'
 	-@echo ' '
Index: firmware/Debug/source/subdir_rules.mk
===================================================================
diff -u -r3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/source/subdir_rules.mk	(.../subdir_rules.mk)	(revision 3fd6cf20cc9b436941e6f4f8e4c7507fa291f0c1)
+++ firmware/Debug/source/subdir_rules.mk	(.../subdir_rules.mk)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -6,14 +6,14 @@
 source/%.obj: ../source/%.c $(GEN_OPTS) | $(GEN_FILES)
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: ARM Compiler'
-	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/workspace/dgfirmware/firmware/App" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Modes" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Services" --include_path="/home/fw/workspace/dgfirmware/firmware" --include_path="/home/fw/workspace/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="source/$(basename $(<F)).d_raw" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/wsdg/dgfirmware/firmware/App" --include_path="/home/fw/wsdg/dgfirmware/firmware/Common" --include_path="/home/fw/wsdg/dgfirmware/firmware/FWCommon" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Modes" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Services" --include_path="/home/fw/wsdg/dgfirmware/firmware" --include_path="/home/fw/wsdg/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="source/$(basename $(<F)).d_raw" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
 source/%.obj: ../source/%.asm $(GEN_OPTS) | $(GEN_FILES)
 	@echo 'Building file: "$<"'
 	@echo 'Invoking: ARM Compiler'
-	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/workspace/dgfirmware/firmware/App" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Modes" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/workspace/dgfirmware/firmware/App/Services" --include_path="/home/fw/workspace/dgfirmware/firmware" --include_path="/home/fw/workspace/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="source/$(basename $(<F)).d_raw" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
+	"/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/bin/armcl" -mv7R4 --code_state=32 --float_support=VFPv3D16 -me --include_path="/home/fw/wsdg/dgfirmware/firmware/App" --include_path="/home/fw/wsdg/dgfirmware/firmware/Common" --include_path="/home/fw/wsdg/dgfirmware/firmware/FWCommon" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Tasks" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Modes" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Drivers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Controllers" --include_path="/home/fw/wsdg/dgfirmware/firmware/App/Services" --include_path="/home/fw/wsdg/dgfirmware/firmware" --include_path="/home/fw/wsdg/dgfirmware/firmware/include" --include_path="/home/fw/ti/ccs910/ccs/tools/compiler/ti-cgt-arm_18.12.2.LTS/include" --define=__TI_VIM_128CH__ -g --diag_warning=225 --diag_wrap=off --display_error_number --enum_type=packed --abi=eabi --preproc_with_compile --preproc_dependency="source/$(basename $(<F)).d_raw" --obj_directory="source" $(GEN_OPTS__FLAG) "$(shell echo $<)"
 	@echo 'Finished building: "$<"'
 	@echo ' '
 
Index: firmware/Debug/source/subdir_vars.mk
===================================================================
diff -u -raa2d2d9c54eda4fbc18a3cdcba48222cd4b4177f -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/source/subdir_vars.mk	(.../subdir_vars.mk)	(revision aa2d2d9c54eda4fbc18a3cdcba48222cd4b4177f)
+++ firmware/Debug/source/subdir_vars.mk	(.../subdir_vars.mk)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -14,6 +14,7 @@
 ../source/sys_pmu.asm 
 
 C_SRCS += \
+../source/adc.c \
 ../source/can.c \
 ../source/crc.c \
 ../source/ecap.c \
@@ -42,6 +43,7 @@
 ../source/system.c 
 
 C_DEPS += \
+./source/adc.d \
 ./source/can.d \
 ./source/crc.d \
 ./source/ecap.d \
@@ -70,6 +72,7 @@
 ./source/system.d 
 
 OBJS += \
+./source/adc.obj \
 ./source/can.obj \
 ./source/crc.obj \
 ./source/dabort.obj \
@@ -110,6 +113,7 @@
 ./source/sys_pmu.d 
 
 OBJS__QUOTED += \
+"source/adc.obj" \
 "source/can.obj" \
 "source/crc.obj" \
 "source/dabort.obj" \
@@ -143,6 +147,7 @@
 "source/system.obj" 
 
 C_DEPS__QUOTED += \
+"source/adc.d" \
 "source/can.d" \
 "source/crc.d" \
 "source/ecap.d" \
@@ -178,6 +183,7 @@
 "source/sys_pmu.d" 
 
 C_SRCS__QUOTED += \
+"../source/adc.c" \
 "../source/can.c" \
 "../source/crc.c" \
 "../source/ecap.c" \
Index: firmware/Debug/sources.mk
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/Debug/sources.mk	(.../sources.mk)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/Debug/sources.mk	(.../sources.mk)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -112,10 +112,10 @@
 # Every subdirectory with source files must be described here
 SUBDIRS := \
 . \
-App/Controllers \
 App/Drivers \
 App/Modes \
 App/Services \
 App/Tasks \
+FWCommon \
 source \
 
Index: firmware/include/adc.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/adc.h	(.../adc.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/adc.h	(.../adc.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -229,8 +229,31 @@
     uint32 CONFIG_PARCR;
 }adc_config_reg_t;
 
+#define ADC1_OPMODECR_CONFIGVALUE		0x81140001U
+#define ADC1_CLOCKCR_CONFIGVALUE		(25U)
 
+#define ADC1_G0MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U)
+#define ADC1_G1MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000020U | (uint32)0x00000000U | (uint32)0x00000000U)
+#define ADC1_G2MODECR_CONFIGVALUE		((uint32)ADC_12_BIT | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)0x00000000U)
 
+#define ADC1_G0SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
+#define ADC1_G1SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
+#define ADC1_G2SRC_CONFIGVALUE 			((uint32)0x00000000U | (uint32)ADC1_EVENT)
+
+#define ADC1_BNDCR_CONFIGVALUE			((uint32)((uint32)0U << 16U)|(0U + 3U))
+#define ADC1_BNDEND_CONFIGVALUE			(2U)
+
+#define ADC1_G0SAMP_CONFIGVALUE			(0U)
+#define ADC1_G1SAMP_CONFIGVALUE			(0U)
+#define ADC1_G2SAMP_CONFIGVALUE			(0U)
+
+#define ADC1_G0SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
+#define ADC1_G1SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
+#define ADC1_G2SAMPDISEN_CONFIGVALUE	((uint32)((uint32)0U << 8U) | 0x00000000U)
+
+#define ADC1_PARCR_CONFIGVALUE			(0x00000005U)
+
+
 /** 
  *  @defgroup ADC ADC
  *  @brief Analog To Digital Converter Module.
@@ -261,6 +284,8 @@
 void adcSetEVTPin(adcBASE_t *adc, uint32 value);
 uint32 adcGetEVTPin(adcBASE_t *adc);
 
+void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type);
+void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type);
 
 /** @fn void adcNotification(adcBASE_t *adc, uint32 group)
 *   @brief Group notification
Index: firmware/include/can.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/can.h	(.../can.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/can.h	(.../can.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -630,7 +630,7 @@
 
 
 /* Configuration registers initial value for CAN1*/
-#define CAN1_CTL_CONFIGVALUE      ((uint32)0x00000200U \
+#define CAN1_CTL_CONFIGVALUE      ((uint32)0x00000000U \
                                  | (uint32)0x00000000U \
                                  | (uint32)((uint32)0x00000005U  << 10U) | 0x00020002U)
 #define CAN1_ES_CONFIGVALUE         0x00000007U 
@@ -639,8 +639,22 @@
                                  | (uint32)((uint32)((2U + 3U) - 1U) << 8U) \
                                  | (uint32)((uint32)(3U - 1U) << 6U) | (uint32)45U)
 #define CAN1_TEST_CONFIGVALUE       0x00000080U 
-#define CAN1_ABOTR_CONFIGVALUE    ((uint32)(103U))
+#define CAN1_ABOTR_CONFIGVALUE    ((uint32)(0U))
 #define CAN1_INTMUX0_CONFIGVALUE  ((uint32)0x00000000U \
+                                 | (uint32)0x00000002U \
+                                 | (uint32)0x00000004U \
+                                 | (uint32)0x00000008U \
+                                 | (uint32)0x00000010U \
+                                 | (uint32)0x00000020U \
+                                 | (uint32)0x00000040U \
+                                 | (uint32)0x00000080U \
+                                 | (uint32)0x00000100U \
+                                 | (uint32)0x00000200U \
+                                 | (uint32)0x00000400U \
+                                 | (uint32)0x00000800U \
+                                 | (uint32)0x00001000U \
+                                 | (uint32)0x00002000U \
+                                 | (uint32)0x00004000U \
                                  | (uint32)0x00000000U \
                                  | (uint32)0x00000000U \
                                  | (uint32)0x00000000U \
@@ -657,20 +671,6 @@
                                  | (uint32)0x00000000U \
                                  | (uint32)0x00000000U \
                                  | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
-                                 | (uint32)0x00000000U \
                                  | (uint32)0x00000000U)
 
 #define CAN1_INTMUX1_CONFIGVALUE  ((uint32)0x00000000U \
Index: firmware/include/etpwm.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/etpwm.h	(.../etpwm.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/etpwm.h	(.../etpwm.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -468,13 +468,13 @@
 
 #define ETPWM1_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM1_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM1_TBPRD_CONFIGVALUE          1000U
+#define ETPWM1_TBPRD_CONFIGVALUE          25833U
 #define ETPWM1_CMPCTL_CONFIGVALUE         0x00000000U
-#define ETPWM1_CMPA_CONFIGVALUE           50U
-#define ETPWM1_CMPB_CONFIGVALUE           50U
+#define ETPWM1_CMPA_CONFIGVALUE           0U
+#define ETPWM1_CMPB_CONFIGVALUE           0U
 #define ETPWM1_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
 #define ETPWM1_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
-#define ETPWM1_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM1_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) 
 #define ETPWM1_DBRED_CONFIGVALUE          1U
 #define ETPWM1_DBFED_CONFIGVALUE          1U
 #define ETPWM1_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
@@ -483,7 +483,7 @@
 #define ETPWM1_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
 #define ETPWM1_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
 #define ETPWM1_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
-#define ETPWM1_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM1_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
 #define ETPWM1_DCTRIPSEL_CONFIGVALUE      0x00000000U
 #define ETPWM1_DCACTL_CONFIGVALUE         0x00000000U
 #define ETPWM1_DCBCTL_CONFIGVALUE         0x00000000U
@@ -494,13 +494,13 @@
 
 #define ETPWM2_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM2_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM2_TBPRD_CONFIGVALUE          1000U
+#define ETPWM2_TBPRD_CONFIGVALUE          25833U
 #define ETPWM2_CMPCTL_CONFIGVALUE         0x00000000U
-#define ETPWM2_CMPA_CONFIGVALUE           50U
-#define ETPWM2_CMPB_CONFIGVALUE           50U
+#define ETPWM2_CMPA_CONFIGVALUE           0U
+#define ETPWM2_CMPB_CONFIGVALUE           0U
 #define ETPWM2_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
 #define ETPWM2_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
-#define ETPWM2_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM2_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) 
 #define ETPWM2_DBRED_CONFIGVALUE          1U
 #define ETPWM2_DBFED_CONFIGVALUE          1U
 #define ETPWM2_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
@@ -509,7 +509,7 @@
 #define ETPWM2_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
 #define ETPWM2_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
 #define ETPWM2_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
-#define ETPWM2_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM2_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
 #define ETPWM2_DCTRIPSEL_CONFIGVALUE      0x00000000U
 #define ETPWM2_DCACTL_CONFIGVALUE         0x00000000U
 #define ETPWM2_DCBCTL_CONFIGVALUE         0x00000000U
@@ -520,13 +520,13 @@
 
 #define ETPWM3_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM3_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM3_TBPRD_CONFIGVALUE          1000U
+#define ETPWM3_TBPRD_CONFIGVALUE          25833U
 #define ETPWM3_CMPCTL_CONFIGVALUE         0x00000000U
-#define ETPWM3_CMPA_CONFIGVALUE           50U
-#define ETPWM3_CMPB_CONFIGVALUE           50U
+#define ETPWM3_CMPA_CONFIGVALUE           0U
+#define ETPWM3_CMPB_CONFIGVALUE           0U
 #define ETPWM3_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
 #define ETPWM3_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
-#define ETPWM3_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM3_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) 
 #define ETPWM3_DBRED_CONFIGVALUE          1U
 #define ETPWM3_DBFED_CONFIGVALUE          1U
 #define ETPWM3_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
@@ -535,7 +535,7 @@
 #define ETPWM3_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
 #define ETPWM3_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
 #define ETPWM3_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
-#define ETPWM3_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM3_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
 #define ETPWM3_DCTRIPSEL_CONFIGVALUE      0x00000000U
 #define ETPWM3_DCACTL_CONFIGVALUE         0x00000000U
 #define ETPWM3_DCBCTL_CONFIGVALUE         0x00000000U
@@ -546,13 +546,13 @@
 
 #define ETPWM4_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM4_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM4_TBPRD_CONFIGVALUE          1000U
+#define ETPWM4_TBPRD_CONFIGVALUE          25833U
 #define ETPWM4_CMPCTL_CONFIGVALUE         0x00000000U
-#define ETPWM4_CMPA_CONFIGVALUE           50U
-#define ETPWM4_CMPB_CONFIGVALUE           50U
+#define ETPWM4_CMPA_CONFIGVALUE           0U
+#define ETPWM4_CMPB_CONFIGVALUE           0U
 #define ETPWM4_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
 #define ETPWM4_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
-#define ETPWM4_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM4_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) 
 #define ETPWM4_DBRED_CONFIGVALUE          1U
 #define ETPWM4_DBFED_CONFIGVALUE          1U
 #define ETPWM4_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
@@ -561,7 +561,7 @@
 #define ETPWM4_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
 #define ETPWM4_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
 #define ETPWM4_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
-#define ETPWM4_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM4_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
 #define ETPWM4_DCTRIPSEL_CONFIGVALUE      0x00000000U
 #define ETPWM4_DCACTL_CONFIGVALUE         0x00000000U
 #define ETPWM4_DCBCTL_CONFIGVALUE         0x00000000U
@@ -572,10 +572,10 @@
 
 #define ETPWM5_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM5_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM5_TBPRD_CONFIGVALUE          1000U
+#define ETPWM5_TBPRD_CONFIGVALUE          102U
 #define ETPWM5_CMPCTL_CONFIGVALUE         0x00000000U
-#define ETPWM5_CMPA_CONFIGVALUE           50U
-#define ETPWM5_CMPB_CONFIGVALUE           50U
+#define ETPWM5_CMPA_CONFIGVALUE           52U
+#define ETPWM5_CMPB_CONFIGVALUE           52U
 #define ETPWM5_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
 #define ETPWM5_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
 #define ETPWM5_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
@@ -587,7 +587,7 @@
 #define ETPWM5_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
 #define ETPWM5_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
 #define ETPWM5_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
-#define ETPWM5_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM5_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
 #define ETPWM5_DCTRIPSEL_CONFIGVALUE      0x00000000U
 #define ETPWM5_DCACTL_CONFIGVALUE         0x00000000U
 #define ETPWM5_DCBCTL_CONFIGVALUE         0x00000000U
@@ -598,13 +598,13 @@
 
 #define ETPWM6_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM6_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM6_TBPRD_CONFIGVALUE          1000U
+#define ETPWM6_TBPRD_CONFIGVALUE          25833U
 #define ETPWM6_CMPCTL_CONFIGVALUE         0x00000000U
-#define ETPWM6_CMPA_CONFIGVALUE           50U
-#define ETPWM6_CMPB_CONFIGVALUE           50U
+#define ETPWM6_CMPA_CONFIGVALUE           0U
+#define ETPWM6_CMPB_CONFIGVALUE           0U
 #define ETPWM6_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
 #define ETPWM6_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
-#define ETPWM6_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM6_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) 
 #define ETPWM6_DBRED_CONFIGVALUE          1U
 #define ETPWM6_DBFED_CONFIGVALUE          1U
 #define ETPWM6_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
@@ -613,7 +613,7 @@
 #define ETPWM6_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
 #define ETPWM6_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
 #define ETPWM6_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
-#define ETPWM6_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM6_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
 #define ETPWM6_DCTRIPSEL_CONFIGVALUE      0x00000000U
 #define ETPWM6_DCACTL_CONFIGVALUE         0x00000000U
 #define ETPWM6_DCBCTL_CONFIGVALUE         0x00000000U
@@ -624,13 +624,13 @@
 
 #define ETPWM7_TBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 7U) | (uint16)((uint16)0U << 10U))
 #define ETPWM7_TBPHS_CONFIGVALUE          0x00000000U
-#define ETPWM7_TBPRD_CONFIGVALUE          1000U
+#define ETPWM7_TBPRD_CONFIGVALUE          25833U
 #define ETPWM7_CMPCTL_CONFIGVALUE         0x00000000U
-#define ETPWM7_CMPA_CONFIGVALUE           50U
-#define ETPWM7_CMPB_CONFIGVALUE           50U
+#define ETPWM7_CMPA_CONFIGVALUE           0U
+#define ETPWM7_CMPB_CONFIGVALUE           0U
 #define ETPWM7_AQCTLA_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 4U))
 #define ETPWM7_AQCTLB_CONFIGVALUE         ((uint16)((uint16)ActionQual_Set << 0U) | (uint16)((uint16)ActionQual_Clear << 8U))
-#define ETPWM7_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)0U << 0U)) 
+#define ETPWM7_DBCTL_CONFIGVALUE          ((uint16)((uint16)0U << 5U) | (uint16)((uint16)0u << 4U) | (uint16)((uint16)0U << 3U) | (uint16)((uint16)0U << 2U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)0U << 0U)) 
 #define ETPWM7_DBRED_CONFIGVALUE          1U
 #define ETPWM7_DBFED_CONFIGVALUE          1U
 #define ETPWM7_TZSEL_CONFIGVALUE          (0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U)
@@ -639,7 +639,7 @@
 #define ETPWM7_TZEINT_CONFIGVALUE         (0x0000U  | 0x0000U | 0x0000U | 0x0000U | 0x0000U| 0x0000U)
 #define ETPWM7_ETSEL_CONFIGVALUE          ((uint16)(((uint16)NO_EVENT == 0U)? 0x0000U : 0x0008U) | (uint16)NO_EVENT | (uint16)0x0000U | (uint16)0x0000U | (uint16)((uint16)DCAEVT1 << 8U) | (uint16)((uint16)DCBEVT1 << 12U))
 #define ETPWM7_ETPS_CONFIGVALUE           ((uint16)1U | (uint16)((uint16)1U << 8U)  | (uint16)((uint16)1U << 12U))
-#define ETPWM7_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)1U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
+#define ETPWM7_PCCTL_CONFIGVALUE          ((uint16)((uint16)0U << 0U) | (uint16)((uint16)0U << 1U) | (uint16)((uint16)3U << 8U) | (uint16)((uint16)0U << 5U))
 #define ETPWM7_DCTRIPSEL_CONFIGVALUE      0x00000000U
 #define ETPWM7_DCACTL_CONFIGVALUE         0x00000000U
 #define ETPWM7_DCBCTL_CONFIGVALUE         0x00000000U
Index: firmware/include/gio.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/gio.h	(.../gio.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/gio.h	(.../gio.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -89,18 +89,18 @@
 								 | (uint32)((uint32)0U << 15U))
 
 
-#define GIO_INTENASET_CONFIGVALUE ((uint32)((uint32)1U << 0U) \
-							     | (uint32)((uint32)1U << 1U) \
+#define GIO_INTENASET_CONFIGVALUE ((uint32)((uint32)0U << 0U) \
+							     | (uint32)((uint32)0U << 1U) \
 							     | (uint32)((uint32)0U << 2U) \
 							     | (uint32)((uint32)0U << 3U) \
 							     | (uint32)((uint32)0U << 4U) \
 							     | (uint32)((uint32)0U << 5U) \
 							     | (uint32)((uint32)0U << 6U) \
 							     | (uint32)((uint32)0U << 7U) \
-								 | (uint32)((uint32)1U << 8U) \
-								 | (uint32)((uint32)1U << 9U) \
-								 | (uint32)((uint32)1U << 10U)\
-								 | (uint32)((uint32)1U << 11U)\
+								 | (uint32)((uint32)0U << 8U) \
+								 | (uint32)((uint32)0U << 9U) \
+								 | (uint32)((uint32)0U << 10U)\
+								 | (uint32)((uint32)0U << 11U)\
 								 | (uint32)((uint32)0U << 12U)\
 								 | (uint32)((uint32)0U << 13U)\
 								 | (uint32)((uint32)0U << 14U)\
@@ -123,10 +123,10 @@
 								 | (uint32)((uint32)0U << 14U)\
 								 | (uint32)((uint32)0U << 15U))
 
-#define GIO_PORTADIR_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTADIR_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U))
 #define GIO_PORTAPDR_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
-#define GIO_PORTAPSL_CONFIGVALUE	((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
-#define GIO_PORTAPULDIS_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPSL_CONFIGVALUE	((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U))
+#define GIO_PORTAPULDIS_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) |(uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)1U << 6U) | (uint32)((uint32)0U << 7U))
 
 #define GIO_PORTBDIR_CONFIGVALUE	((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
 #define GIO_PORTBPDR_CONFIGVALUE	((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 7U))
Index: firmware/include/mibspi.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/mibspi.h	(.../mibspi.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/mibspi.h	(.../mibspi.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -188,18 +188,78 @@
     uint32 CONFIG_UERRCTRL;
 }mibspi_config_reg_t;
 
+#define MIBSPI1_GCR1_CONFIGVALUE     (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
+#define MIBSPI1_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+#define MIBSPI1_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 
+#define MIBSPI1_PCFUN_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) |  (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U))
+#define MIBSPI1_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) |  (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
+#define MIBSPI1_PCPDR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) |  (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
+#define MIBSPI1_PCDIS_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) |  (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 25U))
+#define MIBSPI1_PCPSL_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) |  (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 25U))
 
+#define MIBSPI1_DELAY_CONFIGVALUE    ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U))
 
+#define MIBSPI1_FMT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI1_FMT1_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI1_FMT2_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI1_FMT3_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U))
+
+#define MIBSPI1_MIBSPIE_CONFIGVALUE  1U
+#define MIBSPI1_LTGPEND_CONFIGVALUE  ((uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U))
+
+#define MIBSPI1_TGCTRL0_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U)))
+#define MIBSPI1_TGCTRL1_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)8U << 8U)))
+#define MIBSPI1_TGCTRL2_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U) << 8U)))
+#define MIBSPI1_TGCTRL3_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL4_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL5_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL6_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI1_TGCTRL7_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U)))
+
+#define MIBSPI1_UERRCTRL_CONFIGVALUE (0x00000005U)
+
+
+#define MIBSPI3_GCR1_CONFIGVALUE     (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
+#define MIBSPI3_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)1U << 6U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 0U))
+#define MIBSPI3_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI3_PCFUN_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+#define MIBSPI3_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCPDR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCDIS_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 5U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U))
+#define MIBSPI3_PCPSL_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 4U) | (uint32)((uint32)1U << 5U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U))
+
+#define MIBSPI3_DELAY_CONFIGVALUE    ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U))
+
+#define MIBSPI3_FMT0_CONFIGVALUE     ((uint32)((uint32)20U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)8U << 0U))
+#define MIBSPI3_FMT1_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI3_FMT2_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U))
+#define MIBSPI3_FMT3_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 23U) | (uint32)((uint32)0U << 22U) | (uint32)((uint32)0U << 21U) | (uint32)((uint32)0U << 20U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)102U << 8U) | (uint32)((uint32)16U << 0U))
+
+#define MIBSPI3_MIBSPIE_CONFIGVALUE  1U
+#define MIBSPI3_LTGPEND_CONFIGVALUE  ((uint32)((uint32)((11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U))
+
+#define MIBSPI3_TGCTRL0_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)0U << 8U)))
+#define MIBSPI3_TGCTRL1_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)11U << 8U)))
+#define MIBSPI3_TGCTRL2_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U) << 8U)))
+#define MIBSPI3_TGCTRL3_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL4_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL5_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL6_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U)))
+#define MIBSPI3_TGCTRL7_CONFIGVALUE  (0xFFFF7FFFU & ((uint32)((uint32)1U << 30U) | (uint32)((uint32)0U << 29U) | (uint32)((uint32)TRG_ALWAYS << 20U) | (uint32)((uint32)TRG_DISABLED << 16U) | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U)))
+
+#define MIBSPI3_UERRCTRL_CONFIGVALUE (0x00000005U)
+
 #define MIBSPI5_GCR1_CONFIGVALUE     (0x01000000U | (uint32)((uint32)1U << 1U) | 1U)
 #define MIBSPI5_INT0_CONFIGVALUE     ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U)  | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 #define MIBSPI5_LVL_CONFIGVALUE      ((uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 6U) | (uint32)((uint32)0U << 4U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 0U))
 
-#define MIBSPI5_PCFUN_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U))
-#define MIBSPI5_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
+#define MIBSPI5_PCFUN_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U))
+#define MIBSPI5_PCDIR_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
 #define MIBSPI5_PCPDR_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
 #define MIBSPI5_PCDIS_CONFIGVALUE    ((uint32)((uint32)0U << 0U) | (uint32)((uint32)0U << 1U) | (uint32)((uint32)0U << 2U) | (uint32)((uint32)0U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 9U) | (uint32)((uint32)0U << 10U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 11U) | (uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 17U) | (uint32)((uint32)0U << 18U) | (uint32)((uint32)0U << 19U) | (uint32)((uint32)0U << 25U) | (uint32)((uint32)0U << 26U) | (uint32)((uint32)0U << 27U))
-#define MIBSPI5_PCPSL_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)1U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U))
+#define MIBSPI5_PCPSL_CONFIGVALUE    ((uint32)((uint32)1U << 0U) | (uint32)((uint32)1U << 1U) | (uint32)((uint32)1U << 2U) | (uint32)((uint32)1U << 3U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)1U << 9U) | (uint32)((uint32)1U << 10U) | (uint32)((uint32)1U << 16U) | (uint32)((uint32)1U << 11U) | (uint32)((uint32)1U << 24U) | (uint32)((uint32)1U << 17U) | (uint32)((uint32)1U << 18U) | (uint32)((uint32)1U << 19U) | (uint32)((uint32)1U << 25U) | (uint32)((uint32)1U << 26U) | (uint32)((uint32)1U << 27U))
 
 #define MIBSPI5_DELAY_CONFIGVALUE    ((uint32)((uint32)0U << 24U) | (uint32)((uint32)0U << 16U) | (uint32)((uint32)0U << 8U) | (uint32)((uint32)0U << 0U))
 
@@ -251,6 +311,8 @@
 void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype);
 void mibspiDisableLoopback(mibspiBASE_t *mibspi);
 void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT);
+void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type);
+void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type);
 void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type);
 
 /** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags)
Index: firmware/include/rti.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/rti.h	(.../rti.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/rti.h	(.../rti.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -256,7 +256,7 @@
 #define RTI_CAPCTRL_CONFIGVALUE  (0U | 0U)
 #define RTI_COMPCTRL_CONFIGVALUE (0x00000000U | 0x00000100U | 0x00000000U | 0x00000000U)
 #define RTI_UDCP0_CONFIGVALUE    10334U
-#define RTI_UDCP1_CONFIGVALUE    51668U
+#define RTI_UDCP1_CONFIGVALUE    103335U
 #define RTI_UDCP2_CONFIGVALUE    82668U
 #define RTI_UDCP3_CONFIGVALUE    516675U
 
Index: firmware/include/sys_core.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/sys_core.h	(.../sys_core.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/sys_core.h	(.../sys_core.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -72,7 +72,7 @@
 *
 *	@note: Use this macro for SVC Mode Stack length (in bytes)
 */
-#define SVC_STACK_LENGTH    0x00000100U
+#define SVC_STACK_LENGTH    0x00000400U
 
 /** @def FIQ_STACK_LENGTH
 *   @brief FIQ Mode Stack length (in bytes)
@@ -81,7 +81,7 @@
 *
 *	@note: Use this macro for FIQ Mode Stack length (in bytes)
 */
-#define FIQ_STACK_LENGTH    0x00000100U
+#define FIQ_STACK_LENGTH    0x00001000U
 
 /** @def IRQ_STACK_LENGTH
 *   @brief IRQ Mode Stack length (in bytes)
@@ -90,7 +90,7 @@
 *
 *	@note: Use this macro for IRQ Mode Stack length (in bytes)
 */
-#define IRQ_STACK_LENGTH    0x00000100U
+#define IRQ_STACK_LENGTH    0x00001000U
 
 /** @def ABORT_STACK_LENGTH
 *   @brief ABORT Mode Stack length (in bytes)
@@ -99,7 +99,7 @@
 *
 *	@note: Use this macro for ABORT Mode Stack length (in bytes)
 */
-#define ABORT_STACK_LENGTH  0x00000100U
+#define ABORT_STACK_LENGTH  0x00000200U
 
 /** @def UNDEF_STACK_LENGTH
 *   @brief UNDEF Mode Stack length (in bytes)
@@ -108,7 +108,7 @@
 *
 *	@note: Use this macro for UNDEF Mode Stack length (in bytes)
 */
-#define UNDEF_STACK_LENGTH  0x00000100U
+#define UNDEF_STACK_LENGTH  0x00000200U
 
 /* System Core Interface Functions */
 
Index: firmware/include/sys_vim.h
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/include/sys_vim.h	(.../sys_vim.h)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/include/sys_vim.h	(.../sys_vim.h)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -94,7 +94,9 @@
 extern void rtiCompare1Interrupt(void);
 extern void rtiCompare3Interrupt(void);
 extern void linHighLevelInterrupt(void);
+extern void adc1Group1Interrupt(void);
 extern void can1HighLevelInterrupt(void);
+extern void can1LowLevelInterrupt(void);
 extern void dmaBTCAInterrupt(void);
 extern void sciHighLevelInterrupt(void);
 
@@ -144,7 +146,7 @@
                                 | (uint32)((uint32)SYS_IRQ << 12U)\
                                 | (uint32)((uint32)SYS_FIQ << 13U)\
                                 | (uint32)((uint32)SYS_IRQ << 14U)\
-                                | (uint32)((uint32)SYS_IRQ << 15U)\
+                                | (uint32)((uint32)SYS_FIQ << 15U)\
                                 | (uint32)((uint32)SYS_FIQ << 16U)\
                                 | (uint32)((uint32)SYS_IRQ << 17U)\
                                 | (uint32)((uint32)SYS_IRQ << 18U)\
@@ -276,7 +278,7 @@
                                     | (uint32)((uint32)0U << 12U)\
                                     | (uint32)((uint32)1U << 13U)\
                                     | (uint32)((uint32)0U << 14U)\
-                                    | (uint32)((uint32)0U << 15U)\
+                                    | (uint32)((uint32)1U << 15U)\
                                     | (uint32)((uint32)1U << 16U)\
                                     | (uint32)((uint32)0U << 17U)\
                                     | (uint32)((uint32)0U << 18U)\
@@ -290,7 +292,7 @@
                                     | (uint32)((uint32)0U << 26U)\
                                     | (uint32)((uint32)0U << 27U)\
                                     | (uint32)((uint32)0U << 28U)\
-                                    | (uint32)((uint32)0U << 29U)\
+                                    | (uint32)((uint32)1U << 29U)\
                                     | (uint32)((uint32)0U << 30U)\
                                     | (uint32)((uint32)0U << 31U))
 						
Index: firmware/source/adc.c
===================================================================
diff -u
--- firmware/source/adc.c	(revision 0)
+++ firmware/source/adc.c	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -0,0 +1,1012 @@
+/** @file adc.c 
+*   @brief ADC Driver Source File
+*   @date 11-Dec-2018
+*   @version 04.07.01
+*
+*   This file contains:
+*   - API Functions
+*   - Interrupt Handlers
+*   .
+*   which are relevant for the ADC driver.
+*/
+
+/* 
+* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com  
+* 
+* 
+*  Redistribution and use in source and binary forms, with or without 
+*  modification, are permitted provided that the following conditions 
+*  are met:
+*
+*    Redistributions of source code must retain the above copyright 
+*    notice, this list of conditions and the following disclaimer.
+*
+*    Redistributions in binary form must reproduce the above copyright
+*    notice, this list of conditions and the following disclaimer in the 
+*    documentation and/or other materials provided with the   
+*    distribution.
+*
+*    Neither the name of Texas Instruments Incorporated nor the names of
+*    its contributors may be used to endorse or promote products derived
+*    from this software without specific prior written permission.
+*
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+/* USER CODE BEGIN (0) */
+/* USER CODE END */
+
+/* Include Files */
+
+#include "adc.h"
+#include "sys_vim.h"
+
+/* USER CODE BEGIN (1) */
+/* USER CODE END */
+
+
+/** @fn void adcInit(void)
+*   @brief Initializes ADC Driver
+*
+*   This function initializes the ADC driver.
+*
+*/
+/* USER CODE BEGIN (2) */
+/* USER CODE END */
+/* SourceId : ADC_SourceId_001 */
+/* DesignId : ADC_DesignId_001 */
+/* Requirements : HL_SR185 */
+void adcInit(void)
+{
+/* USER CODE BEGIN (3) */
+/* USER CODE END */
+
+    /** @b Initialize @b ADC1: */
+
+    /** - Reset ADC module */
+    adcREG1->RSTCR = 1U;
+    adcREG1->RSTCR = 0U;
+
+    /** - Enable 12-BIT ADC  */
+    adcREG1->OPMODECR |= 0x80000000U;
+	
+    /** - Setup prescaler */
+    adcREG1->CLOCKCR = 25U;
+ 
+    /** - Setup memory boundaries */
+    adcREG1->BNDCR  = (uint32)((uint32)0U << 16U) | (0U + 3U);
+    adcREG1->BNDEND = (adcREG1->BNDEND & 0xFFFF0000U) | (2U);
+ 
+    /** - Setup event group conversion mode
+    *     - Setup data format
+    *     - Enable/Disable channel id in conversion result
+    *     - Enable/Disable continuous conversion
+    */
+    adcREG1->GxMODECR[0U] = (uint32)ADC_12_BIT
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U;
+
+    /** - Setup event group hardware trigger
+     *     - Setup hardware trigger edge
+     *     - Setup hardware trigger source
+     */
+    adcREG1->EVSRC = (uint32)0x00000000U
+                   | (uint32)ADC1_EVENT;
+
+    /** - Setup event group sample window */
+    adcREG1->EVSAMP = 0U;
+
+    /** - Setup event group sample discharge 
+    *     - Setup discharge prescaler
+    *     - Enable/Disable discharge
+    */
+    adcREG1->EVSAMPDISEN = (uint32)((uint32)0U << 8U)
+                         | (uint32)0x00000000U;
+
+    /** - Setup group 1 conversion mode
+    *     - Setup data format
+    *     - Enable/Disable channel id in conversion result
+    *     - Enable/Disable continuous conversion
+    */
+    adcREG1->GxMODECR[1U] = (uint32)ADC_12_BIT
+                          | (uint32)0x00000020U
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U;
+
+    /** - Setup group 1 hardware trigger
+     *     - Setup hardware trigger edge
+     *     - Setup hardware trigger source
+     */
+    adcREG1->G1SRC = (uint32)0x00000000U
+                   | (uint32)ADC1_EVENT;
+
+    /** - Setup group 1 sample window */
+    adcREG1->G1SAMP = 0U;
+
+    /** - Setup group 1 sample discharge 
+    *     - Setup discharge prescaler
+    *     - Enable/Disable discharge
+    */
+    adcREG1->G1SAMPDISEN = (uint32)((uint32)0U << 8U)
+                         | (uint32)0x00000000U;
+
+    /** - Setup group 2 conversion mode
+     *     - Setup data format
+     *     - Enable/Disable channel id in conversion result
+     *     - Enable/Disable continuous conversion
+     */
+    adcREG1->GxMODECR[2U] = (uint32)ADC_12_BIT
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U
+                          | (uint32)0x00000000U;
+
+    /** - Setup group 2 hardware trigger
+	*     - Setup hardware trigger edge
+    *     - Setup hardware trigger source
+	*/
+    adcREG1->G2SRC = (uint32)0x00000000U
+                   | (uint32)ADC1_EVENT;
+
+    /** - Setup group 2 sample window */
+    adcREG1->G2SAMP = 0U;
+
+    /** - Setup group 2 sample discharge 
+    *     - Setup discharge prescaler
+    *     - Enable/Disable discharge
+    */
+    adcREG1->G2SAMPDISEN = (uint32)((uint32)0U << 8U)
+                         | (uint32)0x00000000U;
+
+    /** - ADC1 EVT pin output value */
+    adcREG1->EVTOUT = 0U;
+
+    /** - ADC1 EVT pin direction */
+    adcREG1->EVTDIR = 0U;
+	
+    /** - ADC1 EVT pin open drain enable */
+	adcREG1->EVTPDR = 0U;
+
+    /** - ADC1 EVT pin pullup / pulldown selection */
+	adcREG1->EVTPSEL = 1U;
+
+    /** - ADC1 EVT pin pullup / pulldown enable*/
+	adcREG1->EVTDIS = 0U;
+	
+	/** - Enable ADC module */
+    adcREG1->OPMODECR |= 0x80140001U;
+	
+    /** - Wait for buffer initialization complete */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while (((adcREG1->BNDEND & 0xFFFF0000U) >> 16U ) != 0U) 
+    { 
+	} /* Wait */
+    
+    /** - Setup parity */
+    adcREG1->PARCR = 0x00000005U;
+
+
+/* USER CODE BEGIN (4) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (5) */
+/* USER CODE END */
+
+
+/** - s_adcSelect is used as constant table for channel selection */
+static const uint32 s_adcSelect[2U][3U] =
+{
+    {0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U,
+    0x00000001U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000080U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00010000U |
+    0x00020000U |
+    0x00040000U |
+    0x00080000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U,
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U},
+    {0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U ,
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U,
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U |
+    0x00000000U}
+};
+
+/** - s_adcFiFoSize is used as constant table for channel selection */
+static const uint32 s_adcFiFoSize[2U][3U] =
+{
+    {0U,
+    6U,
+    32U},
+    {16U,
+    16U,
+    16U}
+};
+
+/* USER CODE BEGIN (6) */
+/* USER CODE END */
+
+/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group)
+*   @brief Starts an ADC conversion
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function starts a conversion of the ADC hardware group.
+*
+*/
+/* SourceId : ADC_SourceId_002 */
+/* DesignId : ADC_DesignId_002 */
+/* Requirements : HL_SR186 */
+void adcStartConversion(adcBASE_t *adc, uint32 group)
+{
+    uint32 index = (adc == adcREG1) ? 0U : 1U;
+
+/* USER CODE BEGIN (7) */
+/* USER CODE END */
+
+    /** - Setup FiFo size */
+    adc->GxINTCR[group] = s_adcFiFoSize[index][group];
+
+    /** - Start Conversion */
+    adc->GxSEL[group] = s_adcSelect[index][group];
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (8) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (9) */
+/* USER CODE END */
+
+
+/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group)
+*   @brief Stops an ADC conversion
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function stops a conversion of the ADC hardware group.
+*
+*/
+/* SourceId : ADC_SourceId_003 */
+/* DesignId : ADC_DesignId_003 */
+/* Requirements : HL_SR187 */
+void adcStopConversion(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (10) */
+/* USER CODE END */
+
+    /** - Stop Conversion */
+    adc->GxSEL[group] = 0U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
+
+
+/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group)
+*   @brief Resets FiFo read and write pointer.
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function resets the FiFo read and write pointers.
+*
+*/
+/* SourceId : ADC_SourceId_004 */
+/* DesignId : ADC_DesignId_004*/
+/* Requirements : HL_SR188 */
+void adcResetFiFo(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (13) */
+/* USER CODE END */
+
+    /** - Reset FiFo */
+    adc->GxFIFORESETCR[group] = 1U;
+
+    /**   @note The function adcInit has to be called before this function can be used.\n
+    *           the conversion should be stopped before calling this function. 
+    */
+
+/* USER CODE BEGIN (14) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (15) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data)
+*   @brief Gets converted a ADC values
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*   @param[out] data Pointer to store ADC converted data
+*   @return The function will return the number of converted values copied into data buffer:
+*
+*   This function writes a ADC message into a ADC message box.
+*
+*/
+/* SourceId : ADC_SourceId_005 */
+/* DesignId : ADC_DesignId_005 */
+/* Requirements : HL_SR189 */
+uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data)
+{
+    uint32  i;
+    uint32  buf;
+    uint32  mode;    
+    uint32  index = (adc == adcREG1) ? 0U : 1U;
+
+	uint32  intcr_reg = adc->GxINTCR[group];
+    uint32  count = (intcr_reg >= 256U) ? s_adcFiFoSize[index][group] : (s_adcFiFoSize[index][group] - (uint32)(intcr_reg & 0xFFU));
+    adcData_t *ptr = data; 
+
+/* USER CODE BEGIN (16) */
+/* USER CODE END */
+
+    mode = (adc->OPMODECR & ADC_12_BIT_MODE);
+
+    if(mode == ADC_12_BIT_MODE)
+      {
+        /** -  Get conversion data and channel/pin id */
+        for (i = 0U; i < count; i++)
+        {
+          buf        = adc->GxBUF[group].BUF0;
+		  /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+          ptr->value = (uint16)(buf & 0xFFFU);
+          ptr->id    = (uint32)((buf >> 16U) & 0x1FU);
+          /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+		  ptr++;
+        }
+      }
+      else
+      {
+        /** -  Get conversion data and channel/pin id */
+        for (i = 0U; i < count; i++)
+        {
+          buf        = adc->GxBUF[group].BUF0;
+		  /*SAFETYMCUSW 45 D MR:21.1 <APPROVED> "Valid non NULL input parameters are only allowed in this driver" */
+          ptr->value = (uint16)(buf & 0x3FFU);
+          ptr->id    = (uint32)((buf >> 10U) & 0x1FU);
+          /*SAFETYMCUSW 567 S MR:17.1,17.4 <APPROVED> "Pointer increment needed" */
+		  ptr++;
+        }
+      }
+
+
+    adc->GxINTFLG[group] = 9U;
+
+    /**   @note The function adcInit has to be called before this function can be used.\n
+    *           The user is responsible to initialize the message box.
+    */
+
+/* USER CODE BEGIN (17) */
+/* USER CODE END */
+
+    return count;
+}
+
+/* USER CODE BEGIN (18) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group)
+*   @brief Checks if FiFo buffer is full
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*   @return The function will return:
+*           - 0: When FiFo buffer is not full   
+*           - 1: When FiFo buffer is full   
+*           - 3: When FiFo buffer overflow occurred    
+*
+*   This function checks FiFo buffer status.
+*
+*/
+/* SourceId : ADC_SourceId_006 */
+/* DesignId : ADC_DesignId_006 */
+/* Requirements : HL_SR190 */
+uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group)
+{
+    uint32 flags;
+
+/* USER CODE BEGIN (19) */
+/* USER CODE END */
+
+    /** - Read FiFo flags */
+    flags = adc->GxINTFLG[group] & 3U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (20) */
+/* USER CODE END */
+
+    return flags;
+}
+
+/* USER CODE BEGIN (21) */
+/* USER CODE END */
+
+
+/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group)
+*   @brief Checks if Conversion is complete
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*   @return The function will return:
+*           - 0: When is not finished   
+*           - 8: When conversion is complete   
+*
+*   This function checks if conversion is complete.
+*
+*/
+/* SourceId : ADC_SourceId_007 */
+/* DesignId : ADC_DesignId_007 */
+/* Requirements : HL_SR191 */
+uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group)
+{
+    uint32 flags;
+
+/* USER CODE BEGIN (22) */
+/* USER CODE END */
+
+    /** - Read conversion flags */
+    flags = adc->GxINTFLG[group] & 8U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (23) */
+/* USER CODE END */
+
+    return flags;
+}
+
+/* USER CODE BEGIN (24) */
+/* USER CODE END */
+
+/** @fn void adcCalibration(adcBASE_t *adc)
+*   @brief Computes offset error using Calibration mode
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   This function computes offset error using Calibration mode
+*
+*/
+/* SourceId : ADC_SourceId_008 */
+/* DesignId : ADC_DesignId_010 */
+/* Requirements : HL_SR194 */
+void adcCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (25) */
+/* USER CODE END */
+    
+	uint32 conv_val[5U]={0U,0U,0U,0U,0U};
+	uint32 loop_index=0U;
+	uint32 offset_error=0U;
+	uint32 backup_mode;
+	
+	/** - Backup Mode before Calibration  */
+	backup_mode = adc->OPMODECR;
+	
+	/** - Enable 12-BIT ADC  */
+	adc->OPMODECR |= 0x80000000U;
+
+	/* Disable all channels for conversion */
+	adc->GxSEL[0U]=0x00U;
+	adc->GxSEL[1U]=0x00U;
+	adc->GxSEL[2U]=0x00U;
+
+	for(loop_index=0U;loop_index<4U;loop_index++)
+	{
+		/* Disable Self Test and Calibration mode */
+		adc->CALCR=0x0U;
+	
+		switch(loop_index)
+		{
+			case 0U : 	/* Test 1 : Bride En = 0 , HiLo =0 */
+						adc->CALCR=0x0U;
+						break;
+
+			case 1U :	/* Test 1 : Bride En = 0 , HiLo =1 */
+						adc->CALCR=0x0100U;
+						break;
+
+			case 2U : 	/* Test 1 : Bride En = 1 , HiLo =0 */
+						adc->CALCR=0x0200U;
+						break;
+		
+			case 3U : 	/* Test 1 : Bride En = 1 , HiLo =1 */
+						adc->CALCR=0x0300U;
+						break;
+			default :
+			            break;
+		}
+	
+		/* Enable Calibration mode */
+		adc->CALCR|=0x1U;
+	
+		/* Start calibration conversion */
+		adc->CALCR|=0x00010000U;
+
+		/* Wait for calibration conversion to complete */
+		/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+		while((adc->CALCR & 0x00010000U)==0x00010000U)
+	    { 
+	    } /* Wait */
+
+		/* Read converted value */
+		conv_val[loop_index]= adc->CALR;
+	}
+
+	/* Disable Self Test and Calibration mode */
+	adc->CALCR=0x0U;
+
+	/* Compute the Offset error correction value */
+	conv_val[4U]=conv_val[0U]+ conv_val[1U] + conv_val[2U] + conv_val[3U];
+
+	conv_val[4U]=(conv_val[4U]/4U);
+
+	offset_error=conv_val[4U]-0x7FFU;
+
+	/*Write the offset error to the Calibration register */
+	/* Load 2;s complement of the computed value to ADCALR register */
+	offset_error=~offset_error;
+	offset_error=offset_error & 0xFFFU;
+	offset_error=offset_error+1U;
+
+	adc->CALR = offset_error;
+
+  /** - Restore Mode after Calibration  */
+	adc->OPMODECR = backup_mode;
+	
+ /**   @note The function adcInit has to be called before using this function. */
+
+/* USER CODE BEGIN (26) */
+/* USER CODE END */
+}
+
+
+/** @fn void adcMidPointCalibration(adcBASE_t *adc)
+*   @brief Computes offset error using Mid Point Calibration mode
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*	@return This function will return offset error using Mid Point Calibration mode
+*
+*   This function computes offset error using Mid Point Calibration mode
+*
+*/
+/* SourceId : ADC_SourceId_009 */
+/* DesignId : ADC_DesignId_011 */
+/* Requirements : HL_SR195 */
+uint32 adcMidPointCalibration(adcBASE_t *adc)
+{
+/* USER CODE BEGIN (27) */
+/* USER CODE END */
+    
+	uint32 conv_val[3U]={0U,0U,0U};
+	uint32 loop_index=0U;
+	uint32 offset_error=0U;
+	uint32 backup_mode;
+	
+	/** - Backup Mode before Calibration  */
+	backup_mode = adc->OPMODECR;
+	
+	/** - Enable 12-BIT ADC  */
+	adc->OPMODECR |= 0x80000000U;
+
+	/* Disable all channels for conversion */
+	adc->GxSEL[0U]=0x00U;
+	adc->GxSEL[1U]=0x00U;
+	adc->GxSEL[2U]=0x00U;
+
+	for(loop_index=0U;loop_index<2U;loop_index++)
+	{
+		/* Disable Self Test and Calibration mode */
+		adc->CALCR=0x0U;
+	
+		switch(loop_index)
+		{
+			case 0U : 	/* Test 1 : Bride En = 0 , HiLo =0 */
+						adc->CALCR=0x0U;
+						break;
+
+			case 1U :	/* Test 1 : Bride En = 0 , HiLo =1 */
+						adc->CALCR=0x0100U;
+						break;
+
+			default :
+			            break;						
+
+		}
+	
+		/* Enable Calibration mode */
+		adc->CALCR|=0x1U;
+	
+		/* Start calibration conversion */
+		adc->CALCR|=0x00010000U;
+
+		/* Wait for calibration conversion to complete */
+		/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+		while((adc->CALCR & 0x00010000U)==0x00010000U)
+	    { 
+	    } /* Wait */
+
+		/* Read converted value */
+		conv_val[loop_index]= adc->CALR;
+	}
+
+	/* Disable Self Test and Calibration mode */
+	adc->CALCR=0x0U;
+
+	/* Compute the Offset error correction value */
+	conv_val[2U]=(conv_val[0U])+ (conv_val[1U]);
+
+	conv_val[2U]=(conv_val[2U]/2U);
+
+	offset_error=conv_val[2U]-0x7FFU;
+
+	/* Write the offset error to the Calibration register           */
+	/* Load 2's complement of the computed value to ADCALR register */
+	offset_error=~offset_error;
+	offset_error=offset_error+1U;
+	offset_error=offset_error & 0xFFFU;
+
+	adc->CALR = offset_error;
+
+  /** - Restore Mode after Calibration  */
+	adc->OPMODECR = backup_mode;
+	
+	return(offset_error);
+
+ /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (28) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (29) */
+/* USER CODE END */
+
+/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group)
+*   @brief Enable notification
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function will enable the notification of a conversion.
+*   In single conversion mode for conversion complete and
+*   in continuous conversion mode when the FiFo buffer is full.
+*
+*/
+/* SourceId : ADC_SourceId_010 */
+/* DesignId : ADC_DesignId_008 */
+/* Requirements : HL_SR192 */
+void adcEnableNotification(adcBASE_t *adc, uint32 group)
+{
+    uint32 notif = (((uint32)(adc->GxMODECR[group]) & 2U) == 2U) ? 1U : 8U;
+
+/* USER CODE BEGIN (30) */
+/* USER CODE END */
+
+    adc->GxINTENA[group] = notif;
+
+    /**   @note The function adcInit has to be called before this function can be used.\n
+    *           This function should be called before the conversion is started
+    */
+
+/* USER CODE BEGIN (31) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (32) */
+/* USER CODE END */
+
+
+/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group)
+*   @brief Disable notification
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*              - adcREG2: ADC2 module pointer
+*   @param[in] group Hardware group of ADC module:
+*              - adcGROUP0: ADC event group
+*              - adcGROUP1: ADC group 1
+*              - adcGROUP2: ADC group 2
+*
+*   This function will disable the notification of a conversion.
+*/
+/* SourceId : ADC_SourceId_011 */
+/* DesignId : ADC_DesignId_009 */
+/* Requirements : HL_SR193 */
+void adcDisableNotification(adcBASE_t *adc, uint32 group)
+{
+/* USER CODE BEGIN (33) */
+/* USER CODE END */
+
+    adc->GxINTENA[group] = 0U;
+
+    /**   @note The function adcInit has to be called before this function can be used. */
+
+/* USER CODE BEGIN (34) */
+/* USER CODE END */
+}
+
+/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value)
+*   @brief Set ADCEVT pin
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*   @param[in] value Value to be set: 0 or 1
+*
+*   This function will set the ADC EVT pin if configured as an output pin.
+*/
+/* SourceId : ADC_SourceId_020 */
+/* DesignId : ADC_DesignId_014 */
+/* Requirements : HL_SR529 */
+void adcSetEVTPin(adcBASE_t *adc, uint32 value)
+{
+    adc->EVTOUT = value;
+}
+
+/** @fn uint32 adcGetEVTPin(adcBASE_t *adc)
+*   @brief Set ADCEVT pin
+*   @param[in] adc Pointer to ADC module:
+*              - adcREG1: ADC1 module pointer
+*   @return Value of the ADC EVT pin: 0 or 1
+*
+*   This function will return the value of ADC EVT pin.
+*/
+/* SourceId : ADC_SourceId_021 */
+/* DesignId : ADC_DesignId_015 */
+/* Requirements : HL_SR529 */
+uint32 adcGetEVTPin(adcBASE_t *adc)
+{
+    return adc->EVTIN;
+}
+
+/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*	@param[in] *config_reg: pointer to the struct to which the initial or current 
+*                           value of the configuration registers need to be stored
+*	@param[in] type: 	whether initial or current value of the configuration registers need to be stored
+*						- InitialValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*						- CurrentValue: initial value of the configuration registers will be stored 
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type') 
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : ADC_SourceId_012 */
+/* DesignId : ADC_DesignId_012 */
+/* Requirements : HL_SR203 */
+void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type)
+{
+	if (type == InitialValue)
+	{
+        config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE;
+        config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE;
+        config_reg->CONFIG_GxMODECR[0U] = ADC1_G0MODECR_CONFIGVALUE;
+        config_reg->CONFIG_GxMODECR[1U] = ADC1_G1MODECR_CONFIGVALUE;
+        config_reg->CONFIG_GxMODECR[2U] = ADC1_G2MODECR_CONFIGVALUE;
+        config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE;
+        config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE;
+        config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE;
+        config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE;
+        config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE;
+        config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE;
+        config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE;
+        config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE;
+        config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE;
+        config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE;
+        config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE;
+        config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE;
+	}
+	else
+	{
+        config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR;
+        config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR;
+        config_reg->CONFIG_GxMODECR[0U] = adcREG1->GxMODECR[0U];
+        config_reg->CONFIG_GxMODECR[1U] = adcREG1->GxMODECR[1U];
+        config_reg->CONFIG_GxMODECR[2U] = adcREG1->GxMODECR[2U];
+        config_reg->CONFIG_G0SRC = adcREG1->EVSRC;
+        config_reg->CONFIG_G1SRC = adcREG1->G1SRC;
+        config_reg->CONFIG_G2SRC = adcREG1->G2SRC;
+        config_reg->CONFIG_BNDCR = adcREG1->BNDCR;
+        config_reg->CONFIG_BNDEND = adcREG1->BNDEND;
+        config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP;
+        config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP;
+        config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP;
+        config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN;
+        config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN;
+        config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN;
+        config_reg->CONFIG_PARCR = adcREG1->PARCR;
+	}
+}
+
+
+/* USER CODE BEGIN (35) */
+/* USER CODE END */
+
+
+/* USER CODE BEGIN (38) */
+/* USER CODE END */
+/** @fn void adc1Group1Interrupt(void)
+*   @brief ADC1 Group 1 Interrupt Handler
+*/
+#pragma CODE_STATE(adc1Group1Interrupt, 32)
+#pragma INTERRUPT(adc1Group1Interrupt, FIQ)
+
+/* SourceId : ADC_SourceId_015 */
+/* DesignId : ADC_DesignId_013 */
+/* Requirements : HL_SR197, HL_SR196 */
+void adc1Group1Interrupt(void)
+{
+/* USER CODE BEGIN (39) */
+/* USER CODE END */
+    
+    adcREG1->GxINTFLG[1U] = 9U;
+
+    adcNotification(adcREG1, adcGROUP1);
+
+/* USER CODE BEGIN (40) */
+/* USER CODE END */
+}
+
+
+
+
Index: firmware/source/can.c
===================================================================
diff -u -r88b7f489c8da945997f1516600a30032393f5088 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/can.c	(.../can.c)	(revision 88b7f489c8da945997f1516600a30032393f5088)
+++ firmware/source/can.c	(.../can.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -104,7 +104,7 @@
     *     - Disable status interrupts
     *     - Enter initialization mode
     */
-    canREG1->CTL = (uint32)0x00000200U 
+    canREG1->CTL = (uint32)0x00000000U 
                  | (uint32)0x00000000U 
                  | (uint32)((uint32)0x00000005U  << 10U)
                  | (uint32)0x00020043U;
@@ -114,6 +114,20 @@
 
     /** - Assign interrupt level for messages */
     canREG1->INTMUXx[0U] = (uint32)0x00000000U
+                         | (uint32)0x00000002U
+                         | (uint32)0x00000004U
+                         | (uint32)0x00000008U
+                         | (uint32)0x00000010U
+                         | (uint32)0x00000020U
+                         | (uint32)0x00000040U
+                         | (uint32)0x00000080U
+                         | (uint32)0x00000100U
+                         | (uint32)0x00000200U
+                         | (uint32)0x00000400U
+                         | (uint32)0x00000800U
+                         | (uint32)0x00001000U
+                         | (uint32)0x00002000U
+                         | (uint32)0x00004000U
                          | (uint32)0x00000000U
                          | (uint32)0x00000000U
                          | (uint32)0x00000000U
@@ -130,20 +144,6 @@
                          | (uint32)0x00000000U
                          | (uint32)0x00000000U
                          | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
-                         | (uint32)0x00000000U
                          | (uint32)0x00000000U;
 
     canREG1->INTMUXx[1U] = (uint32)0x00000000U
@@ -180,7 +180,7 @@
                          | (uint32)0x00000000U;
 
     /** - Setup auto bus on timer period */
-    canREG1->ABOTR = (uint32)103U;
+    canREG1->ABOTR = (uint32)0U;
 
     /** - Initialize message 1 
     *     - Wait until IF1 is ready for use 
@@ -196,9 +196,9 @@
     } /* Wait */
 
 
-    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x002U & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x1U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 1U;
 
@@ -215,9 +215,9 @@
     { 
     } /* Wait */
 
-    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x008U & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x2U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 2U;
 
@@ -234,9 +234,9 @@
     { 
     } /* Wait */
 
-    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x010U & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x4U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 3U;
 
@@ -253,9 +253,9 @@
     { 
     } /* Wait */
 
-    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x080U & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x8U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 4U;
 
@@ -272,9 +272,9 @@
     { 
     } /* Wait */
 
-    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x402U & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x10U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF1CMD  = (uint8) 0xF8U;
     canREG1->IF1NO   = 5U;
 
@@ -291,12 +291,88 @@
     { 
     } /* Wait */
 
-    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x00000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x403U & (uint32)0x000007FFU) << (uint32)18U);
-    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x40U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
     canREG1->IF2CMD  = (uint8) 0xF8U;
     canREG1->IF2NO   = 6U;
 
+    /** - Initialize message 7 
+    *     - Wait until IF1 is ready for use 
+    *     - Set message mask
+    *     - Set message control word
+    *     - Set message arbitration
+    *     - Set IF1 control byte
+    *     - Set IF1 message number
+    */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
+
+    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x80U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF1CMD  = (uint8) 0xF8U;
+    canREG1->IF1NO   = 7U;
+
+    /** - Initialize message 8 
+    *     - Wait until IF2 is ready for use 
+    *     - Set message mask
+    *     - Set message control word
+    *     - Set message arbitration
+    *     - Set IF2 control byte
+    *     - Set IF2 message number
+    */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
+
+    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x200U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2CMD  = (uint8) 0xF8U;
+    canREG1->IF2NO   = 8U;
+
+    /** - Initialize message 9 
+    *     - Wait until IF1 is ready for use 
+    *     - Set message mask
+    *     - Set message control word
+    *     - Set message arbitration
+    *     - Set IF1 control byte
+    *     - Set IF1 message number
+    */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
+
+    canREG1->IF1MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x00000000U | (uint32)((uint32)((uint32)0x402U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF1MCTL = 0x00001000U | (uint32)0x00000400U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF1CMD  = (uint8) 0xF8U;
+    canREG1->IF1NO   = 9U;
+
+    /** - Initialize message 10 
+    *     - Wait until IF2 is ready for use 
+    *     - Set message mask
+    *     - Set message control word
+    *     - Set message arbitration
+    *     - Set IF2 control byte
+    *     - Set IF2 message number
+    */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF2STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
+
+    canREG1->IF2MSK  = 0xC0000000U | (uint32)((uint32)((uint32)0x000007FFU & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2ARB  = (uint32)0x80000000U | (uint32)0x40000000U | (uint32)0x20000000U | (uint32)((uint32)((uint32)0x403U & (uint32)0x1FFFFFFFU) << (uint32)0U);
+    canREG1->IF2MCTL = 0x00001000U | (uint32)0x00000800U | (uint32)0x00000000U | (uint32)0x00000080U | (uint32)8U;
+    canREG1->IF2CMD  = (uint8) 0xF8U;
+    canREG1->IF2NO   = 10U;
+
     /** - Setup IF1 for data transmission 
     *     - Wait until IF1 is ready for use 
     *     - Set IF1 control byte
@@ -1525,8 +1601,49 @@
 
 }
 
+/* USER CODE BEGIN (43) */
+/* USER CODE END */
 
+/** @fn void can1LowLevelInterrupt(void)
+*   @brief CAN1 Level 1 Interrupt Handler
+*/
+#pragma CODE_STATE(can1LowLevelInterrupt, 32)
+#pragma INTERRUPT(can1LowLevelInterrupt, FIQ)
 
+/* SourceId : CAN_SourceId_021 */
+/* DesignId : CAN_DesignId_019 */
+/* Requirements : HL_SR221, HL_SR223 */
+void can1LowLevelInterrupt(void)
+{
+    uint32 messageBox = canREG1->INT >> 16U;
 
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
 
+    /** - Setup IF1 for clear pending interrupt flag */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
 
+    canREG1->IF1CMD = 0x08U;
+    /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 <APPROVED> "LDRA Tool issue" */
+    canREG1->IF1NO  = (uint8) messageBox;
+    
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Potentially infinite loop found - Hardware Status check for execution sequence" */
+    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
+    { 
+    } /* Wait */
+    canREG1->IF1CMD = 0x87U;
+
+    canMessageNotification(canREG1, messageBox);
+
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+
+}
+
+
+
+
+
Index: firmware/source/etpwm.c
===================================================================
diff -u -rdd790ad31a95776e2f3d72fc8eac786f956ab945 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/etpwm.c	(.../etpwm.c)	(revision dd790ad31a95776e2f3d72fc8eac786f956ab945)
+++ firmware/source/etpwm.c	(.../etpwm.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -82,13 +82,13 @@
     etpwmREG1->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG1->TBPRD = 1000U;
+    etpwmREG1->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG1->CMPA = 50U;
+    etpwmREG1->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG1->CMPB = 50U;
+    etpwmREG1->CMPB = 0U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG1->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -107,7 +107,7 @@
                       | (uint16)((uint16)0u << 4U)    /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                       | (uint16)((uint16)0U << 3U)    /* Enable/Disable EPWMxB invert       */
                       | (uint16)((uint16)0U << 2U)    /* Enable/Disable EPWMxA invert       */
-                      | (uint16)((uint16)0U << 1U)    /* Enable/Disable Rising Edge Delay   */
+                      | (uint16)((uint16)1U << 1U)    /* Enable/Disable Rising Edge Delay   */
                       | (uint16)((uint16)0U << 0U));  /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -122,7 +122,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG1->PCCTL = ((uint16)((uint16)0U << 0U)    /* Enable/Disable chopper module */
-                      | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                      | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                       | (uint16)((uint16)3U << 8U)    /* Chopping Clock Duty Cycle */
                       | (uint16)((uint16)0U << 5U));  /* Chopping Clock Frequency */
 
@@ -177,13 +177,13 @@
     etpwmREG2->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG2->TBPRD = 1000U;
+    etpwmREG2->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG2->CMPA = 50U;
+    etpwmREG2->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG2->CMPB = 50U;
+    etpwmREG2->CMPB = 0U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG2->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -202,7 +202,7 @@
                       | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                       | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                       | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                      | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                      | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                       | (uint16)((uint16)0U << 0U));   /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -217,7 +217,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG2->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
-                      | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                      | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                       | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                       | (uint16)((uint16)0U << 5U));  /* Chopping Clock Frequency */
 
@@ -272,13 +272,13 @@
     etpwmREG3->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG3->TBPRD = 1000U;
+    etpwmREG3->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG3->CMPA = 50U;
+    etpwmREG3->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG3->CMPB = 50U;
+    etpwmREG3->CMPB = 0U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG3->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -297,7 +297,7 @@
                       | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                       | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                       | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                      | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                      | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                       | (uint16)((uint16)0U << 0U));   /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -312,7 +312,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG3->PCCTL = ((uint16)((uint16)0U << 0U) /* Enable/Disable chopper module */
-                      | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                      | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                       | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                       | (uint16)((uint16)0U << 5U));  /* Chopping Clock Frequency */
 
@@ -368,13 +368,13 @@
     etpwmREG4->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG4->TBPRD = 1000U;
+    etpwmREG4->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG4->CMPA = 50U;
+    etpwmREG4->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG4->CMPB = 50U;
+    etpwmREG4->CMPB = 0U;
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
     etpwmREG4->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U)
@@ -393,7 +393,7 @@
                      | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                      | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                      | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                     | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                     | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                      | (uint16)((uint16)0U << 0U);    /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -408,7 +408,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG4->PCCTL = (uint16)((uint16)0U << 0U)  /* Enable/Disable chopper module */
-                     | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                     | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                      | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                      | (uint16)((uint16)0U << 5U);   /* Chopping Clock Frequency */
 
@@ -454,102 +454,6 @@
     etpwmREG4->ETPS |= ((uint16)((uint16)1U << 8U)
                       | (uint16)((uint16)1U << 12U));
 
-    /** @b initialize @b ETPWM5 */
-
-    /** - Sets high speed time-base clock prescale bits */
-    etpwmREG5->TBCTL = (uint16)0U << 7U;
-
-    /** - Sets time-base clock prescale bits */
-    etpwmREG5->TBCTL |= (uint16)((uint16)0U << 10U);
-
-    /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG5->TBPRD = 1000U;
-
-    /** - Setup the duty cycle for PWMA */
-    etpwmREG5->CMPA = 50U;
-
-    /** - Setup the duty cycle for PWMB */
-    etpwmREG5->CMPB = 50U;
-
-    /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
-    etpwmREG5->AQCTLA = ((uint16)((uint16)ActionQual_Set   << 0U) 
-                       | (uint16)((uint16)ActionQual_Clear << 4U));
-
-    /** - Force EPWMxB output high when counter reaches zero and low when counter reaches Compare B value */
-    etpwmREG5->AQCTLB = ((uint16)((uint16)ActionQual_Set   << 0U) 
-                       | (uint16)((uint16)ActionQual_Clear << 8U));
-
-    /** - Mode setting for Dead Band Module
-    *     -Select the input mode for Dead Band Module
-    *     -Select the output mode for Dead Band Module
-    *     -Select Polarity of the output PWMs
-    */
-    etpwmREG5->DBCTL = (uint16)((uint16)0U << 5U) /* Source for Falling edge delay(0-PWMA, 1-PWMB) */
-                     | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
-                     | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
-                     | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                     | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
-                     | (uint16)((uint16)0U << 0U);    /* Enable/Disable Falling Edge Delay  */
-
-    /** - Set the rising edge delay  */
-    etpwmREG5->DBRED = 1U;
-
-    /** - Set the falling edge delay  */
-    etpwmREG5->DBFED = 1U;
-
-    /** - Enable the chopper module for ETPWMx
-    *     -Sets the One shot pulse width in a chopper modulated wave
-    *     -Sets the dutycycle for the subsequent pulse train
-    *     -Sets the period for the subsequent pulse train
-    */
-    etpwmREG5->PCCTL = (uint16)((uint16)0U << 0U)  /* Enable/Disable chopper module */
-                     | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
-                     | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
-                     | (uint16)((uint16)0U << 5U);   /* Chopping Clock Frequency */
-
-
-        /** - Set trip source enable */
-    etpwmREG5->TZSEL = 0x0000U    /** - Enable/Disable TZ1 as a one-shot trip source */
-                     | 0x0000U    /** - Enable/Disable TZ2 as a one-shot trip source */
-                     | 0x0000U    /** - Enable/Disable TZ3 as a one-shot trip source */
-                     | 0x0000U    /** - Enable/Disable TZ4 as a one-shot trip source */
-                     | 0x0000U    /** - Enable/Disable TZ5 as a one-shot trip source */
-                     | 0x0000U    /** - Enable/Disable TZ6 as a one-shot trip source */
-                     | 0x0000U     /** - Enable/Disable TZ1 as a CBC trip source      */
-                     | 0x0000U    /** - Enable/Disable TZ2 as a CBC trip source      */
-                     | 0x0000U    /** - Enable/Disable TZ3 as a CBC trip source      */
-                     | 0x0000U    /** - Enable/Disable TZ4 as a CBC trip source      */
-                     | 0x0000U    /** - Enable/Disable TZ5 as a CBC trip source        */
-                     | 0x0000U;   /** - Enable/Disable TZ6 as a CBC trip source      */
-
-    /** - Set interrupt enable */
-    etpwmREG5->TZEINT = 0x0000U    /** - Enable/Disable Digital Comparator Output A Event 1 */
-                      | 0x0000U    /** - Enable/Disable Digital Comparator Output A Event 2 */
-                      | 0x0000U    /** - Enable/Disable Digital Comparator Output A Event 1 */
-                      | 0x0000U    /** - Enable/Disable Digital Comparator Output A Event 2 */
-                      | 0x0000U    /** - Enable/Disable one-shot interrupt generation       */
-                      | 0x0000U;   /** - Enable/Disable cycle-by-cycle interrupt generation */
-
-    /** - Sets up the event for interrupt */
-    etpwmREG5->ETSEL = (uint16)NO_EVENT;
-
-    if ((etpwmREG5->ETSEL & 0x0007U) != 0U)
-    {
-        etpwmREG5->ETSEL |= 0x0008U;
-    }
-    /** - Setup the frequency of the interrupt generation */
-    etpwmREG5->ETPS = 1U;
-
-    /** - Sets up the ADC SOC interrupt */
-    etpwmREG5->ETSEL |= (uint16)(0x0000U)
-                      | (uint16)(0x0000U)
-                      | (uint16)((uint16)DCAEVT1 << 8U)
-                      | (uint16)((uint16)DCBEVT1 << 12U);
-
-    /** - Sets up the ADC SOC period */
-    etpwmREG5->ETPS |= ((uint16)((uint16)1U << 8U)
-                      | (uint16)((uint16)1U << 12U));
-
     /** @b initialize @b ETPWM6 */
 
     /** - Sets high speed time-base clock prescale bits */
@@ -559,13 +463,13 @@
     etpwmREG6->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG6->TBPRD = 1000U;
+    etpwmREG6->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG6->CMPA = 50U;
+    etpwmREG6->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG6->CMPB = 50U;
+    etpwmREG6->CMPB = 0U;
 
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
@@ -585,7 +489,7 @@
                      | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                      | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                      | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                     | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                     | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                      | (uint16)((uint16)0U << 0U);    /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -600,7 +504,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG6->PCCTL = (uint16)((uint16)0U << 0U)  /* Enable/Disable chopper module */
-                     | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                     | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                      | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                      | (uint16)((uint16)0U << 5U);   /* Chopping Clock Frequency */
 
@@ -657,13 +561,13 @@
     etpwmREG7->TBCTL |= (uint16)((uint16)0U << 10U);
 
     /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/
-    etpwmREG7->TBPRD = 1000U;
+    etpwmREG7->TBPRD = 25833U;
 
     /** - Setup the duty cycle for PWMA */
-    etpwmREG7->CMPA = 50U;
+    etpwmREG7->CMPA = 0U;
 
     /** - Setup the duty cycle for PWMB */
-    etpwmREG7->CMPB = 50U;
+    etpwmREG7->CMPB = 0U;
 
 
     /** - Force EPWMxA output high when counter reaches zero and low when counter reaches Compare A value */
@@ -683,7 +587,7 @@
                      | (uint16)((uint16)0U << 4U) /* Source for Rising edge delay(0-PWMA, 1-PWMB)  */
                      | (uint16)((uint16)0U << 3U)  /* Enable/Disable EPWMxB invert       */
                      | (uint16)((uint16)0U << 2U)  /* Enable/Disable EPWMxA invert       */
-                     | (uint16)((uint16)0U << 1U) /* Enable/Disable Rising Edge Delay   */
+                     | (uint16)((uint16)1U << 1U) /* Enable/Disable Rising Edge Delay   */
                      | (uint16)((uint16)0U << 0U);    /* Enable/Disable Falling Edge Delay  */
 
     /** - Set the rising edge delay  */
@@ -698,7 +602,7 @@
     *     -Sets the period for the subsequent pulse train
     */
     etpwmREG7->PCCTL = (uint16)((uint16)0U << 0U)  /* Enable/Disable chopper module */
-                     | (uint16)((uint16)1U << 1U)    /* One-shot Pulse Width */
+                     | (uint16)((uint16)0U << 1U)    /* One-shot Pulse Width */
                      | (uint16)((uint16)3U << 8U)  /* Chopping Clock Duty Cycle */
                      | (uint16)((uint16)0U << 5U);   /* Chopping Clock Frequency */
 
Index: firmware/source/gio.c
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/gio.c	(.../gio.c)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/gio.c	(.../gio.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -73,7 +73,7 @@
     /** - Port A output values */
     gioPORTA->DOUT = (uint32)((uint32)0U << 0U)  /* Bit 0 */
                    | (uint32)((uint32)0U << 1U)  /* Bit 1 */
-                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)1U << 2U)  /* Bit 2 */
                    | (uint32)((uint32)0U << 3U)  /* Bit 3 */
                    | (uint32)((uint32)0U << 4U)  /* Bit 4 */
                    | (uint32)((uint32)0U << 5U)  /* Bit 5 */
@@ -83,11 +83,11 @@
     /** - Port A direction */
     gioPORTA->DIR  = (uint32)((uint32)0U << 0U)  /* Bit 0 */
                    | (uint32)((uint32)0U << 1U)  /* Bit 1 */
-                   | (uint32)((uint32)0U << 2U)  /* Bit 2 */
+                   | (uint32)((uint32)1U << 2U)  /* Bit 2 */
                    | (uint32)((uint32)0U << 3U)  /* Bit 3 */
                    | (uint32)((uint32)0U << 4U)  /* Bit 4 */
                    | (uint32)((uint32)0U << 5U)  /* Bit 5 */
-                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)1U << 6U)  /* Bit 6 */
                    | (uint32)((uint32)0U << 7U); /* Bit 7 */
 
     /** - Port A open drain enable */
@@ -107,7 +107,7 @@
                    | (uint32)((uint32)0U << 3U)  /* Bit 3 */
                    | (uint32)((uint32)0U << 4U)  /* Bit 4 */
                    | (uint32)((uint32)0U << 5U)  /* Bit 5 */
-                   | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                   | (uint32)((uint32)1U << 6U)  /* Bit 6 */
                    | (uint32)((uint32)0U << 7U); /* Bit 7 */
 
     /** - Port A pullup / pulldown enable*/
@@ -117,7 +117,7 @@
                       | (uint32)((uint32)0U << 3U)  /* Bit 3 */
                       | (uint32)((uint32)0U << 4U)  /* Bit 4 */
                       | (uint32)((uint32)0U << 5U)  /* Bit 5 */
-                      | (uint32)((uint32)0U << 6U)  /* Bit 6 */
+                      | (uint32)((uint32)1U << 6U)  /* Bit 6 */
                       | (uint32)((uint32)0U << 7U); /* Bit 7 */
 
     /** @b initialize @b Port @b B */
@@ -221,18 +221,18 @@
     gioREG->FLG = 0xFFU;
 
     /** - enable interrupts */
-    gioREG->ENASET = (uint32)((uint32)1U << 0U)   /* Bit 0 */
-                   | (uint32)((uint32)1U << 1U)   /* Bit 1 */
+    gioREG->ENASET = (uint32)((uint32)0U << 0U)   /* Bit 0 */
+                   | (uint32)((uint32)0U << 1U)   /* Bit 1 */
                    | (uint32)((uint32)0U << 2U)   /* Bit 2 */
                    | (uint32)((uint32)0U << 3U)   /* Bit 3 */
                    | (uint32)((uint32)0U << 4U)   /* Bit 4 */
                    | (uint32)((uint32)0U << 5U)   /* Bit 5 */
                    | (uint32)((uint32)0U << 6U)   /* Bit 6 */
                    | (uint32)((uint32)0U << 7U)   /* Bit 7 */
-                   | (uint32)((uint32)1U << 8U)   /* Bit 8  */
-                   | (uint32)((uint32)1U << 9U)   /* Bit 9  */
-                   | (uint32)((uint32)1U << 10U)  /* Bit 10 */
-                   | (uint32)((uint32)1U << 11U)  /* Bit 11 */
+                   | (uint32)((uint32)0U << 8U)   /* Bit 8  */
+                   | (uint32)((uint32)0U << 9U)   /* Bit 9  */
+                   | (uint32)((uint32)0U << 10U)  /* Bit 10 */
+                   | (uint32)((uint32)0U << 11U)  /* Bit 11 */
                    | (uint32)((uint32)0U << 12U)  /* Bit 12 */
                    | (uint32)((uint32)0U << 13U)  /* Bit 13 */
                    | (uint32)((uint32)0U << 14U)  /* Bit 14 */
Index: firmware/source/mibspi.c
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/mibspi.c	(.../mibspi.c)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/mibspi.c	(.../mibspi.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -64,8 +64,963 @@
 /* USER CODE END */
 
 
+    /** @b initialize @b MIBSPI1 */
 
+    /** bring MIBSPI out of reset */
+    mibspiREG1->GCR0 = 0U;
+    mibspiREG1->GCR0 = 1U;
 
+    /** enable MIBSPI1 multibuffered mode and enable buffer RAM */
+    mibspiREG1->MIBSPIE = (mibspiREG1->MIBSPIE & 0xFFFFFFFEU) | 1U;
+
+    /** MIBSPI1 master mode and clock configuration */
+    mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
+                  | 1U);  /* MASTER */
+
+    /** MIBSPI1 enable pin configuration */
+    mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
+
+    /** - Delays */
+    mibspiREG1->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
+                      | (uint32)((uint32)0U << 16U)  /* T2CDELAY */
+                      | (uint32)((uint32)0U << 8U)   /* T2EDELAY */
+                      | (uint32)((uint32)0U << 0U);  /* C2EDELAY */
+
+    /** - Data Format 0 */
+    mibspiREG1->FMT0 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 1 */
+    mibspiREG1->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 2 */
+    mibspiREG1->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 3 */
+    mibspiREG1->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Default Chip Select */
+    mibspiREG1->DEF = (uint32)(0xFFU);
+
+    /** - wait for buffer initialization complete before accessing MibSPI registers */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((mibspiREG1->FLG & 0x01000000U) != 0U)
+    {
+    } /* Wait */
+
+    /** enable MIBSPI RAM Parity */
+    mibspiREG1->UERRCTRL = (mibspiREG1->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U);
+
+    /** - initialize transfer groups */
+    mibspiREG1->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)0U << 8U);  /* start buffer */
+
+    mibspiREG1->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)8U << 8U);  /* start buffer */
+
+    mibspiREG1->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U) << 8U);  /* start buffer */
+
+    mibspiREG1->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG1->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG1->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG1->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG1->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(8U+0U+0U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+
+    mibspiREG1->TGCTRL[8U] = (uint32)(8U+0U+0U+0U+0U+0U+0U+0U) << 8U;
+
+    mibspiREG1->LTGPEND = (mibspiREG1->LTGPEND & 0xFFFF00FFU) | (uint32)((uint32)((8U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
+
+    /** - initialize buffer ram */
+    {
+        i = 0U;
+
+#if (8U > 0U)
+        {
+
+#if (8U > 1U)
+
+            while (i < (8U-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU);  /* chip select */
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU);  /* chip select */
+
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U)-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U)-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_2)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U)-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_3)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_4)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_5)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_6)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((8U+0U+0U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM1->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_7)) & (uint16)0x00FFU);  /* chip select */
+            i++;
+        }
+#endif
+    }
+
+    /** - set interrupt levels */
+    mibspiREG1->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
+                    | (uint32)((uint32)0U << 8U)  /* RXINT */
+                    | (uint32)((uint32)0U << 6U)  /* OVRNINT */
+                    | (uint32)((uint32)0U << 4U)  /* BITERR */
+                    | (uint32)((uint32)0U << 3U)  /* DESYNC */
+                    | (uint32)((uint32)0U << 2U)  /* PARERR */
+                    | (uint32)((uint32)0U << 1U)  /* TIMEOUT */
+                    | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+    /** - clear any pending interrupts */
+    mibspiREG1->FLG |= 0xFFFFU;
+
+    /** - enable interrupts */
+    mibspiREG1->INT0 = (mibspiREG1->INT0 & 0xFFFF0000U)
+                     | (uint32)((uint32)0U << 9U)  /* TXINT */
+                     | (uint32)((uint32)0U << 8U)  /* RXINT */
+                     | (uint32)((uint32)0U << 6U)  /* OVRNINT */
+                     | (uint32)((uint32)0U << 4U)  /* BITERR */
+                     | (uint32)((uint32)0U << 3U)  /* DESYNC */
+                     | (uint32)((uint32)0U << 2U)  /* PARERR */
+                     | (uint32)((uint32)0U << 1U)  /* TIMEOUT */
+                     | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+    /** @b initialize @b MIBSPI1 @b Port */
+
+    /** - MIBSPI1 Port output values */
+    mibspiREG1->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO[0] */
+                    | (uint32)((uint32)0U << 11U)  /* SOMI[0] */
+                    | (uint32)((uint32)0U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+    /** - MIBSPI1 Port direction */
+    mibspiREG1->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO[0] */
+                    | (uint32)((uint32)0U << 11U)  /* SOMI[0] */
+                    | (uint32)((uint32)0U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+    /** - MIBSPI1 Port open drain enable */
+    mibspiREG1->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO[0] */
+                    | (uint32)((uint32)0U << 11U)  /* SOMI[0] */
+                    | (uint32)((uint32)0U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+    /** - MIBSPI1 Port pullup / pulldown selection */
+    mibspiREG1->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO[0] */
+                    | (uint32)((uint32)1U << 11U)  /* SOMI[0] */
+                    | (uint32)((uint32)1U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)1U << 25U); /* SOMI[1] */
+
+    /** - MIBSPI1 Port pullup / pulldown enable*/
+    mibspiREG1->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO[0] */
+                    | (uint32)((uint32)0U << 11U)  /* SOMI[0] */
+                    | (uint32)((uint32)0U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)0U << 25U); /* SOMI[1] */
+
+    /* MIBSPI1 set all pins to functional */
+    mibspiREG1->PC0 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO[0] */
+                    | (uint32)((uint32)1U << 11U)  /* SOMI[0] */
+                    | (uint32)((uint32)1U << 17U)  /* SIMO[1] */
+                    | (uint32)((uint32)1U << 25U); /* SOMI[1] */
+
+    /** - Finally start MIBSPI1 */
+    mibspiREG1->GCR1 = (mibspiREG1->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
+
+
+
+     /** @b initialize @b MIBSPI3 */
+
+    /** bring MIBSPI out of reset */
+    mibspiREG3->GCR0 = 0U;
+    mibspiREG3->GCR0 = 1U;
+
+    /** enable MIBSPI3 multibuffered mode and enable buffer RAM */
+    mibspiREG3->MIBSPIE = (mibspiREG3->MIBSPIE & 0xFFFFFFFEU) | 1U;
+
+    /** MIBSPI3 master mode and clock configuration */
+    mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFFFFFFFCU) | ((uint32)((uint32)1U << 1U)  /* CLOKMOD */
+                  | 1U);  /* MASTER */
+
+    /** MIBSPI3 enable pin configuration */
+    mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFEFFFFFFU) | (uint32)((uint32)0U << 24U);  /* ENABLE HIGHZ */
+
+    /** - Delays */
+    mibspiREG3->DELAY = (uint32)((uint32)0U << 24U)  /* C2TDELAY */
+                      | (uint32)((uint32)0U << 16U)  /* T2CDELAY */
+                      | (uint32)((uint32)0U << 8U)   /* T2EDELAY */
+                      | (uint32)((uint32)0U << 0U);  /* C2EDELAY */
+
+    /** - Data Format 0 */
+    mibspiREG3->FMT0 = (uint32)((uint32)20U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)1U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)8U << 0U); /* data word length */
+
+    /** - Data Format 1 */
+    mibspiREG3->FMT1 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 2 */
+    mibspiREG3->FMT2 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Data Format 3 */
+    mibspiREG3->FMT3 = (uint32)((uint32)0U << 24U)  /* wdelay */
+                     | (uint32)((uint32)0U << 23U)  /* parity Polarity */
+                     | (uint32)((uint32)0U << 22U)  /* parity enable */
+                     | (uint32)((uint32)0U << 21U)  /* wait on enable */
+                     | (uint32)((uint32)0U << 20U)  /* shift direction */
+                     | (uint32)((uint32)0U << 17U)  /* clock polarity */
+                     | (uint32)((uint32)0U << 16U)  /* clock phase */
+                     | (uint32)((uint32)102U << 8U)  /* baudrate prescale */
+                     | (uint32)((uint32)16U << 0U); /* data word length */
+
+    /** - Default Chip Select */
+    mibspiREG3->DEF = (uint32)(0xFFU);
+
+    /** - wait for buffer initialization complete before accessing MibSPI registers */
+    /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
+    while ((mibspiREG3->FLG & 0x01000000U) != 0U)
+    {
+    } /* Wait */
+
+    /** enable MIBSPI RAM Parity */
+    mibspiREG3->UERRCTRL = (mibspiREG3->UERRCTRL & 0xFFFFFFF0U) | (0x00000005U);
+
+    /** - initialize transfer groups */
+    mibspiREG3->TGCTRL[0U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)0U << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[1U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)11U << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[2U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(11U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[3U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(11U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[4U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(11U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[5U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(11U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[6U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(11U+0U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+    mibspiREG3->TGCTRL[7U] = (uint32)((uint32)1U << 30U)  /* oneshot */
+                           | (uint32)((uint32)0U << 29U)  /* pcurrent reset */
+                           | (uint32)((uint32)TRG_ALWAYS << 20U)  /* trigger event */
+                           | (uint32)((uint32)TRG_DISABLED << 16U)  /* trigger source */
+                           | (uint32)((uint32)(11U+0U+0U+0U+0U+0U+0U) << 8U);  /* start buffer */
+
+
+    mibspiREG3->TGCTRL[8U] = (uint32)(11U+0U+0U+0U+0U+0U+0U+0U) << 8U;
+
+    mibspiREG3->LTGPEND = (mibspiREG3->LTGPEND & 0xFFFF00FFU) | (uint32)(((uint32)(11U+0U+0U+0U+0U+0U+0U+0U)-1U) << 8U);
+
+    /** - initialize buffer ram */
+    {
+        i = 0U;
+
+#if (11U > 0U)
+        {
+
+#if (11U > 1U)
+
+            while (i < (11U-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)1U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU);  /* chip select */
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU);  /* chip select */
+
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((11U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((11U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((11U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((11U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((11U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((11U+0U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+            i++;
+        }
+#endif
+
+#if (0U > 0U)
+        {
+
+#if (0U > 1U)
+
+            while (i < ((11U+0U+0U+0U+0U+0U+0U+0U)-1U))
+            {
+                mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                          | (uint16)((uint16)0U << 12U)  /* chip select hold */
+                                          | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                          | (uint16)((uint16)0U << 11U)  /* lock transmission */
+                                          | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                          | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+
+                i++;
+            }
+#endif
+            mibspiRAM3->tx[i].control = (uint16)((uint16)4U << 13U)  /* buffer mode */
+                                      | (uint16)((uint16)0U << 12U) /* chip select hold */
+                                      | (uint16)((uint16)0U << 10U)  /* enable WDELAY */
+                                      | (uint16)((uint16)0U << 8U)  /* data format */
+										  /*SAFETYMCUSW 334 S MR:10.5 <APPROVED> "LDRA Tool issue" */
+                                      | ((uint16)(~((uint16)0xFFU ^ (uint16)CS_NONE)) & (uint16)0x00FFU);  /* chip select */
+            i++;
+        }
+#endif
+    }
+
+    /** - set interrupt levels */
+    mibspiREG3->LVL = (uint32)((uint32)0U << 9U)  /* TXINT */
+                    | (uint32)((uint32)0U << 8U)  /* RXINT */
+                    | (uint32)((uint32)0U << 6U)  /* OVRNINT */
+                    | (uint32)((uint32)0U << 4U)  /* BITERR */
+                    | (uint32)((uint32)0U << 3U)  /* DESYNC */
+                    | (uint32)((uint32)0U << 2U)  /* PARERR */
+                    | (uint32)((uint32)0U << 1U)  /* TIMEOUT */
+                    | (uint32)((uint32)0U << 0U); /* DLENERR */
+
+    /** - clear any pending interrupts */
+    mibspiREG3->FLG |= 0xFFFFU;
+
+    /** - enable interrupts */
+    mibspiREG3->INT0 = (mibspiREG3->INT0 & 0xFFFF0000U)
+                     | (uint32)((uint32)0U << 9U)  /* TXINT */
+                     | (uint32)((uint32)0U << 8U)  /* RXINT */
+                     | (uint32)((uint32)1U << 6U)  /* OVRNINT */
+                     | (uint32)((uint32)1U << 4U)  /* BITERR */
+                     | (uint32)((uint32)1U << 3U)  /* DESYNC */
+                     | (uint32)((uint32)1U << 2U)  /* PARERR */
+                     | (uint32)((uint32)1U << 1U)  /* TIMEOUT */
+                     | (uint32)((uint32)1U << 0U); /* DLENERR */
+
+    /** @b initialize @b MIBSPI3 @b Port */
+
+    /** - MIBSPI3 Port output values */
+    mibspiREG3->PC3 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+    /** - MIBSPI3 Port direction */
+    mibspiREG3->PC1 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+    /** - MIBSPI3 Port open drain enable */
+    mibspiREG3->PC6 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+
+    /** - MIBSPI3 Port pullup / pulldown selection */
+    mibspiREG3->PC8 = (uint32)((uint32)1U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)1U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)1U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)1U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO */
+                    | (uint32)((uint32)1U << 11U); /* SOMI */
+
+
+    /** - MIBSPI3 Port pullup / pulldown enable*/
+    mibspiREG3->PC7 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)0U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)0U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 9U)  /* CLK */
+                    | (uint32)((uint32)0U << 10U)  /* SIMO */
+                    | (uint32)((uint32)0U << 11U); /* SOMI */
+
+
+    /* MIBSPI3 set all pins to functional */
+    mibspiREG3->PC0 = (uint32)((uint32)0U << 0U)  /* SCS[0] */
+                    | (uint32)((uint32)1U << 1U)  /* SCS[1] */
+                    | (uint32)((uint32)0U << 2U)  /* SCS[2] */
+                    | (uint32)((uint32)0U << 3U)  /* SCS[3] */
+                    | (uint32)((uint32)0U << 4U)  /* SCS[4] */
+                    | (uint32)((uint32)1U << 5U)  /* SCS[5] */
+                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 9U)  /* CLK */
+                    | (uint32)((uint32)1U << 10U)  /* SIMO */
+                    | (uint32)((uint32)1U << 11U); /* SOMI */
+
+    /** - Finally start MIBSPI3 */
+    mibspiREG3->GCR1 = (mibspiREG3->GCR1 & 0xFEFFFFFFU) | 0x01000000U;
+
+
+
     /** @b initialize @b MIBSPI5 */
 
     /** bring MIBSPI out of reset */
@@ -481,7 +1436,7 @@
                     | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)1U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)1U << 3U)  /* SCS[3] */
-                    | (uint32)((uint32)0U << 8U)  /* ENA */
+                    | (uint32)((uint32)1U << 8U)  /* ENA */
                     | (uint32)((uint32)1U << 9U)  /* CLK */
                     | (uint32)((uint32)1U << 10U)  /* SIMO[0] */
                     | (uint32)((uint32)1U << 11U)  /* SOMI[0] */
@@ -513,7 +1468,7 @@
                     | (uint32)((uint32)1U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)1U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)1U << 3U)  /* SCS[3] */
-                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
                     | (uint32)((uint32)1U << 9U)  /* CLK */
                     | (uint32)((uint32)1U << 10U)  /* SIMO[0] */
                     | (uint32)((uint32)1U << 11U)  /* SOMI[0] */
@@ -545,7 +1500,7 @@
                     | (uint32)((uint32)0U << 1U)  /* SCS[1] */
                     | (uint32)((uint32)0U << 2U)  /* SCS[2] */
                     | (uint32)((uint32)0U << 3U)  /* SCS[3] */
-                    | (uint32)((uint32)1U << 8U)  /* ENA */
+                    | (uint32)((uint32)0U << 8U)  /* ENA */
                     | (uint32)((uint32)0U << 9U)  /* CLK */
                     | (uint32)((uint32)0U << 10U)  /* SIMO[0] */
                     | (uint32)((uint32)0U << 11U)  /* SOMI[0] */
@@ -857,7 +1812,159 @@
 /* USER CODE END */
 }
 
+/** @fn void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current
+*                           value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type')
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : MIBSPI_SourceId_012 */
+/* DesignId : MIBSPI_DesignId_012 */
+/* Requirements : HL_SR166 */
+void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_GCR1       = MIBSPI1_GCR1_CONFIGVALUE;
+        config_reg->CONFIG_INT0       = MIBSPI1_INT0_CONFIGVALUE;
+        config_reg->CONFIG_LVL        = MIBSPI1_LVL_CONFIGVALUE;
+        config_reg->CONFIG_PCFUN      = MIBSPI1_PCFUN_CONFIGVALUE;
+        config_reg->CONFIG_PCDIR      = MIBSPI1_PCDIR_CONFIGVALUE;
+        config_reg->CONFIG_PCPDR      = MIBSPI1_PCPDR_CONFIGVALUE;
+        config_reg->CONFIG_PCDIS      = MIBSPI1_PCDIS_CONFIGVALUE;
+        config_reg->CONFIG_PCPSL      = MIBSPI1_PCPSL_CONFIGVALUE;
+        config_reg->CONFIG_DELAY      = MIBSPI1_DELAY_CONFIGVALUE;
+        config_reg->CONFIG_FMT0       = MIBSPI1_FMT0_CONFIGVALUE;
+        config_reg->CONFIG_FMT1       = MIBSPI1_FMT1_CONFIGVALUE;
+        config_reg->CONFIG_FMT2       = MIBSPI1_FMT2_CONFIGVALUE;
+        config_reg->CONFIG_FMT3       = MIBSPI1_FMT3_CONFIGVALUE;
+        config_reg->CONFIG_MIBSPIE    = MIBSPI1_MIBSPIE_CONFIGVALUE;
+        config_reg->CONFIG_LTGPEND    = MIBSPI1_LTGPEND_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[0U] = MIBSPI1_TGCTRL0_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[1U] = MIBSPI1_TGCTRL1_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[2U] = MIBSPI1_TGCTRL2_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[3U] = MIBSPI1_TGCTRL3_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[4U] = MIBSPI1_TGCTRL4_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[5U] = MIBSPI1_TGCTRL5_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[6U] = MIBSPI1_TGCTRL6_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[7U] = MIBSPI1_TGCTRL7_CONFIGVALUE;
+        config_reg->CONFIG_UERRCTRL   = MIBSPI1_UERRCTRL_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_GCR1       = mibspiREG1->GCR1;
+        config_reg->CONFIG_INT0       = mibspiREG1->INT0;
+        config_reg->CONFIG_LVL        = mibspiREG1->LVL;
+        config_reg->CONFIG_PCFUN      = mibspiREG1->PC0;
+        config_reg->CONFIG_PCDIR      = mibspiREG1->PC1;
+        config_reg->CONFIG_PCPDR      = mibspiREG1->PC6;
+        config_reg->CONFIG_PCDIS      = mibspiREG1->PC7;
+        config_reg->CONFIG_PCPSL      = mibspiREG1->PC8;
+        config_reg->CONFIG_DELAY      = mibspiREG1->DELAY;
+        config_reg->CONFIG_FMT0       = mibspiREG1->FMT0;
+        config_reg->CONFIG_FMT1       = mibspiREG1->FMT1;
+        config_reg->CONFIG_FMT2       = mibspiREG1->FMT2;
+        config_reg->CONFIG_FMT3       = mibspiREG1->FMT3;
+        config_reg->CONFIG_MIBSPIE    = mibspiREG1->MIBSPIE;
+        config_reg->CONFIG_LTGPEND    = mibspiREG1->LTGPEND;
+        config_reg->CONFIG_TGCTRL[0U] = mibspiREG1->TGCTRL[0U];
+        config_reg->CONFIG_TGCTRL[1U] = mibspiREG1->TGCTRL[1U];
+        config_reg->CONFIG_TGCTRL[2U] = mibspiREG1->TGCTRL[2U];
+        config_reg->CONFIG_TGCTRL[3U] = mibspiREG1->TGCTRL[3U];
+        config_reg->CONFIG_TGCTRL[4U] = mibspiREG1->TGCTRL[4U];
+        config_reg->CONFIG_TGCTRL[5U] = mibspiREG1->TGCTRL[5U];
+        config_reg->CONFIG_TGCTRL[6U] = mibspiREG1->TGCTRL[6U];
+        config_reg->CONFIG_TGCTRL[7U] = mibspiREG1->TGCTRL[7U];
+        config_reg->CONFIG_UERRCTRL   = mibspiREG1->UERRCTRL;
+    }
+}
 
+/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type)
+*   @brief Get the initial or current values of the configuration registers
+*
+*    @param[in] *config_reg: pointer to the struct to which the initial or current
+*                           value of the configuration registers need to be stored
+*    @param[in] type:     whether initial or current value of the configuration registers need to be stored
+*                        - InitialValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*                        - CurrentValue: initial value of the configuration registers will be stored
+*                                       in the struct pointed by config_reg
+*
+*   This function will copy the initial or current value (depending on the parameter 'type')
+*   of the configuration registers to the struct pointed by config_reg
+*
+*/
+/* SourceId : MIBSPI_SourceId_013 */
+/* DesignId : MIBSPI_DesignId_012 */
+/* Requirements : HL_SR166 */
+void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type)
+{
+    if (type == InitialValue)
+    {
+        config_reg->CONFIG_GCR1       = MIBSPI3_GCR1_CONFIGVALUE;
+        config_reg->CONFIG_INT0       = MIBSPI3_INT0_CONFIGVALUE;
+        config_reg->CONFIG_LVL        = MIBSPI3_LVL_CONFIGVALUE;
+        config_reg->CONFIG_PCFUN      = MIBSPI3_PCFUN_CONFIGVALUE;
+        config_reg->CONFIG_PCDIR      = MIBSPI3_PCDIR_CONFIGVALUE;
+        config_reg->CONFIG_PCPDR      = MIBSPI3_PCPDR_CONFIGVALUE;
+        config_reg->CONFIG_PCDIS      = MIBSPI3_PCDIS_CONFIGVALUE;
+        config_reg->CONFIG_PCPSL      = MIBSPI3_PCPSL_CONFIGVALUE;
+        config_reg->CONFIG_DELAY      = MIBSPI3_DELAY_CONFIGVALUE;
+        config_reg->CONFIG_FMT0       = MIBSPI3_FMT0_CONFIGVALUE;
+        config_reg->CONFIG_FMT1       = MIBSPI3_FMT1_CONFIGVALUE;
+        config_reg->CONFIG_FMT2       = MIBSPI3_FMT2_CONFIGVALUE;
+        config_reg->CONFIG_FMT3       = MIBSPI3_FMT3_CONFIGVALUE;
+        config_reg->CONFIG_MIBSPIE    = MIBSPI3_MIBSPIE_CONFIGVALUE;
+        config_reg->CONFIG_LTGPEND    = MIBSPI3_LTGPEND_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[0U] = MIBSPI3_TGCTRL0_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[1U] = MIBSPI3_TGCTRL1_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[2U] = MIBSPI3_TGCTRL2_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[3U] = MIBSPI3_TGCTRL3_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[4U] = MIBSPI3_TGCTRL4_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[5U] = MIBSPI3_TGCTRL5_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[6U] = MIBSPI3_TGCTRL6_CONFIGVALUE;
+        config_reg->CONFIG_TGCTRL[7U] = MIBSPI3_TGCTRL7_CONFIGVALUE;
+        config_reg->CONFIG_UERRCTRL   = MIBSPI3_UERRCTRL_CONFIGVALUE;
+    }
+    else
+    {
+    /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
+        config_reg->CONFIG_GCR1       = mibspiREG3->GCR1;
+        config_reg->CONFIG_INT0       = mibspiREG3->INT0;
+        config_reg->CONFIG_LVL        = mibspiREG3->LVL;
+        config_reg->CONFIG_PCFUN      = mibspiREG3->PC0;
+        config_reg->CONFIG_PCDIR      = mibspiREG3->PC1;
+        config_reg->CONFIG_PCPDR      = mibspiREG3->PC6;
+        config_reg->CONFIG_PCDIS      = mibspiREG3->PC7;
+        config_reg->CONFIG_PCPSL      = mibspiREG3->PC8;
+        config_reg->CONFIG_DELAY      = mibspiREG3->DELAY;
+        config_reg->CONFIG_FMT0       = mibspiREG3->FMT0;
+        config_reg->CONFIG_FMT1       = mibspiREG3->FMT1;
+        config_reg->CONFIG_FMT2       = mibspiREG3->FMT2;
+        config_reg->CONFIG_FMT3       = mibspiREG3->FMT3;
+        config_reg->CONFIG_MIBSPIE    = mibspiREG3->MIBSPIE;
+        config_reg->CONFIG_LTGPEND    = mibspiREG3->LTGPEND;
+        config_reg->CONFIG_TGCTRL[0U] = mibspiREG3->TGCTRL[0U];
+        config_reg->CONFIG_TGCTRL[1U] = mibspiREG3->TGCTRL[1U];
+        config_reg->CONFIG_TGCTRL[2U] = mibspiREG3->TGCTRL[2U];
+        config_reg->CONFIG_TGCTRL[3U] = mibspiREG3->TGCTRL[3U];
+        config_reg->CONFIG_TGCTRL[4U] = mibspiREG3->TGCTRL[4U];
+        config_reg->CONFIG_TGCTRL[5U] = mibspiREG3->TGCTRL[5U];
+        config_reg->CONFIG_TGCTRL[6U] = mibspiREG3->TGCTRL[6U];
+        config_reg->CONFIG_TGCTRL[7U] = mibspiREG3->TGCTRL[7U];
+        config_reg->CONFIG_UERRCTRL   = mibspiREG3->UERRCTRL;
+    }
+}
 
 /** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t type)
 *   @brief Get the initial or current values of the configuration registers
@@ -940,3 +2047,5 @@
 
 
 
+
+
Index: firmware/source/notification.c
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/notification.c	(.../notification.c)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/notification.c	(.../notification.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -50,11 +50,13 @@
 
 #include "esm.h"
 #include "sys_selftest.h"
+#include "adc.h"
 #include "can.h"
 #include "gio.h"
 #include "mibspi.h"
 #include "sci.h"
 #include "rti.h"
+#include "etpwm.h"
 #include "sys_dma.h"
 
 /* USER CODE BEGIN (0) */
@@ -109,6 +111,16 @@
 
 /* USER CODE BEGIN (10) */
 /* USER CODE END */
+#pragma WEAK(adcNotification)
+void adcNotification(adcBASE_t *adc, uint32 group)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (11) */
+/* USER CODE END */
+}
+
+/* USER CODE BEGIN (12) */
+/* USER CODE END */
 #pragma WEAK(canErrorNotification)
 void canErrorNotification(canBASE_t *node, uint32 notification)
 {
@@ -181,7 +193,24 @@
 /* USER CODE BEGIN (43) */
 /* USER CODE END */
 
+#pragma WEAK(etpwmNotification)
+void etpwmNotification(etpwmBASE_t *node)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (44) */
+/* USER CODE END */
+}
+#pragma WEAK(etpwmTripNotification)
+void etpwmTripNotification(etpwmBASE_t *node,uint16 flags)
+{
+/*  enter user code between the USER CODE BEGIN and USER CODE END. */
+/* USER CODE BEGIN (45) */
+/* USER CODE END */
+}
 
+/* USER CODE BEGIN (46) */
+/* USER CODE END */
+
 /* USER CODE BEGIN (47) */
 /* USER CODE END */
 
Index: firmware/source/pinmux.c
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/pinmux.c	(.../pinmux.c)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/pinmux.c	(.../pinmux.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -170,23 +170,23 @@
 
     pinMuxReg->PINMMR0 =    PINMUX_PIN_1_GIOB_3 | PINMUX_PIN_2_GIOA_0 | PINMUX_PIN_3_MIBSPI3NCS_3 | PINMUX_PIN_4_MIBSPI3NCS_2;
     
-    pinMuxReg->PINMMR1 =    PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_HET1_11;
+    pinMuxReg->PINMMR1 =    PINMUX_PIN_5_GIOA_1 | PINMUX_PIN_6_MIBSPI3NCS_4;
     
-    pinMuxReg->PINMMR2 =    PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_GIOA_5;
+    pinMuxReg->PINMMR2 =    PINMUX_PIN_9_GIOA_2 | PINMUX_PIN_14_ETPWM1A;
     
-    pinMuxReg->PINMMR3 =    PINMUX_PIN_15_HET1_22 | PINMUX_PIN_16_GIOA_6;
+    pinMuxReg->PINMMR3 =    PINMUX_PIN_15_W2FC_SE0O | PINMUX_PIN_16_GIOA_6;
     
-    pinMuxReg->PINMMR4 =    PINMUX_PIN_22_GIOA_7 | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03;
+    pinMuxReg->PINMMR4 =    PINMUX_PIN_22_ETPWM2A | PINMUX_PIN_23_HET1_01 | PINMUX_PIN_24_HET1_03;
     
-    pinMuxReg->PINMMR5 =    PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_HET1_02 | PINMUX_PIN_31_HET1_05;
+    pinMuxReg->PINMMR5 =    PINMUX_PIN_25_HET1_0 | PINMUX_PIN_30_ETPWM3A | PINMUX_PIN_31_HET1_05;
     
-    pinMuxReg->PINMMR6 =    PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_HET1_09;
+    pinMuxReg->PINMMR6 =    PINMUX_PIN_33_HET1_07 | PINMUX_PIN_35_ETPWM7A;
     
     pinMuxReg->PINMMR7 =    PINMUX_PIN_37_MIBSPI3NCS_1 | PINMUX_PIN_38_SCIRX;
     
     pinMuxReg->PINMMR8 =    PINMUX_PIN_39_SCITX | PINMUX_PIN_40_MIBSPI1NCS_2 | PINMUX_PIN_41_HET1_15;
     
-    pinMuxReg->PINMMR9 =  ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_MIBSPI3NENA | PINMUX_PIN_55_MIBSPI3NCS_0;
+    pinMuxReg->PINMMR9 =  ((~(pinMuxReg->PINMMR9 >> 18U) & 0x00000001U ) << 18U) | PINMUX_PIN_54_MIBSPI3NCS_5 | PINMUX_PIN_55_MIBSPI3NCS_0;
     
     pinMuxReg->PINMMR10 =   PINMUX_PIN_86_AD1EVT;
     
@@ -224,7 +224,7 @@
     /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */
     pinMuxReg->PINMMR26 =   ((~(pinMuxReg->PINMMR0 >> 18U) & 0x00000001U ) << 0U) | ((~(pinMuxReg->PINMMR9 >> 10U) & 0x00000001U ) << 8U);
     
-    pinMuxReg->PINMMR27 =   PINMUX_PIN_32_MIBSPI5NCS_0;
+    pinMuxReg->PINMMR27 =   PINMUX_PIN_32_ETPWM4A;
         
     pinMuxReg->PINMMR29 =   0x01010101U;
 
@@ -236,7 +236,7 @@
 
     pinMuxReg->PINMMR33 =   PINMUX_PIN_36_HET1_04 | PINMUX_PIN_51_MIBSPI3SOMI | PINMUX_PIN_52_MIBSPI3SIMO | PINMUX_PIN_53_MIBSPI3CLK;
 
-    pinMuxReg->PINMMR34 =   PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_HET1_18 | PINMUX_PIN_141_HET1_20;
+    pinMuxReg->PINMMR34 =   PINMUX_PIN_139_HET1_16 | PINMUX_PIN_140_ETPWM6A | PINMUX_PIN_141_HET1_20;
 
     
 /* USER CODE BEGIN (3) */
Index: firmware/source/rti.c
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/rti.c	(.../rti.c)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/rti.c	(.../rti.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -123,10 +123,10 @@
     rtiREG1->CMP[0U].UDCPx = 10334U;
 
     /** - Setup compare 1 value. This value is compared with selected free running counter. */
-    rtiREG1->CMP[1U].COMPx = 51668U;
+    rtiREG1->CMP[1U].COMPx = 103335U;
 
     /** - Setup update compare 1 value. This value is added to the compare 1 value on each compare match. */
-    rtiREG1->CMP[1U].UDCPx = 51668U;
+    rtiREG1->CMP[1U].UDCPx = 103335U;
 
     /** - Setup compare 2 value. This value is compared with selected free running counter. */
     rtiREG1->CMP[2U].COMPx = 82668U;
Index: firmware/source/sys_core.asm
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/sys_core.asm	(.../sys_core.asm)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/sys_core.asm	(.../sys_core.asm)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -161,11 +161,11 @@
         bx    lr
 
 userSp  .word 0x08000000+0x00001000
-svcSp   .word 0x08000000+0x00001000+0x00000100
-fiqSp   .word 0x08000000+0x00001000+0x00000100+0x00000100
-irqSp   .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100
-abortSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100
-undefSp .word 0x08000000+0x00001000+0x00000100+0x00000100+0x00000100+0x00000100+0x00000100
+svcSp   .word 0x08000000+0x00001000+0x00000400
+fiqSp   .word 0x08000000+0x00001000+0x00000400+0x00001000
+irqSp   .word 0x08000000+0x00001000+0x00000400+0x00001000+0x00001000
+abortSp .word 0x08000000+0x00001000+0x00000400+0x00001000+0x00001000+0x00000200
+undefSp .word 0x08000000+0x00001000+0x00000400+0x00001000+0x00001000+0x00000200+0x00000200
 
     .endasmfunc
 
Index: firmware/source/sys_link.cmd
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/sys_link.cmd	(.../sys_link.cmd)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -56,8 +56,8 @@
 {
     VECTORS (X)  : origin=0x00000000 length=0x00000020
     FLASH0  (RX) : origin=0x00000020 length=0x0013FFE0
-    STACKS  (RW) : origin=0x08000000 length=0x00001500
-    RAM     (RW) : origin=0x08001500 length=0x0002eb00
+    STACKS  (RW) : origin=0x08000000 length=0x00003800
+    RAM     (RW) : origin=0x08003800 length=0x0002c800
 
 /* USER CODE BEGIN (2) */
 /* USER CODE END */
Index: firmware/source/sys_main.c
===================================================================
diff -u -rdcbd821e41803adc6e582d909207bc97f85ff939 -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/sys_main.c	(.../sys_main.c)	(revision dcbd821e41803adc6e582d909207bc97f85ff939)
+++ firmware/source/sys_main.c	(.../sys_main.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -52,19 +52,23 @@
 /* USER CODE BEGIN (1) */
 #include "system.h"
 #include "sys_dma.h"
+#include "adc.h"
 #include "can.h"
+#include "etpwm.h"
 #include "gio.h"
 #include "mibspi.h"
 #include "sci.h"
 #include "rti.h"
 
 #include "Common.h"
-#include "AlarmLamp.h"
+#include "AlarmMgmt.h"
 #include "CommBuffers.h"
 #include "CPLD.h"
 #include "FPGA.h"
+#include "InternalADC.h"
 #include "MsgQueues.h"
 #include "OperationModes.h"
+#include "RTC.h"
 #include "SafetyShutdown.h"
 #include "SystemComm.h"
 #include "TaskBG.h"
@@ -122,7 +126,15 @@
 static void initProcessor( void )
 {
     gioInit();      // configure GPIO pins
-    mibspiInit();   // re-purposing MIBSPI5 I/O/C pins as GPIO
+    adcInit();      // configure internal ADC channels
+    mibspiInit();   // configure MIBSPI3 and re-purpose MIBSPI1 & 5 pins for GPIO
+    etpwmInit();    // configure PWMs
+        etpwmSetCmpA( etpwmREG1, 0 );
+        etpwmSetCmpA( etpwmREG2, 0 );
+        etpwmSetCmpA( etpwmREG3, 0 );
+        etpwmSetCmpA( etpwmREG4, 0 );
+        etpwmSetCmpA( etpwmREG6, 0 );
+        etpwmSetCmpA( etpwmREG7, 0 );
     canInit();      // CAN1 = CAN, re-purposing CAN2 and CAN3 Rx and Tx pins as GPIO
     sciInit();      // SCI1 used for PC serial interface, SCI2 used for FPGA serial interface
     dmaEnable();    // enable DMA
@@ -141,9 +153,11 @@
     initTimers();
     initSafetyShutdown();
     initCPLD();
-    initAlarmLamp();
+    initAlarmMgmt();
     initWatchdogMgmt();
     initFPGA();
+    initInternalADC();
+    initRTC();
     initCommBuffers();
     initMsgQueues();
     initSystemComm();
Index: firmware/source/sys_vim.c
===================================================================
diff -u -reff7b1575f008f81b29ef906f6346fac6012d3ab -rf068446fdb7889d320ddb6ffbd58f347ce0501e7
--- firmware/source/sys_vim.c	(.../sys_vim.c)	(revision eff7b1575f008f81b29ef906f6346fac6012d3ab)
+++ firmware/source/sys_vim.c	(.../sys_vim.c)	(revision f068446fdb7889d320ddb6ffbd58f347ce0501e7)
@@ -84,7 +84,7 @@
     &phantomInterrupt,            /* Channel 12 */
     &linHighLevelInterrupt,            /* Channel 13 */
     &phantomInterrupt,            /* Channel 14 */
-    &phantomInterrupt,            /* Channel 15 */
+    &adc1Group1Interrupt,            /* Channel 15 */
     &can1HighLevelInterrupt,            /* Channel 16 */
     &phantomInterrupt,            /* Channel 17 */
     &phantomInterrupt,            /* Channel 18 */
@@ -98,7 +98,7 @@
     &phantomInterrupt,            /* Channel 26 */
     &phantomInterrupt,            /* Channel 27 */
     &phantomInterrupt,            /* Channel 28 */
-    &phantomInterrupt,            /* Channel 29 */
+    &can1LowLevelInterrupt,            /* Channel 29 */
     &phantomInterrupt,            /* Channel 30 */
     &phantomInterrupt,            /* Channel 31 */
     &phantomInterrupt,            /* Channel 32 */
@@ -242,7 +242,7 @@
                     | (uint32)((uint32)SYS_IRQ << 12U)
                     | (uint32)((uint32)SYS_FIQ << 13U)
                     | (uint32)((uint32)SYS_IRQ << 14U)
-                    | (uint32)((uint32)SYS_IRQ << 15U)
+                    | (uint32)((uint32)SYS_FIQ << 15U)
                     | (uint32)((uint32)SYS_FIQ << 16U)
                     | (uint32)((uint32)SYS_IRQ << 17U)
                     | (uint32)((uint32)SYS_IRQ << 18U)
@@ -377,7 +377,7 @@
                         | (uint32)((uint32)0U << 12U)
                         | (uint32)((uint32)1U << 13U)
                         | (uint32)((uint32)0U << 14U)
-                        | (uint32)((uint32)0U << 15U)
+                        | (uint32)((uint32)1U << 15U)
                         | (uint32)((uint32)1U << 16U)
                         | (uint32)((uint32)0U << 17U)
                         | (uint32)((uint32)0U << 18U)
@@ -391,7 +391,7 @@
                         | (uint32)((uint32)0U << 26U)
                         | (uint32)((uint32)0U << 27U)
                         | (uint32)((uint32)0U << 28U)
-                        | (uint32)((uint32)0U << 29U)
+                        | (uint32)((uint32)1U << 29U)
                         | (uint32)((uint32)0U << 30U)
                         | (uint32)((uint32)0U << 31U);