Index: dialin/dg/dialysate_generator.py
===================================================================
diff -u -r14df1dbadf3b33261c5f4ca5e18f97a43638cd91 -r9bdd9da89efbd6125c4929f883b995ca77bc1c18
--- dialin/dg/dialysate_generator.py	(.../dialysate_generator.py)	(revision 14df1dbadf3b33261c5f4ca5e18f97a43638cd91)
+++ dialin/dg/dialysate_generator.py	(.../dialysate_generator.py)	(revision 9bdd9da89efbd6125c4929f883b995ca77bc1c18)
@@ -288,6 +288,8 @@
         minor = struct.unpack('B', bytearray(message['message'][self.START_POS_MINOR:self.END_POS_MINOR]))
         micro = struct.unpack('B', bytearray(message['message'][self.START_POS_MICRO:self.END_POS_MICRO]))
         build = struct.unpack('H', bytearray(message['message'][self.START_POS_BUILD:self.END_POS_BUILD]))
+        compatility = struct.unpack('i', bytearray(
+            message['message'][self.START_POS_COMP:self.END_POS_COMP]))
 
         fpga_id = struct.unpack('B', bytearray(
             message['message'][self.START_POS_FPGA_ID:self.END_POS_FPGA_ID]))
@@ -299,7 +301,7 @@
             message['message'][self.START_POS_FPGA_LAB:self.END_POS_FPGA_LAB]))
 
         if all([len(each) > 0 for each in [major, minor, micro, build]]):
-            self.dg_version = f"v{major[0]}.{minor[0]}.{micro[0]}-{build[0]}"
+            self.dg_version = f"v{major[0]}.{minor[0]}.{micro[0]}-{build[0]}-{compatility[0]}"
             self.logger.debug(f"DG VERSION: {self.dg_version}")
 
         if all([len(each) > 0 for each in [fpga_major, fpga_minor, fpga_id, fpga_lab]]):
Index: dialin/hd/ui_proxy.py
===================================================================
diff -u -rdaf41630cdfa8862e83723349ab2994ca3741485 -r9bdd9da89efbd6125c4929f883b995ca77bc1c18
--- dialin/hd/ui_proxy.py	(.../ui_proxy.py)	(revision daf41630cdfa8862e83723349ab2994ca3741485)
+++ dialin/hd/ui_proxy.py	(.../ui_proxy.py)	(revision 9bdd9da89efbd6125c4929f883b995ca77bc1c18)
@@ -56,6 +56,8 @@
     END_POS_MICRO = START_POS_MICRO + 1
     START_POS_BUILD = END_POS_MICRO
     END_POS_BUILD = START_POS_BUILD + 2
+    START_POS_COMP = END_POS_BUILD
+    END_POS_COMP = START_POS_COMP + 4
 
     # FPGA
     START_POS_FPGA_ID = END_POS_BUILD
@@ -500,6 +502,8 @@
             message['message'][self.START_POS_MICRO:self.END_POS_MICRO]))
         build = struct.unpack('H', bytearray(
             message['message'][self.START_POS_BUILD:self.END_POS_BUILD]))
+        compatility = struct.unpack('i', bytearray(
+            message['message'][self.START_POS_COMP:self.END_POS_COMP]))
 
         fpga_id = struct.unpack('B', bytearray(
             message['message'][self.START_POS_FPGA_ID:self.END_POS_FPGA_ID]))
@@ -511,7 +515,7 @@
             message['message'][self.START_POS_FPGA_LAB:self.END_POS_FPGA_LAB]))
 
         if all([len(each) > 0 for each in [major, minor, micro, build]]):
-            self.hd_version = f"v{major[0]}.{minor[0]}.{micro[0]}-{build[0]}"
+            self.hd_version = f"v{major[0]}.{minor[0]}.{micro[0]}-{build[0]}-{compatility[0]}"
             self.logger.debug(f"HD VERSION: {self.hd_version}")
 
         if all([len(each) > 0 for each in [fpga_major, fpga_minor, fpga_id, fpga_lab]]):