Index: dialin/common/msg_ids.py
===================================================================
diff -u -r1428c8a63bfcfe3b31667a9dbbf9d50d13105e63 -rf26e9473ddcf393ae7b8e1ca852067507c82b3be
--- dialin/common/msg_ids.py	(.../msg_ids.py)	(revision 1428c8a63bfcfe3b31667a9dbbf9d50d13105e63)
+++ dialin/common/msg_ids.py	(.../msg_ids.py)	(revision f26e9473ddcf393ae7b8e1ca852067507c82b3be)
@@ -381,6 +381,7 @@
     MSG_ID_HD_RESET_ALL_TEST_CONFIGURATIONS = 0x8096
     MSG_ID_HD_SET_TEST_CONFIGURATION = 0x8097
     MSG_ID_HD_SIGNAL_RECOVER_FROM_FAULT_MODE = 0x8098
+    MSG_ID_HD_RAM_STATUS_OVERRIDE = 0x8099
 
     MSG_ID_DG_TESTER_LOGIN_REQUEST = 0xA000
     MSG_ID_DG_ALARM_STATE_OVERRIDE = 0xA001
@@ -494,6 +495,7 @@
     MSG_ID_DG_SIGNAL_RECOVER_FROM_FAULT_MODE = 0xA06F
     MSG_ID_DG_DRAIN_MODE_BROADCAST_INTERVAL_OVERRIDE = 0xA070
     MSG_ID_DG_DIALIN_RO_ONLY_MODE_STATUS_REQUEST = 0xA071
+    MSG_ID_DG_RAM_STATUS_OVERRIDE = 0xA072
 
     MSG_ID_HD_DEBUG_EVENT = 0xFFF1
     MSG_ID_DG_DEBUG_EVENT = 0xFFF2
Index: dialin/dg/dialysate_generator.py
===================================================================
diff -u -r924711ba9c3534e7e977b8c28d5b49e98d1a5c7b -rf26e9473ddcf393ae7b8e1ca852067507c82b3be
--- dialin/dg/dialysate_generator.py	(.../dialysate_generator.py)	(revision 924711ba9c3534e7e977b8c28d5b49e98d1a5c7b)
+++ dialin/dg/dialysate_generator.py	(.../dialysate_generator.py)	(revision f26e9473ddcf393ae7b8e1ca852067507c82b3be)
@@ -566,3 +566,45 @@
                                               message_id=MsgIds.MSG_ID_DG_DIALIN_CHECK_IN.value)
         self.can_interface.send(message)
         return True
+
+    def cmd_dg_ram_status_override(self, ram_reg: int = 0, status: int = 0, reset: int = NO_RESET) -> int:
+        """
+        Constructs and sends the RAM status override command
+        Constraints:
+            Must be logged into DG.
+
+        RAM Status Bits:
+        SERR                  0x00000001  Bit 0 - Single-bit error in TCRAM Module Error Status Register
+        ADDR_DEC_FAIL         0x00000004  Bit 2 - Address decode failed in TCRAM Module Error Status Register
+        ADDR_COMP_LOGIC_FAIL  0x00000010  Bit 4 - Address decode logic element failed in TCRAM Module Error Status Register
+        DERR                  0x00000020  Bit 5 - Multiple bit error in TCRAM Module Error Status Register
+        RADDR_PAR_FAIL        0x00000100  Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register
+        WADDR_PAR_FAIL        0x00000200  Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register
+
+        @param ram_reg: integer - the RAM regsiter. 0 or 1
+        @param status: integer - bitmap of the status values listed aboves
+        @param reset:  integer - 1 to reset a previous override, 0 to override
+        @return: 1 if successful, zero otherwise
+        """
+
+        rst = integer_to_bytearray(reset)
+        reg = integer_to_bytearray(ram_reg)
+        sts = integer_to_bytearray(status & 0x0000FFFF)
+        payload = rst + sts + reg
+
+        message = DenaliMessage.build_message(channel_id=DenaliChannels.dialin_to_dg_ch_id,
+                                              message_id=MsgIds.MSG_ID_DG_RAM_STATUS_OVERRIDE.value,
+                                              payload=payload)
+
+        self.logger.debug(f"Overriding RAM Status Register {reg} to {str(sts)}")
+
+        # Send message
+        received_message = self.can_interface.send(message)
+
+        # If there is content...
+        if received_message is not None:
+            # response payload is OK or not OK
+            return received_message['message'][DenaliMessage.PAYLOAD_START_INDEX]
+        else:
+            self.logger.debug("Timeout!!!!")
+            return False
\ No newline at end of file
Index: dialin/hd/hemodialysis_device.py
===================================================================
diff -u -r92ba68da956156e22596a1dec25bebde27beb60a -rf26e9473ddcf393ae7b8e1ca852067507c82b3be
--- dialin/hd/hemodialysis_device.py	(.../hemodialysis_device.py)	(revision 92ba68da956156e22596a1dec25bebde27beb60a)
+++ dialin/hd/hemodialysis_device.py	(.../hemodialysis_device.py)	(revision f26e9473ddcf393ae7b8e1ca852067507c82b3be)
@@ -751,3 +751,45 @@
                                               message_id=MsgIds.MSG_ID_HD_DIALIN_CHECK_IN.value)
         self.can_interface.send(message)
         return True
+
+    def cmd_hd_ram_status_override(self, ram_reg: int = 0, status: int = 0, reset: int = NO_RESET) -> int:
+        """
+        Constructs and sends the RAM status override command
+        Constraints:
+            Must be logged into HD.
+
+        RAM Status Bits:
+        SERR                  0x00000001  Bit 0 - Single-bit error in TCRAM Module Error Status Register
+        ADDR_DEC_FAIL         0x00000004  Bit 2 - Address decode failed in TCRAM Module Error Status Register
+        ADDR_COMP_LOGIC_FAIL  0x00000010  Bit 4 - Address decode logic element failed in TCRAM Module Error Status Register
+        DERR                  0x00000020  Bit 5 - Multiple bit error in TCRAM Module Error Status Register
+        RADDR_PAR_FAIL        0x00000100  Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register
+        WADDR_PAR_FAIL        0x00000200  Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register
+
+        @param ram_reg: integer - the RAM regsiter. 0 or 1
+        @param status: integer - bitmap of the status values listed aboves
+        @param reset:  integer - 1 to reset a previous override, 0 to override
+        @return: 1 if successful, zero otherwise
+        """
+
+        rst = integer_to_bytearray(reset)
+        reg = integer_to_bytearray(ram_reg)
+        sts = integer_to_bytearray(status & 0x0000FFFF)
+        payload = rst + sts + reg
+
+        message = DenaliMessage.build_message(channel_id=DenaliChannels.dialin_to_hd_ch_id,
+                                              message_id=MsgIds.MSG_ID_HD_RAM_STATUS_OVERRIDE.value,
+                                              payload=payload)
+
+        self.logger.debug(f"Overriding RAM Status Register {reg} to {str(sts)}")
+
+        # Send message
+        received_message = self.can_interface.send(message)
+
+        # If there is content...
+        if received_message is not None:
+            # response payload is OK or not OK
+            return received_message['message'][DenaliMessage.PAYLOAD_START_INDEX]
+        else:
+            self.logger.debug("Timeout!!!!")
+            return False
\ No newline at end of file