Index: Integrity.c
===================================================================
diff -u -r2c508d911fedf7fea1a081f449070aeed248b85c -r686674c278c3ba5e8a4f151de11f2c83cfb61c88
--- Integrity.c	(.../Integrity.c)	(revision 2c508d911fedf7fea1a081f449070aeed248b85c)
+++ Integrity.c	(.../Integrity.c)	(revision 686674c278c3ba5e8a4f151de11f2c83cfb61c88)
@@ -54,6 +54,8 @@
 static SELF_TEST_STATUS_T integrityTestStatus;                  ///< Current firmware integrity test status.
 static U32 processorRAMStatusCounter;                           ///< Counter used to check processor RAM error.
 static BOOL singleBitRAMErrorFlag;                              ///< Flag to signal the processor RAM error.
+static OVERRIDE_U32_T tcram1ErrStat;                            ///< TCRAM Module 1 Status Register.
+static OVERRIDE_U32_T tcram2ErrStat;                            ///< TCRAM Module 2 Status Register.
 
 /*********************************************************************//**
  * @brief
@@ -70,6 +72,14 @@
     integrityTestStatus = SELF_TEST_STATUS_IN_PROGRESS;
     processorRAMStatusCounter = 0;
     singleBitRAMErrorFlag = FALSE;
+    tcram1ErrStat.data = 0;
+    tcram1ErrStat.ovData = 0;
+    tcram1ErrStat.ovInitData = 0;
+    tcram1ErrStat.override = OVERRIDE_RESET;
+    tcram2ErrStat.data = 0;
+    tcram2ErrStat.ovData = 0;
+    tcram2ErrStat.ovInitData = 0;
+    tcram2ErrStat.override = OVERRIDE_RESET;
 }
 
 /********************************************************************************//**
@@ -81,41 +91,40 @@
  ***********************************************************************************/
 void execRAMMonitor( void )
 {
-    U32 tcram1ErrStat, tcram2ErrStat = 0;
     U32 err1, err2 = 0;
 
     // Check for processor RAM error
     if ( ++processorRAMStatusCounter > RAM_ERROR_CHECK_TIME_THRESHOLD )
     {
-        tcram1ErrStat = tcram1REG->RAMERRSTATUS;    // B0TCM in TCRAM Module Error Status Register
-        tcram2ErrStat = tcram2REG->RAMERRSTATUS;    // B1TCM in TCRAM Module Error Status Register
+        tcram1ErrStat.data = tcram1REG->RAMERRSTATUS;    // B0TCM in TCRAM Module Error Status Register
+        tcram2ErrStat.data = tcram2REG->RAMERRSTATUS;    // B1TCM in TCRAM Module Error Status Register
 
-        err1 = tcram1ErrStat & SERR;    // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register
-        err2 = tcram2ErrStat & SERR;    // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register
+        err1 = getU32OverrideValue( &tcram1ErrStat ) & SERR;    // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register
+        err2 = getU32OverrideValue( &tcram2ErrStat ) & SERR;    // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register
 
         if( ( err1 != 0 ) || ( err2 != 0 ) )
         {
             if ( FALSE == singleBitRAMErrorFlag )
             {
                 // Log the single-bit RAM error event once only
 #ifdef _DG_
-                SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
+                SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, err1, err2 );
 #else
-                SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
+                SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, err1, err2 );
 #endif
                 singleBitRAMErrorFlag = TRUE;
             }
         }
 
-        err1 = tcram1ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
-        err2 = tcram2ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
+        err1 = getU32OverrideValue( &tcram1ErrStat ) & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
+        err2 = getU32OverrideValue( &tcram2ErrStat ) & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
 
         if ( ( err1 != 0 ) || ( err2 != 0 ) )
         {
 #ifdef _DG_
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, err1, err2 );
 #else
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_CPU_RAM_ERROR, err1, err2 );
 #endif
         }
 
@@ -173,5 +182,78 @@
 
     return integrityTestStatus;
 }
+
+
+/*************************************************************************
+ *                       TEST SUPPORT FUNCTIONS
+ *************************************************************************/
+
+
+/*********************************************************************//**
+ * @brief
+ * The testSetRAMStatusOverride function sets the override of the
+ * ram status module.
+ * @details Inputs: none
+ * @details Outputs: TCRAM status
+ * @param reg ram register to override
+ * @param status the status to be overriden
+ * @return TRUE if reset successful, FALSE if not
+ *************************************************************************/
+BOOL testSetRAMStatusOverride( int reg, int status )
+{
+    BOOL result = FALSE;
+
+    if ( TRUE == isTestingActivated() )
+    {
+        result = TRUE;
+
+        if ( 0 == reg )
+        {
+            tcram1ErrStat.ovData = vol;
+            tcram1ErrStat.override = OVERRIDE_KEY;
+        }
+
+        else
+        {
+            tcram2ErrStat.ovData = vol;
+            tcram2ErrStat.override = OVERRIDE_KEY;
+        }
+    }
+
+    return result;
+}
+
+/*********************************************************************//**
+ * @brief
+ * The testResetRAMStatusOverride function resets the override of the
+ * ram status module.
+ * @details Inputs: none
+ * @details Outputs: TCRAM status
+ * @param reg ram register to override
+ * @return TRUE if reset successful, FALSE if not
+ *************************************************************************/
+BOOL testResetRAMStatusOverride( int reg )
+{
+    BOOL result = FALSE;
+
+    if ( TRUE == isTestingActivated() )
+    {
+        result = TRUE;
+
+        if ( 0 == reg )
+        {
+            tcram1ErrStat.override = OVERRIDE_RESET;
+            tcram1ErrStat.ovData = tcram1ErrStat.ovInitData;
+        }
+
+        else
+        {
+            tcram2ErrStat.override = OVERRIDE_RESET;
+            tcram2ErrStat.ovData = tcram2ErrStat.ovInitData;
+        }
+    }
+
+    return result;
+}
 
 /**@}*/