Index: Integrity.c
===================================================================
diff -u -r50e7f4d9ef30a97775b25ecb351ba8f171c4d4fc -r9f5f85b3bddb2b94f5ec4111cdc33077892cae77
--- Integrity.c	(.../Integrity.c)	(revision 50e7f4d9ef30a97775b25ecb351ba8f171c4d4fc)
+++ Integrity.c	(.../Integrity.c)	(revision 9f5f85b3bddb2b94f5ec4111cdc33077892cae77)
@@ -17,12 +17,13 @@
 
 #include <crc_tbl.h>
 
+#include "reg_tcram.h"
+
 #include "Integrity.h"
 #include "SafetyShutdown.h"
-#include "Utilities.h"
-#include "reg_tcram.h"
-#include "DGDefs.h"
+#include "SystemCommMessages.h"
 #include "TaskGeneral.h"
+#include "Utilities.h"
 
 /**
  *  @addtogroup Integrity
@@ -84,6 +85,7 @@
     {
         tcram1ErrStat = tcram1REG->RAMERRSTATUS;    // B0TCM in TCRAM Module Error Status Register
         tcram2ErrStat = tcram2REG->RAMERRSTATUS;    // B1TCM in TCRAM Module Error Status Register
+
         err1 = tcram1ErrStat & SERR;    // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register
         err2 = tcram2ErrStat & SERR;    // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register
 
@@ -92,7 +94,11 @@
             if ( FALSE == singleBitRAMErrorFlag )
             {
               // Log the single-bit RAM error event once only
-              SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, 0, 0 );
+#ifdef _DG_
+              SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
+#else
+              SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
+#endif
               singleBitRAMErrorFlag = TRUE;
             }
         }
@@ -102,7 +108,11 @@
 
         if ( ( err1 != 0 ) || ( err2 != 0 ) )
         {
+#ifdef _DG_
             SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );
+#else
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );
+#endif
         }
 
         processorRAMStatusCounter = 0;