Index: Integrity.c
===================================================================
diff -u -r55d6c97f2ce3636c21b235c7a0a4ac3715f5226e -rb4a03e5576f906fe58c426b3962dc8a349433d18
--- Integrity.c	(.../Integrity.c)	(revision 55d6c97f2ce3636c21b235c7a0a4ac3715f5226e)
+++ Integrity.c	(.../Integrity.c)	(revision b4a03e5576f906fe58c426b3962dc8a349433d18)
@@ -36,12 +36,12 @@
 
 #define CRC_TABLE_STARTING_ADDR             0x20                ///< The starting address of CRC table for firmware image.
 #define MAX_CRC_CALC_DATA_SIZE              0x8000              ///< The maximum size of data for each CRC calculation.
-#define SERR                    0x00000001          ///< Bit 0 - Single-bit error in TCRAM Module Error Status Register
-#define ADDR_DEC_FAIL           0x00000004          ///< Bit 2 - Address decode failed in TCRAM Module Error Status Register
-#define ADDR_COMP_LOGIC_FAIL    0x00000010          ///< Bit 4 - Address decode logic element failed in TCRAM Module Error Status Register
-#define DERR                    0x00000020          ///< Bit 5 - Multiple bit error in TCRAM Module Error Status Register
-#define RADDR_PAR_FAIL          0x00000100          ///< Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register
-#define WADDR_PAR_FAIL          0x00000200          ///< Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register
+#define SERR                                0x00000001          ///< Bit 0 - Single-bit error in TCRAM Module Error Status Register
+#define ADDR_DEC_FAIL                       0x00000004          ///< Bit 2 - Address decode failed in TCRAM Module Error Status Register
+#define ADDR_COMP_LOGIC_FAIL                0x00000010          ///< Bit 4 - Address decode logic element failed in TCRAM Module Error Status Register
+#define DERR                                0x00000020          ///< Bit 5 - Multiple bit error in TCRAM Module Error Status Register
+#define RADDR_PAR_FAIL                      0x00000100          ///< Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register
+#define WADDR_PAR_FAIL                      0x00000200          ///< Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register
 
 /// Time threshold to check RAM error is 2 seconds
 static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((2 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL);
@@ -52,8 +52,8 @@
 static U32 currentProcessedSize;                                ///< Current data size processed for CRC calculation.
 static U32 crcCalculated;                                       ///< The calculated CRC value.
 static SELF_TEST_STATUS_T integrityTestStatus;                  ///< Current firmware integrity test status.
-static U32 processorRAMStatusCounter = 0;                       ///< Counter used to check processor RAM error.
-static BOOL singleBitRAMErrorFlag = FALSE;                      ///< Flag to signal the processor RAM error.
+static U32 processorRAMStatusCounter;                           ///< Counter used to check processor RAM error.
+static BOOL singleBitRAMErrorFlag;                              ///< Flag to signal the processor RAM error.
 
 /*********************************************************************//**
  * @brief
@@ -68,6 +68,8 @@
     currentProcessedSize = 0;
     crcCalculated = 0;
     integrityTestStatus = SELF_TEST_STATUS_IN_PROGRESS;
+    processorRAMStatusCounter = 0;
+    singleBitRAMErrorFlag = FALSE;
 }
 
 /********************************************************************************//**
@@ -97,11 +99,11 @@
             {
               // Log the single-bit RAM error event once only
 #ifdef _DG_
-              SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
+                SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
 #else
-              SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
+                SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat );
 #endif
-              singleBitRAMErrorFlag = TRUE;
+                singleBitRAMErrorFlag = TRUE;
             }
         }