Index: Integrity.c =================================================================== diff -u -rdeccca7f64383d627e700a8bb929742eb33d947a -r59871c9964559b5137781af9c2eeed6bab18ef73 --- Integrity.c (.../Integrity.c) (revision deccca7f64383d627e700a8bb929742eb33d947a) +++ Integrity.c (.../Integrity.c) (revision 59871c9964559b5137781af9c2eeed6bab18ef73) @@ -1,21 +1,24 @@ /************************************************************************** * -* Copyright (c) 2021-2022 Diality Inc. - All Rights Reserved. +* Copyright (c) 2021-2024 Diality Inc. - All Rights Reserved. * * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. * * @file Integrity.c * -* @author (last) Sean Nash -* @date (last) 29-Jun-2022 +* @author (last) Dara Navaei +* @date (last) 29-Sep-2023 * * @author (original) Quang Nguyen * @date (original) 29-May-2021 * ***************************************************************************/ +#ifndef _VECTORCAST_ +// This header file is disabled in VectorCAST because this is a TI library and VectorCAST uses GNU 7.4 compiler for testing #include +#endif #include "reg_tcram.h" @@ -34,15 +37,55 @@ // ********** private definitions ********** +#ifndef _VECTORCAST_ +// This address is redefined in VectorCAST again #define CRC_TABLE_STARTING_ADDR 0x20 ///< The starting address of CRC table for firmware image. +#endif #define MAX_CRC_CALC_DATA_SIZE 0x8000 ///< The maximum size of data for each CRC calculation. #define SERR 0x00000001 ///< Bit 0 - Single-bit error in TCRAM Module Error Status Register #define ADDR_DEC_FAIL 0x00000004 ///< Bit 2 - Address decode failed in TCRAM Module Error Status Register #define ADDR_COMP_LOGIC_FAIL 0x00000010 ///< Bit 4 - Address decode logic element failed in TCRAM Module Error Status Register #define DERR 0x00000020 ///< Bit 5 - Multiple bit error in TCRAM Module Error Status Register #define RADDR_PAR_FAIL 0x00000100 ///< Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register #define WADDR_PAR_FAIL 0x00000200 ///< Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register - + + +#ifdef _VECTORCAST_ +// Since VectorCAST does not have access to #include , the structures are defined here so VectoCAST can compile and +// instrument the code for Dev testing +/*********************************************************/ +/* CRC Record Data Structure */ +/* NOTE: The list of fields and the size of each field */ +/* varies by target and memory model. */ +/*********************************************************/ +typedef struct crc_record +{ +uint64_t crc_value; +uint32_t crc_alg_ID; /* CRC algorithm ID */ +uint32_t addr; /* Starting address */ +uint32_t size; /* size of data in bytes */ +uint32_t padding; /* explicit padding so layout is the same */ + /* for COFF and ELF */ +} CRC_RECORD; + +/*********************************************************/ +/* CRC Table Data Structure */ +/*********************************************************/ +typedef struct crc_table +{ +uint32_t rec_size; +uint32_t num_recs; +CRC_RECORD recs[1]; +} CRC_TABLE; + +// Defined a CRC table here since the start address of the CRC table in the firmware will cause a segmentation fault in VectorCAST +// The CRC_TABLE_STARTING_ADDR in undefined at the top and is defined here again with pointing to the testTable address that has +// been define here. +// NOTE: User prefix code was not used because defining the structures at the top would cause compilation errors +CRC_TABLE testTable; +#define CRC_TABLE_STARTING_ADDR &testTable +#endif + /// Time threshold to check RAM error is 2 seconds static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((2 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL); @@ -54,6 +97,8 @@ static SELF_TEST_STATUS_T integrityTestStatus; ///< Current firmware integrity test status. static U32 processorRAMStatusCounter; ///< Counter used to check processor RAM error. static BOOL singleBitRAMErrorFlag; ///< Flag to signal the processor RAM error. +static OVERRIDE_U32_T tcram1ErrStat; ///< TCRAM Module 1 Status Register. +static OVERRIDE_U32_T tcram2ErrStat; ///< TCRAM Module 2 Status Register. /*********************************************************************//** * @brief @@ -70,6 +115,14 @@ integrityTestStatus = SELF_TEST_STATUS_IN_PROGRESS; processorRAMStatusCounter = 0; singleBitRAMErrorFlag = FALSE; + tcram1ErrStat.data = 0; + tcram1ErrStat.ovData = 0; + tcram1ErrStat.ovInitData = 0; + tcram1ErrStat.override = OVERRIDE_RESET; + tcram2ErrStat.data = 0; + tcram2ErrStat.ovData = 0; + tcram2ErrStat.ovInitData = 0; + tcram2ErrStat.override = OVERRIDE_RESET; } /********************************************************************************//** @@ -81,41 +134,40 @@ ***********************************************************************************/ void execRAMMonitor( void ) { - U32 tcram1ErrStat, tcram2ErrStat = 0; U32 err1, err2 = 0; // Check for processor RAM error if ( ++processorRAMStatusCounter > RAM_ERROR_CHECK_TIME_THRESHOLD ) { - tcram1ErrStat = tcram1REG->RAMERRSTATUS; // B0TCM in TCRAM Module Error Status Register - tcram2ErrStat = tcram2REG->RAMERRSTATUS; // B1TCM in TCRAM Module Error Status Register + tcram1ErrStat.data = tcram1REG->RAMERRSTATUS; // B0TCM in TCRAM Module Error Status Register + tcram2ErrStat.data = tcram2REG->RAMERRSTATUS; // B1TCM in TCRAM Module Error Status Register - err1 = tcram1ErrStat & SERR; // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register - err2 = tcram2ErrStat & SERR; // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register + err1 = getU32OverrideValue( &tcram1ErrStat ) & SERR; // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register + err2 = getU32OverrideValue( &tcram2ErrStat ) & SERR; // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register if( ( err1 != 0 ) || ( err2 != 0 ) ) { if ( FALSE == singleBitRAMErrorFlag ) { // Log the single-bit RAM error event once only #ifdef _DG_ - SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat ); + SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, err1, err2 ); #else - SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat ); + SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, err1, err2 ); #endif singleBitRAMErrorFlag = TRUE; } } - err1 = tcram1ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL); - err2 = tcram2ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL); + err1 = getU32OverrideValue( &tcram1ErrStat ) & ( SERR | ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL ); + err2 = getU32OverrideValue( &tcram2ErrStat ) & ( SERR | ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL ); if ( ( err1 != 0 ) || ( err2 != 0 ) ) { #ifdef _DG_ - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat ); + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, err1, err2 ); #else - SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat ); + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_CPU_RAM_ERROR, err1, err2 ); #endif } @@ -173,5 +225,78 @@ return integrityTestStatus; } + + +/************************************************************************* + * TEST SUPPORT FUNCTIONS + *************************************************************************/ + + +/*********************************************************************//** + * @brief + * The testSetRAMStatusOverride function sets the override of the + * ram status module. + * @details Inputs: none + * @details Outputs: TCRAM status + * @param reg ram register to override + * @param status the status to be overriden + * @return TRUE if reset successful, FALSE if not + *************************************************************************/ +BOOL testSetRAMStatusOverride( U32 reg, U32 status ) +{ + BOOL result = FALSE; + + if ( TRUE == isTestingActivated() ) + { + result = TRUE; + + if ( 0 == reg ) + { + tcram1ErrStat.ovData = status; + tcram1ErrStat.override = OVERRIDE_KEY; + } + + else + { + tcram2ErrStat.ovData = status; + tcram2ErrStat.override = OVERRIDE_KEY; + } + } + + return result; +} + +/*********************************************************************//** + * @brief + * The testResetRAMStatusOverride function resets the override of the + * ram status module. + * @details Inputs: none + * @details Outputs: TCRAM status + * @param reg ram register to override + * @return TRUE if reset successful, FALSE if not + *************************************************************************/ +BOOL testResetRAMStatusOverride( U32 reg ) +{ + BOOL result = FALSE; + + if ( TRUE == isTestingActivated() ) + { + result = TRUE; + + if ( 0 == reg ) + { + tcram1ErrStat.override = OVERRIDE_RESET; + tcram1ErrStat.ovData = tcram1ErrStat.ovInitData; + } + + else + { + tcram2ErrStat.override = OVERRIDE_RESET; + tcram2ErrStat.ovData = tcram2ErrStat.ovInitData; + } + } + + return result; +} /**@}*/