Index: Integrity.c =================================================================== diff -u -re878d8487b148c6acd14e8acc42a211552ae35e3 -raf3a8fc95a8688b75a6f50e0081e4795024eeff5 --- Integrity.c (.../Integrity.c) (revision e878d8487b148c6acd14e8acc42a211552ae35e3) +++ Integrity.c (.../Integrity.c) (revision af3a8fc95a8688b75a6f50e0081e4795024eeff5) @@ -37,7 +37,9 @@ // ********** private definitions ********** +#ifndef _VECTORCAST_ #define CRC_TABLE_STARTING_ADDR 0x20 ///< The starting address of CRC table for firmware image. +#endif #define MAX_CRC_CALC_DATA_SIZE 0x8000 ///< The maximum size of data for each CRC calculation. #define SERR 0x00000001 ///< Bit 0 - Single-bit error in TCRAM Module Error Status Register #define ADDR_DEC_FAIL 0x00000004 ///< Bit 2 - Address decode failed in TCRAM Module Error Status Register @@ -46,6 +48,7 @@ #define RADDR_PAR_FAIL 0x00000100 ///< Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register #define WADDR_PAR_FAIL 0x00000200 ///< Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register + #ifdef _VECTORCAST_ // Since VectorCAST does not have access to #include , the structures are defined here so VectoCAST can compile and // instrument the code for Dev testing @@ -64,7 +67,6 @@ /* for COFF and ELF */ } CRC_RECORD; - /*********************************************************/ /* CRC Table Data Structure */ /*********************************************************/ @@ -74,8 +76,15 @@ uint32_t num_recs; CRC_RECORD recs[1]; } CRC_TABLE; + +// Defined a CRC table here since the start address of the CRC table in the firmware will cause a segmentation fault in VectorCAST +// The CRC_TABLE_STARTING_ADDR in undefined at the top and is defined here again with pointing to the testTable address that has +// been define here. +// NOTE: User prefix code was not used because defining the structures at the top would cause compilation errors +CRC_TABLE testTable; +#define CRC_TABLE_STARTING_ADDR &testTable #endif - + /// Time threshold to check RAM error is 2 seconds static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((2 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL); @@ -149,8 +158,8 @@ } } - err1 = getU32OverrideValue( &tcram1ErrStat ) & ( SERR | ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL); - err2 = getU32OverrideValue( &tcram2ErrStat ) & ( SERR | ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL); + err1 = getU32OverrideValue( &tcram1ErrStat ) & ( SERR | ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL ); + err2 = getU32OverrideValue( &tcram2ErrStat ) & ( SERR | ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL ); if ( ( err1 != 0 ) || ( err2 != 0 ) ) {