Index: RTC.c =================================================================== diff -u -r5d573b11d640b5b97c10a7d290c7c39cfa684ab6 -re1f9404958c9ddab9b004399fb0870e09e37512b --- RTC.c (.../RTC.c) (revision 5d573b11d640b5b97c10a7d290c7c39cfa684ab6) +++ RTC.c (.../RTC.c) (revision e1f9404958c9ddab9b004399fb0870e09e37512b) @@ -23,173 +23,177 @@ // ********** Definitions ********** -#define RTC_REG_1_12_HOUR_MODE_MASK 0x0004 // 12-hour mode mask -#define RTC_REG_1_PORO 0x0008 // Power On Reset Override -#define RTC_REG_1_CLK_STOPPED_MASK 0x0020 // RTC source clock mask -#define RTC_REG_1_UNUSED_MASK 0x0040 // Unused mask -#define RTC_REG_1_EXT_CLK_MODE_MASK 0x0080 // RTC external clock test mode mask +#define RTC_REG_1_12_HOUR_MODE_MASK 0x0004 ///< 12-hour mode mask (0x0004) +#define RTC_REG_1_PORO 0x0008 ///< Power On Reset Override (0x0008) +#define RTC_REG_1_CLK_STOPPED_MASK 0x0020 ///< RTC source clock mask (0x0020) +#define RTC_REG_1_UNUSED_MASK 0x0040 ///< Unused mask (0x0040) +#define RTC_REG_1_EXT_CLK_MODE_MASK 0x0080 ///< RTC external clock test mode mask (0x0080) -#define RTC_REG_2_MSF_MASK 0x0080 // Minute or second interrupt mask -#define RTC_REG_2_CDTF_MASK 0x0008 // Countdown timer interrupt mask -#define RTC_REG_2_AF_MASK 0x0010 // Alarm interrupt mask -#define RTC_REG_2_TSF2_MASK 0x0020 // Timestamp interrupt mask +#define RTC_REG_2_MSF_MASK 0x0080 ///< Minute or second interrupt mask (0x0080) +#define RTC_REG_2_CDTF_MASK 0x0008 ///< Countdown timer interrupt mask (0x0008) +#define RTC_REG_2_AF_MASK 0x0010 ///< Alarm interrupt mask (0x0010) +#define RTC_REG_2_TSF2_MASK 0x0020 ///< Timestamp interrupt mask (0x0020) -#define RTC_REG_3_BF_MASK 0x0008 // Battery status interrupt flag -#define RTC_REG_3_BLF_MASK 0x0004 // Battery status low flag +#define RTC_REG_3_BF_MASK 0x0008 ///< Battery status interrupt flag (0x0008) +#define RTC_REG_3_BLF_MASK 0x0004 ///< Battery status low flag (0x0004) // Indices used to check values read from RTC -#define RTC_REG_1_INDEX 1U -#define RTC_REG_2_INDEX 2U -#define RTC_REG_3_INDEX 3U -#define RTC_SECONDS_INDEX 4U -#define RTC_MINUTES_INDEX 5U -#define RTC_HOURS_INDEX 6U -#define RTC_DAYS_INDEX 7U -#define RTC_WEEKDAYS_INDEX 8U -#define RTC_MONTHS_INDEX 9U -#define RTC_YEARS_INDEX 10U +#define RTC_REG_1_INDEX 1U ///< RTC control register 1 index +#define RTC_REG_2_INDEX 2U ///< RTC control register 2 index +#define RTC_REG_3_INDEX 3U ///< RTC control register 3 index +#define RTC_SECONDS_INDEX 4U ///< RTC seconds index +#define RTC_MINUTES_INDEX 5U ///< RTC minutes index +#define RTC_HOURS_INDEX 6U ///< RTC hours index +#define RTC_DAYS_INDEX 7U ///< RTC days index +#define RTC_WEEKDAYS_INDEX 8U ///< RTC weekdays index +#define RTC_MONTHS_INDEX 9U ///< RTC months index +#define RTC_YEARS_INDEX 10U ///< RTC years index // Time and date acceptable ranges -#define MAX_ALLOWED_SECONDS 59U -#define MAX_ALLOWED_MINUTES 59U -#define MAX_ALLWOED_HOURS 23U -#define MAX_ALLOWED_DAYS 31U -#define MIN_ALLOWED_DAYS 1U -#define MAX_ALLOWED_MONTHS 12U -#define MIN_ALLOWED_MONTHS 1U -#define MAX_ALLOWED_YEARS 99U +#define MAX_ALLOWED_SECONDS 59U ///< Max allowed seconds (59) +#define MAX_ALLOWED_MINUTES 59U ///< Max allowed minutes (59) +#define MAX_ALLWOED_HOURS 23U ///< Max allowed hours (23) +#define MAX_ALLOWED_DAYS 31U ///< Max allowed days (31) +#define MIN_ALLOWED_DAYS 1U ///< Min allowed days (1) +#define MAX_ALLOWED_MONTHS 12U ///< Max allowed months (12) +#define MIN_ALLOWED_MONTHS 1U ///< Min allowed months (1) +#define MAX_ALLOWED_YEARS 99U ///< Max allowed years (99) -#define BUFFER_INDEX_0 0U -#define BUFFER_INDEX_1 1U -#define BUFFER_INDEX_2 2U -#define BUFFER_INDEX_3 3U -#define BUFFER_INDEX_4 4U +#define BUFFER_INDEX_0 0U ///< Buffer index 0 +#define BUFFER_INDEX_1 1U ///< Buffer index 1 +#define BUFFER_INDEX_2 2U ///< Buffer index 2 +#define BUFFER_INDEX_3 3U ///< Buffer index 3 +#define BUFFER_INDEX_4 4U ///< Buffer index 4 -#define MIBSPI_MAX_BUFFER_LENGTH 127U -#define MIBSPI_CONTINUOUS_MODE 4U -#define MIBSPI_CHIP_SELECT_ACTIVE 1U -#define MIBSPI_CHIP_SELECT_DEACTIVE 0U -#define MIBSPI_NO_WDELAY 0U -#define MIBSPI_LOCK_TG 0U -#define MIBSPI_DATA_FORMAT_ZERO 0U -#define MIBSPI_GROUP_ZERO 0U +#define MIBSPI_MAX_BUFFER_LENGTH 127U ///< MibSPI max buffer length (127) +#define MIBSPI_CONTINUOUS_MODE 4U ///< MibSPI continuous mode (4) +#define MIBSPI_CHIP_SELECT_ACTIVE 1U ///< MibSPI chip select active (1) +#define MIBSPI_CHIP_SELECT_DEACTIVE 0U ///< MibSPI chip select deactive (0) +#define MIBSPI_NO_WDELAY 0U ///< MibSPI no wdelay (0) +#define MIBSPI_LOCK_TG 0U ///< MibSPI lock TG (0) +#define MIBSPI_DATA_FORMAT_ZERO 0U ///< MibSPI data format zero (0) +#define MIBSPI_GROUP_ZERO 0U ///< MibSPI group zero (0) -#define MIBSPI_BUFFER_MODE_BIT_SHIFT_13 13U -#define MIBSPI_CHIP_SELECT_BIT_SHIFT_12 12U -#define MIBSPI_NO_WDELAY_BIT_SHIFT_10 10U -#define MIBSPI_LOCK_TRANS_BIT_SHIFT_11 11U -#define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 8U -#define MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 8U +#define MIBSPI_BUFFER_MODE_BIT_SHIFT_13 13U ///< MibSPI buffer mode bit shift by 13 (13) +#define MIBSPI_CHIP_SELECT_BIT_SHIFT_12 12U ///< MibSPI chip select big shift by 12 (12) +#define MIBSPI_NO_WDELAY_BIT_SHIFT_10 10U ///< MibSPI no wdelay bit shift by 10 (10) +#define MIBSPI_LOCK_TRANS_BIT_SHIFT_11 11U ///< MibSPI lock trans bit shift by 11 (11) +#define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 8U ///< MibSPI data format zero bit shift by 8 (8) +#define MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 8U ///< MibSPI tran but shift by 8 (8) -#define RTC_RAM_PREP_BUFFER_LENGTH 3U -#define RTC_TIMESTAMP_BUFFER_LENGTH 8U -#define RTC_GENERAL_BUFFER_LENGTH 11U +#define RTC_RAM_PREP_BUFFER_LENGTH 3U ///< RTC RAM prep buffer length (3) +#define RTC_TIMESTAMP_BUFFER_LENGTH 8U ///< RTC RAM timestamp buffer length (8) +#define RTC_GENERAL_BUFFER_LENGTH 11U ///< RTC general buffer length (11) -#define RTC_PREP_RAM_INDEX 0U -#define RTC_RAM_HIGH_ADDRESS_INDEX 1U -#define RTC_RAM_LOW_ADDRESS_INDEX 2U -#define RTC_RAM_COMMAND_INDEX 3U +#define RTC_PREP_RAM_INDEX 0U ///< RTC prep RAM index (0) +#define RTC_RAM_HIGH_ADDRESS_INDEX 1U ///< RTC RAM high address index (1) +#define RTC_RAM_LOW_ADDRESS_INDEX 2U ///< RTC RAM low address index (2) +#define RTC_RAM_COMMAND_INDEX 3U ///< RTC RAM command index (3) -#define RTC_READ_FROM_REG0 0x00A0 // RTC read from address 0 -#define RTC_WRITE_TO_REG3 0x0023 // Seconds register -#define RTC_WRITE_TO_REG0 0x0020 -#define RTC_PREP_RAM_READ_WRITE 0x003A // RTC cmd prior to RAM ops -#define RTC_WRITE_TO_RAM 0x003C // RTC RAM write -#define RTC_READ_FROM_RAM 0x00BD // RTC RAM read +#define RTC_READ_FROM_REG0 0x00A0 ///< Read from RTC register0 (0x00A0) +#define RTC_WRITE_TO_REG3 0x0023 ///< Write to RTC from seconds register (0x0023) +#define RTC_WRITE_TO_REG0 0x0020 ///< Write to RTC from register0 (0x0020) +#define RTC_PREP_RAM_READ_WRITE 0x003A ///< RTC RAM command for read or write (0x003A) +#define RTC_WRITE_TO_RAM 0x003C ///< RTC write to RAM command (0x003C) +#define RTC_READ_FROM_RAM 0x00BD ///< RTC read from RAM command (0x00BD) -#define RTC_ACCURACY_TIMEOUT 1000U // ms -#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050U // ms -#define RTC_PUBLISH_INTERVAL 18U // Task general counts +#define RTC_ACCURACY_TIMEOUT 1000U ///< RTC accuracy timeout in ms (1000) +#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050U ///< RTC accuracy timeout tolerance in ms (1050) +#define RTC_PUBLISH_INTERVAL 18U ///< RTC publish interval in counts (18) -#define TIMER_COUNTER_TO_REQUEST_READ 18U -#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3U -#define MAX_ALLOWED_RTC_RAM_BYTES 100U -#define MAX_ALLOWED_RTC_RAM_ADDRESS 512U -#define TEN 10U -#define YEAR_2000 2000U -#define EPOCH_YEAR 1900U -#define YEAR_1900_TO_1970_SECONDS_DIFF 2208988800U +#define TIMER_COUNTER_TO_REQUEST_READ 18U ///< Timer counter for reading time from RTC (18) +#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3U ///< Max allowed failed RTC transfers (3) +#define MAX_ALLOWED_RTC_RAM_BYTES 100U ///< Max allowed RTC RAM bytes to be accepted from a caller (100) +#define MAX_ALLOWED_RTC_RAM_ADDRESS 512U ///< Max allowed RTC RAM legal address (512) +#define TEN 10U ///< Ten +#define YEAR_2000 2000U ///< Year 2000 +#define EPOCH_YEAR 1900U ///< Reference year to calculate epoch (1900) +#define YEAR_1900_TO_1970_SECONDS_DIFF 2208988800U ///< Difference in seconds from 1/1/1900 to 1/1/1970 (2208988800) #ifdef _VECTORCAST_ -#define LOCAL_TO_GTM_TIME_CONVERSION 8U +#define LOCAL_TO_GTM_TIME_CONVERSION 8U ///< Local time to GTM conversion for VectorCAST #endif +/// RTC self test state enums typedef enum RTC_Self_Test_States { - RTC_SELF_TEST_STATE_START = 0, - RTC_SELF_TEST_STATE_CHECK_CTRL_REGS, - RTC_SELF_TEST_STATE_WAIT_FOR_FIRST_SECOND, - RTC_SELF_TEST_STATE_WAIT_FOR_SECOND_SECOND, - RTC_SELF_TEST_STATE_CHECK_ACCURACY, - RTC_SELF_TEST_STATE_COMPLETE, - NUM_OF_RTC_SELF_TEST_STATES + RTC_SELF_TEST_STATE_START = 0, ///< Self test start + RTC_SELF_TEST_STATE_CHECK_CTRL_REGS, ///< Self test check control registers + RTC_SELF_TEST_STATE_WAIT_FOR_FIRST_SECOND, ///< Self test wait for first second + RTC_SELF_TEST_STATE_WAIT_FOR_SECOND_SECOND, ///< Self test wait for second second + RTC_SELF_TEST_STATE_CHECK_ACCURACY, ///< Self test check time accuracy + RTC_SELF_TEST_STATE_COMPLETE, ///< Self test complete + NUM_OF_RTC_SELF_TEST_STATES ///< Total number of self test states } RTC_SELF_TEST_STATE_T; +/// Read date states enums typedef enum RTC_Read_Data { - RTC_SEND_COMMAND = 0, - RTC_WAIT_FOR_TRANSFER_AND_READ, - RTC_SERVICE_COMPLETE, - NUM_OF_RTC_SERVICE_STATES + RTC_SEND_COMMAND = 0, ///< RTC send command + RTC_WAIT_FOR_TRANSFER_AND_READ, ///< RTC wait for transfer and read + RTC_SERVICE_COMPLETE, ///< RTC service complete + NUM_OF_RTC_SERVICE_STATES ///< Total number of RTC read date states } RTC_GET_DATA_STATE_T; +/// RTC exec state enums typedef enum RTC_Exec_State { - RTC_EXEC_STATE_WAIT_FOR_POST = 0, - RTC_EXEC_STATE_IDLE, - RTC_EXEC_STATE_PREP_RAM, - RTC_EXEC_STATE_WRITE_TO_RAM, - RTC_EXEC_STATE_READ_FROM_RAM, - RTC_EXEC_STATE_READ, - RTC_EXEC_STATE_WRITE, - RTC_EXEC_STATE_FAULT, - NUM_OF_RTC_EXEC_STATES + RTC_EXEC_STATE_WAIT_FOR_POST = 0, ///< Exec state wait for post + RTC_EXEC_STATE_IDLE, ///< Exec state idle + RTC_EXEC_STATE_PREP_RAM, ///< Exec state prep RAM + RTC_EXEC_STATE_WRITE_TO_RAM, ///< Exec state write to RAM + RTC_EXEC_STATE_READ_FROM_RAM, ///< Exec state read from RAM + RTC_EXEC_STATE_READ, ///< Exec state read + RTC_EXEC_STATE_WRITE, ///< Exec state write + RTC_EXEC_STATE_FAULT, ///< Exec state fault + NUM_OF_RTC_EXEC_STATES ///< Total number of exec states } RTC_EXEC_STATE_T; #pragma pack(push,4) +/// Timestamp struct typedef struct { - U16 seconds; - U16 minutes; - U16 hours; - U16 days; - U16 weekdays; - U16 months; - U16 years; + U16 seconds; ///< Seconds + U16 minutes; ///< Minutes + U16 hours; ///< Hours + U16 days; ///< Days + U16 weekdays; ///< Weekdays + U16 months; ///< Months + U16 years; ///< Years } RTC_TIMESTAMP_T; #pragma pack(pop) // ********** private data ********** -static RTC_SELF_TEST_STATE_T RTCSelfTestState = RTC_SELF_TEST_STATE_START; -static RTC_GET_DATA_STATE_T RTCServiceState = RTC_SEND_COMMAND; -static RTC_EXEC_STATE_T RTCExecState = RTC_EXEC_STATE_WAIT_FOR_POST; -static SELF_TEST_STATUS_T RTCSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; -static RTC_RAM_STATUS_T RTCRAMStatus = RTC_RAM_STATUS_IDLE; -static RTC_RAM_STATE_T RTCRAMState = RTC_RAM_STATE_READY; -static RTC_TIMESTAMP_T RTCTimestampStruct; -static RTC_TIMESTAMP_T RTCNewTimestampStruct; +static RTC_SELF_TEST_STATE_T RTCSelfTestState = RTC_SELF_TEST_STATE_START; ///< Self test variable +static RTC_GET_DATA_STATE_T RTCServiceState = RTC_SEND_COMMAND; ///< RTC get data variable +static RTC_EXEC_STATE_T RTCExecState = RTC_EXEC_STATE_WAIT_FOR_POST; ///< RTC exec state variable +static SELF_TEST_STATUS_T RTCSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; ///< RTC self test status variable +static RTC_RAM_STATUS_T RTCRAMStatus = RTC_RAM_STATUS_IDLE; ///< RTC RAM status variable +static RTC_RAM_STATE_T RTCRAMState = RTC_RAM_STATE_READY; ///< RTC RAM state +static RTC_TIMESTAMP_T RTCTimestampStruct; ///< Timestamp struct +static RTC_TIMESTAMP_T RTCNewTimestampStruct; ///< New timestamp struct -static U32 RTCSelfTestTimer = 0; -static U32 RTCPreviousSecond = 0; // Previous second is used to compare seconds in POST -static U32 RAMBufferLength = 0; -static U32 lastEpochTime = 0; // Last value that has been converted to epoch -static U32 previousTransferLength = 0; +static U32 RTCSelfTestTimer = 0; ///< Self test timer +static U32 RTCPreviousSecond = 0; ///< Previous second +static U32 RAMBufferLength = 0; ///< RAM buffer length +static U32 lastEpochTime = 0; ///< last epoch time +static U32 previousTransferLength = 0; ///< Previous transfer length -static U32 timeCounter = 1; -static U32 numberOfFailedRTCTransfers = 1; +static U32 timeCounter = 1; ///< Initial time counter (1) +static U32 numberOfFailedRTCTransfers = 1; ///< Initial number of failed RTC transactions (1) -static BOOL hasWriteToRTCRequested = FALSE; -static BOOL hasWriteToRAMRequested = FALSE; -static BOOL hasReadFromRAMRequested = FALSE; -static BOOL isRTCServiceOnEntry = FALSE; -static BOOL isTimestampBufferReady = FALSE; +static BOOL hasWriteToRTCRequested = FALSE; ///< Flag to request RTC write +static BOOL hasWriteToRAMRequested = FALSE; ///< Flag to write to RTC RAM +static BOOL hasReadFromRAMRequested = FALSE; ///< Flag to read from RTC RAM +static BOOL isRTCServiceOnEntry = FALSE; ///< Flag to check if service is on entry +static BOOL isTimestampBufferReady = FALSE; ///< Flag to check if the timestamp buffer is ready -static U16 rxBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; -static U16 txBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; +static U16 rxBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; ///< Buffer to receive data from RTC +static U16 txBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; ///< Buffer to transmit data to RTC -static U16 prepRAMBuffer[ RTC_RAM_PREP_BUFFER_LENGTH ]; -static U16 RAMBuffer[ MIBSPI_MAX_BUFFER_LENGTH ]; +static U16 prepRAMBuffer[ RTC_RAM_PREP_BUFFER_LENGTH ]; ///< Buffer to send prep commands to RTC RAM +static U16 RAMBuffer[ MIBSPI_MAX_BUFFER_LENGTH ]; ///< Buffer to read RTC RAM data // ********** Private function prototypes ********* @@ -325,14 +329,14 @@ case RTC_SELF_TEST_STATE_COMPLETE: - // Done with the state - // TODO: If POST failed, set the proper alarm + // Done with POST regardless of the results break; default: - // TODO: Add the alarms + SET_ALARM_WITH_2_U32_DATA ( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_RTC_SELF_TEST_INVALID_STATE, RTCSelfTestState ); RTCSelfTestResult = SELF_TEST_STATUS_FAILED; + RTCSelfTestState = RTC_SELF_TEST_STATE_COMPLETE; break; } @@ -389,10 +393,13 @@ case RTC_EXEC_STATE_FAULT: - // Something failed set the alarms + // Something failed, we shouldn't be here break; default: + + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_RTC_EXEC_INVALID_STATE, RTCExecState ); + RTCExecState = RTC_EXEC_STATE_FAULT; break; } }