Index: Common.h =================================================================== diff -u -r7af12502ddbf9528ce1a8088c42690a0d4385952 -r2ab9e69d455e8014b471eed94a83383bd33b9d58 --- Common.h (.../Common.h) (revision 7af12502ddbf9528ce1a8088c42690a0d4385952) +++ Common.h (.../Common.h) (revision 2ab9e69d455e8014b471eed94a83383bd33b9d58) @@ -19,25 +19,6 @@ #include "hal_stdtypes.h" -// ********** build switches ********** - -#ifndef _VECTORCAST_ -// #define RM46_EVAL_BOARD_TARGET 1 -// #define BREADBOARD2_TARGET 1 -// #define SIMULATE_UI 1 -// #define DEBUG_ENABLED 1 -// #define DISABLE_CRC_ERROR 1 -// #define DISABLE_MOTOR_CURRENT_ERRORS 1 -// #define SHOW_RAW_FLOW_VALUES 1 -// #define CAN_TEST 1 - - #ifdef DEBUG_ENABLED - #include - #include - #endif -#endif -//#define UF_TEST_ENABLED 1 - /** * @defgroup CommonHeader CommonHeader * @brief Provides commonly used definitions and macros. @@ -190,17 +171,12 @@ #define _enable_IRQ() #define _disable_IRQ() #define _enable_FIQ() - #ifndef _MINGW_ - #pragma WEAK(can1LowLevelInterrupt) - void can1LowLevelInterrupt(void) {} - #pragma WEAK(can1HighLevelInterrupt) - void can1HighLevelInterrupt(void) {} - #endif + #define _disable_FIQ() #define fabs(v) ((v) < 0.0 ? ((v) * -1.0) : (v)) #endif -// include alarm mgmt header +// include alarm mgmt header so any module can trigger an alarm #include "AlarmMgmt.h" // include test support definitions and macros Index: RTC.c =================================================================== diff -u -r63f1a64ffe1e8e98f6bde950a3f6542a053d32a3 -r2ab9e69d455e8014b471eed94a83383bd33b9d58 --- RTC.c (.../RTC.c) (revision 63f1a64ffe1e8e98f6bde950a3f6542a053d32a3) +++ RTC.c (.../RTC.c) (revision 2ab9e69d455e8014b471eed94a83383bd33b9d58) @@ -15,7 +15,6 @@ **************************************************************************/ #include // For calculating epoch -#include "Common.h" #include "Timers.h" #include "RTC.h" #include "mibspi.h" @@ -894,14 +893,14 @@ | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIFT_10 ) /* enable WDELAY */ | (uint16)( (uint16)MIBSPI_LOCK_TG << MIBSPI_LOCK_TRANS_BIT_SHIFT_11 ) /* lock transmission */ | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 ) /* data format */ - | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU ); /* chip select */ i++; } mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE << MIBSPI_BUFFER_MODE_BIT_SHIFT_13 ) /* buffer mode */ | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE << MIBSPI_CHIP_SELECT_BIT_SHIFT_12 ) /* chip select hold */ | (uint16)( (uint16)MIBSPI_NO_WDELAY << MIBSPI_NO_WDELAY_BIT_SHIFT_10 ) /* enable WDELAY */ | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 ) /* data format */ - | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU ); /* chip select */ + | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU ); /* chip select */ transferStatus = TRUE; } @@ -1167,12 +1166,12 @@ } else { - result = RTC_EXEC_STATE_FAULT; + result = RTC_EXEC_STATE_IDLE;//RTC_EXEC_STATE_FAULT; } } else if ( RTCServiceState == RTC_SERVICE_COMPLETE ) { - result = RTC_EXEC_STATE_FAULT; + result = RTC_EXEC_STATE_IDLE;//RTC_EXEC_STATE_FAULT; } return result;