Index: Integrity.c
===================================================================
diff -u -r310b61154f321481bed8638cad8117b336d76a29 -r50e7f4d9ef30a97775b25ecb351ba8f171c4d4fc
--- Integrity.c	(.../Integrity.c)	(revision 310b61154f321481bed8638cad8117b336d76a29)
+++ Integrity.c	(.../Integrity.c)	(revision 50e7f4d9ef30a97775b25ecb351ba8f171c4d4fc)
@@ -20,9 +20,9 @@
 #include "Integrity.h"
 #include "SafetyShutdown.h"
 #include "Utilities.h"
-#include "reg_tcram.h"      // DN-02SEPT2022
-#include "DGDefs.h"         // DN-02SEPT2022
-#include "TaskGeneral.h"    // DN-02SEPT2022
+#include "reg_tcram.h"
+#include "DGDefs.h"
+#include "TaskGeneral.h"
 
 /**
  *  @addtogroup Integrity
@@ -46,10 +46,10 @@
 static U32 currentProcessedSize;                                ///< Current data size processed for CRC calculation.
 static U32 crcCalculated;                                       ///< The calculated CRC value.
 static SELF_TEST_STATUS_T integrityTestStatus;                  ///< Current firmware integrity test status.
-static U32 processorRAMStatusCounter = 0;                       ///< Counter used to check processor RAM error.  - DN-01SEPT2022
-static BOOL singleBitRAMErrorFlag = FALSE;                      ///< Flag to signal the processor RAM error. - DN-01SEPT2022
+static U32 processorRAMStatusCounter = 0;                       ///< Counter used to check processor RAM error.
+static BOOL singleBitRAMErrorFlag = FALSE;                      ///< Flag to signal the processor RAM error.
 /// Time threshold to check RAM error is 2 seconds
-static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((2 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL);    // DN-02SEPT2022
+static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((2 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL);
 
 
 /*********************************************************************//**
@@ -74,7 +74,7 @@
  * @details Outputs: system event log or alarm  activated if RAM error is detected.
  * @return none
  ***********************************************************************************/
-void execRAMMonitor( void )     // DN-02SEPT2022
+void execRAMMonitor( void )
 {
     U32 tcram1ErrStat, tcram2ErrStat = 0;
     U32 err1, err2 = 0;
@@ -87,8 +87,6 @@
         err1 = tcram1ErrStat & SERR;    // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register
         err2 = tcram2ErrStat & SERR;    // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register
 
-        err1 = SERR; err2 = SERR;   // Force values for testing only - DN-06SEPT2022
-
         if( ( err1 != 0 ) || ( err2 != 0 ) )
         {
             if ( FALSE == singleBitRAMErrorFlag )
@@ -99,14 +97,12 @@
             }
         }
 
-        tcram1ErrStat = ADDR_DEC_FAIL; tcram2ErrStat = DERR;   // Force values for testing only - DN-06SEPT2022
-
         err1 = tcram1ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
         err2 = tcram2ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
 
         if ( ( err1 != 0 ) || ( err2 != 0 ) )
         {
-            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );     // Commented out for debug only - DN-07SEPT2022
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );
         }
 
         processorRAMStatusCounter = 0;