Index: RTC.c
===================================================================
diff -u -r9f52ecfab3f14d3b1e2085c2f0424a18a93b243c -r8ba5809ebcb21ab17250a9aa983b8b01c80c1dbe
--- RTC.c	(.../RTC.c)	(revision 9f52ecfab3f14d3b1e2085c2f0424a18a93b243c)
+++ RTC.c	(.../RTC.c)	(revision 8ba5809ebcb21ab17250a9aa983b8b01c80c1dbe)
@@ -895,14 +895,14 @@
                                       | (uint16)( (uint16)MIBSPI_NO_WDELAY          << MIBSPI_NO_WDELAY_BIT_SHIFT_10 )          /* enable WDELAY */
                                       | (uint16)( (uint16)MIBSPI_LOCK_TG            << MIBSPI_LOCK_TRANS_BIT_SHIFT_11 )        /* lock transmission */
                                       | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO   << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 )  /* data format */
-                                      | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU );                    /* chip select */
+                                      | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU );                    /* chip select */
             i++;
         }
         mibspiRAM3->tx[i].control = (uint16)( (uint16)MIBSPI_CONTINUOUS_MODE        << MIBSPI_BUFFER_MODE_BIT_SHIFT_13 )       /* buffer mode */
                                   | (uint16)( (uint16)MIBSPI_CHIP_SELECT_DEACTIVE   << MIBSPI_CHIP_SELECT_BIT_SHIFT_12 )       /* chip select hold */
                                   | (uint16)( (uint16)MIBSPI_NO_WDELAY              << MIBSPI_NO_WDELAY_BIT_SHIFT_10 )          /* enable WDELAY */
                                   | (uint16)( (uint16)MIBSPI_DATA_FORMAT_ZERO       << MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 )  /* data format */
-                                  | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_0)) & (uint16)0x00FFU );                        /* chip select */
+                                  | ((uint16)( ~((uint16)0xFFU ^ (uint16)CS_1)) & (uint16)0x00FFU );                        /* chip select */
 
         transferStatus = TRUE;
     }