Index: FlashDrvr/CGT.CCS.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/CGT.CCS.h (.../CGT.CCS.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/CGT.CCS.h (.../CGT.CCS.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- Index: FlashDrvr/Compatibility.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/Compatibility.h (.../Compatibility.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/Compatibility.h (.../Compatibility.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- Index: FlashDrvr/Constants.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/Constants.h (.../Constants.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/Constants.h (.../Constants.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- Index: FlashDrvr/F021.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/F021.h (.../F021.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/F021.h (.../F021.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- Index: FlashDrvr/FapiFunctions.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/FapiFunctions.h (.../FapiFunctions.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/FapiFunctions.h (.../FapiFunctions.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- Index: FlashDrvr/Helpers.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/Helpers.h (.../Helpers.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/Helpers.h (.../Helpers.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- @@ -32,10 +47,10 @@ /* Macro allowing a write to a locked FSM register */ #define FAPI_WRITE_LOCKED_FSM_REGISTER(mRegister,mValue) \ - do { \ - FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x5U; \ - (mRegister) = (mValue); \ - FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x2U; \ + do { \ + FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x5U; \ + (mRegister) = (mValue); \ + FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x2U; \ } while(0) @@ -45,8 +60,8 @@ #define EI16(idx) ((idx) ^ 1) #define EI8(idx) ((idx) ^ 3) #else - #define EI16(idx) (idx) - #define EI8(idx) (idx) + #define EI16(idx) (idx) + #define EI8(idx) (idx) #endif /* These are helper functions to handle generic Big Endian/Little Endian code bases */ Index: FlashDrvr/Registers.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/Registers.h (.../Registers.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/Registers.h (.../Registers.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- Index: FlashDrvr/Registers_FMC_LE.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/Registers_FMC_LE.h (.../Registers_FMC_LE.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/Registers_FMC_LE.h (.../Registers_FMC_LE.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- @@ -46,11 +61,11 @@ uint32_t u32Register; /* Read Control Register, bits 31:0 */ struct { - uint32_t PFUENA :1;/*!< Read Mode, bit 0 */ - uint32_t PFUENB :1;/*!< Address Setup Wait State Enable, bit 4 */ - uint32_t _FRDCNTL_Reserved_07_02 :6;/*!< Reserved, bits 7:5 */ - uint32_t RWAIT :4;/*!< Random Read Wait State, bits 11:8 */ - uint32_t _FRDCNTL_Reserved_31_12 :20;/*!< Reserved, bits 31:12 */ + uint32_t PFUENA :1;/*!< Read Mode, bit 0 */ + uint32_t PFUENB :1;/*!< Address Setup Wait State Enable, bit 4 */ + uint32_t _FRDCNTL_Reserved_07_02 :6;/*!< Reserved, bits 7:5 */ + uint32_t RWAIT :4;/*!< Random Read Wait State, bits 11:8 */ + uint32_t _FRDCNTL_Reserved_31_12 :20;/*!< Reserved, bits 31:12 */ } FRDCNTRL_BITS; } FrdCntl; @@ -67,7 +82,7 @@ uint32_t _FEDACCTRL1_Reserved_03_00 :4;/* !< Reserved bit 03:00 */ uint32_t EZCV :1;/*!< Zero Condition Valid, bit 4 */ uint32_t EOCV :1;/*!< One Condition Valid, bit 5 */ - uint32_t _FEDACCTRL1_Reserved_31_06 :26;/*!< Reserved, bits 31:06 */ + uint32_t _FEDACCTRL1_Reserved_31_06 :26;/*!< Reserved, bits 31:06 */ } FEDACCTRL1_BITS; } FedAcCtrl1; @@ -77,7 +92,7 @@ uint32_t _Reserved_10; /* Reserved Address Locations 0x10 */ - /*! + /*! Defines whole and bit level accesses to the Port A Error and Status Register - 0x14 */ union FEDAC_PASTATUS @@ -86,16 +101,16 @@ struct { uint32_t _FEDACPASTATUS_Reserved_09_00 :10; /* !< Reserved bits 09:00 */ - uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ - uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ - uint32_t _FEDACPASTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ - uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ - uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ - uint32_t _FEDACPASTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t _FEDACPASTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ + uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ + uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ + uint32_t _FEDACPASTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ } FEDAC_PASTATUS_BITS; } FedacPAStatus; - /*! + /*! Defines whole and bit level accesses to the Port B Error and Status Register - 0x18 */ union FEDAC_PBSTATUS @@ -104,35 +119,35 @@ struct { uint32_t _FEDACPBSTATUS_Reserved_09_00 :10; /*!< Reserved bits 09:00 */ - uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ - uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ - uint32_t _FEDACPBSTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ - uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ - uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ - uint32_t _FEDACPBSTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t _FEDACPBSTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ + uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ + uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ + uint32_t _FEDACPBSTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ } FEDAC_PBSTATUS_BITS; - } FedacPBStatus; + } FedacPBStatus; - /*! + /*! Defines whole and bit level accesses to the Global Error and Status Register - 0x1C */ union FEDAC_GBLSTATUS { uint32_t u32Register; /* Global Error and Status Register ,bits 31:0 */ struct { - uint32_t _FEDACGLBSTATUS_Reserved_12_00 :13; /*!< Reserved bits 12:00 */ - uint32_t IMPLICIT_UNC_ERR :1;/*!< UnCorrectable error during implicit two reads from OTP, bit 13 */ - uint32_t IMPLICIT_COR_ERR :1;/*!< Correctable error during implicit two reads from OTP, bit 14 */ - uint32_t RCR_ERR :1;/*!< L2FMC_Config_out port correction, bit 15 */ - uint32_t _FEDACGLBSTATUS_Reserved_23_16 :8; /*!< Reserved bits 23:16 */ - uint32_t FSM_DONE :1;/*!< FSM done event, bit 24 */ - uint32_t RVF_EVT :1;/*!< FSM Command Read_Verify failed error event, bit 25 */ - uint32_t _FEDACGLBSTATUS_Reserved_31_26 :6 ;/*!< Reserved bits 31:26 */ + uint32_t _FEDACGLBSTATUS_Reserved_12_00 :13; /*!< Reserved bits 12:00 */ + uint32_t IMPLICIT_UNC_ERR :1;/*!< UnCorrectable error during implicit two reads from OTP, bit 13 */ + uint32_t IMPLICIT_COR_ERR :1;/*!< Correctable error during implicit two reads from OTP, bit 14 */ + uint32_t RCR_ERR :1;/*!< L2FMC_Config_out port correction, bit 15 */ + uint32_t _FEDACGLBSTATUS_Reserved_23_16 :8; /*!< Reserved bits 23:16 */ + uint32_t FSM_DONE :1;/*!< FSM done event, bit 24 */ + uint32_t RVF_EVT :1;/*!< FSM Command Read_Verify failed error event, bit 25 */ + uint32_t _FEDACGLBSTATUS_Reserved_31_26 :6 ;/*!< Reserved bits 31:26 */ } FEDAC_GLBSTATUS_BITS; - } FedacGblStatus; + } FedacGblStatus; - uint32_t _Reserved_20; /* Reserved Address Locations 0x20 */ + uint32_t _Reserved_20; /* Reserved Address Locations 0x20 */ /*! Defines whole and bit level accesses to the Error Detection Sector Disable Register - 0x24 @@ -143,13 +158,13 @@ struct { uint32_t SectorID0 :6;/*!< Sector ID0 , bits 05:00 */ - uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ - uint32_t SectorID0_inverse :6;/*!< Sector ID0 Inverse, bits 13:08 */ - uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ - uint32_t SectorID1 :6;/*!< Sector ID1 , bits 21:16 */ - uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ - uint32_t SectorID1_inverse :6;/*!< Sector ID1 Inverse, bits 29:24 */ - uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ + uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ + uint32_t SectorID0_inverse :6;/*!< Sector ID0 Inverse, bits 13:08 */ + uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ + uint32_t SectorID1 :6;/*!< Sector ID1 , bits 21:16 */ + uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ + uint32_t SectorID1_inverse :6;/*!< Sector ID1 Inverse, bits 29:24 */ + uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ } FEDACSDIS_BITS; } FedAcsDis; @@ -162,7 +177,7 @@ struct { uint32_t RET_ZERO :5;/*!< This field always returns 0000, bits 4:0 */ - uint32_t PRIM_ADD_TAG :27;/*!< Primary Address Tag Register, bits 31:5 */ + uint32_t PRIM_ADD_TAG :27;/*!< Primary Address Tag Register, bits 31:5 */ } FPRIM_ADD_TAG_BITS; } FprimAddTag; @@ -175,11 +190,11 @@ struct { uint32_t RET_ZERO :5;/*!< This field always returns 0000, bits 4:0 */ - uint32_t DUP_ADD_TAG :27;/*!< Duplicate Address Tag Register, bits 31:5 */ + uint32_t DUP_ADD_TAG :27;/*!< Duplicate Address Tag Register, bits 31:5 */ } FDUP_ADD_TAG_BITS; } FdupAddTag; - /*! + /*! Defines whole and bit level accesses to the Bank Sector Enable Register - 0x30 */ union FBPROT @@ -188,11 +203,11 @@ struct { uint32_t PROTL1DIS :1; /*!< Level 1 Protection Disabled, bit 0 */ - uint32_t _FBPROT_Reserved_31_01 :31;/*!< Reserved, bits 31:1 */ + uint32_t _FBPROT_Reserved_31_01 :31;/*!< Reserved, bits 31:1 */ } FBPROT_BITS; } Fbprot; - /*! + /*! Defines whole and bit level accesses to the Bank Protection Register - 0x34 */ union FBSE @@ -201,7 +216,7 @@ struct { uint32_t BSE :16;/*!< Bank Sector Enable, bits 15:0 */ - uint32_t _FBSE_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + uint32_t _FBSE_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ } FBSE_BITS; } Fbse; @@ -214,7 +229,7 @@ struct { uint32_t BUSY :8; /*!< Bank Busy, bits 7:0 */ - uint32_t _FBBUSY_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + uint32_t _FBBUSY_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ } FBPROT_BITS; } Fbbusy; @@ -227,9 +242,9 @@ struct { uint32_t VREADS :8;/*!< VREAD Setup, bits 7:0 */ - uint32_t _FBAC_Reserved_15_08 :8;/*!< Reserved, bits 15:8 */ - uint32_t OTPPROTDIS :8;/*!< OTP Sector Protection Disable, bits 23:16 */ - uint32_t _FBAC_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + uint32_t _FBAC_Reserved_15_08 :8;/*!< Reserved, bits 15:8 */ + uint32_t OTPPROTDIS :8;/*!< OTP Sector Protection Disable, bits 23:16 */ + uint32_t _FBAC_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ } FBAC_BITS; } Fbac; @@ -242,14 +257,14 @@ struct { uint32_t BANKPWR0 :2;/*!< Bank 0 Fallback Power Mode, bits 15:14 */ - uint32_t BANKPWR1 :2;/*!< Bank 1 Fallback Power Mode, bits 15:14 */ - uint32_t BANKPWR2 :2;/*!< Bank 2 Fallback Power Mode, bits 15:14 */ - uint32_t BANKPWR3 :2;/*!< Bank 3 Fallback Power Mode, bits 15:14 */ - uint32_t BANKPWR4 :2;/*!< Bank 4 Fallback Power Mode, bits 15:14 */ - uint32_t BANKPWR5 :2;/*!< Bank 5 Fallback Power Mode, bits 15:14 */ - uint32_t BANKPWR6 :2;/*!< Bank 6 Fallback Power Mode, bits 15:14 */ - uint32_t BANKPWR7 :2;/*!< Bank 7 Fallback Power Mode, bits 15:14 */ - uint32_t _FBAC_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + uint32_t BANKPWR1 :2;/*!< Bank 1 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR2 :2;/*!< Bank 2 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR3 :2;/*!< Bank 3 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR4 :2;/*!< Bank 4 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR5 :2;/*!< Bank 5 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR6 :2;/*!< Bank 6 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR7 :2;/*!< Bank 7 Fallback Power Mode, bits 15:14 */ + uint32_t _FBAC_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ } FBFALLBACK_BITS; } Fbfallback; @@ -262,10 +277,10 @@ struct { uint32_t BANKRDY :8;/*!< Bank Ready, bits 7:0 */ - uint32_t _FBPRDY_Reserved_14_08 :7;/*!< Reserved, bits 14:8 */ - uint32_t PUMPRDY :1;/*!< Pump Ready, bit 15 */ - uint32_t BANKBUSY :8;/*!< Bank Busy with FSM, SW_INTF, CPU or PMT, bits 23:16 */ - uint32_t _FBPRDY_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + uint32_t _FBPRDY_Reserved_14_08 :7;/*!< Reserved, bits 14:8 */ + uint32_t PUMPRDY :1;/*!< Pump Ready, bit 15 */ + uint32_t BANKBUSY :8;/*!< Bank Busy with FSM, SW_INTF, CPU or PMT, bits 23:16 */ + uint32_t _FBPRDY_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ } FBPRDY_BITS; } Fbprdy; @@ -277,17 +292,17 @@ uint32_t u32Register; /* Flash Pump Access Control Register 1, bits 31:0 */ struct { - uint32_t PUMPPWR :1; /*!< Flash Charge Pump Fallback Power Mode, bit 0 */ - uint32_t _FPAC1_Reserved_15_01 :15;/*!< Reserved, bits 15:1 */ - uint32_t PSBEEP :12;/*!< Pump Sleep, bits 27:16 */ - uint32_t _FPAC1_Reserved_31_28 :4; /*!< Reserved, bits 31:28 */ + uint32_t PUMPPWR :1; /*!< Flash Charge Pump Fallback Power Mode, bit 0 */ + uint32_t _FPAC1_Reserved_15_01 :15;/*!< Reserved, bits 15:1 */ + uint32_t PSBEEP :12;/*!< Pump Sleep, bits 27:16 */ + uint32_t _FPAC1_Reserved_31_28 :4; /*!< Reserved, bits 31:28 */ } FPAC1_BITS; } Fpac1; - uint32_t _Reserved_4C; /* Reserved Address Locations 0x4C */ + uint32_t _Reserved_4C; /* Reserved Address Locations 0x4C */ - /*! + /*! Defines whole and bit level accesses to the Module Access Control Register - 0x50 */ union FMAC @@ -296,7 +311,7 @@ struct { uint32_t BANK :3; /*!< Bank Enable, bits 2:0 */ - uint32_t _FMAC_Reserved_31_03 :29; /*!< Reserved, bits 31:3 */ + uint32_t _FMAC_Reserved_31_03 :29; /*!< Reserved, bits 31:3 */ } FMAC_BITS; } Fmac; @@ -308,26 +323,26 @@ uint32_t u32Register; /* Module Status Register, bits 31:0 */ struct { - uint32_t SLOCK :1; /*!< Sector Lock Status, bit 0 */ - uint32_t PSUSP :1; /*!< Program Suspend, bit 1 */ - uint32_t ESUSP :1; /*!< Erase Suspend, bit 2 */ - uint32_t VOLSTAT :1; /*!< Core Voltage Status, bit 3 */ - uint32_t CSTAT :1; /*!< Command Status, bit 4 */ - uint32_t INVDAT :1; /*!< Invalid Data, bit 5 */ - uint32_t PGM :1; /*!< Program Active, bit 6 */ - uint32_t ERS :1; /*!< Erase Active, bit 7 */ - uint32_t BUSY :1; /*!< Busy, bit 8 */ - uint32_t CV :1; /*!< Compact Verify, bit 9 */ - uint32_t EV :1; /*!< Erase verify, bit 10 */ - uint32_t PCV :1; /*!< Precondidition verify, bit 11 */ - uint32_t PGV :1; /*!< Program verify, bit 12 */ - uint32_t DBT :1; /*!< Disturbance Test Fail, bit 13 */ - uint32_t ILA :1; /*!< Illegal Address, bit 14 */ - uint32_t RVF :1; /*!< Read Verify Failure, bit 15 */ - uint32_t RDVER :1; /*!< Read Verify command currently underway, bit 16 */ - uint32_t RVSUSP :1; /*!< Read Verify Suspend, bit 17 */ - uint32_t _FMSTAT_Reserved_31_18 :14;/*!< Reserved, bits 31:18 */ - } FMSTAT_BITS; + uint32_t SLOCK :1; /*!< Sector Lock Status, bit 0 */ + uint32_t PSUSP :1; /*!< Program Suspend, bit 1 */ + uint32_t ESUSP :1; /*!< Erase Suspend, bit 2 */ + uint32_t VOLSTAT :1; /*!< Core Voltage Status, bit 3 */ + uint32_t CSTAT :1; /*!< Command Status, bit 4 */ + uint32_t INVDAT :1; /*!< Invalid Data, bit 5 */ + uint32_t PGM :1; /*!< Program Active, bit 6 */ + uint32_t ERS :1; /*!< Erase Active, bit 7 */ + uint32_t BUSY :1; /*!< Busy, bit 8 */ + uint32_t CV :1; /*!< Compact Verify, bit 9 */ + uint32_t EV :1; /*!< Erase verify, bit 10 */ + uint32_t PCV :1; /*!< Precondidition verify, bit 11 */ + uint32_t PGV :1; /*!< Program verify, bit 12 */ + uint32_t DBT :1; /*!< Disturbance Test Fail, bit 13 */ + uint32_t ILA :1; /*!< Illegal Address, bit 14 */ + uint32_t RVF :1; /*!< Read Verify Failure, bit 15 */ + uint32_t RDVER :1; /*!< Read Verify command currently underway, bit 16 */ + uint32_t RVSUSP :1; /*!< Read Verify Suspend, bit 17 */ + uint32_t _FMSTAT_Reserved_31_18 :14;/*!< Reserved, bits 31:18 */ + } FMSTAT_BITS; } FmStat; /*! @@ -355,13 +370,13 @@ struct { uint32_t EMU_ECC :8; /*!< EEPROM Emulation ECC, bits 7:0 */ - uint32_t _FEMU_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + uint32_t _FEMU_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ } FEMU_ECC_BITS; } FemuEcc; - uint32_t _Reserved_64; /* Reserved Address Locations 0x64 */ - - /*! + uint32_t _Reserved_64; /* Reserved Address Locations 0x64 */ + + /*! Defines whole and bit level accesses to the EEPROM Emulation Address Register - 0x68 */ union FEMU_ADDR @@ -370,7 +385,7 @@ struct { uint32_t _FEMU_ADDR_Reserved_02_00 :3;/*!< Reserved, bits 02:00 */ - uint32_t EMU_ADDR :29;/*!< EEPROM Emulation Address, bits 31:03 */ + uint32_t EMU_ADDR :29;/*!< EEPROM Emulation Address, bits 31:03 */ } FEMU_ADDR_BITS; } FemuAddr; @@ -383,13 +398,13 @@ struct { uint32_t DIAGMODE :3;/*!< Diagnostic Mode, bits 2:0 */ - uint32_t _FDIAGCTRL_Reserved_07_03 :5;/*!< Reserved, bits 7:3 */ - uint32_t DIAG_BUF_SEL :3;/*!< Diagnostic Buffer Select, bits 10:8 */ - uint32_t _FDIAGCTRL_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ - uint32_t DIAG_EN_KEY :4;/*!< Diagnostic Enable Key, bits 19:16 */ - uint32_t _FDIAGCTRL_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ - uint32_t DIAG_TRIG :1;/*!< Diagnostic Trigger, bit 24 */ - uint32_t _FDIAGCTRL_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + uint32_t _FDIAGCTRL_Reserved_07_03 :5;/*!< Reserved, bits 7:3 */ + uint32_t DIAG_BUF_SEL :3;/*!< Diagnostic Buffer Select, bits 10:8 */ + uint32_t _FDIAGCTRL_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ + uint32_t DIAG_EN_KEY :4;/*!< Diagnostic Enable Key, bits 19:16 */ + uint32_t _FDIAGCTRL_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t DIAG_TRIG :1;/*!< Diagnostic Trigger, bit 24 */ + uint32_t _FDIAGCTRL_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ } FDIAGCTRL_BITS; } FdiagCtrl; @@ -401,16 +416,16 @@ union FRAW_ADDR { uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ - struct + struct { - uint32_t _FRAW_ADDR_Reserved_04_00 :5;/*!< Reserved, bits 04:00 */ - uint32_t RAW_ADDR :27;/*!< EEPROM Emulation Address, bits 31:05 */ + uint32_t _FRAW_ADDR_Reserved_04_00 :5;/*!< Reserved, bits 04:00 */ + uint32_t RAW_ADDR :27;/*!< EEPROM Emulation Address, bits 31:05 */ } FRAW_ADDR_BITS; } FrawAddr; uint32_t _Reserved_78; /* Reserved Address Locations 0x78 */ - - /*! + + /*! Defines whole and bit level accesses to the Parity Override Register - 0x7C */ union FPAR_OVR @@ -419,29 +434,29 @@ struct { uint32_t DAT_INV_PAR :8; /*!< Data Odd Parity, bits 7:0 */ - uint32_t _FPAR_OVR_Reserved_08 :1; /*!< Reserved , bit 8 */ - uint32_t PAR_OVR_KEY :3; /*!< Parity Override Key, bits 11:9 */ - uint32_t BUS_PAR_DIS :4; /*!< Disable bus parity, bits 15:12 */ - uint32_t BNK_INV_PAR :1; /*!< Buffer Invert Parity, bit 16 */ - uint32_t _FPAR_OVR_Reserved_31_17 :15;/*!< Reserved, bits 31:17 */ + uint32_t _FPAR_OVR_Reserved_08 :1; /*!< Reserved , bit 8 */ + uint32_t PAR_OVR_KEY :3; /*!< Parity Override Key, bits 11:9 */ + uint32_t BUS_PAR_DIS :4; /*!< Disable bus parity, bits 15:12 */ + uint32_t BNK_INV_PAR :1; /*!< Buffer Invert Parity, bit 16 */ + uint32_t _FPAR_OVR_Reserved_31_17 :15;/*!< Reserved, bits 31:17 */ } FPAR_OVR_BITS; } FparOvr; - + - uint32_t _Reserved_80_B0[13];/* Reserved Address Locations 0x80 - 0xB0 */ + uint32_t _Reserved_80_B0[13];/* Reserved Address Locations 0x80 - 0xB0 */ /*! Defines whole and bit level accesses to the Reset Config and JSM Key Valid Register - 0xB4 */ union RCR_JSM_VALID { uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ - struct + struct { - uint32_t RCR_VALID :1;/*!< RCR Key Valid, bits 0 */ - uint32_t JSM_VALID :1;/*!< JSM Key Valid, bits 1 */ - uint32_t _RCR_JSM_VALID_Reserved_31_02 :30;/*!< Reserved , bits 31:02 */ - } RCR_JSM_VALID_BITS; + uint32_t RCR_VALID :1;/*!< RCR Key Valid, bits 0 */ + uint32_t JSM_VALID :1;/*!< JSM Key Valid, bits 1 */ + uint32_t _RCR_JSM_VALID_Reserved_31_02 :30;/*!< Reserved , bits 31:02 */ + } RCR_JSM_VALID_BITS; } RcrJsmValid; /*! @@ -450,16 +465,16 @@ union ACC_THRESHOLD { uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ - struct + struct { - uint32_t ACC_THRESH_CNT :12;/*!< Crossbar access time threshold count, bits 11:00 */ - uint32_t _ACC_THRESHOLD_Reserved_31_12 :20;/*!< Reserved , bits 31:12 */ - } ACC_THRESHOLD_BITS; + uint32_t ACC_THRESH_CNT :12;/*!< Crossbar access time threshold count, bits 11:00 */ + uint32_t _ACC_THRESHOLD_Reserved_31_12 :20;/*!< Reserved , bits 31:12 */ + } ACC_THRESHOLD_BITS; } AccThreshold; uint32_t _Reserved_BC;/* Reserved Address Locations 0xBC */ - /*! + /*! Defines whole and bit level accesses to the EEPROM Error Detection Sector Disable Register - 0xC0 */ union FEDACSDIS2 @@ -468,19 +483,19 @@ struct { uint32_t SectorID2 :6;/*!< Sector ID2 , bits 05:00 */ - uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ - uint32_t SectorID2_inverse :6;/*!< Sector ID2 Inverse, bits 13:08 */ - uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ - uint32_t SectorID3 :6;/*!< Sector ID3 , bits 21:16 */ - uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ - uint32_t SectorID3_inverse :6;/*!< Sector ID3 Inverse, bits 29:24 */ - uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ + uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ + uint32_t SectorID2_inverse :6;/*!< Sector ID2 Inverse, bits 13:08 */ + uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ + uint32_t SectorID3 :6;/*!< Sector ID3 , bits 21:16 */ + uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ + uint32_t SectorID3_inverse :6;/*!< Sector ID3 Inverse, bits 29:24 */ + uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ } FEDACSDIS_BITS; } FedAcsDis2; uint32_t _Reserved_C4_CC[3];/* Reserved Address Locations 0xC4-0xCC */ - /*! + /*! Defines whole and bit level accesses to the RCR Lower word - 0xD0 */ union RCRVALUE0 @@ -506,7 +521,7 @@ uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ } JSMKey0; - /*! + /*! Defines whole and bit level accesses to the JSM Key1 - 0xE4 */ union JSMKEY1 @@ -532,7 +547,7 @@ uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ } JSMKey3; - uint32_t _Reserved_F0_10C[8];/* Reserved Address Locations 0xF0 - 0x10C */ + uint32_t _Reserved_F0_10C[8];/* Reserved Address Locations 0xF0 - 0x10C */ /*! @@ -551,8 +566,8 @@ struct { uint32_t Reserved_23_00 :24; - uint32_t AutoCalc_EN :1;/*!< Sector ID3 Inverse, bits 29:24 */ - uint32_t Reserved_31_30 :7;/*!< Reserved bits, 31:30 */ + uint32_t AutoCalc_EN :1;/*!< Sector ID3 Inverse, bits 29:24 */ + uint32_t Reserved_31_30 :7;/*!< Reserved bits, 31:30 */ } FTCTRL_BITS; } Ftctrl; @@ -633,9 +648,9 @@ struct { uint32_t u8Bytes31_24:8; - uint32_t u8Bytes23_16:8; - uint32_t u8Bytes15_08:8; - uint32_t u8Bytes07_00:8; + uint32_t u8Bytes23_16:8; + uint32_t u8Bytes15_08:8; + uint32_t u8Bytes07_00:8; } FWPWRITE_ECC_BYTES; } FwpwriteEcc; @@ -650,7 +665,7 @@ struct { uint32_t FSMCMD :6; /*!< Flash State Machine Command, bits 5:0 */ - uint32_t _FSM_COMMAND_Reserved_31_06 :26;/*!< Reserved, bits 31:6 */ + uint32_t _FSM_COMMAND_Reserved_31_06 :26;/*!< Reserved, bits 31:6 */ } FSM_COMMAND_BITS; } FsmCommand; @@ -665,7 +680,7 @@ struct { uint32_t WR_ENA :3; /*!< FSM Write Enable, bits 2:0 */ - uint32_t _FSM_WR_ENA_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ + uint32_t _FSM_WR_ENA_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ } FSM_WR_ENA_BITS; } FsmWrEna; @@ -679,10 +694,10 @@ uint32_t u32Register; /* FSM Sector, bits 31:0 */ struct { - uint32_t SEC_OUT :4; /*!< Sector from Address decoder, bits 3:0 */ - uint32_t SECTOR :4; /*!< Current sector used by FSM, bits 7:4 */ - uint32_t FLEE_SECT_ETXN :8; /*!< FLEE Sector Extension bits, bits 15:8 */ - uint32_t SECT_ERASED :16;/*!< Sectors Erased, bits 31:16 */ + uint32_t SEC_OUT :4; /*!< Sector from Address decoder, bits 3:0 */ + uint32_t SECTOR :4; /*!< Current sector used by FSM, bits 7:4 */ + uint32_t FLEE_SECT_ETXN :8; /*!< FLEE Sector Extension bits, bits 15:8 */ + uint32_t SECT_ERASED :16;/*!< Sectors Erased, bits 31:16 */ } FSM_SECTOR_BITS; } FsmSector; @@ -698,9 +713,9 @@ struct { uint32_t FSMEXECUTE :5; /*!< FSM Command Execute, bits 4:0 */ - uint32_t _FSM_EXECUTE_Reserved_15_05 :11;/*!< Reserved, bits 15:5 */ - uint32_t SUSPEND_NOW :4; /*!< FSM Command Suspend, bits 19:16 */ - uint32_t _FSM_EXECUTE_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + uint32_t _FSM_EXECUTE_Reserved_15_05 :11;/*!< Reserved, bits 15:5 */ + uint32_t SUSPEND_NOW :4; /*!< FSM Command Suspend, bits 19:16 */ + uint32_t _FSM_EXECUTE_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ } FSM_EXECUTE_BITS; } FsmExecute; @@ -713,14 +728,14 @@ struct { uint32_t _EEPROM_CONFIG_Reserved_15_00 :16;/*!< Reserved, bits 15:0 */ - uint32_t EWAIT :4; /*!< EEPROM Wait state Counter, bits 19:16 */ - uint32_t _EEPROM_CONFIG_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + uint32_t EWAIT :4; /*!< EEPROM Wait state Counter, bits 19:16 */ + uint32_t _EEPROM_CONFIG_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ } EEPROM_CONFIG_BITS; } EepromConfig; uint32_t _Reserved_2BC; /* Reserved Address Locations 0x2BC */ - - /*! + + /*! Defines whole and bit level accesses to the FSM Sector1 Register - 0x2C0 */ union FSM_SECTOR_1 @@ -738,8 +753,8 @@ uint32_t _Reserved_2C8_3FC[78];/* Reserved Address Locations 0x2C8 - 0x3FC */ - - /*! + + /*! Defines whole and bit level accesses to the FCFG BANK Register - 0x400 */ union FCFG_BANK_1 @@ -748,11 +763,11 @@ struct { uint32_t _FCFG_BANK_Reserved_3_0 :4; /*!< Reserved bits 3:0 */ - uint32_t MAIN_BANK_WIDTH :12;/*!< MAIN_BANK_WIDTH, bits 15:4 */ - uint32_t _FCFG_BANK_Reserved_19_16 :4; /*!< Reserved bits 19:16 */ - uint32_t EE_BANK_WIDTH :12;/*!< EE_BANK_WIDTH, bits 31:20 */ + uint32_t MAIN_BANK_WIDTH :12;/*!< MAIN_BANK_WIDTH, bits 15:4 */ + uint32_t _FCFG_BANK_Reserved_19_16 :4; /*!< Reserved bits 19:16 */ + uint32_t EE_BANK_WIDTH :12;/*!< EE_BANK_WIDTH, bits 31:20 */ } FCFG_BANK_BITS; - } FcfgBank; + } FcfgBank; }Fapi_FmcRegistersType; #else @@ -1262,13 +1277,13 @@ uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ struct { - uint32_t Reserved_00 :1;/*!< Reserved bit, 00 */ - uint32_t Test_EN :1;/*!< Test Enable bit 1 */ - uint32_t Reserved_23_02 :14;/*!< Reserved bits, 23:02 */ - uint32_t WKData_Blk_Clr :1;/*!< Block clearing of FWPWRTITE, bit 16 */ - uint32_t Reserved_23_17 :7;/*!< Reserved bits, 23:17 */ - uint32_t AutoCalc_EN :1;/*!< Auto Calc Enable bit 24 */ - uint32_t Reserved_31_25 :7;/*!< Reserved bits, 31:25 */ + uint32_t Reserved_00 :1;/*!< Reserved bit, 00 */ + uint32_t Test_EN :1;/*!< Test Enable bit 1 */ + uint32_t Reserved_23_02 :14;/*!< Reserved bits, 23:02 */ + uint32_t WKData_Blk_Clr :1;/*!< Block clearing of FWPWRTITE, bit 16 */ + uint32_t Reserved_23_17 :7;/*!< Reserved bits, 23:17 */ + uint32_t AutoCalc_EN :1;/*!< Auto Calc Enable bit 24 */ + uint32_t Reserved_31_25 :7;/*!< Reserved bits, 31:25 */ } FTCTRL_BITS; } Ftctrl; Index: FlashDrvr/Types.h =================================================================== diff -u -r51178541e201275f227c8b3e8084a455bb78cf39 -rb2eb8548de53d6b88342ee551a929a9fe166a1f9 --- FlashDrvr/Types.h (.../Types.h) (revision 51178541e201275f227c8b3e8084a455bb78cf39) +++ FlashDrvr/Types.h (.../Types.h) (revision b2eb8548de53d6b88342ee551a929a9fe166a1f9) @@ -1,3 +1,18 @@ +/************************************************************************** +* +* Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. +* +* THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN +* WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. +* +* @file +* +* @date 10-Mar-2020 +* @author Sean +* +* @brief PLEASE WRITE A BRIEF +* +**************************************************************************/ /********************************************************************************************************************** * COPYRIGHT * ------------------------------------------------------------------------------------------------------------------- @@ -74,10 +89,10 @@ #endif #if !defined(false) -#define false 0U +#define false 0U #endif #if !defined(true) -#define true 1U +#define true 1U #endif /*****************************************************************************/ @@ -320,7 +335,7 @@ #if defined(_LITTLE_ENDIAN) typedef union { - volatile struct + volatile struct { #if defined (_C28X) uint16_t ChecksumLength:16; /* 0x150 bits 15:0 */ @@ -436,7 +451,7 @@ #else typedef union { - volatile struct + volatile struct { uint32_t OtpVersion:16; /* 0x150 bits 31:16 */ uint32_t ChecksumLength:16; /* 0x150 bits 15:0 */ @@ -540,8 +555,8 @@ uint16_t u16FlowCheck; uint16_t u16WaferYCoordinate; uint16_t u16WaferXCoordinate; -#else - uint16_t u16Reserved; +#else + uint16_t u16Reserved; uint16_t u16NumberOfBanks; uint16_t u16DevicePackage; uint16_t u16DeviceMemorySize;