Index: Common.h =================================================================== diff -u -r5a6ad1d7cd7a517fbf0a8eb1293cb6d4d0dff13b -rdeccca7f64383d627e700a8bb929742eb33d947a --- Common.h (.../Common.h) (revision 5a6ad1d7cd7a517fbf0a8eb1293cb6d4d0dff13b) +++ Common.h (.../Common.h) (revision deccca7f64383d627e700a8bb929742eb33d947a) @@ -8,7 +8,7 @@ * @file Common.h * * @author (last) Dara Navaei -* @date (last) 21-May-2022 +* @date (last) 21-Sep-2022 * * @author (original) Sean * @date (original) 04-Feb-2020 @@ -34,7 +34,7 @@ typedef float F32; ///< 32-bit floating point type typedef double F64; ///< 64-bit floating point type -typedef long long U64; ///< 64-bit signed integer type +typedef long long S64; ///< 64-bit signed integer type typedef unsigned int U32; ///< 32-bit unsigned integer type typedef int S32; ///< 32-bit signed integer type typedef unsigned short U16; ///< 16-bit unsigned integer type @@ -121,6 +121,8 @@ #define BITS_12_FULL_SCALE 4096 ///< Full scale range for 12 bit ADC or DAC #define BITS_14_FULL_SCALE 16384 ///< Full scale range for 14 bit ADC or DAC #define BITS_16_FULL_SCALE 65536 ///< Full scale range for 16 bit ADC or DAC +#define BITS_24_FULL_SCALE 16777216 ///< Full scale range for 24 bit ADC or DAC +#define HALF 0.5F ///< Half // **** Common Macros **** Index: Integrity.c =================================================================== diff -u -r6b11ea4a37a54cd47af543900dfa68dac27c8c7e -rdeccca7f64383d627e700a8bb929742eb33d947a --- Integrity.c (.../Integrity.c) (revision 6b11ea4a37a54cd47af543900dfa68dac27c8c7e) +++ Integrity.c (.../Integrity.c) (revision deccca7f64383d627e700a8bb929742eb33d947a) @@ -17,9 +17,15 @@ #include +#include "reg_tcram.h" + #include "Integrity.h" #include "SafetyShutdown.h" -#include "Utilities.h" +#include "SystemCommMessages.h" +#include "TaskGeneral.h" +#include "Utilities.h" +#include "DGDefs.h" +#include "HDDefs.h" /** * @addtogroup Integrity @@ -30,13 +36,24 @@ #define CRC_TABLE_STARTING_ADDR 0x20 ///< The starting address of CRC table for firmware image. #define MAX_CRC_CALC_DATA_SIZE 0x8000 ///< The maximum size of data for each CRC calculation. +#define SERR 0x00000001 ///< Bit 0 - Single-bit error in TCRAM Module Error Status Register +#define ADDR_DEC_FAIL 0x00000004 ///< Bit 2 - Address decode failed in TCRAM Module Error Status Register +#define ADDR_COMP_LOGIC_FAIL 0x00000010 ///< Bit 4 - Address decode logic element failed in TCRAM Module Error Status Register +#define DERR 0x00000020 ///< Bit 5 - Multiple bit error in TCRAM Module Error Status Register +#define RADDR_PAR_FAIL 0x00000100 ///< Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register +#define WADDR_PAR_FAIL 0x00000200 ///< Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register +/// Time threshold to check RAM error is 2 seconds +static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((2 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL); + // ********** private data ********** static U32 currentRecord; ///< Current CRC table record to check. static U32 currentProcessedSize; ///< Current data size processed for CRC calculation. static U32 crcCalculated; ///< The calculated CRC value. static SELF_TEST_STATUS_T integrityTestStatus; ///< Current firmware integrity test status. +static U32 processorRAMStatusCounter; ///< Counter used to check processor RAM error. +static BOOL singleBitRAMErrorFlag; ///< Flag to signal the processor RAM error. /*********************************************************************//** * @brief @@ -51,8 +68,61 @@ currentProcessedSize = 0; crcCalculated = 0; integrityTestStatus = SELF_TEST_STATUS_IN_PROGRESS; + processorRAMStatusCounter = 0; + singleBitRAMErrorFlag = FALSE; } +/********************************************************************************//** + * @brief + * The execRAMMonitor function monitors the processor RAM status. + * @details Inputs: none + * @details Outputs: system event log or alarm activated if RAM error is detected. + * @return none + ***********************************************************************************/ +void execRAMMonitor( void ) +{ + U32 tcram1ErrStat, tcram2ErrStat = 0; + U32 err1, err2 = 0; + + // Check for processor RAM error + if ( ++processorRAMStatusCounter > RAM_ERROR_CHECK_TIME_THRESHOLD ) + { + tcram1ErrStat = tcram1REG->RAMERRSTATUS; // B0TCM in TCRAM Module Error Status Register + tcram2ErrStat = tcram2REG->RAMERRSTATUS; // B1TCM in TCRAM Module Error Status Register + + err1 = tcram1ErrStat & SERR; // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register + err2 = tcram2ErrStat & SERR; // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register + + if( ( err1 != 0 ) || ( err2 != 0 ) ) + { + if ( FALSE == singleBitRAMErrorFlag ) + { + // Log the single-bit RAM error event once only +#ifdef _DG_ + SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat ); +#else + SEND_EVENT_WITH_2_U32_DATA( HD_EVENT_CPU_RAM_ERROR_STATUS, tcram1ErrStat, tcram2ErrStat ); +#endif + singleBitRAMErrorFlag = TRUE; + } + } + + err1 = tcram1ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL); + err2 = tcram2ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL); + + if ( ( err1 != 0 ) || ( err2 != 0 ) ) + { +#ifdef _DG_ + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat ); +#else + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_HD_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat ); +#endif + } + + processorRAMStatusCounter = 0; + } +} + /*********************************************************************//** * @brief * The execIntegrityTest function executes the integrity check for firmware image. Index: Timers.c =================================================================== diff -u -r62e9c2f5e63c5f9813d410e684ec1e2eb092e176 -rdeccca7f64383d627e700a8bb929742eb33d947a --- Timers.c (.../Timers.c) (revision 62e9c2f5e63c5f9813d410e684ec1e2eb092e176) +++ Timers.c (.../Timers.c) (revision deccca7f64383d627e700a8bb929742eb33d947a) @@ -7,8 +7,8 @@ * * @file Timers.c * -* @author (last) Sean Nash -* @date (last) 24-Sep-2020 +* @author (last) Dara Navaei +* @date (last) 29-Jul-2022 * * @author (original) Sean * @date (original) 17-Feb-2020 Index: Utilities.h =================================================================== diff -u -r51fff72291e1b83cc32e8f28bad7f821dfcc5b9c -rdeccca7f64383d627e700a8bb929742eb33d947a --- Utilities.h (.../Utilities.h) (revision 51fff72291e1b83cc32e8f28bad7f821dfcc5b9c) +++ Utilities.h (.../Utilities.h) (revision deccca7f64383d627e700a8bb929742eb33d947a) @@ -7,8 +7,8 @@ * * @file Utilities.h * -* @author (last) Michael Garthwaite -* @date (last) 22-Feb-2022 +* @author (last) Dara Navaei +* @date (last) 09-Aug-2022 * * @author (original) Sean * @date (original) 17-Feb-2020 @@ -63,6 +63,13 @@ NUM_OF_CRITICAL_DATA_TYPES ///< Total number of critical data types } CRITICAL_DATA_TYPES_T; +/// Semaphore items +typedef enum Semaphores +{ + SEMAPHORE_RTC = 0, ///< Semaphore RTC + NUM_OF_SEMAPHORES, ///< Number of semaphores +} SEMAPHORE_T; + /// Record structure for alarm data of any supported type. typedef union { @@ -88,7 +95,7 @@ U32 crc32( U32 const initialValue, const U08 *address, U32 len ); U16 crc16( const U08 *address, U32 len ); U08 crc8( const U08 *address, U32 len ); -U08 crc4( U08* buffer ); +U08 crc4( U16* buffer, U32 byteCount ); U32 u32DiffWithWrap( U32 start, U32 end ); S32 u32BiDiffWithWrap( U32 start, U32 end ); U16 u16DiffWithWrap( U16 start, U16 end ); @@ -100,7 +107,12 @@ BOOL isCriticalDataInRange( CRITICAL_DATA_T *data ); void resetCriticalData( CRITICAL_DATA_T *data ); U32 hexStrToDec( U08 const * const valuePtr, U08 size ); -BOOL isCriticalDataSet( CRITICAL_DATA_T *data ); ///< Determines if critcal data has been set. +BOOL isCriticalDataSet( CRITICAL_DATA_T *data ); ///< Determines if critical data has been set. + +void initSemaphores( void ); +BOOL getSemaphore( SEMAPHORE_T s ); +void releaseSemaphore( SEMAPHORE_T s ); +BOOL isSemaphoreReleased( SEMAPHORE_T s ); /**@}*/