Index: FlashDriver/CGT.CCS.h =================================================================== diff -u --- FlashDriver/CGT.CCS.h (revision 0) +++ FlashDriver/CGT.CCS.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,54 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: CGT.CCS.h + * + * Description: TI CCS compiler specific info used by the F021 API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef CGT_CCS_H_ +#define CGT_CCS_H_ + +#if defined(__big_endian__) /* is big endian compile */ +#if !defined(_BIG_ENDIAN) + #define _BIG_ENDIAN /* FAPI generic define for big endian */ +#endif +#elif defined(__little_endian__) /* is little endian compile */ +#if !defined(_LITTLE_ENDIAN) + #define _LITTLE_ENDIAN /* FAPI generic define for little endian */ +#endif +#endif + +/* Defines the method to indicate packed enums */ +#if defined(__TI_GNU_ATTRIBUTE_SUPPORT__) && (__TI_GNU_ATTRIBUTE_SUPPORT__==1) +/* --gcc option enabled so we can specify this */ +#define ATTRIBUTE_PACKED __attribute__((packed)) +#else +/* --gcc option not enabled so we cannot specify this */ +#define ATTRIBUTE_PACKED +#endif + + +#endif /* CGT_CCS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: CGT.CCS.h + *********************************************************************************************************************/ Index: FlashDriver/Compatibility.h =================================================================== diff -u --- FlashDriver/Compatibility.h (revision 0) +++ FlashDriver/Compatibility.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,54 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Compatibility.h + * + * Description: A set of macro defines to provide backwards compatibility to v1.x API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef COMPATIBILITY_H_ +#define COMPATIBILITY_H_ + +/*LDRA_NOANALYSIS*/ +/* This header file is intended for backwards compatibility only and is not meant to be MISRA-C compliant */ + +/* Define to provide backwards compatibility with Fapi_initializeFlashApi() */ +#define Fapi_initializeAPI(mControlRegister,mFrequency) (Fapi_initializeFlashBanks((mFrequency))) + +/* Define to provide backwards compatibility with Fapi_getFsmStatus() */ +#define Fapi_getFsmStatus() (FAPI_GET_FSM_STATUS) + +/* Define to provide backwards compatibility with Fapi_issueFsmSuspendCommand() */ +#define Fapi_issueFsmSuspendCommand() (FAPI_SUSPEND_FSM) + +/* Define to provide backwards compatibility with Fapi_writeEwaitValue() */ +#define Fapi_writeEwaitValue(mEwait) (FAPI_WRITE_EWAIT((mEwait))) + +/* Define to provide backwards compatibility with Fapi_checkFsmForReady() */ +#define Fapi_checkFsmForReady() (FAPI_CHECK_FSM_READY_BUSY) + + +#endif +/*LDRA_ANALYSIS*/ + +/********************************************************************************************************************** + * END OF FILE: Compatibility.h + *********************************************************************************************************************/ Index: FlashDriver/Constants.h =================================================================== diff -u --- FlashDriver/Constants.h (revision 0) +++ FlashDriver/Constants.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,67 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Constants.h + * + * Description: A set of Constant Values used by the Flash Memory Controller. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef CONSTANTS_H_ +#define CONSTANTS_H_ + +/* Specifies the bit mask for determining all address bits exclusive of the offest + imposed by the memory map register */ +#define F021_PROGRAM_ADDRESS_MASK 0x07FFFFFFU + +/* Specifies the Offset to the TI OTP */ +#define F021_PROGRAM_TIOTP_OFFSET 0xF0080000U + +/* FMC memory map defines */ +#define F021_FLASH_MAP_BEGIN 0x00000000U +#define F021_FLASH_MAP_END 0x00FFFFFFU +#define F021_OTP_MAP_BEGIN 0xF0000000U +#define F021_OTP_MAP_END 0xF000FFFFU +#define F021_OTPECC_MAP_BEGIN 0xF0040000U +#define F021_OTPECC_MAP_END 0xF0041FFFU +#define F021_EEPROMECC_MAP_BEGIN 0xF0100000U +#define F021_EEPROMECC_MAP_END 0xF01FFFFFU +#define F021_EEPROM_MAP_BEGIN 0xF0200000U +#define F021_EEPROM_MAP_END 0xF03FFFFFU +#define F021_FLASHECC_MAP_BEGIN 0xF0400000U +#define F021_FLASHECC_MAP_END 0xF04FFFFFU + +#define F021_CPU0_REGISTER_ADDRESS 0xFFF87000U + +/* Specific TI OTP Offsets */ +#define F021_TIOTP_PER_BANK_SIZE 0x2000U +#define F021_TIOTP_SETTINGS_BASE 0x150U +#define F021_TIOTP_BANK_SECTOR_OFFSET 0x158U + +/* Define to map the direct access to the TI OTP memory */ +#define F021_TIOTP_BASE_ADDRESS ((Fapi_TiOtpBytesType *)(F021_PROGRAM_TIOTP_OFFSET + F021_TIOTP_SETTINGS_BASE)) + +#define F021_MINIMUM_HCLK_FREQUENCY 10U + +#endif /* CONSTANTS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Constants.h + *********************************************************************************************************************/ Index: FlashDriver/F021.h =================================================================== diff -u --- FlashDriver/F021.h (revision 0) +++ FlashDriver/F021.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,52 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: F021.h + * + * Description: Main include file for F021 devices. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef F021_H_ +#define F021_H_ + +#if !defined(F021) + #define F021 +#endif + +#if !defined(_FMC) + #define _FMC +#endif + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +#include "Types.h" +#include "Helpers.h" +#include "Constants.h" +#include "Registers.h" +#include "FapiFunctions.h" +#include "Compatibility.h" + +#endif /*F021_H_*/ + +/********************************************************************************************************************** + * END OF FILE: F021.h + *********************************************************************************************************************/ Index: FlashDriver/F021_API_CortexR4_LE_L2FMC_V3D16_NDS.lib =================================================================== diff -u Binary files differ Index: FlashDriver/FapiFunctions.h =================================================================== diff -u --- FlashDriver/FapiFunctions.h (revision 0) +++ FlashDriver/FapiFunctions.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,185 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: FapiFunctions.h + * + * Description: All the FAPI function extern definitions. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef FAPI_FUNCTIONS_H_ +#define FAPI_FUNCTIONS_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flash C API functions*/ + +/* Flash State Machine commands */ +extern Fapi_StatusType Fapi_enableMainBankSectors(uint16_t u16SectorsEnables); + +extern Fapi_StatusType Fapi_enableEepromBankSectors( + uint32_t u32SectorsEnables_31_0, + uint32_t u32SectorsEnables_63_32 + ); + +extern Fapi_StatusType Fapi_enableFsmDoneEvent(void); + +extern Fapi_StatusType Fapi_disableFsmDoneEvent(void); + +extern Fapi_StatusType Fapi_initializeFlashBanks(uint32_t u32HclkFrequency); + +extern Fapi_StatusType Fapi_setActiveFlashBank(Fapi_FlashBankType oNewFlashBank); + +extern Fapi_StatusType Fapi_enableBanksForOtpWrite(uint8_t u8Banks); + +extern Fapi_StatusType Fapi_disableBanksForOtpWrite(void); + +/* Functions only available on devices with L2FMC Flash controllers */ +#if defined(_L2FMC) + +extern Fapi_StatusType Fapi_enableAutoEccCalculation(void); +extern Fapi_StatusType Fapi_disableAutoEccCalculation(void); + +#endif /* defined(_L2FMC) */ + +extern void Fapi_flushPipeline(void); + +extern uint32_t* Fapi_remapEccAddress(uint32_t u32EccAddress); + +extern uint32_t Fapi_remapMainAddress(uint32_t u32MainAddress); + +extern boolean_t Fapi_isAddressEcc(uint32_t u32Address); + +extern boolean_t Fapi_isAddressEEPROM(uint32_t u32Address); + +/* Async Commands */ +extern Fapi_StatusType Fapi_issueAsyncCommandWithAddress( + Fapi_FlashStateCommandsType oCommand, + uint32_t* pu32StartAddress + ); + +extern Fapi_StatusType Fapi_issueAsyncCommand(Fapi_FlashStateCommandsType oCommand); + +/* Info Commands */ +extern Fapi_LibraryInfoType Fapi_getLibraryInfo(void); +extern Fapi_DeviceInfoType Fapi_getDeviceInfo(void); +extern Fapi_StatusType Fapi_getBankSectors( + Fapi_FlashBankType oBank, + Fapi_FlashBankSectorsType* poFlashBankSectors + ); +extern uint32_t Fapi_getNumberOfBankSectors( uint32_t u32Bank); +/* Read commands */ +extern Fapi_StatusType Fapi_doBlankCheck( + uint32_t* pu32StartAddress, + uint32_t u32Length, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern Fapi_StatusType Fapi_doMarginRead( + uint32_t* pu32StartAddress, + uint32_t* pu32ReadBuffer, + uint32_t u32Length, + Fapi_FlashReadMarginModeType oReadMode + ); + +extern Fapi_StatusType Fapi_doVerify( + uint32_t* pu32StartAddress, + uint32_t u32Length, + uint32_t* pu32CheckValueBuffer, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern uint32_t Fapi_calculatePsa( + uint32_t* pu32StartAddress, + uint32_t u32Length, + uint32_t u32PsaSeed, + Fapi_FlashReadMarginModeType oReadMode + ); + +extern Fapi_StatusType Fapi_doPsaVerify( + uint32_t* pu32StartAddress, + uint32_t u32Length, + uint32_t u32PsaValue, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern Fapi_StatusType Fapi_doBlankCheckByByte( + uint8_t* pu8StartAddress, + uint32_t u32Length, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +extern Fapi_StatusType Fapi_doMarginReadByByte( + uint8_t* pu8StartAddress, + uint8_t* pu8ReadBuffer, + uint32_t u32Length, + Fapi_FlashReadMarginModeType oReadMode + ); + +extern Fapi_StatusType Fapi_doVerifyByByte( + uint8_t* pu8StartAddress, + uint32_t u32Length, + uint8_t* pu8CheckValueBuffer, + Fapi_FlashStatusWordType* poFlashStatusWord + ); + +/* Programming Commands */ +extern Fapi_StatusType Fapi_issueProgrammingCommand( + uint32_t* pu32StartAddress, + uint8_t* pu8DataBuffer, + uint8_t u8DataBufferSizeInBytes, + uint8_t* pu8EccBuffer, + uint8_t u8EccBufferSizeInBytes, + Fapi_FlashProgrammingCommandsType oMode + ); + +extern Fapi_StatusType Fapi_issueProgrammingCommandForEccAddresses( + uint32_t* pu32StartAddress, + uint8_t* pu8EccBuffer, + uint8_t u8EccBufferSizeInBytes + ); + +/* Utility Commands */ +extern Fapi_StatusType Fapi_waitDelay(volatile uint32_t u32WaitDelay); + +extern uint32_t Fapi_calculateFletcherChecksum( + uint32_t u32Address, + uint32_t u32Length + ); + +extern uint8_t Fapi_calculateEcc( + uint32_t u32Address, + uint64_t u64Data + ); + +/* User Defined Functions */ +extern Fapi_StatusType Fapi_serviceWatchdogTimer(void); + +#ifdef __cplusplus +} +#endif + +#endif /*FAPI_FUNCTIONS_H_*/ + +/********************************************************************************************************************** + * END OF FILE: FapiFunctions.h + *********************************************************************************************************************/ Index: FlashDriver/Helpers.h =================================================================== diff -u --- FlashDriver/Helpers.h (revision 0) +++ FlashDriver/Helpers.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,83 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Helpers.h + * + * Description: These helper Macros are to facilitate common operations. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef HELPERS_H_ +#define HELPERS_H_ + +/* Quick Register referencing macro */ +#define REGISTER(mRegister) (* (volatile uint32_t* )(mRegister)) + +/* Macro allowing a write to a locked FSM register */ +#define FAPI_WRITE_LOCKED_FSM_REGISTER(mRegister,mValue) \ + do { \ + FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x5U; \ + (mRegister) = (mValue); \ + FLASH_CONTROL_REGISTER->FsmWrEna.FSM_WR_ENA_BITS.WR_ENA = 0x2U; \ + } while(0) + + + +/* These are helper functions to handle generic Big Endian/Little Endian code bases */ +#if defined(_LITTLE_ENDIAN) + #define EI16(idx) ((idx) ^ 1) + #define EI8(idx) ((idx) ^ 3) +#else + #define EI16(idx) (idx) + #define EI8(idx) (idx) +#endif + +/* These are helper functions to handle generic Big Endian/Little Endian code bases */ +#if defined(_L2FMC) && defined(_BIG_ENDIAN) +#define L2EI16(idx) ((idx) ^ 1) +#define L2EI8(idx) ((idx) ^ 3) +#else +#define L2EI16 EI16 +#define L2EI8 EI8 +#endif + +/* Macro that reads the FMSTAT register and indicates if the FSM is Ready or Busy */ +#define FAPI_CHECK_FSM_READY_BUSY \ + (FLASH_CONTROL_REGISTER->FmStat.FMSTAT_BITS.BUSY ? Fapi_Status_FsmBusy : Fapi_Status_FsmReady) + +/* Macro that clears the FSM_DONE event */ +#define FAPI_CLEAR_FSM_DONE_EVENT (FLASH_CONTROL_REGISTER->FedAcStatus.FEDACSTATUS_BITS.FSM_DONE = 1U) + +/* Macro that returns the value in the FMStat Register */ +#define FAPI_GET_FSM_STATUS (FLASH_CONTROL_REGISTER->FmStat.u32Register) + +/* Macro that issues a Suspend command to the FSM */ +#define FAPI_SUSPEND_FSM \ + FAPI_WRITE_LOCKED_FSM_REGISTER(FLASH_CONTROL_REGISTER->FsmExecute.FSM_EXECUTE_BITS.SUSPEND_NOW, 0x5U) + +/* Macro to set the EWAIT value */ +#define FAPI_WRITE_EWAIT(_mEwait) \ + FAPI_WRITE_LOCKED_FSM_REGISTER(FLASH_CONTROL_REGISTER->EepromConfig.EEPROM_CONFIG_BITS.EWAIT,(_mEwait)) + +#endif /* HELPERS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Helpers.h + *********************************************************************************************************************/ Index: FlashDriver/Registers.h =================================================================== diff -u --- FlashDriver/Registers.h (revision 0) +++ FlashDriver/Registers.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,92 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Registers.h + * + * Description: A complete mapping of the F021 Flash Registers facilitating named access to the F021 Flash Registers. + * This file will select the appropriate definitions based on selected compile Endianness. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef REGISTERS_H_ +#define REGISTERS_H_ + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +/*LDRA_NOANALYSIS*/ +/*LDRA_INSPECTED 42 S MR: 3.5 "Necessary for FMC register definitions" */ +/*LDRA_INSPECTED 74 S MR: 18.4 "Necessary for FMC register definitions" */ +#if defined(_LITTLE_ENDIAN) + #include "Registers_FMC_LE.h" +#else + #include "Registers_FMC_BE.h" +#endif +/*LDRA_ANALYSIS*/ + +/* Certain non released devices did not contain this information in the FMC */ +#if defined(_BIG_ENDIAN) && defined(__TI_TMS470_V7M3__) + #define WIDTH_MAIN_BANK 0x10U; + #define WIDTH_MAIN_ECC 0x2U; + #define WIDTH_EEPROM_BANK 0x10U; + #define WIDTH_EEPROM_ECC 0x2U; +#else + /* Macro to get the width of the Data on Main Banks */ + #define WIDTH_MAIN_BANK ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.MAIN_BANK_WIDTH \ + & (uint32_t)0x1C0U) >> 3U)) + /* Macro to get the width of the ECC on Main Banks */ + #define WIDTH_MAIN_ECC ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.MAIN_BANK_WIDTH \ + & (uint32_t)0x038U) >> 3U)) + /* Macro to get the width of the Data on EEPROM Bank */ + #define WIDTH_EEPROM_BANK ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.EE_BANK_WIDTH \ + & (uint32_t)0x0C0U) >> 3U)) + /* Macro to get the width of the ECC on EEPROM Bank */ + #define WIDTH_EEPROM_ECC ((uint8_t)(( (uint32_t)FLASH_CONTROL_REGISTER->FcfgBank.FCFG_BANK_BITS.EE_BANK_WIDTH \ + & (uint32_t)0x018U) >> 3U)) +#endif + +/* Typedef pointer to Fapi_FmcRegistersType */ +typedef Fapi_FmcRegistersType* pFapi_FmcRegistersType; + +/* Typedef byte pointer to FWPWRITEx Registers */ +typedef volatile uint8_t FwpWriteByteAccessorType; +/* Typedef dword pointer to FWPWRITEx Registers */ +typedef volatile uint32_t FwpWriteDWordAccessorType; + +/* Offset from FMC base address to the start of the FWPWRITEx registers */ +#define FWP_WRITE_OFFSET 0x120U +/* Macro that creates a byte accessor pointer to the FWPWRITEx registers */ +#define FWPWRITE_BYTE_ACCESSOR_ADDRESS ((FwpWriteByteAccessorType*)(F021_CPU0_REGISTER_ADDRESS + 0x120U)) +/* Macro that creates a byte accessor pointer to the FWPWRITE_ECC register */ +#define FWPWRITE_ECC_BYTE_ACCESSOR_ADDRESS ((FwpWriteByteAccessorType*)(F021_CPU0_REGISTER_ADDRESS + 0x140U)) +/* Macro that creates a dword accessor pointer to the FWPWRITEx registers */ +#define FWPWRITE_DWORD_ACCESSOR_ADDRESS ((FwpWriteDWordAccessorType*)(F021_CPU0_REGISTER_ADDRESS + 0x120U)) + +/* Macro that creates an object pointer to the start of the FMC registers */ +#define FLASH_CONTROL_REGISTER ((pFapi_FmcRegistersType)(F021_CPU0_REGISTER_ADDRESS)) + +/* Macro that defines the base address for the FMC registers structure */ +#define F021_CPU0_BASE_ADDRESS ((Fapi_FmcRegistersType*)F021_CPU0_REGISTER_ADDRESS) + +#endif /* REGISTERS_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Registers.h + *********************************************************************************************************************/ Index: FlashDriver/Registers_FMC_LE.h =================================================================== diff -u --- FlashDriver/Registers_FMC_LE.h (revision 0) +++ FlashDriver/Registers_FMC_LE.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,1592 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Registers_FMC_LE.h + * + * Description: A complete mapping of the F021 Flash Registers facilitating named access to the F021 Flash Registers. + * This file is for Little Endian devices. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef REGISTERS_LE_H_ +#define REGISTERS_LE_H_ + +/* Flash Configuration Registers */ + +/*! + Structure describing the Flash Wrapper registers allowing register and bit + level accesses. +*/ +#if defined(_L2FMC) +typedef volatile struct FMC_REGISTERS +{ + /*! + Defines whole and bit level accesses to the Read Control Register - 0x00 + */ + + union FRDCNTL + { + uint32_t u32Register; /* Read Control Register, bits 31:0 */ + struct + { + uint32_t PFUENA :1;/*!< Read Mode, bit 0 */ + uint32_t PFUENB :1;/*!< Address Setup Wait State Enable, bit 4 */ + uint32_t _FRDCNTL_Reserved_07_02 :6;/*!< Reserved, bits 7:5 */ + uint32_t RWAIT :4;/*!< Random Read Wait State, bits 11:8 */ + uint32_t _FRDCNTL_Reserved_31_12 :20;/*!< Reserved, bits 31:12 */ + } FRDCNTRL_BITS; + } FrdCntl; + + uint32_t _Reserved_04; /* Reserved Address Locations 0x04 */ + + /*! + Defines whole and bit level accesses to the Error Correction Control Register1 - 0x08 + */ + union FEDACCTRL1 + { + uint32_t u32Register; /* Error Correction Control Register1, bits 31:0 */ + struct + { + uint32_t _FEDACCTRL1_Reserved_03_00 :4;/* !< Reserved bit 03:00 */ + uint32_t EZCV :1;/*!< Zero Condition Valid, bit 4 */ + uint32_t EOCV :1;/*!< One Condition Valid, bit 5 */ + uint32_t _FEDACCTRL1_Reserved_31_06 :26;/*!< Reserved, bits 31:06 */ + + } FEDACCTRL1_BITS; + } FedAcCtrl1; + + + uint32_t _Reserved_0C; /* Reserved Address Locations 0x0C */ + + uint32_t _Reserved_10; /* Reserved Address Locations 0x10 */ + + /*! + Defines whole and bit level accesses to the Port A Error and Status Register - 0x14 + */ + union FEDAC_PASTATUS + { + uint32_t u32Register; /* Port A Error and Status Register, bits 31:0 */ + struct + { + uint32_t _FEDACPASTATUS_Reserved_09_00 :10; /* !< Reserved bits 09:00 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t _FEDACPASTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ + uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ + uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ + uint32_t _FEDACPASTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ + } FEDAC_PASTATUS_BITS; + } FedacPAStatus; + + /*! + Defines whole and bit level accesses to the Port B Error and Status Register - 0x18 + */ + union FEDAC_PBSTATUS + { + uint32_t u32Register; /* Port B Error and Status Register, bits 31:0 */ + struct + { + uint32_t _FEDACPBSTATUS_Reserved_09_00 :10; /*!< Reserved bits 09:00 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error , bits 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t _FEDACPBSTATUS_Reserved_13_12 :2; /*!< Reserved bits 13:12 */ + uint32_t MCMD_PAR_ERR :1;/*!< Parity error in MCmd while Mcmd=Idle or in MRespAccept, bit 14 */ + uint32_t ACC_TOUT :1;/*!< Crossbar access timeout/ Internal address parity error, bit 15 */ + uint32_t _FEDACPBSTATUS_Reserved_31_16 :16 ;/*!< Reserved bits 31:17 */ + } FEDAC_PBSTATUS_BITS; + } FedacPBStatus; + + /*! + Defines whole and bit level accesses to the Global Error and Status Register - 0x1C + */ + union FEDAC_GBLSTATUS + { + uint32_t u32Register; /* Global Error and Status Register ,bits 31:0 */ + struct + { + uint32_t _FEDACGLBSTATUS_Reserved_12_00 :13; /*!< Reserved bits 12:00 */ + uint32_t IMPLICIT_UNC_ERR :1;/*!< UnCorrectable error during implicit two reads from OTP, bit 13 */ + uint32_t IMPLICIT_COR_ERR :1;/*!< Correctable error during implicit two reads from OTP, bit 14 */ + uint32_t RCR_ERR :1;/*!< L2FMC_Config_out port correction, bit 15 */ + uint32_t _FEDACGLBSTATUS_Reserved_23_16 :8; /*!< Reserved bits 23:16 */ + uint32_t FSM_DONE :1;/*!< FSM done event, bit 24 */ + uint32_t RVF_EVT :1;/*!< FSM Command Read_Verify failed error event, bit 25 */ + uint32_t _FEDACGLBSTATUS_Reserved_31_26 :6 ;/*!< Reserved bits 31:26 */ + } FEDAC_GLBSTATUS_BITS; + } FedacGblStatus; + + uint32_t _Reserved_20; /* Reserved Address Locations 0x20 */ + + /*! + Defines whole and bit level accesses to the Error Detection Sector Disable Register - 0x24 + */ + union FEDACSDIS + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID0 :6;/*!< Sector ID0 , bits 05:00 */ + uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ + uint32_t SectorID0_inverse :6;/*!< Sector ID0 Inverse, bits 13:08 */ + uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ + uint32_t SectorID1 :6;/*!< Sector ID1 , bits 21:16 */ + uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ + uint32_t SectorID1_inverse :6;/*!< Sector ID1 Inverse, bits 29:24 */ + uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ + } FEDACSDIS_BITS; + } FedAcsDis; + + /*! + Defines whole and bit level accesses to the Primary Address Tag Register - 0x28 + */ + union FPRIM_ADD_TAG + { + uint32_t u32Register; /* Primary Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :5;/*!< This field always returns 0000, bits 4:0 */ + uint32_t PRIM_ADD_TAG :27;/*!< Primary Address Tag Register, bits 31:5 */ + } FPRIM_ADD_TAG_BITS; + } FprimAddTag; + + /*! + Defines whole and bit level accesses to the Redundant Address Tag Register - 0x2C + */ + union FDUP_ADD_TAG + { + uint32_t u32Register; /* Duplicate Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :5;/*!< This field always returns 0000, bits 4:0 */ + uint32_t DUP_ADD_TAG :27;/*!< Duplicate Address Tag Register, bits 31:5 */ + } FDUP_ADD_TAG_BITS; + } FdupAddTag; + + /*! + Defines whole and bit level accesses to the Bank Sector Enable Register - 0x30 + */ + union FBPROT + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t PROTL1DIS :1; /*!< Level 1 Protection Disabled, bit 0 */ + uint32_t _FBPROT_Reserved_31_01 :31;/*!< Reserved, bits 31:1 */ + } FBPROT_BITS; + } Fbprot; + + /*! + Defines whole and bit level accesses to the Bank Protection Register - 0x34 + */ + union FBSE + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t BSE :16;/*!< Bank Sector Enable, bits 15:0 */ + uint32_t _FBSE_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FBSE_BITS; + } Fbse; + + /*! + Defines whole and bit level accesses to the Bank Busy Register - 0x38 + */ + union FBBUSY + { + uint32_t u32Register; /* Bank Busy Register, bits 31:0 */ + struct + { + uint32_t BUSY :8; /*!< Bank Busy, bits 7:0 */ + uint32_t _FBBUSY_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FBPROT_BITS; + } Fbbusy; + + /*! + Defines whole and bit level accesses to the Bank Access Control Register - 0x3C + */ + union FBAC + { + uint32_t u32Register; /* Bank Access Control Register, bits 31:0 */ + struct + { + uint32_t VREADS :8;/*!< VREAD Setup, bits 7:0 */ + uint32_t _FBAC_Reserved_15_08 :8;/*!< Reserved, bits 15:8 */ + uint32_t OTPPROTDIS :8;/*!< OTP Sector Protection Disable, bits 23:16 */ + uint32_t _FBAC_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBAC_BITS; + } Fbac; + + /*! + Defines whole and bit level accesses to the Bank Power mode Register - 0x40 + */ + union FBFALLBACK + { + uint32_t u32Register; /* Bank Fallback Power Register, bits 31:0 */ + struct + { + uint32_t BANKPWR0 :2;/*!< Bank 0 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR1 :2;/*!< Bank 1 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR2 :2;/*!< Bank 2 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR3 :2;/*!< Bank 3 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR4 :2;/*!< Bank 4 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR5 :2;/*!< Bank 5 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR6 :2;/*!< Bank 6 Fallback Power Mode, bits 15:14 */ + uint32_t BANKPWR7 :2;/*!< Bank 7 Fallback Power Mode, bits 15:14 */ + uint32_t _FBAC_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FBFALLBACK_BITS; + } Fbfallback; + + /*! + Defines whole and bit level accesses to the Bank/Pump Ready Register - 0x44 + */ + union FBPRDY + { + uint32_t u32Register; /* Bank/Pump Ready Register, bits 31:0 */ + struct + { + uint32_t BANKRDY :8;/*!< Bank Ready, bits 7:0 */ + uint32_t _FBPRDY_Reserved_14_08 :7;/*!< Reserved, bits 14:8 */ + uint32_t PUMPRDY :1;/*!< Pump Ready, bit 15 */ + uint32_t BANKBUSY :8;/*!< Bank Busy with FSM, SW_INTF, CPU or PMT, bits 23:16 */ + uint32_t _FBPRDY_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBPRDY_BITS; + } Fbprdy; + + /*! + Defines whole and bit level accesses to the Pump Access Control Register 1 - 0x48 + */ + union FPAC1 + { + uint32_t u32Register; /* Flash Pump Access Control Register 1, bits 31:0 */ + struct + { + uint32_t PUMPPWR :1; /*!< Flash Charge Pump Fallback Power Mode, bit 0 */ + uint32_t _FPAC1_Reserved_15_01 :15;/*!< Reserved, bits 15:1 */ + uint32_t PSBEEP :12;/*!< Pump Sleep, bits 27:16 */ + uint32_t _FPAC1_Reserved_31_28 :4; /*!< Reserved, bits 31:28 */ + } FPAC1_BITS; + } Fpac1; + + + uint32_t _Reserved_4C; /* Reserved Address Locations 0x4C */ + + /*! + Defines whole and bit level accesses to the Module Access Control Register - 0x50 + */ + union FMAC + { + uint32_t u32Register; /* Module Access Control Register, bits 31:0 */ + struct + { + uint32_t BANK :3; /*!< Bank Enable, bits 2:0 */ + uint32_t _FMAC_Reserved_31_03 :29; /*!< Reserved, bits 31:3 */ + } FMAC_BITS; + } Fmac; + + /*! + Defines whole and bit level accesses to the Module Status Register - 0x54 + */ + union FMSTAT + { + uint32_t u32Register; /* Module Status Register, bits 31:0 */ + struct + { + uint32_t SLOCK :1; /*!< Sector Lock Status, bit 0 */ + uint32_t PSUSP :1; /*!< Program Suspend, bit 1 */ + uint32_t ESUSP :1; /*!< Erase Suspend, bit 2 */ + uint32_t VOLSTAT :1; /*!< Core Voltage Status, bit 3 */ + uint32_t CSTAT :1; /*!< Command Status, bit 4 */ + uint32_t INVDAT :1; /*!< Invalid Data, bit 5 */ + uint32_t PGM :1; /*!< Program Active, bit 6 */ + uint32_t ERS :1; /*!< Erase Active, bit 7 */ + uint32_t BUSY :1; /*!< Busy, bit 8 */ + uint32_t CV :1; /*!< Compact Verify, bit 9 */ + uint32_t EV :1; /*!< Erase verify, bit 10 */ + uint32_t PCV :1; /*!< Precondidition verify, bit 11 */ + uint32_t PGV :1; /*!< Program verify, bit 12 */ + uint32_t DBT :1; /*!< Disturbance Test Fail, bit 13 */ + uint32_t ILA :1; /*!< Illegal Address, bit 14 */ + uint32_t RVF :1; /*!< Read Verify Failure, bit 15 */ + uint32_t RDVER :1; /*!< Read Verify command currently underway, bit 16 */ + uint32_t RVSUSP :1; /*!< Read Verify Suspend, bit 17 */ + uint32_t _FMSTAT_Reserved_31_18 :14;/*!< Reserved, bits 31:18 */ + } FMSTAT_BITS; + } FmStat; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data MSW Register - 0x58 + */ + union FEMU_DMSW + { + uint32_t u32Register; /* EEPROM Emulation Data MSW Register, bits 31:0 */ + } FemuDmsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data LSW Register - 0x5C + */ + union FEMU_DLSW + { + uint32_t u32Register; /* EEPROM Emulation Data LSW Register, bits 31:0 */ + } FemuDlsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation ECC Register - 0x60 + */ + union FEMU_ECC + { + uint32_t u32Register; /* EEPROM Emulation ECC Register, bits 31:0 */ + struct + { + uint32_t EMU_ECC :8; /*!< EEPROM Emulation ECC, bits 7:0 */ + uint32_t _FEMU_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FEMU_ECC_BITS; + } FemuEcc; + + uint32_t _Reserved_64; /* Reserved Address Locations 0x64 */ + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Address Register - 0x68 + */ + union FEMU_ADDR + { + uint32_t u32Register; /* EEPROM Emulation Address, bits 31:0 */ + struct + { + uint32_t _FEMU_ADDR_Reserved_02_00 :3;/*!< Reserved, bits 02:00 */ + uint32_t EMU_ADDR :29;/*!< EEPROM Emulation Address, bits 31:03 */ + } FEMU_ADDR_BITS; + } FemuAddr; + + /*! + Defines whole and bit level accesses to the Diagnostic Control Register - 0x6C + */ + union FDIAGCTRL + { + uint32_t u32Register; /* Diagnostic Control Register, bits 31:0 */ + struct + { + uint32_t DIAGMODE :3;/*!< Diagnostic Mode, bits 2:0 */ + uint32_t _FDIAGCTRL_Reserved_07_03 :5;/*!< Reserved, bits 7:3 */ + uint32_t DIAG_BUF_SEL :3;/*!< Diagnostic Buffer Select, bits 10:8 */ + uint32_t _FDIAGCTRL_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ + uint32_t DIAG_EN_KEY :4;/*!< Diagnostic Enable Key, bits 19:16 */ + uint32_t _FDIAGCTRL_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t DIAG_TRIG :1;/*!< Diagnostic Trigger, bit 24 */ + uint32_t _FDIAGCTRL_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FDIAGCTRL_BITS; + } FdiagCtrl; + + uint32_t _Reserved_70; /* Reserved Address Locations 0x70 */ + + /*! + Defines whole and bit level accesses to the Uncorrected Raw Data High Register - 0x70 + */ + union FRAW_ADDR + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + struct + { + uint32_t _FRAW_ADDR_Reserved_04_00 :5;/*!< Reserved, bits 04:00 */ + uint32_t RAW_ADDR :27;/*!< EEPROM Emulation Address, bits 31:05 */ + } FRAW_ADDR_BITS; + } FrawAddr; + + uint32_t _Reserved_78; /* Reserved Address Locations 0x78 */ + + /*! + Defines whole and bit level accesses to the Parity Override Register - 0x7C + */ + union FPAR_OVR + { + uint32_t u32Register; /* Parity Override, bits 31:0 */ + struct + { + uint32_t DAT_INV_PAR :8; /*!< Data Odd Parity, bits 7:0 */ + uint32_t _FPAR_OVR_Reserved_08 :1; /*!< Reserved , bit 8 */ + uint32_t PAR_OVR_KEY :3; /*!< Parity Override Key, bits 11:9 */ + uint32_t BUS_PAR_DIS :4; /*!< Disable bus parity, bits 15:12 */ + uint32_t BNK_INV_PAR :1; /*!< Buffer Invert Parity, bit 16 */ + uint32_t _FPAR_OVR_Reserved_31_17 :15;/*!< Reserved, bits 31:17 */ + } FPAR_OVR_BITS; + } FparOvr; + + + uint32_t _Reserved_80_B0[13];/* Reserved Address Locations 0x80 - 0xB0 */ + + /*! + Defines whole and bit level accesses to the Reset Config and JSM Key Valid Register - 0xB4 + */ + union RCR_JSM_VALID + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + struct + { + uint32_t RCR_VALID :1;/*!< RCR Key Valid, bits 0 */ + uint32_t JSM_VALID :1;/*!< JSM Key Valid, bits 1 */ + uint32_t _RCR_JSM_VALID_Reserved_31_02 :30;/*!< Reserved , bits 31:02 */ + } RCR_JSM_VALID_BITS; + } RcrJsmValid; + + /*! + Defines whole and bit level accesses to the Crossbar access time threshold Register - 0xB8 + */ + union ACC_THRESHOLD + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + struct + { + uint32_t ACC_THRESH_CNT :12;/*!< Crossbar access time threshold count, bits 11:00 */ + uint32_t _ACC_THRESHOLD_Reserved_31_12 :20;/*!< Reserved , bits 31:12 */ + } ACC_THRESHOLD_BITS; + } AccThreshold; + + uint32_t _Reserved_BC;/* Reserved Address Locations 0xBC */ + + /*! + Defines whole and bit level accesses to the EEPROM Error Detection Sector Disable Register - 0xC0 + */ + union FEDACSDIS2 + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID2 :6;/*!< Sector ID2 , bits 05:00 */ + uint32_t _FEDACSDIS_Reserved_07_06 :2;/*!< Reserved bits, 07:06 */ + uint32_t SectorID2_inverse :6;/*!< Sector ID2 Inverse, bits 13:08 */ + uint32_t _FEDACSDIS_Reserved_15_14 :2;/*!< Reserved bits, 15:14 */ + uint32_t SectorID3 :6;/*!< Sector ID3 , bits 21:16 */ + uint32_t _FEDACSDIS_Reserved_23_22 :2;/*!< Reserved bits, 23:22 */ + uint32_t SectorID3_inverse :6;/*!< Sector ID3 Inverse, bits 29:24 */ + uint32_t _FEDACSDIS_Reserved_31_30 :2;/*!< Reserved bits, 31:30 */ + } FEDACSDIS_BITS; + } FedAcsDis2; + + uint32_t _Reserved_C4_CC[3];/* Reserved Address Locations 0xC4-0xCC */ + + /*! + Defines whole and bit level accesses to the RCR Lower word - 0xD0 + */ + union RCRVALUE0 + { + uint32_t u32Register; /* RCR Lower word, bits 31:0 */ + } RcrValue0; + + /*! + Defines whole and bit level accesses to the RCR Upper word - 0xD4 + */ + union RCRVALUE1 + { + uint32_t u32Register; /* RCR Upper word, bits 31:0 */ + } RcrValue1; + + uint32_t _Reserved_D8_DC[2];/* Reserved Address Locations 0xD8-0xDC */ + + /*! + Defines whole and bit level accesses to the JSM Key0 - 0xE0 + */ + union JSMKEY0 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey0; + + /*! + Defines whole and bit level accesses to the JSM Key1 - 0xE4 + */ + union JSMKEY1 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey1; + + + /*! + Defines whole and bit level accesses to the JSM Key2 - 0xE8 + */ + union JSMKEY2 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey2; + + + /*! + Defines whole and bit level accesses to the JSM Key3 - 0xEC + */ + union JSMKEY3 + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } JSMKey3; + + uint32_t _Reserved_F0_10C[8];/* Reserved Address Locations 0xF0 - 0x10C */ + + + /*! + Defines whole and bit level accesses to the Bank Addr Register - 0x110 + */ + union FADDR + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } Faddr; + + uint32_t _Reserved_114_118[2]; /* Reserved Address Locations 0x114-0x118 */ + + union FTCTRL + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t Reserved_23_00 :24; + uint32_t AutoCalc_EN :1;/*!< Sector ID3 Inverse, bits 29:24 */ + uint32_t Reserved_31_30 :7;/*!< Reserved bits, 31:30 */ + } FTCTRL_BITS; + } Ftctrl; + + /*! + Defines whole and bit level accesses to the FWPWRITE0 Register - 0x120 + */ + union FWPWRITE0 + { + uint32_t u32Register; /* FWPWRITE0 Register, bits 31:0 */ + } Fwpwrite0; + + /*! + Defines whole and bit level accesses to the FWPWRITE1 Register - 0x124 + */ + union FWPWRITE1 + { + uint32_t u32Register; /* FWPWRITE1 Register, bits 31:0 */ + } Fwpwrite1; + + /*! + Defines whole and bit level accesses to the FWPWRITE2 Register - 0x128 + */ + union FWPWRITE2 + { + uint32_t u32Register; /* FWPWRITE2 Register, bits 31:0 */ + } Fwpwrite2; + + /*! + Defines whole and bit level accesses to the FWPWRITE3 Register - 0x12C + */ + union FWPWRITE3 + { + uint32_t u32Register; /* FWPWRITE3 Register, bits 31:0 */ + } Fwpwrite3; + + /*! + Defines whole and bit level accesses to the FWPWRITE4 Register - 0x130 + */ + union FWPWRITE4 + { + uint32_t u32Register; /* FWPWRITE4 Register, bits 31:0 */ + } Fwpwrite4; + + /*! + Defines whole and bit level accesses to the FWPWRITE5 Register - 0x134 + */ + union FWPWRITE5 + { + uint32_t u32Register; /* FWPWRITE5 Register, bits 31:0 */ + } Fwpwrite5; + + /*! + Defines whole and bit level accesses to the FWPWRITE6 Register - 0x138 + */ + union FWPWRITE6 + { + uint32_t u32Register; /* FWPWRITE6 Register, bits 31:0 */ + } Fwpwrite6; + + /*! + Defines whole and bit level accesses to the FWPWRITE7 Register - 0x13C + */ + union FWPWRITE7 + { + uint32_t u32Register; /* FWPWRITE7 Register, bits 31:0 */ + } Fwpwrite7; + + /*! + Defines whole and bit level accesses to the FWPWRITE_ECC Register - 0x140 + */ + union FWPWRITE_ECC + { + uint32_t u32Register; /* FWPWRITE_ECC Register, bits 31:0 */ + struct + { + uint32_t WPDATA_287_256; /*!< WPDATA[287:256], bits 31:0 */ + } FWPWRITE_ECC_BITS; + struct + { + uint32_t u8Bytes31_24:8; + uint32_t u8Bytes23_16:8; + uint32_t u8Bytes15_08:8; + uint32_t u8Bytes07_00:8; + } FWPWRITE_ECC_BYTES; + } FwpwriteEcc; + + uint32_t _Reserved_144_208[50]; /* Reserved Address Locations 0x144-0x208 */ + + /*! + Defines whole and bit level accesses to the FSM Command Register - 0x20C + */ + union FSM_COMMAND + { + uint32_t u32Register; /* FSM Command, bits 31:0 */ + struct + { + uint32_t FSMCMD :6; /*!< Flash State Machine Command, bits 5:0 */ + uint32_t _FSM_COMMAND_Reserved_31_06 :26;/*!< Reserved, bits 31:6 */ + } FSM_COMMAND_BITS; + } FsmCommand; + + uint32_t _Reserved_210_284[30]; /* Reserved Address Locations 0x210-0x284 */ + + /*! + Defines whole and bit level accesses to the FSM Register Write Enable- 0x288 + */ + union FSM_WR_ENA + { + uint32_t u32Register; /* FSM Register Write Enable, bits 31:0 */ + struct + { + uint32_t WR_ENA :3; /*!< FSM Write Enable, bits 2:0 */ + uint32_t _FSM_WR_ENA_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ + } FSM_WR_ENA_BITS; + } FsmWrEna; + + uint32_t _Reserved_28C_2A0[6]; /* Reserved Address Locations 0x28C-0x2A0 */ + + /*! + Defines whole and bit level accesses to the FSM Sector Register - 0x2A4 + */ + union FSM_SECTOR + { + uint32_t u32Register; /* FSM Sector, bits 31:0 */ + struct + { + uint32_t SEC_OUT :4; /*!< Sector from Address decoder, bits 3:0 */ + uint32_t SECTOR :4; /*!< Current sector used by FSM, bits 7:4 */ + uint32_t FLEE_SECT_ETXN :8; /*!< FLEE Sector Extension bits, bits 15:8 */ + uint32_t SECT_ERASED :16;/*!< Sectors Erased, bits 31:16 */ + } FSM_SECTOR_BITS; + } FsmSector; + + uint32_t _Reserved_2A8_2B0[3]; /* Reserved Address Locations 0x2A8-0x2B0 */ + + + /*! + Defines whole and bit level accesses to the FSM Command Execute Register - 0x2B4 + */ + union FSM_EXECUTE + { + uint32_t u32Register; /* FSM Command Execute, bits 31:0 */ + struct + { + uint32_t FSMEXECUTE :5; /*!< FSM Command Execute, bits 4:0 */ + uint32_t _FSM_EXECUTE_Reserved_15_05 :11;/*!< Reserved, bits 15:5 */ + uint32_t SUSPEND_NOW :4; /*!< FSM Command Suspend, bits 19:16 */ + uint32_t _FSM_EXECUTE_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + } FSM_EXECUTE_BITS; + } FsmExecute; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation configuration Register - 0x2B8 + */ + union EEPROM_CONFIG + { + uint32_t u32Register; /* EEPROM Emulation configuration, bits 31:0 */ + struct + { + uint32_t _EEPROM_CONFIG_Reserved_15_00 :16;/*!< Reserved, bits 15:0 */ + uint32_t EWAIT :4; /*!< EEPROM Wait state Counter, bits 19:16 */ + uint32_t _EEPROM_CONFIG_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + } EEPROM_CONFIG_BITS; + } EepromConfig; + + uint32_t _Reserved_2BC; /* Reserved Address Locations 0x2BC */ + + /*! + Defines whole and bit level accesses to the FSM Sector1 Register - 0x2C0 + */ + union FSM_SECTOR_1 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector1; + + /*! + Defines whole and bit level accesses to the FSM Sector2 Register - 0x2C4 + */ + union FSM_SECTOR_2 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector2; + + uint32_t _Reserved_2C8_3FC[78];/* Reserved Address Locations 0x2C8 - 0x3FC */ + + + /*! + Defines whole and bit level accesses to the FCFG BANK Register - 0x400 + */ + union FCFG_BANK_1 + { + uint32_t u32Register; /* Flash Bank configuration, bits 31:0 */ + struct + { + uint32_t _FCFG_BANK_Reserved_3_0 :4; /*!< Reserved bits 3:0 */ + uint32_t MAIN_BANK_WIDTH :12;/*!< MAIN_BANK_WIDTH, bits 15:4 */ + uint32_t _FCFG_BANK_Reserved_19_16 :4; /*!< Reserved bits 19:16 */ + uint32_t EE_BANK_WIDTH :12;/*!< EE_BANK_WIDTH, bits 31:20 */ + } FCFG_BANK_BITS; + } FcfgBank; + + }Fapi_FmcRegistersType; +#else +typedef volatile struct FMC_REGISTERS +{ + /*! + Defines whole and bit level accesses to the Read Control Register - 0x00 + */ + union FRDCNTL + { + uint32_t u32Register; /* Read Control Register, bits 31:0 */ + struct + { + uint32_t ENPIPE :1;/*!< Read Mode, bit 0 */ + uint32_t _FRDCNTL_Reserved_03_01 :3;/*!< Reserved, bits 3:1 */ + uint32_t ASWSTEN :1;/*!< Address Setup Wait State Enable, bit 4 */ + uint32_t _FRDCNTL_Reserved_07_05 :3;/*!< Reserved, bits 7:5 */ + uint32_t RWAIT :4;/*!< Random Read Wait State, bits 11:8 */ + uint32_t _FRDCNTL_Reserved_31_12 :20;/*!< Reserved, bits 31:12 */ + } FRDCNTRL_BITS; + } FrdCntl; + + uint32_t _Reserved_04; /* Reserved Address Locations 0x04 */ + + /*! + Defines whole and bit level accesses to the Error Correction Control Register1 - 0x08 + */ + union FEDACCTRL1 + { + uint32_t u32Register; /* Error Correction Control Register1, bits 31:0 */ + struct + { + uint32_t EDACEN :4;/*!< Error Detection and Correction Enable, bits 3:0 */ + uint32_t EZCV :1;/*!< Zero Condition Valid, bit 4 */ + uint32_t EOCV :1;/*!< One Condition Valid, bit 5 */ + uint32_t _FEDACCTRL1_Reserved_07_06 :2;/*!< Reserved, bits 7:6 */ + uint32_t EPEN :1;/*!< Error Profiling Enable, bit 8 */ + uint32_t EZFEN :1;/*!< Error on Zero Fail Enable, bit 9 */ + uint32_t EOFEN :1;/*!< Error on One Fail Enable, bit 10 */ + uint32_t _FEDACCTRL1_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ + uint32_t EDACMODE :4;/*!< Error Correction Mode, bits 19:16 */ + uint32_t _FEDACCTRL1_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t SUSP_IGNR :1;/*!< Suspend Ignore, bit 24 */ + uint32_t _FEDACCTRL1_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FEDACCTRL1_BITS; + } FedAcCtrl1; + + /*! + Defines whole and bit level accesses to the Error Correction Control Register2 - 0x0C + */ + union FEDACCTRL2 + { + uint32_t u32Register; /* Error Correction Control Register2, bits 31:0 */ + struct + { + uint32_t SEC_THRESHOLD :16;/*!< Single Error Correction Threshold, bits 15:0 */ + uint32_t _FEDACCTRL2_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FEDACCTRL2_BITS; + } FedAcCtrl2; + + /*! + Defines whole and bit level accesses to the Error Correction Counter Register - 0x10 + */ + union FCOR_ERR_CNT + { + uint32_t u32Register; /* Error Correction Counter Register, bits 31:0 */ + struct + { + uint32_t FERRCNT :16;/*!< Correctable Error Counter, bits 15:0 */ + uint32_t _FCOR_ERR_CNT_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FCOR_ERR_CNT_BITS; + } FcorErrCnt; + + /*! + Defines whole and bit level accesses to the Correctable Error Address Register - 0x14 + */ + union FCOR_ERR_ADD + { + uint32_t u32Register; /* Correctable Error Address Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t COR_ERR_ADD :29;/*!< Correctable Error Address, bits 31:3 */ + } FCOR_ERR_ADD_BITS; + } FcorErrAdd; + + /*! + Defines whole and bit level accesses to the Correctable Error Position Register - 0x18 + */ + union FCOR_ERR_POS + { + uint32_t u32Register; /* Correctable Error Position Register, bits 31:0 */ + struct + { + uint32_t ERR_POS :8; /*!< Single Error Position, bits 7:0 */ + uint32_t TYPE :1; /*!< Error Type, bit 8 */ + uint32_t BUS2 :1; /*!< Bus 2 error position, bit 9 */ + uint32_t _FCOR_ERR_POS_Reserved_31_10 :22;/*!< Reserved, bits 31:10 */ + } FCOR_ERR_POS_BITS; + } FcorErrPos; + + /*! + Defines whole and bit level accesses to the Error Status Register - 0x1C + */ + union FEDACSTATUS + { + uint32_t u32Register; /* Error Status Register, bits 31:0 */ + struct + { + uint32_t ERR_PRF_FLG :1;/*!< Error Profiling Status Flag, bit 0 */ + uint32_t ERR_ZERO_FLG :1;/*!< Error On Zero Fail Status Flag, bit 1 */ + uint32_t ERR_ONE_FLG :1;/*!< Error On One Fail Status Flag, bit 2 */ + uint32_t D_COR_ERR :1;/*!< Diagnostic Correctable Error Status Flag, bit 3 */ + uint32_t _FEDACSTATUS_Reserved_7_4 :4;/*!< Reserved, bits 7:4 */ + uint32_t B1_UNC_ERR :1;/*!< Bus1 Uncorrectable Error Flag, bit 8 */ + uint32_t _FEDACSTATUS_Reserved_9 :1;/*!< Reserved, bit 9 */ + uint32_t ADD_PAR_ERR :1;/*!< Address Parity Error, bit 10 */ + uint32_t ADD_TAG_ERR :1;/*!< Address Tag Register Error Status Flag, bit 11 */ + uint32_t D_UNC_ERR :1;/*!< Diagnostic Un-correctable Error Status Flag, bit 12 */ + uint32_t _FEDACSTATUS_Reserved_15_13 :3;/*!< Reserved, bits 15:13 */ + uint32_t B2_COR_ERR :1;/*!< Bus2 Correctable Error, bit 16 */ + uint32_t B2_UNC_ERR :1;/*!< Bus2 Uncorrectable Error, bit 17 */ + uint32_t ECC_B2_MAL_ERR :1;/*!< Bus2 ECC Malfunction Status Flag, bit 18 */ + uint32_t COMB2_MAL_G :1;/*!< Bus2 Compare Malfunction Flag, bit 19 */ + uint32_t _FEDACSTATUS_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t FSM_DONE :1;/*!< FSM is Finished, bit 24 */ + uint32_t _FEDACSTATUS_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FEDACSTATUS_BITS; + } FedAcStatus; + + /*! + Defines whole and bit level accesses to the Un-correctable Error Address Register - 0x20 + */ + union FUNC_ERR_ADD + { + uint32_t u32Register; /* Error Status Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t UNC_ERR_ADD :29;/*!< Un-correctable Error Address, bits 31:3 */ + } FUNC_ERR_ADD_BITS; + } FuncErrAdd; + + /*! + Defines whole and bit level accesses to the Error Detection Sector Disable Register - 0x24 + */ + union FEDACSDIS + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID0 :4;/*!< Sector ID0 , bits 3:0 */ + uint32_t _FEDACSDIS_Reserved_04 :1;/*!< Reserved, bit 4 */ + uint32_t BankID0 :3;/*!< Bank ID0 , bits 7:5 */ + uint32_t SectorID0_inverse :4;/*!< Sector ID0 Inverse, bits 11:8 */ + uint32_t _FEDACSDIS_Reserved_12 :1;/*!< Reserved, bit 12 */ + uint32_t BankID0_inverse :3;/*!< Bank ID0 Inverse, bits 15:13 */ + uint32_t SectorID1 :4;/*!< Sector ID1 , bits 19:16 */ + uint32_t _FEDACSDIS_Reserved_20 :1;/*!< Reserved, bit 20 */ + uint32_t BankID1 :3;/*!< Bank ID1 , bits 23:21 */ + uint32_t SectorID1_inverse :4;/*!< Sector ID1 Inverse, bits 27:24 */ + uint32_t _FEDACSDIS_Reserved_28 :1;/*!< Reserved, bit 28 */ + uint32_t BankID1_inverse :3;/*!< Bank ID1 Inverse, bits 31:29 */ + } FEDACSDIS_BITS; + } FedAcsDis; + + /*! + Defines whole and bit level accesses to the Primary Address Tag Register - 0x28 + */ + union FPRIM_ADD_TAG + { + uint32_t u32Register; /* Primary Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :4;/*!< This field always returns 0000, bits 3:0 */ + uint32_t PRIM_ADD_TAG :28;/*!< Primary Address Tag Register, bits 31:4 */ + } FPRIM_ADD_TAG_BITS; + } FprimAddTag; + + /*! + Defines whole and bit level accesses to the Redundant Address Tag Register - 0x2C + */ + union FDUP_ADD_TAG + { + uint32_t u32Register; /* Duplicate Address Tag Register, bits 31:0 */ + struct + { + uint32_t RET_ZERO :4;/*!< This field always returns 0000, bits 3:0 */ + uint32_t DUP_ADD_TAG :28;/*!< Primary Address Tag Register, bits 31:4 */ + } FDUP_ADD_TAG_BITS; + } FdupAddTag; + + /*! + Defines whole and bit level accesses to the Bank Sector Enable Register - 0x30 + */ + union FBPROT + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t PROTL1DIS :1; /*!< Level 1 Protection Disabled, bit 0 */ + uint32_t _FBPROT_Reserved_31_01 :31;/*!< Reserved, bits 31:1 */ + } FBPROT_BITS; + } Fbprot; + + /*! + Defines whole and bit level accesses to the Bank Protection Register - 0x34 + */ + union FBSE + { + uint32_t u32Register; /* Bank Protection Register, bits 31:0 */ + struct + { + uint32_t BSE :16;/*!< Bank Sector Enable, bits 15:0 */ + uint32_t _FBSE_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FBSE_BITS; + } Fbse; + + /*! + Defines whole and bit level accesses to the Bank Busy Register - 0x38 + */ + union FBBUSY + { + uint32_t u32Register; /* Bank Busy Register, bits 31:0 */ + struct + { + uint32_t BUSY :8; /*!< Bank Busy, bits 7:0 */ + uint32_t _FBBUSY_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FBPROT_BITS; + } Fbbusy; + + /*! + Defines whole and bit level accesses to the Bank Access Control Register - 0x3C + */ + union FBAC + { + uint32_t u32Register; /* Bank Access Control Register, bits 31:0 */ + struct + { + uint32_t VREADS :8;/*!< VREAD Setup, bits 7:0 */ + uint32_t BAGP :8;/*!< Bank Active Grace Period, bits 15:8 */ + uint32_t OTPPROTDIS :8;/*!< OTP Sector Protection Disable, bits 23:16 */ + uint32_t _FBAC_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBAC_BITS; + } Fbac; + + /*! + Defines whole and bit level accesses to the Bank Fallback Power Register - 0x40 + */ + union FBFALLBACK + { + uint32_t u32Register; /* Bank Fallback Power Register, bits 31:0 */ + struct + { + uint32_t BANKPWR0 :2;/*!< Bank 0 Fallback Power Mode, bits 1:0 */ + uint32_t BANKPWR1 :2;/*!< Bank 1 Fallback Power Mode, bits 3:2 */ + uint32_t BANKPWR2 :2;/*!< Bank 2 Fallback Power Mode, bits 5:4 */ + uint32_t BANKPWR3 :2;/*!< Bank 3 Fallback Power Mode, bits 7:6 */ + uint32_t BANKPWR4 :2;/*!< Bank 4 Fallback Power Mode, bits 9:8 */ + uint32_t BANKPWR5 :2;/*!< Bank 5 Fallback Power Mode, bits 11:10 */ + uint32_t BANKPWR6 :2;/*!< Bank 6 Fallback Power Mode, bits 13:12 */ + uint32_t BANKPWR7 :2;/*!< Bank 7 Fallback Power Mode, bits 15:14 */ + uint32_t REG_PWRSAV :4;/*!< Power saving clocking control, bits 19:16 */ + uint32_t _FBAC_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t FSM_PWRSAV :4;/*!< Power saving clocking control, bits 27:24 */ + uint32_t _FBAC_Reserved_31_28 :4;/*!< Reserved, bits 31:28 */ + } FBFALLBACK_BITS; + } Fbfallback; + + /*! + Defines whole and bit level accesses to the Bank/Pump Ready Register - 0x44 + */ + union FBPRDY + { + uint32_t u32Register; /* Bank/Pump Ready Register, bits 31:0 */ + struct + { + uint32_t BANKRDY :8;/*!< Bank Ready, bits 7:0 */ + uint32_t _FBPRDY_Reserved_14_08 :7;/*!< Reserved, bits 14:8 */ + uint32_t PUMPRDY :1;/*!< Pump Ready, bit 15 */ + uint32_t BANKBUSY :8;/*!< Bank Busy with FSM, SW_INTF, CPU or PMT, bits 23:16 */ + uint32_t _FBPRDY_Reserved_31_24 :8;/*!< Reserved, bits 31:24 */ + } FBPRDY_BITS; + } Fbprdy; + + /*! + Defines whole and bit level accesses to the Pump Access Control Register 1 - 0x48 + */ + union FPAC1 + { + uint32_t u32Register; /* Flash Pump Access Control Register 1, bits 31:0 */ + struct + { + uint32_t PUMPPWR :1; /*!< Flash Charge Pump Fallback Power Mode, bit 0 */ + uint32_t _FPAC1_Reserved_15_01 :15;/*!< Reserved, bits 15:1 */ + uint32_t PSLEEP :11;/*!< Pump Sleep, bits 26:16 */ + uint32_t _FPAC1_Reserved_31_27 :5; /*!< Reserved, bits 31:27 */ + } FPAC1_BITS; + } Fpac1; + + /*! + Defines whole and bit level accesses to the Pump Access Control Register 2 - 0x4C + */ + union FPAC2 + { + uint32_t u32Register; /* Flash Pump Access Control Register 2, bits 31:0 */ + struct + { + uint32_t PAGP :16;/*!< Pump Active Grace Period, bits 15:0 */ + uint32_t _FPAC2_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } FPAC2_BITS; + } Fpac2; + + /*! + Defines whole and bit level accesses to the Module Access Control Register - 0x50 + */ + union FMAC + { + uint32_t u32Register; /* Module Access Control Register, bits 31:0 */ + struct + { + uint32_t BANK :3; /*!< Bank Enable, bits 2:0 */ + uint32_t _FMAC_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ + } FMAC_BITS; + } Fmac; + + /*! + Defines whole and bit level accesses to the Module Status Register - 0x54 + */ + union FMSTAT + { + uint32_t u32Register; /* Module Status Register, bits 31:0 */ + struct + { + uint32_t SLOCK :1; /*!< Sector Lock Status, bit 0 */ + uint32_t PSUSP :1; /*!< Program Suspend, bit 1 */ + uint32_t ESUSP :1; /*!< Erase Suspend, bit 2 */ + uint32_t VOLSTAT :1; /*!< Core Voltage Status, bit 3 */ + uint32_t CSTAT :1; /*!< Command Status, bit 4 */ + uint32_t INVDAT :1; /*!< Invalid Data, bit 5 */ + uint32_t PGM :1; /*!< Program Active, bit 6 */ + uint32_t ERS :1; /*!< Erase Active, bit 7 */ + uint32_t BUSY :1; /*!< Busy, bit 8 */ + uint32_t CV :1; /*!< Compact Verify, bit 9 */ + uint32_t EV :1; /*!< Erase verify, bit 10 */ + uint32_t PCV :1; /*!< Precondidition verify, bit 11 */ + uint32_t PGV :1; /*!< Program verify, bit 12 */ + uint32_t DBT :1; /*!< Disturbance Test Fail, bit 13 */ + uint32_t ILA :1; /*!< Illegal Address, bit 14 */ + uint32_t RVF :1; /*!< Read Verify Failure, bit 15 */ + uint32_t RDVER :1; /*!< Read Verify command currently underway, bit 16 */ + uint32_t RVSUSP :1; /*!< Read Verify Suspend, bit 17 */ + uint32_t _FMSTAT_Reserved_31_18 :14;/*!< Reserved, bits 31:18 */ + } FMSTAT_BITS; + } FmStat; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data MSW Register - 0x58 + */ + union FEMU_DMSW + { + uint32_t u32Register; /* EEPROM Emulation Data MSW Register, bits 31:0 */ + } FemuDmsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Data LSW Register - 0x5C + */ + union FEMU_DLSW + { + uint32_t u32Register; /* EEPROM Emulation Data LSW Register, bits 31:0 */ + } FemuDlsw; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation ECC Register - 0x60 + */ + union FEMU_ECC + { + uint32_t u32Register; /* EEPROM Emulation ECC Register, bits 31:0 */ + struct + { + uint32_t EMU_ECC :8; /*!< EEPROM Emulation ECC, bits 7:0 */ + uint32_t _FEMU_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FEMU_ECC_BITS; + } FemuEcc; + + uint32_t _Reserved_64; /* Reserved Address Locations 0x64 */ + + /*! + Defines whole and bit level accesses to the EEPROM Emulation Address Register - 0x68 + */ + union FEMU_ADDR + { + uint32_t u32Register; /* EEPROM Emulation Address, bits 31:0 */ + struct + { + uint32_t EMU_ADDR :22;/*!< EEPROM Emulation Address, bits 21:0 */ + uint32_t _FEMU_ADDR_Reserved_31_22 :10;/*!< Reserved, bits 31:22 */ + } FEMU_ADDR_BITS; + } FemuAddr; + + /*! + Defines whole and bit level accesses to the Diagnostic Control Register - 0x6C + */ + union FDIAGCTRL + { + uint32_t u32Register; /* Diagnostic Control Register, bits 31:0 */ + struct + { + uint32_t DIAGMODE :3;/*!< Diagnostic Mode, bits 2:0 */ + uint32_t _FDIAGCTRL_Reserved_07_03 :5;/*!< Reserved, bits 7:3 */ + uint32_t DIAG_BUF_SEL :2;/*!< Diagnostic Buffer Select, bits 9:8 */ + uint32_t _FDIAGCTRL_Reserved_11_10 :2;/*!< Reserved, bits 11:10 */ + uint32_t DIAG_ECC_SEL :3;/*!< Diagnostic SECDED Select, bits 14-12 */ + uint32_t _FDIAGCTRL_Reserved_15 :1;/*!< Reserved, bit 15 */ + uint32_t DIAG_EN_KEY :4;/*!< Diagnostic Enable Key, bits 19:16 */ + uint32_t _FDIAGCTRL_Reserved_23_20 :4;/*!< Reserved, bits 23:20 */ + uint32_t DIAG_TRIG :1;/*!< Diagnostic Trigger, bit 24 */ + uint32_t _FDIAGCTRL_Reserved_31_25 :7;/*!< Reserved, bits 31:25 */ + } FDIAGCTRL_BITS; + } FdiagCtrl; + + /*! + Defines whole and bit level accesses to the Uncorrected Raw Data High Register - 0x70 + */ + union FRAW_DATAH + { + uint32_t u32Register; /* Uncorrected Raw Data High, bits 31:0 */ + } FrawDatah; + + /*! + Defines whole and bit level accesses to the Uncorrected Raw Data Low Register - 0x74 + */ + union FRAW_DATAL + { + uint32_t u32Register; /* Uncorrected Raw Data Low, bits 31:0 */ + } FrawDatal; + + /*! + Defines whole and bit level accesses to the Uncorrected Raw ECC Register - 0x78 + */ + union FRAW_ECC + { + uint32_t u32Register; /* Uncorrected Raw ECC, bits 31:0 */ + struct + { + uint32_t RAW_ECC :8; /*!< Uncorrected Raw ECC, bits 7:0 */ + uint32_t _FRAW_ECC_Reserved_31_08 :24;/*!< Reserved, bits 31:8 */ + } FRAW_ECC_BITS; + } FrawEcc; + + /*! + Defines whole and bit level accesses to the Parity Override Register - 0x7C + */ + union FPAR_OVR + { + uint32_t u32Register; /* Parity Override, bits 31:0 */ + struct + { + uint32_t DAT_INV_PAR :8; /*!< Data Odd Parity, bits 7:0 */ + uint32_t ADD_INV_PAR :1; /*!< Address Odd Parity, bit 8 */ + uint32_t PAR_OVR_KEY :3; /*!< Parity Override Key, bits 11:9 */ + uint32_t BUS_PAR_DIS :4; /*!< Disable bus parity, bits 15:12 */ + uint32_t BNK_INV_PAR :1; /*!< Buffer Invert Parity, bit 16 */ + uint32_t _FPAR_OVR_Reserved_31_17 :15;/*!< Reserved, bits 31:17 */ + } FPAR_OVR_BITS; + } FparOvr; + + uint32_t _Reserved_80_BC[16];/* Reserved Address Locations 0x80 - 0xBC */ + + /*! + Defines whole and bit level accesses to the Error Detection Sector Disable2 Register - 0xC0 + */ + union FEDACSDIS2 + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t SectorID2 :4;/*!< Sector ID2 , bits 3:0 */ + uint32_t _FEDACSDIS2_Reserved_4 :1;/*!< Reserved, bit 4 */ + uint32_t BankID2 :3;/*!< Bank ID2 , bits 7:5 */ + uint32_t SectorID2_inverse :4;/*!< Sector ID2 Inverse, bits 11:8 */ + uint32_t _FEDACSDIS2_Reserved_12 :1;/*!< Reserved, bit 12 */ + uint32_t BankID2_inverse :3;/*!< Bank ID2 Inverse, bits 15:13 */ + uint32_t SectorID3 :4;/*!< Sector ID3 , bits 19:16 */ + uint32_t _FEDACSDIS2_Reserved_20 :1;/*!< Reserved, bit 20 */ + uint32_t BankID3 :3;/*!< Bank ID3 , bits 23:21 */ + uint32_t SectorID3_inverse :4;/*!< Sector ID3 Inverse, bits 27:24 */ + uint32_t _FEDACSDIS2_Reserved_28 :1;/*!< Reserved, bit 28 */ + uint32_t BankID3_inverse :3;/*!< Bank ID3 Inverse, bits 31:29 */ + } FEDACSDIS2_BITS; + } FedAcsDis2; + + uint32_t _Reserved_C4_10C[19];/* Reserved Address Locations 0xC4 - 0x10C */ + + /*! + Defines whole and bit level accesses to the Bank Addr Register - 0x110 + */ + union FADDR + { + uint32_t u32Register; /* Bank Addr Register, bits 31:0 */ + } Faddr; + + uint32_t _Reserved_114_118[2]; /* Reserved Address Locations 0x114-0x118 */ + + union FTCTRL + { + uint32_t u32Register; /* Error Detection Sector Disable Register, bits 31:0 */ + struct + { + uint32_t Reserved_00 :1;/*!< Reserved bit, 00 */ + uint32_t Test_EN :1;/*!< Test Enable bit 1 */ + uint32_t Reserved_23_02 :14;/*!< Reserved bits, 23:02 */ + uint32_t WKData_Blk_Clr :1;/*!< Block clearing of FWPWRTITE, bit 16 */ + uint32_t Reserved_23_17 :7;/*!< Reserved bits, 23:17 */ + uint32_t AutoCalc_EN :1;/*!< Auto Calc Enable bit 24 */ + uint32_t Reserved_31_25 :7;/*!< Reserved bits, 31:25 */ + } FTCTRL_BITS; + } Ftctrl; + + + + /*! + Defines whole and bit level accesses to the FWPWRITE0 Register - 0x120 + */ + union FWPWRITE0 + { + uint32_t u32Register; /* FWPWRITE0 Register, bits 31:0 */ + } Fwpwrite0; + + /*! + Defines whole and bit level accesses to the FWPWRITE1 Register - 0x124 + */ + union FWPWRITE1 + { + uint32_t u32Register; /* FWPWRITE1 Register, bits 31:0 */ + } Fwpwrite1; + + /*! + Defines whole and bit level accesses to the FWPWRITE2 Register - 0x128 + */ + union FWPWRITE2 + { + uint32_t u32Register; /* FWPWRITE2 Register, bits 31:0 */ + } Fwpwrite2; + + /*! + Defines whole and bit level accesses to the FWPWRITE3 Register - 0x12C + */ + union FWPWRITE3 + { + uint32_t u32Register; /* FWPWRITE3 Register, bits 31:0 */ + } Fwpwrite3; + + /*! + Defines whole and bit level accesses to the FWPWRITE4 Register - 0x130 + */ + union FWPWRITE4 + { + uint32_t u32Register; /* FWPWRITE4 Register, bits 31:0 */ + } Fwpwrite4; + + /*! + Defines whole and bit level accesses to the FWPWRITE5 Register - 0x134 + */ + union FWPWRITE5 + { + uint32_t u32Register; /* FWPWRITE5 Register, bits 31:0 */ + } Fwpwrite5; + + /*! + Defines whole and bit level accesses to the FWPWRITE6 Register - 0x138 + */ + union FWPWRITE6 + { + uint32_t u32Register; /* FWPWRITE6 Register, bits 31:0 */ + } Fwpwrite6; + + /*! + Defines whole and bit level accesses to the FWPWRITE7 Register - 0x13C + */ + union FWPWRITE7 + { + uint32_t u32Register; /* FWPWRITE7 Register, bits 31:0 */ + } Fwpwrite7; + + /*! + Defines whole and bit level accesses to the FWPWRITE_ECC Register - 0x140 + */ + union FWPWRITE_ECC + { + uint32_t u32Register; /* FWPWRITE_ECC Register, bits 31:0 */ + struct + { + uint32_t WPDATA_287_256; /*!< WPDATA[287:256], bits 31:0 */ + } FWPWRITE_ECC_BITS; + struct + { + uint32_t u8Bytes31_24:8; + uint32_t u8Bytes23_16:8; + uint32_t u8Bytes15_08:8; + uint32_t u8Bytes07_00:8; + } FWPWRITE_ECC_BYTES; + } FwpwriteEcc; + + uint32_t _Reserved_144_208[50]; /* Reserved Address Locations 0x144-0x208 */ + + /*! + Defines whole and bit level accesses to the FSM Command Register - 0x20C + */ + union FSM_COMMAND + { + uint32_t u32Register; /* FSM Command, bits 31:0 */ + struct + { + uint32_t FSMCMD :6; /*!< Flash State Machine Command, bits 5:0 */ + uint32_t _FSM_COMMAND_Reserved_31_06 :26;/*!< Reserved, bits 31:6 */ + } FSM_COMMAND_BITS; + } FsmCommand; + + uint32_t _Reserved_210_284[30]; /* Reserved Address Locations 0x210-0x284 */ + + /*! + Defines whole and bit level accesses to the FSM Register Write Enable- 0x288 + */ + union FSM_WR_ENA + { + uint32_t u32Register; /* FSM Register Write Enable, bits 31:0 */ + struct + { + uint32_t WR_ENA :3; /*!< FSM Write Enable, bits 2:0 */ + uint32_t _FSM_WR_ENA_Reserved_31_03 :29;/*!< Reserved, bits 31:3 */ + } FSM_WR_ENA_BITS; + } FsmWrEna; + + uint32_t _Reserved_28C_2A0[6]; /* Reserved Address Locations 0x28C-0x2A0 */ + + /*! + Defines whole and bit level accesses to the FSM Sector Register - 0x2A4 + */ + union FSM_SECTOR + { + uint32_t u32Register; /* FSM Sector, bits 31:0 */ + struct + { + uint32_t _FSM_SECTOR_Reserved_15_0 :8; /*!< Reserved, bits 15:8 */ + uint32_t SECT_ERASED :16;/*!< Sectors Erased, bits 31:16 */ + } FSM_SECTOR_BITS; + } FsmSector; + + uint32_t _Reserved_2A8_2B0[3]; /* Reserved Address Locations 0x2A8-0x2B0 */ + + /*! + Defines whole and bit level accesses to the FSM Command Execute Register - 0x2B4 + */ + union FSM_EXECUTE + { + uint32_t u32Register; /* FSM Command Execute, bits 31:0 */ + struct + { + uint32_t FSMEXECUTE :5; /*!< FSM Command Execute, bits 4:0 */ + uint32_t _FSM_EXECUTE_Reserved_15_05 :11; /*!< Reserved, bits 15:5 */ + uint32_t SUSPEND_NOW :4; /*!< FSM Command Suspend, bits 19:16 */ + uint32_t _FSM_EXECUTE_Reserved_31_20 :12; /*!< Reserved, bits 31:20 */ + } FSM_EXECUTE_BITS; + } FsmExecute; + + /*! + Defines whole and bit level accesses to the EEPROM Emulation configuration Register - 0x2B8 + */ + union EEPROM_CONFIG + { + uint32_t u32Register; /* EEPROM Emulation configuration, bits 31:0 */ + struct + { + uint32_t AUTOSTART_GRACE :8; /*!< Auto-suspend Startup Grace Period, bits 7:0 */ + uint32_t AUTOSUSP_EN :1; /*!< Auto-suspend Enable, bit 8 */ + uint32_t _EEPROM_CONFIG_Reserved_15_09 :7; /*!< Reserved, bits 15:9 */ + uint32_t EWAIT :4; /*!< EEPROM Wait state Counter, bits 19:16 */ + uint32_t _EEPROM_CONFIG_Reserved_31_20 :12; /*!< Reserved, bits 31:20 */ + } EEPROM_CONFIG_BITS; + } EepromConfig; + + uint32_t _Reserved_2BC; /* Reserved Address Locations 0x2BC */ + + /*! + Defines whole and bit level accesses to the FSM Sector1 Register - 0x2C0 + */ + union FSM_SECTOR_1 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector1; + + /*! + Defines whole and bit level accesses to the FSM Sector2 Register - 0x2C4 + */ + union FSM_SECTOR_2 + { + uint32_t u32Register; /* FSM Sector1, bits 31:0 */ + } FsmSector2; + + uint32_t _Reserved_2C8_304[16];/* Reserved Address Locations 0x2C8 - 0x304 */ + + /*! + Defines whole and bit level accesses to the EEPROM Error Correction Control Register1 - 0x308 + */ + union EE_CTRL1 + { + uint32_t u32Register; /* EEPROM Error Correction Control Register1, bits 31:0 */ + struct + { + uint32_t EE_EDACEN :4;/*!< Error Detection and Correction Enable, bits 3:0 */ + uint32_t EE_ALL0_OK :1;/*!< Zero Condition Valid, bit 4 */ + uint32_t EE_ALL1_OK :1;/*!< One Condition Valid, bit 5 */ + uint32_t _EE_CTRL1_Reserved_07_06 :2;/*!< Reserved, bits 7:6 */ + uint32_t EE_PEN :1;/*!< Error Profiling Enable, bit 8 */ + uint32_t EE_EZFEN :1;/*!< Error on Zero Fail Enable, bit 9 */ + uint32_t EE_EOFEN :1;/*!< Error on One Fail Enable, bit 10 */ + uint32_t _EE_CTRL1_Reserved_15_11 :5;/*!< Reserved, bits 15:11 */ + uint32_t EE_EDACMODE :4;/*!< Error Correction Mode, bits 19:16 */ + uint32_t _EE_CTRL1_Reserved_31_20 :12;/*!< Reserved, bits 31:20 */ + } EE_CTRL1_BITS; + } EeCtrl1; + + /*! + Defines whole and bit level accesses to the EEPROM Error Correction Control Register2 - 0x30C + */ + union EE_CTRL2 + { + uint32_t u32Register; /* EEPROM Error Correction Control Register2, bits 31:0 */ + struct + { + uint32_t EE_SEC_THRESHOLD :16;/*!< EEPROM Single Error Correction Threshold, bits 15:0 */ + uint32_t _EE_CTRL2_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } EE_CTRL2_BITS; + } EeCtrl2; + + /*! + Defines whole and bit level accesses to the EEPROM Error Correction Counter Register - 0x310 + */ + union EE_COR_ERR_CNT + { + uint32_t u32Register; /* EEPROM Error Correction Counter Register, bits 31:0 */ + struct + { + uint32_t EE_ERRCNT :16;/*!< Correctable Error Counter, bits 15:0 */ + uint32_t _EE_COR_ERR_CNT_Reserved_31_16 :16;/*!< Reserved, bits 31:16 */ + } EE_COR_ERR_CNT_BITS; + } EeCorErrCnt; + + /*! + Defines whole and bit level accesses to the EEPROM Correctable Error Address Register - 0x314 + */ + union EE_COR_ERR_ADD + { + uint32_t u32Register; /* Correctable Error Address Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t COR_ERR_ADD :29;/*!< Correctable Error Address, bits 31:3 */ + } EE_COR_ERR_ADD_BITS; + } EeCorErrAdd; + + /*! + Defines whole and bit level accesses to the EEPROM Correctable Error Position Register - 0x318 + */ + union EE_COR_ERR_POS + { + uint32_t u32Register; /* EEPROM Correctable Error Position Register, bits 31:0 */ + struct + { + uint32_t EE_ERR_POS :8; /*!< Single Error Position, bits 7:0 */ + uint32_t TYPE :1; /*!< Error Type, bit 8 */ + uint32_t _EE_COR_ERR_POS_Reserved_31_9 :22;/*!< Reserved, bits 31:9 */ + } EE_COR_ERR_POS_BITS; + } EeCorErrPos; + + /*! + Defines whole and bit level accesses to the EEPROM Error Status Register - 0x31C + */ + union EE_STATUS + { + uint32_t u32Register; /* EEPROM Error Status Register, bits 31:0 */ + struct + { + uint32_t EE_ERR_PRF_FLG :1;/*!< Error Profiling Status Flag, bit 0 */ + uint32_t EE_ERR_ZERO_FLG :1;/*!< Error On Zero Fail Status Flag, bit 1 */ + uint32_t EE_ERR_ONE_FLG :1;/*!< Error On One Fail Status Flag, bit 2 */ + uint32_t EE_D_COR_ERR :1;/*!< Diagnostic Correctable Error Status Flag, bit 3 */ + uint32_t EE_CME :1;/*!< EE ECC Malfunction Status Flag, bit 4 */ + uint32_t _EE_STATUS_Reserved_5 :1;/*!< Reserved, bit 5 */ + uint32_t EE_CMG :1;/*!< EE Compare Malfunction Flag, bit 6 */ + uint32_t _EE_STATUS_Reserved_7 :1;/*!< Reserved, bit 7 */ + uint32_t EE_UNC_ERR :1;/*!< Multiple bit ECC or Parity Error Status Flag, bit 8 */ + uint32_t _EE_STATUS_Reserved_11_9 :3;/*!< Reserved, bits 11:9 */ + uint32_t EE_D_UNC_ERR :1;/*!< Diagnostic Un-correctable Error Status Flag, bit 12 */ + uint32_t _EE_STATUS_Reserved_31_13 :19;/*!< Reserved, bits 31:13 */ + } EE_STATUS_BITS; + } EeStatus; + + /*! + Defines whole and bit level accesses to the Un-correctable Error Address Register - 0x320 + */ + union EE_UNC_ERR_ADD + { + uint32_t u32Register; /* Error Status Register, bits 31:0 */ + struct + { + uint32_t B_OFF :3;/*!< Byte Offset, bits 2:0 */ + uint32_t UNC_ERR_ADD :29;/*!< Un-correctable Error Address, bits 31:3 */ + } EE_UNC_ERR_ADD_BITS; + } EeUncErrAdd; + + uint32_t _Reserved_324_3FC[55];/* Reserved Address Locations 0x324 - 0x3FC */ + + /*! + Defines whole and bit level accesses to the FCFG BANK Register - 0x400 + */ + union FCFG_BANK_1 + { + uint32_t u32Register; /* Flash Bank configuration, bits 31:0 */ + struct + { + uint32_t _FCFG_BANK_Reserved_3_0 :4; /*!< Reserved bits 3:0 */ + uint32_t MAIN_BANK_WIDTH :12;/*!< MAIN_BANK_WIDTH, bits 15:4 */ + uint32_t _FCFG_BANK_Reserved_19_16 :4; /*!< Reserved bits 19:16 */ + uint32_t EE_BANK_WIDTH :12;/*!< EE_BANK_WIDTH, bits 31:20 */ + } FCFG_BANK_BITS; + } FcfgBank; + +} Fapi_FmcRegistersType; +#endif + +#endif /* REGISTERS_LE_H_ */ + +/********************************************************************************************************************** + * END OF FILE: Registers_FMC_LE.h + *********************************************************************************************************************/ Index: FlashDriver/Types.h =================================================================== diff -u --- FlashDriver/Types.h (revision 0) +++ FlashDriver/Types.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,569 @@ +/********************************************************************************************************************** + * COPYRIGHT + * ------------------------------------------------------------------------------------------------------------------- + * \verbatim + * + * � Copyright 2009-2012 Texas Instruments Incorporated. All rights reserved. + * + * \endverbatim + * ------------------------------------------------------------------------------------------------------------------- + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * + * Project: Hercules� ARM� Safety MCUs - F021 Flash API + * Version: v2.01.01 Build(000830) + * Build Date: 2014-10-21 + * + * File: Types.h + * + * Description: Types used by the F021 API. + *--------------------------------------------------------------------------------------------------------------------- + * Author: John R Hall + *--------------------------------------------------------------------------------------------------------------------- + * + *********************************************************************************************************************/ + + +#ifndef TYPES_H_ +#define TYPES_H_ + +/********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ +/*LDRA_NOANALYSIS*/ +#include +#include +/*LDRA_ANALYSIS*/ + +#if defined(__TI_COMPILER_VERSION__) /* TI CCS Compiler */ +#include "CGT.CCS.h" +#elif defined(__ICCARM__) /* IAR EWARM Compiler */ +#include "CGT.IAR.h" +#elif defined(__ghs__) /* GreenHills Compiler */ +#include "CGT.GHS.h" +#elif defined(__ARMCC_VERSION) /* ARM Compiler */ +#include "CGT.ARM.h" +#elif defined(__GNUC__) /* gcc Compiler */ +#include "CGT.gcc.h" +#else +#error "A valid code generation compiler type was not determined!" +#endif + +#if !defined(_LITTLE_ENDIAN) && !defined(_BIG_ENDIAN) +#error "Target Endianess is not defined" +#endif + + +/*****************************************************************************/ +/* GLOBAL DEFINITIONS */ +/*****************************************************************************/ +#if !defined(HIGH_BYTE_FIRST) +#define HIGH_BYTE_FIRST 0U +#endif + +#if !defined(LOW_BYTE_FIRST) +#define LOW_BYTE_FIRST 1U +#endif + +#if !defined(CPU_BYTE_ORDER) +#if defined(_LITTLE_ENDIAN) + #define CPU_BYTE_ORDER (LOW_BYTE_FIRST) +#else + #define CPU_BYTE_ORDER (HIGH_BYTE_FIRST) +#endif +#endif + +#if !defined(false) +#define false 0U +#endif +#if !defined(true) +#define true 1U +#endif + +/*****************************************************************************/ +/* TYPE DEFINITIONS */ +/*****************************************************************************/ +typedef unsigned char boolean_t; + +/*! + \brief This is used to indicate which Cpu is being used. +*/ +typedef enum +{ + Fapi_MasterCpu, + Fapi_SlaveCpu0 +} ATTRIBUTE_PACKED Fapi_CpuSelectorType; + +/*! + \brief This is used to indicate what type of Cpu is being used. +*/ +typedef enum +{ + ARM7 = 0U, /* ARM7 core, Legacy placeholder */ + M3 = 1U, /* ARM Cortex M3 core */ + R4 = 2U, /* ARM Cortex R4 core without ECC logic */ + R4F = 3U, /* ARM Cortex R4, R4F, and R5 cores with ECC logic*/ + C28 = 4U, /* TI C28x core */ + Undefined1 = 5U, /* To Be Determined. Future core placeholder */ + Undefined2 = 6U, /* To Be Determined. Future core placeholder */ + Undefined3 = 7U /* To Be Determined. Future core placeholder */ +} ATTRIBUTE_PACKED Fapi_CpuType; + +/*! + \brief This is used to indicate what type of Family is being used. +*/ +typedef enum +{ + Family_FMC = 0x00, + Family_L2FMC = 0x10, + Family_Sonata = 0x20, + Family_Stellaris = 0x30, + Family_Future = 0x40 +} ATTRIBUTE_PACKED Fapi_FamilyType; + +/*! + \brief This is used to indicate what type of Address is being used. +*/ +typedef enum +{ + Fapi_Flash, + Fapi_FlashEcc, + Fapi_Otp, + Fapi_OtpEcc, + Fapi_Undefined +} ATTRIBUTE_PACKED Fapi_AddressMemoryType; + +/*! + \brief This is used to return the information from the engineering row in the TI OTP. +*/ +typedef struct +{ + uint32_t u32AsicId; + uint8_t u8Revision; + uint32_t u32LotNumber; + uint16_t u16FlowCheck; + uint16_t u16WaferNumber; + uint16_t u16XCoordinate; + uint16_t u16YCoordinate; +} ATTRIBUTE_PACKED Fapi_EngineeringRowType; + +typedef struct +{ + uint32_t au32StatusWord[4]; +} ATTRIBUTE_PACKED Fapi_FlashStatusWordType; + +/*! + \brief This contains all the possible modes used in the Fapi_IssueAsyncProgrammingCommand(). +*/ +typedef enum +{ + Fapi_AutoEccGeneration, /* This is the default mode for the command and will auto generate the ECC for the + provided data buffer */ + Fapi_DataOnly, /* Command will only process the data buffer */ + Fapi_EccOnly, /* Command will only process the ecc buffer */ + Fapi_DataAndEcc /* Command will process data and ecc buffers */ +} ATTRIBUTE_PACKED Fapi_FlashProgrammingCommandsType; + +/*! + \brief This is used to indicate which Flash bank is being used. +*/ +typedef enum +{ + Fapi_FlashBank0=0, + Fapi_FlashBank1=1, + Fapi_FlashBank2=2, + Fapi_FlashBank3=3, + Fapi_FlashBank4=4, + Fapi_FlashBank5=5, + Fapi_FlashBank6=6, + Fapi_FlashBank7=7 +} ATTRIBUTE_PACKED Fapi_FlashBankType; + +/*! + \brief This is used to indicate what F021 Bank Technology the bank is +*/ +typedef enum +{ + Fapi_FLEP=0, + Fapi_FLEE=1, + Fapi_FLES=2, + Fapi_FLHV=3 +} ATTRIBUTE_PACKED Fapi_FlashBankTechType; + +/*! + \brief This is used to indicate which Flash sector is being used. +*/ +typedef enum +{ + Fapi_FlashSector0, + Fapi_FlashSector1, + Fapi_FlashSector2, + Fapi_FlashSector3, + Fapi_FlashSector4, + Fapi_FlashSector5, + Fapi_FlashSector6, + Fapi_FlashSector7, + Fapi_FlashSector8, + Fapi_FlashSector9, + Fapi_FlashSector10, + Fapi_FlashSector11, + Fapi_FlashSector12, + Fapi_FlashSector13, + Fapi_FlashSector14, + Fapi_FlashSector15, + Fapi_FlashSector16, + Fapi_FlashSector17, + Fapi_FlashSector18, + Fapi_FlashSector19, + Fapi_FlashSector20, + Fapi_FlashSector21, + Fapi_FlashSector22, + Fapi_FlashSector23, + Fapi_FlashSector24, + Fapi_FlashSector25, + Fapi_FlashSector26, + Fapi_FlashSector27, + Fapi_FlashSector28, + Fapi_FlashSector29, + Fapi_FlashSector30, + Fapi_FlashSector31, + Fapi_FlashSector32, + Fapi_FlashSector33, + Fapi_FlashSector34, + Fapi_FlashSector35, + Fapi_FlashSector36, + Fapi_FlashSector37, + Fapi_FlashSector38, + Fapi_FlashSector39, + Fapi_FlashSector40, + Fapi_FlashSector41, + Fapi_FlashSector42, + Fapi_FlashSector43, + Fapi_FlashSector44, + Fapi_FlashSector45, + Fapi_FlashSector46, + Fapi_FlashSector47, + Fapi_FlashSector48, + Fapi_FlashSector49, + Fapi_FlashSector50, + Fapi_FlashSector51, + Fapi_FlashSector52, + Fapi_FlashSector53, + Fapi_FlashSector54, + Fapi_FlashSector55, + Fapi_FlashSector56, + Fapi_FlashSector57, + Fapi_FlashSector58, + Fapi_FlashSector59, + Fapi_FlashSector60, + Fapi_FlashSector61, + Fapi_FlashSector62, + Fapi_FlashSector63 +} ATTRIBUTE_PACKED Fapi_FlashSectorType; + +/*! + \brief This contains all the possible Flash State Machine commands. +*/ +typedef enum +{ + Fapi_ProgramData = 0x0002, + Fapi_EraseSector = 0x0006, + Fapi_EraseBank = 0x0008, + Fapi_ValidateSector = 0x000E, + Fapi_ClearStatus = 0x0010, + Fapi_ProgramResume = 0x0014, + Fapi_EraseResume = 0x0016, + Fapi_ClearMore = 0x0018 +} ATTRIBUTE_PACKED Fapi_FlashStateCommandsType; + +/*LDRA_INSPECTED 495 S MR: 6.3 "This does have a size indicated. LDRA is incorrect" */ +typedef uint32_t Fapi_FlashStatusType; + +/*! + \brief This contains all the possible Flash State Machine commands. +*/ +typedef enum +{ + Fapi_NormalRead = 0x0, + Fapi_RM0 = 0x1, + Fapi_RM1 = 0x2 +} ATTRIBUTE_PACKED Fapi_FlashReadMarginModeType; + +/*! + \brief This is the master type containing all possible returned status codes. +*/ +typedef enum +{ + Fapi_Status_Success=0, /* Function completed successfully */ + Fapi_Status_FsmBusy, /* FSM is Busy */ + Fapi_Status_FsmReady, /* FSM is Ready */ + Fapi_Error_Fail, /* Generic Function Fail code */ + Fapi_Error_NullPointer, /* One of the pointer parameters is a null pointer */ + Fapi_Error_InvalidCommand, /* Command used is invalid for the function called */ + Fapi_Error_InvalidEccAddress, /* Returned if the ECC Address given to a function is invalid for that function */ + Fapi_Error_OtpChecksumMismatch, /* Returned if OTP checksum does not match expected value */ + Fapi_Error_InvalidHclkValue, /* Returned if FClk is above max FClk value - FClk is a calculated from HClk and + RWAIT/EWAIT */ + Fapi_Error_InvalidBank, /* Returned if the specified bank does not exist */ + Fapi_Error_InvalidAddress, /* Returned if the specified Address does not exist in Flash or OTP */ + Fapi_Error_InvalidReadMode, /* Returned if the specified read mode does not exist */ + Fapi_Error_AsyncIncorrectDataBufferLength, /* Returned if Data buffer size specified exceeds Data bank width */ + Fapi_Error_AsyncIncorrectEccBufferLength, /* Returned if ECC buffer size specified exceeds ECC bank width */ + Fapi_Error_AsyncDataEccBufferLengthMismatch, /* Returned if Data buffer size either is not 64bit aligned or Data + length exceeds amount ECC supplied */ + Fapi_Error_FeatureNotAvailable /* FMC feature is not available on this device */ +} ATTRIBUTE_PACKED Fapi_StatusType; + +/*LDRA_NOANALYSIS*/ +/*LDRA_INSPECTED 42 S MR: 3.5 "Necessary for FMC register definitions" */ +/*LDRA_INSPECTED 74 S MR: 18.4 "Necessary for FMC register definitions" */ +#if defined(_LITTLE_ENDIAN) +typedef union +{ + volatile struct + { +#if defined (_C28X) + uint16_t ChecksumLength:16; /* 0x150 bits 15:0 */ + uint16_t OtpVersion:16; /* 0x150 bits 31:16 */ + uint32_t OtpChecksum; /* 0x154 bits 31:0 */ + uint16_t NumberOfBanks:16; /* 0x158 bits 15:0 */ + uint16_t NumberOfSectors:16; /* 0x158 bits 31:16 */ + uint16_t MemorySize:16; /* 0x15C bits 15:0 */ + uint16_t Package:16; /* 0x15C bits 31:16 */ + uint16_t SiliconRevision:8; /* 0x160 bits 7:0 */ + uint16_t AsicNumber_23_8:8; /* 0x160 bits 31:8 */ + uint16_t AsicNumber_31_24:16; /* 0x160 bits 31:8 */ + uint32_t LotNumber; /* 0x164 bits 31:0 */ + uint16_t WaferNumber:16; /* 0x168 bits 15:0 */ + uint16_t Flowbits:16; /* 0x168 bits 31:16 */ + uint16_t YCoordinate:16; /* 0x16C bits 15:0 */ + uint16_t XCoordinate:16; /* 0x16C bits 31:16 */ + uint16_t EVSU:8; /* 0x170 bits 7:0 */ + uint16_t PVSU:8; /* 0x170 bits 15:8 */ + uint16_t ESU:8; /* 0x170 bits 23:16 */ + uint16_t PSU:8; /* 0x170 bits 31:24 */ + uint16_t CVSU:12; /* 0x174 bits 11:0 */ + uint16_t Add_EXEZSU:4; /* 0x174 bits 15:12 */ + uint16_t PVAcc:8; /* 0x174 bits 23:16 */ + uint16_t RVSU:8; /* 0x174 bits 31:24 */ + uint16_t PVH2:8; /* 0x178 bits 7:0 */ + uint16_t PVH:8; /* 0x178 bits 15:8 */ + uint16_t RH:8; /* 0x178 bits 23:16 */ + uint16_t PH:8; /* 0x178 bits 31:24 */ + uint16_t SmFrequency:12; /* 0x17C bits 11:0 */ + uint16_t VSTAT:4; /* 0x17C bits 15:12 */ + uint16_t Sequence:8; /* 0x17C bits 23:16 */ + uint16_t EH:8; /* 0x17C bits 31:24 */ + uint16_t VHV_EStep:16; /* 0x180 bits 15:0 */ + uint16_t VHV_EStart:16; /* 0x180 bits 31:16 */ + uint16_t MAX_PP:16; /* 0x184 bits 15:0 */ + uint16_t OtpReserved1:16; /* 0x184 bits 31:16 */ + uint16_t PROG_PW:16; /* 0x188 bits 15:0 */ + uint16_t MAX_EP:16; /* 0x188 bits 31:16 */ + uint32_t ERA_PW; /* 0x18C bits 31:0 */ + uint16_t VHV_E:16; /* 0x190 bits 15:0 */ + uint16_t VHV_P:16; /* 0x190 bits 31:16 */ + uint16_t VINH:8; /* 0x194 bits 7:0 */ + uint16_t VCG:8; /* 0x194 bits 15:8 */ + uint16_t VHV_PV:16; /* 0x194 bits 31:16 */ + uint16_t OtpReserved2:8; /* 0x198 bits 7:0 */ + uint16_t VRead:8; /* 0x198 bits 15:8 */ + uint16_t VWL_P:8; /* 0x198 bits 23:16 */ + uint16_t VSL_P:8; /* 0x198 bits 31:24 */ + uint32_t ApiChecksum; /* 0x19C bits 15:0 */ + uint32_t OtpReserved3; /* 0x1A0 bits 31:0 */ + uint32_t OtpReserved4; /* 0x1A4 bits 31:0 */ + uint32_t OtpReserved5; /* 0x1A8 bits 31:0 */ + uint32_t OtpReserved6; /* 0x1AC bits 31:0 */ +#else + uint32_t ChecksumLength:16; /* 0x150 bits 15:0 */ + uint32_t OtpVersion:16; /* 0x150 bits 31:16 */ + uint32_t OtpChecksum; /* 0x154 bits 31:0 */ + uint32_t NumberOfBanks:16; /* 0x158 bits 15:0 */ + uint32_t NumberOfSectors:16; /* 0x158 bits 31:16 */ + uint32_t MemorySize:16; /* 0x15C bits 15:0 */ + uint32_t Package:16; /* 0x15C bits 31:16 */ + uint32_t SiliconRevision:8; /* 0x160 bits 7:0 */ + uint32_t AsicNumber:24; /* 0x160 bits 31:8 */ + uint32_t LotNumber; /* 0x164 bits 31:0 */ + uint32_t WaferNumber:16; /* 0x168 bits 15:0 */ + uint32_t Flowbits:16; /* 0x168 bits 31:16 */ + uint32_t YCoordinate:16; /* 0x16C bits 15:0 */ + uint32_t XCoordinate:16; /* 0x16C bits 31:16 */ + uint32_t EVSU:8; /* 0x170 bits 7:0 */ + uint32_t PVSU:8; /* 0x170 bits 15:8 */ + uint32_t ESU:8; /* 0x170 bits 23:16 */ + uint32_t PSU:8; /* 0x170 bits 31:24 */ + uint32_t CVSU:12; /* 0x174 bits 11:0 */ + uint32_t Add_EXEZSU:4; /* 0x174 bits 15:12 */ + uint32_t PVAcc:8; /* 0x174 bits 23:16 */ + uint32_t RVSU:8; /* 0x174 bits 31:24 */ + uint32_t PVH2:8; /* 0x178 bits 7:0 */ + uint32_t PVH:8; /* 0x178 bits 15:8 */ + uint32_t RH:8; /* 0x178 bits 23:16 */ + uint32_t PH:8; /* 0x178 bits 31:24 */ + uint32_t SmFrequency:12; /* 0x17C bits 11:0 */ + uint32_t VSTAT:4; /* 0x17C bits 15:12 */ + uint32_t Sequence:8; /* 0x17C bits 23:16 */ + uint32_t EH:8; /* 0x17C bits 31:24 */ + uint32_t VHV_EStep:16; /* 0x180 bits 15:0 */ + uint32_t VHV_EStart:16; /* 0x180 bits 31:16 */ + uint32_t MAX_PP:16; /* 0x184 bits 15:0 */ + uint32_t OtpReserved1:16; /* 0x184 bits 31:16 */ + uint32_t PROG_PW:16; /* 0x188 bits 15:0 */ + uint32_t MAX_EP:16; /* 0x188 bits 31:16 */ + uint32_t ERA_PW; /* 0x18C bits 31:0 */ + uint32_t VHV_E:16; /* 0x190 bits 15:0 */ + uint32_t VHV_P:16; /* 0x190 bits 31:16 */ + uint32_t VINH:8; /* 0x194 bits 7:0 */ + uint32_t VCG:8; /* 0x194 bits 15:8 */ + uint32_t VHV_PV:16; /* 0x194 bits 31:16 */ + uint32_t OtpReserved2:8; /* 0x198 bits 7:0 */ + uint32_t VRead:8; /* 0x198 bits 15:8 */ + uint32_t VWL_P:8; /* 0x198 bits 23:16 */ + uint32_t VSL_P:8; /* 0x198 bits 31:24 */ + uint32_t ApiChecksum:32; /* 0x19C bits 31:0 */ + uint32_t OtpReserved3:32; /* 0x1A0 bits 31:0 */ + uint32_t OtpReserved4:32; /* 0x1A4 bits 31:0 */ + uint32_t OtpReserved5:32; /* 0x1A8 bits 31:0 */ + uint32_t OtpReserved6:32; /* 0x1AC bits 31:0 */ +#endif + } OTP_VALUE; + volatile uint8_t au8OtpWord[0x60]; + volatile uint16_t au16OtpWord[0x30]; + volatile uint32_t au32OtpWord[0x18]; +}Fapi_TiOtpBytesType; +#else +typedef union +{ + volatile struct + { + uint32_t OtpVersion:16; /* 0x150 bits 31:16 */ + uint32_t ChecksumLength:16; /* 0x150 bits 15:0 */ + uint32_t OtpChecksum; /* 0x154 bits 31:0 */ + uint32_t NumberOfSectors:16; /* 0x158 bits 31:16 */ + uint32_t NumberOfBanks:16; /* 0x158 bits 15:0 */ + uint32_t Package:16; /* 0x15C bits 31:16 */ + uint32_t MemorySize:16; /* 0x15C bits 15:0 */ + uint32_t AsicNumber:24; /* 0x160 bits 31:8 */ + uint32_t SiliconRevision:8; /* 0x160 bits 7:0 */ + uint32_t LotNumber; /* 0x164 bits 31:0 */ + uint32_t Flowbits:16; /* 0x168 bits 31:16 */ + uint32_t WaferNumber:16; /* 0x168 bits 15:0 */ + uint32_t XCoordinate:16; /* 0x16C bits 31:16 */ + uint32_t YCoordinate:16; /* 0x16C bits 15:0 */ + uint32_t PSU:8; /* 0x170 bits 31:24 */ + uint32_t ESU:8; /* 0x170 bits 23:16 */ + uint32_t PVSU:8; /* 0x170 bits 15:8 */ + uint32_t EVSU:8; /* 0x170 bits 7:0 */ + uint32_t RVSU:8; /* 0x174 bits 31:24 */ + uint32_t PVAcc:8; /* 0x174 bits 23:16 */ + uint32_t Add_EXEZSU:4; /* 0x174 bits 15:12 */ + uint32_t CVSU:12; /* 0x174 bits 11:0 */ + uint32_t PH:8; /* 0x178 bits 31:24 */ + uint32_t RH:8; /* 0x178 bits 23:16 */ + uint32_t PVH:8; /* 0x178 bits 15:8 */ + uint32_t PVH2:8; /* 0x178 bits 7:0 */ + uint32_t EH:8; /* 0x17C bits 31:24 */ + uint32_t Sequence:8; /* 0x17C bits 23:16 */ + uint32_t VSTAT:4; /* 0x17C bits 15:12 */ + uint32_t SmFrequency:12; /* 0x17C bits 11:0 */ + uint32_t VHV_EStart:16; /* 0x180 bits 31:16 */ + uint32_t VHV_EStep:16; /* 0x180 bits 15:0 */ + uint32_t OtpReserved1:16; /* 0x184 bits 31:16 */ + uint32_t MAX_PP:16; /* 0x184 bits 15:0 */ + uint32_t MAX_EP:16; /* 0x188 bits 31:16 */ + uint32_t PROG_PW:16; /* 0x188 bits 15:0 */ + uint32_t ERA_PW; /* 0x18C bits 31:0 */ + uint32_t VHV_P:16; /* 0x190 bits 31:16 */ + uint32_t VHV_E:16; /* 0x190 bits 15:0 */ + uint32_t VHV_PV:16; /* 0x194 bits 31:16 */ + uint32_t VCG:8; /* 0x194 bits 15:8 */ + uint32_t VINH:8; /* 0x194 bits 7:0 */ + uint32_t VSL_P:8; /* 0x198 bits 31:24 */ + uint32_t VWL_P:8; /* 0x198 bits 23:16 */ + uint32_t VRead:8; /* 0x198 bits 15:8 */ + uint32_t OtpReserved2:8; /* 0x198 bits 7:0 */ + uint32_t ApiChecksum:32; /* 0x19C bits 31:0 */ + uint32_t OtpReserved3:32; /* 0x1A0 bits 31:0 */ + uint32_t OtpReserved4:32; /* 0x1A4 bits 31:0 */ + uint32_t OtpReserved5:32; /* 0x1A8 bits 31:0 */ + uint32_t OtpReserved6:32; /* 0x1AC bits 31:0 */ + } OTP_VALUE; + volatile uint8_t au8OtpWord[0x60]; + volatile uint16_t au16OtpWord[0x30]; + volatile uint32_t au32OtpWord[0x18]; +}Fapi_TiOtpBytesType; +#endif +/*LDRA_ANALYSIS*/ + +typedef struct TI_OTP_TYPE +{ + Fapi_TiOtpBytesType aOtpBank[8]; +}Fapi_TiOtpType; + +/*! + \brief +*/ +typedef enum +{ + Alpha_Internal, /* For internal TI use only. Not intended to be used by customers */ + Alpha, /* Early Engineering release. May not be functionally complete */ + Beta_Internal, /* For internal TI use only. Not intended to be used by customers */ + Beta, /* Functionally complete, to be used for testing and validation */ + Production /* Fully validated, functionally complete, ready for production use */ +} ATTRIBUTE_PACKED Fapi_ApiProductionStatusType; + +typedef struct +{ + uint8_t u8ApiMajorVersion; + uint8_t u8ApiMinorVersion; + uint8_t u8ApiRevision; + Fapi_ApiProductionStatusType oApiProductionStatus; + uint32_t u32ApiBuildNumber; + uint8_t u8ApiTechnologyType; + uint8_t u8ApiTechnologyRevision; + uint8_t u8ApiEndianness; + uint32_t u32ApiCompilerVersion; +}Fapi_LibraryInfoType; + +typedef struct +{ +#if defined(_LITTLE_ENDIAN) + uint16_t u16NumberOfBanks; + uint16_t u16Reserved; + uint16_t u16DeviceMemorySize; + uint16_t u16DevicePackage; + uint32_t u32AsicId; + uint32_t u32LotNumber; + uint16_t u16WaferNumber; + uint16_t u16FlowCheck; + uint16_t u16WaferYCoordinate; + uint16_t u16WaferXCoordinate; +#else + uint16_t u16Reserved; + uint16_t u16NumberOfBanks; + uint16_t u16DevicePackage; + uint16_t u16DeviceMemorySize; + uint32_t u32AsicId; + uint32_t u32LotNumber; + uint16_t u16FlowCheck; + uint16_t u16WaferNumber; + uint16_t u16WaferXCoordinate; + uint16_t u16WaferYCoordinate; +#endif +}Fapi_DeviceInfoType; + +typedef struct +{ + Fapi_FlashBankTechType oFlashBankTech; + uint32_t u32NumberOfSectors; + uint32_t u32BankStartAddress; + uint16_t au16SectorSizes[16]; +}Fapi_FlashBankSectorsType; + +#endif /* TYPES_H_*/ + +/********************************************************************************************************************** + * END OF FILE: Types.h + *********************************************************************************************************************/ Index: NVDataMgmt.c =================================================================== diff -u --- NVDataMgmt.c (revision 0) +++ NVDataMgmt.c (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,166 @@ +/************************************************************************** + * + * Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file NVDataMgmt.c + * + * @date 11-FEB-2020 + * @author D. Navaei + * + * @brief NVDataMgmt source file + * + **************************************************************************/ + +// Includes + +#include "NVDataMgmt.h" +#include "F021.h" +#include "system.h" + +// Private defines +#define MAX_QUEUE_SIZE 10U +#define ROUNDED_HCLK_FREQ FLOAT_TO_INT_WITH_ROUND(HCLK_FREQ) +#define BANK7_SECTOR_0_31_ENABLE_BIT_MASK 0x0000000F +#define BANK7_SECTOR_32_63_ENABLE_BIT_MASK 0x00000000 + +#define BANK7_SECTOR0_START_ADDRESS 0xF0200000 +#define BANK7_SECTOR0_END_ADDRESS 0xF0203FFF + +#define BANK7_SECTOR1_START_ADDRESS 0xF0204000 +#define BANK7_SECTOR1_END_ADDRESS 0xF0207FFF + +#define BANK7_SECTOR2_START_ADDRESS 0xF0208000 +#define BANK7_SECTOR2_END_ADDRESS 0xF020BFFF + +#define BANK7_SECTOR3_START_ADDRESS 0xF020FFFF +#define BANK7_SECTOR3_END_ADDRESS 0xF020C000 + +typedef enum NVDataMgmt_Self_Test_States +{ + NVDATAMGMT_SELF_TEST_STATE_START = 0, + NVDATAMGMT_SELF_TEST_STATE_READ_MEMORY_DATA, + NVDATAMGMT_SELF_TEST_STATE_CHECK_CRC, + NVDATAMGMT_SELF_TEST_STATE_COMPLETE, + NUM_OF_NVDATAMGMT_SELF_TEST_STATES +} NVDATAMGMT_SELF_TEST_STATE_T; + +typedef enum NVDataMgmt_Exec_State +{ + NVDATAMGMT_EXEC_STATE_WAIT_FOR_POST = 0, + NVDATAMGMT_EXEC_STATE_IDLE, + NVDATAMGMT_EXEC_STATE_WRITE, + NVDATAMGMT_EXEC_STATE_READ, + NVDATAMGMT_EXEC_STATE_FAULT, + NUM_OF_NVDATAMGMT_EXEC_STATES +} NVDATAMGMT_EXEC_STATE_T; + +typedef enum NVDataMgmt_Read_Write +{ + NVDATAMGMT_WRITE = 0, + NVDATAMGMT_READ +} NVDATAMGMT_READ_WRITE_STATE_T; + +typedef enum NVDataMgmt_Location +{ + NVDATAMGMT_EEPROM = 0, + NVDATAMGMT_RTC +} NVDATAMGMT_MEMORY_LOCATION_STATE_T; + +#pragma pack(push,4) +struct memoryOps +{ + NVDATAMGMT_READ_WRITE_STATE_T readWrite; + NVDATAMGMT_MEMORY_LOCATION_STATE_T memoryLocation; + U32 startAddress; + U16* buffer; + U32 length; +}; +#pragma pack(pop) + +// Private functions + +static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestStart( void ); +static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestReadMemoryData( void ); +static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestCheckCRC( void ); + +static NVDATAMGMT_EXEC_STATE_T handleExecWaitForPost( void ); +static NVDATAMGMT_EXEC_STATE_T handleExecIdle( void ); +static NVDATAMGMT_EXEC_STATE_T handleExecWrite( void ); +static NVDATAMGMT_EXEC_STATE_T handleExecRead( void ); + +// Private variables + +struct memoryOps job[ MAX_QUEUE_SIZE ]; +static Fapi_StatusType EEPROMStatus; +static NVDATAMGMT_SELF_TEST_STATE_T NVDataMgmtSelfTestState = NVDATAMGMT_SELF_TEST_STATE_START; +static NVDATAMGMT_EXEC_STATE_T NVDataMgmtExecState = NVDATAMGMT_EXEC_STATE_WAIT_FOR_POST; +static SELF_TEST_STATUS_T NVDataMgmtSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; + + + +/************************************************************************* + * @brief initNVDataMgmt + * The initNVDataMgmt initializes EEPROM + * @details + * Inputs : none + * Outputs : none + * @param none + * @return none + *************************************************************************/ +void initNVDataMgmt( void ) +{ + NVDataMgmtSelfTestState = NVDATAMGMT_SELF_TEST_STATE_START; + + EEPROMStatus = Fapi_initializeFlashBanks( ROUNDED_HCLK_FREQ ); + EEPROMStatus = Fapi_setActiveFlashBank( Fapi_FlashBank7 ); + + EEPROMStatus = Fapi_enableEepromBankSectors( BANK7_SECTOR_0_31_ENABLE_BIT_MASK, BANK7_SECTOR_32_63_ENABLE_BIT_MASK ); +} + +/************************************************************************* + * @brief execNVDataMgmtSelfTest + * The execNVDataMgmtSelfTest runs the NVDataMgmt POST during the self test + * @details + * Inputs : none + * Outputs : SELF_TEST_STATUS_T + * @param none + * @return SELF_TEST_STATUS_T + *************************************************************************/ +SELF_TEST_STATUS_T execNVDataMgmtSelfTest ( void ) +{ + switch( NVDataMgmtSelfTestState ) + { + case NVDATAMGMT_SELF_TEST_STATE_START: + break; + + case NVDATAMGMT_SELF_TEST_STATE_READ_MEMORY_DATA: + break; + + case NVDATAMGMT_SELF_TEST_STATE_CHECK_CRC: + break; + + case NVDATAMGMT_SELF_TEST_STATE_COMPLETE: + break; + + default: + //TODO: Alarm + NVDataMgmtSelfTestResult = SELF_TEST_STATUS_FAILED; + break; + } + + return NVDataMgmtSelfTestResult; +} + +void execNVDataMgmt( void ) +{ + +} + + + + + + Index: NVDataMgmt.h =================================================================== diff -u --- NVDataMgmt.h (revision 0) +++ NVDataMgmt.h (revision e1b34b080d041c571ca4aad8a31104d2773c17df) @@ -0,0 +1,46 @@ +/************************************************************************** + * + * Copyright (c) 2019-2020 Diality Inc. - All Rights Reserved. + * + * THIS CODE MAY NOT BE COPIED OR REPRODUCED IN ANY FORM, IN PART OR IN + * WHOLE, WITHOUT THE EXPLICIT PERMISSION OF THE COPYRIGHT OWNER. + * + * @file NVDataMgmt.h + * + * @date 11-FEB-2020 + * @author D. Navaei + * + * @brief NVDataMgmt header file. + * + **************************************************************************/ + +#ifndef FWCOMMON_NVDATAMGMT_H_ +#define FWCOMMON_NVDATAMGMT_H_ + +#include "Common.h" + +#define SN_BUFFER_LENGTH 10U + +void initNVDataMgmt( void ); + +void execNVDataMgmt( void ); + +SELF_TEST_STATUS_T execNVDataMgmtSelfTest( void ); + +BOOL getSerialNumber( char* buffer ); + +BOOL setSerialNumber( char* buffer ); + +BOOL setMfgData( char* buffer ); + +BOOL getMfgData( char* buffer ); + + + + + + + + + +#endif /* FWCOMMON_NVDATAMGMT_H_ */