Index: NVDataMgmt.c =================================================================== diff -u -r169b3efe1866e53f4d31db0cde00594a7c8ad210 -re1f9404958c9ddab9b004399fb0870e09e37512b --- NVDataMgmt.c (.../NVDataMgmt.c) (revision 169b3efe1866e53f4d31db0cde00594a7c8ad210) +++ NVDataMgmt.c (.../NVDataMgmt.c) (revision e1f9404958c9ddab9b004399fb0870e09e37512b) @@ -22,192 +22,215 @@ #include "NVDataMgmt.h" #include "RTC.h" #include "system.h" -#include "Utilities.h" #include "Timers.h" +#include "Utilities.h" // Private defines -#define QUEUE_MAX_SIZE 20U -#define QUEUE_START_INDEX 0U -#define MIN_QUEUE_COUNT_FOR_DATA_LOG 3U -#define MIN_QUEUE_COUNT_FOR_SECTOR_0 4U +#define QUEUE_MAX_SIZE 20U ///< Max queue size +#define QUEUE_START_INDEX 0U ///< Queue start index +#define MIN_QUEUE_COUNT_FOR_DATA_LOG 3U ///< Min queue required for data log (3) +#define MIN_QUEUE_COUNT_FOR_SECTOR_0 4U ///< Min queue count needed to write all (4) records back in sector 0 // The clock frequency comes from HCLK_FREQ and it has to be rounded up to the // nearest number -#define ROUNDED_HCLK_FREQ FLOAT_TO_INT_WITH_ROUND(HCLK_FREQ) -#define BANK7_SECTOR_0_31_ENABLE_BIT_MASK 0x0000000F -#define BANK7_SECTOR_32_63_ENABLE_BIT_MASK 0x00000000 +#define ROUNDED_HCLK_FREQ FLOAT_TO_INT_WITH_ROUND(HCLK_FREQ) ///< Rounded HCLK for EERPOM clock +#define BANK7_SECTOR_0_31_ENABLE_BIT_MASK 0x0000000F ///< Bank7 sector 0 t0 31 enable mask +#define BANK7_SECTOR_32_63_ENABLE_BIT_MASK 0x00000000 ///< Bank7 sector 32 to 63 enable mask -#define BANK7_SECTOR0_START_ADDRESS 0xF0200000 -#define BANK7_SECTOR0_END_ADDRESS 0xF0203FFF +#define BANK7_SECTOR0_START_ADDRESS 0xF0200000 ///< Bank7 sector 0 start address +#define BANK7_SECTOR0_END_ADDRESS 0xF0203FFF ///< Bank7 sector 0 end address -#define BANK7_SECTOR1_START_ADDRESS 0xF0204000 -#define BANK7_SECTOR1_END_ADDRESS 0xF0207FFF +#define BANK7_SECTOR1_START_ADDRESS 0xF0204000 ///< Bank7 sector 1 start address +#define BANK7_SECTOR1_END_ADDRESS 0xF0207FFF ///< Bank7 sector 1 end address -#define BANK7_SECTOR2_START_ADDRESS 0xF0208000 -#define BANK7_SECTOR2_END_ADDRESS 0xF020BFFF +#define BANK7_SECTOR2_START_ADDRESS 0xF0208000 ///< Bank7 sector 2 start address +#define BANK7_SECTOR2_END_ADDRESS 0xF020BFFF ///< Bank7 sector 2 end address -#define BANK7_SECTOR3_START_ADDRESS 0xF020C000 -#define BANK7_SECTOR3_END_ADDRESS 0xF020FFFF +#define BANK7_SECTOR3_START_ADDRESS 0xF020C000 ///< Bank7 sector 3 start address +#define BANK7_SECTOR3_END_ADDRESS 0xF020FFFF ///< Bank7 sector 3 end address -#define MAX_EEPROM_WRITE_BUFFER_BYTES 16U //Assert -#define MAX_JOB_DATA_SIZE_BYTES 32U -#define LOG_DATA_START_INDEX 0U -#define MAX_NUM_OF_SECTORS_FOR_LOG_DATA 3U +#define MAX_EEPROM_WRITE_BUFFER_BYTES 16U ///< Max allowed bytes for an EEPROM write (16 bytes) + +#define MAX_JOB_DATA_SIZE_BYTES 32U ///< Max bytes per job (32 bytes) +#define LOG_DATA_START_INDEX 0U ///< Log data start index +#define MAX_NUM_OF_SECTORS_FOR_LOG_DATA 3U ///< Max number of sector (3 sectors) #define MAX_LOG_DATA_PER_SECTOR (((BANK7_SECTOR1_END_ADDRESS + 1) - \ - BANK7_SECTOR1_START_ADDRESS) / MAX_JOB_DATA_SIZE_BYTES) -#define MAX_NUM_OF_DATA_LOGS_IN_SECTOR3 (MAX_NUM_OF_SECTORS_FOR_LOG_DATA * MAX_LOG_DATA_PER_SECTOR) -#define MAX_NUM_OF_DATA_LOGS_IN_SECTOR2 ((MAX_NUM_OF_SECTORS_FOR_LOG_DATA - 1) * MAX_LOG_DATA_PER_SECTOR) -#define MAX_NUM_OF_DATA_LOGS_IN_SECTOR1 ((MAX_NUM_OF_SECTORS_FOR_LOG_DATA - 2) * MAX_LOG_DATA_PER_SECTOR) + BANK7_SECTOR1_START_ADDRESS) / MAX_JOB_DATA_SIZE_BYTES) ///< Max log data per sector (512 for now) +#define MAX_NUM_OF_DATA_LOGS_IN_SECTOR3 (MAX_NUM_OF_SECTORS_FOR_LOG_DATA * MAX_LOG_DATA_PER_SECTOR) ///< Max number of accumulated logs in sector 3 (1536) +#define MAX_NUM_OF_DATA_LOGS_IN_SECTOR2 ((MAX_NUM_OF_SECTORS_FOR_LOG_DATA - 1) * MAX_LOG_DATA_PER_SECTOR) ///< Max number of accumulated logs in sector 2 (1024) +#define MAX_NUM_OF_DATA_LOGS_IN_SECTOR1 ((MAX_NUM_OF_SECTORS_FOR_LOG_DATA - 2) * MAX_LOG_DATA_PER_SECTOR) ///< Max number of accumulated logs in sector 1 (512) // Data addresses and length in RTC RAM -#define BOOTLOADER_FLAG_ADDRESS 0x00000000 -#define BOOTLOADER_FLAG_LENGTH_BYTES 4U -#define LOG_RECORD_START_ADDRESS 0x00000010 // 16 -#define MFG_RECORD_START_ADDRESS 0X00000020 // 32 -#define HD_TREATMENT_TIME_ADDRESS 0X00000030 // 48 -#define DG_CONSUMED_WATER_ADDRESS 0X00000040 // 64 -#define SERVICE_DATE_START_ADDRESS 0X00000050 // 80 +#define BOOTLOADER_FLAG_ADDRESS 0x00000000 ///< Bootloader start address in RTC RAM (0) +#define BOOTLOADER_FLAG_LENGTH_BYTES 4U ///< Bootloader number of bytes (4 bytes) +#define LOG_RECORD_START_ADDRESS 0x00000010 // 16 ///< Log record start address in RTC RAM (16) +#define MFG_RECORD_START_ADDRESS 0X00000020 // 32 ///< Log record start address in RTC RAM (32) +#define HD_TREATMENT_TIME_ADDRESS 0X00000030 // 48 ///< HD treatment time start address in RTC RAM (48) +#define DG_CONSUMED_WATER_ADDRESS 0X00000040 // 64 ///< DG water consumption start address in RTC RAM (64) +#define SERVICE_DATE_START_ADDRESS 0X00000050 // 80 ///< Service date record start address in RTC RAM (80) +#define LAST_DISINFECTION_DATE_ADDRESS 0x00000060 // 96 ///< Last disinfection date start address in RTC RAM (96) // Data addresses in EEPROM -#define CALIBRATION_RECORD_START_ADDRESS (BANK7_SECTOR0_START_ADDRESS + 0x100) +#define CALIBRATION_RECORD_START_ADDRESS (BANK7_SECTOR0_START_ADDRESS + 0x100) ///< Calibration record start address in EEPROM -#define COMMAND_TIME_OUT 500U // time in ms +#define COMMAND_TIME_OUT 500U // time in ms ///< Timeout for an EEPROM or RTC command in ms +/// NVDataMgmt self test states typedef enum NVDataMgmt_Self_Test_States { - NVDATAMGMT_SELF_TEST_STATE_START = 0, - NVDATAMGMT_SELF_TEST_STATE_ENABLE_EEPROM, - NVDATAMGMT_SELF_TEST_STATE_READ_BOOTLOADER_FLAG, - NVDATAMGMT_SELF_TEST_STATE_READ_LOG_RECORD, - NVDATAMGMT_SELF_TEST_STATE_READ_TREATMENT_TIME, - NVDATAMGMT_SELF_TEST_STATE_READ_WATER_CONSUMPTION, - NVDATAMGMT_SELF_TEST_STATE_READ_MFG_RECORD, - NVDATAMGMT_SELF_TEST_STATE_READ_CAL_RECORD, - NVDATAMGMT_SELF_TEST_STATE_READ_SERVICE_RECORD, - NVDATAMGMT_SELF_TEST_STATE_CHECK_CRC, - NVDATAMGMT_SELF_TEST_STATE_COMPLETE, - NUM_OF_NVDATAMGMT_SELF_TEST_STATES + NVDATAMGMT_SELF_TEST_STATE_START = 0, ///< Self test start + NVDATAMGMT_SELF_TEST_STATE_ENABLE_EEPROM, ///< Self test enable EERPOM + NVDATAMGMT_SELF_TEST_STATE_READ_BOOTLOADER_FLAG, ///< Self test read bootloader + NVDATAMGMT_SELF_TEST_STATE_READ_LOG_RECORD, ///< Self test read log record + NVDATAMGMT_SELF_TEST_STATE_READ_TREATMENT_TIME, ///< Self test read treatment time + NVDATAMGMT_SELF_TEST_STATE_READ_WATER_CONSUMPTION, ///< Self test read water consumption + NVDATAMGMT_SELF_TEST_STATE_READ_MFG_RECORD, ///< Self test read manufacturing record + NVDATAMGMT_SELF_TEST_STATE_READ_CAL_RECORD, ///< Self test read calibration record + NVDATAMGMT_SELF_TEST_STATE_READ_SERVICE_RECORD, ///< Self test read service record + NVDATAMGMT_SELF_TEST_STATE_READ_LAST_DISINFECTION_DATE, ///< Self test read last disinfection date + NVDATAMGMT_SELF_TEST_STATE_CHECK_CRC, ///< Self test check CRC + NVDATAMGMT_SELF_TEST_STATE_COMPLETE, ///< Self test complete + NUM_OF_NVDATAMGMT_SELF_TEST_STATES ///< Total number of self test states } NVDATAMGMT_SELF_TEST_STATE_T; +/// NVDataMgmt Exec states typedef enum NVDataMgmt_Exec_State { - NVDATAMGMT_EXEC_STATE_WAIT_FOR_POST = 0, - NVDATAMGMT_EXEC_STATE_IDLE, - NVDATAMGMT_EXEC_STATE_WRITE_TO_EEPROM, - NVDATAMGMT_EXEC_STATE_READ_FROM_EEPROM, - NVDATAMGMT_EXEC_STATE_ERASE_EEPROM, - NVDATAMGMT_EXEC_STATE_WRITE_TO_RTC, - NVDATAMGMT_EXEC_STATE_READ_FROM_RTC, - NVDATAMGMT_EXEC_STATE_FAULT, - NUM_OF_NVDATAMGMT_EXEC_STATES + NVDATAMGMT_EXEC_STATE_WAIT_FOR_POST = 0, ///< Exec state wait for POST + NVDATAMGMT_EXEC_STATE_IDLE, ///< Exec state Idle + NVDATAMGMT_EXEC_STATE_WRITE_TO_EEPROM, ///< Exec state write to EEPROM + NVDATAMGMT_EXEC_STATE_READ_FROM_EEPROM, ///< Exec state read from EEPROM + NVDATAMGMT_EXEC_STATE_ERASE_EEPROM, ///< Exec state erase EEPROM + NVDATAMGMT_EXEC_STATE_WRITE_TO_RTC, ///< Exec state write to RTC + NVDATAMGMT_EXEC_STATE_READ_FROM_RTC, ///< Exec state read from RTC + NVDATAMGMT_EXEC_STATE_FAULT, ///< Exec state fault + NUM_OF_NVDATAMGMT_EXEC_STATES ///< Total number of exec states } NVDATAMGMT_EXEC_STATE_T; +/// NVDataMgmt memory operation modes typedef enum NVDataMgmt_Operation { - NVDATAMGMT_NONE = 0, - NVDATAMGMT_WRITE, - NVDATAMGMT_READ, - NVDATAMGMT_ERASE_SECTOR, - NUM_OF_NVDATAMGMT_OPS_STATES + NVDATAMGMT_NONE = 0, ///< Operations mode none + NVDATAMGMT_WRITE, ///< Operation mode write + NVDATAMGMT_READ, ///< Operation mode read + NVDATAMGMT_ERASE_SECTOR, ///< Operation mode erase a sector (EEPROM) + NUM_OF_NVDATAMGMT_OPS_STATES ///< Total number of operation states } NVDATAMGMT_OPERATION_STATE_T; +/// NVDataMgmt memory locations typedef enum NVDataMgmt_Location { - NVDATAMGMT_EEPROM = 0, - NVDATAMGMT_RTC, - NUM_OF_NVDATAMGMT_LOC_STATES + NVDATAMGMT_EEPROM = 0, ///< Location EEPROM + NVDATAMGMT_RTC, ///< Location RTC (RAM) + NUM_OF_NVDATAMGMT_LOC_STATES ///< Total number of location states } NVDATAMGMT_LOCATION_STATE_T; #pragma pack(push, 1) +/// Memory operations struct typedef struct { - NVDATAMGMT_OPERATION_STATE_T memoryOperation; - NVDATAMGMT_LOCATION_STATE_T memoryLocation; - U32* startAddress; - U08 buffer [ MAX_JOB_DATA_SIZE_BYTES ]; - READ_DATA_T* externalAddress; - U32 length; + NVDATAMGMT_OPERATION_STATE_T memoryOperation; ///< Memory operation + NVDATAMGMT_LOCATION_STATE_T memoryLocation; ///< Memory location + U32* startAddress; ///< Operation start address + U08 buffer [ MAX_JOB_DATA_SIZE_BYTES ]; ///< Buffer + READ_DATA_T* externalAddress; ///< External address of a buffer + U32 length; ///< Length of a buffer } MEMORY_OPS_T; +/// Log header struct typedef struct { - U16 recordCount; - U16 nextWriteIndex; - U16 nextReadIndex; + U16 recordCount; ///< Record count + U16 nextWriteIndex; ///< Next write index + U16 nextReadIndex; ///< Next read index + BOOL isHdrCorrupted; ///< Log header corruption flag } LOG_HEADER_T; +/// Log record struct typedef struct { - LOG_HEADER_T logHeader; - U16 crc; + LOG_HEADER_T logHeader; ///< Log header struct + U16 crc; ///< Log header CRC } LOG_RECORD_T; +/// Treatment time struct typedef struct { - U32 treatmentTime; - U16 crc; + U32 treatmentTime; ///< Treatment time + U16 crc; ///< Treatment time CRC } TREATMENT_TIME_RECORD_T; +/// Water consumption struct typedef struct { - U32 waterConsumption; - U16 crc; + U32 waterConsumption; ///< Water consumption + U16 crc; ///< Water consumption CRC } WATER_CONSUMPTION_RECORD_T; +/// Manufacturing data struct typedef struct { - MFG_DATA_T mfgData; - U16 crc; + MFG_DATA_T mfgData; ///< Manufacturing data struct + U16 crc; ///< Manufacturing data CRC } MFG_RECORD_T; +/// Service record struct typedef struct { - SERVICE_DATA_T serviceData; - U16 crc; - + SERVICE_DATA_T serviceData; ///< Service date struct + U16 crc; ///< Service data CRC } SERVICE_RECORD_T; +/// Calibration record struct typedef struct { - CALIBRATION_DATA_T calData; - U16 crc; + CALIBRATION_DATA_T calData; ///< Calibration data struct + U16 crc; ///< Calibration data CRC } CALIBRATION_RECORD_T; +/// last disinfection record struct typedef struct { - U32 epochTime; - U32 eventCode; - U32 subCode; - F32 data1; - F32 data2; - F32 data3; - F32 data4; - F32 data5; + char disinfectionDate [ MAX_DATE_CHARACTERS ]; ///< Disinfection date (char array) + U16 crc; ///< Disinfection date CRC +} LAST_DISINFECTION_RECORD_T; + +/// Log data struct +typedef struct +{ + U32 epochTime; ///< Log data time in epoch + U32 eventCode; ///< Log data event code + U32 subCode; ///< Log data sub code + F32 data1; ///< Log data 1 + F32 data2; ///< Log data 2 + F32 data3; ///< Log data 3 + F32 data4; ///< Log data 4 + F32 data5; ///< Log data 5 } LOG_DATA_T; #pragma pack(pop) // Private variables -static MEMORY_OPS_T jobQueue [ QUEUE_MAX_SIZE ]; -static MEMORY_OPS_T currentJob; -static LOG_RECORD_T logRecord; -static TREATMENT_TIME_RECORD_T treatmentTimeRecord; -static WATER_CONSUMPTION_RECORD_T waterConsumptionRecord; -static LOG_DATA_T logData; -static MFG_RECORD_T mfgRecord; -static CALIBRATION_RECORD_T calibrationRecord; -static SERVICE_RECORD_T serviceRecord; -static U08 queueRearIndex = QUEUE_START_INDEX; -static U08 queueFrontIndex = QUEUE_START_INDEX; -static U08 queueCount = 0; -static NVDATAMGMT_SELF_TEST_STATE_T NVDataMgmtSelfTestState = NVDATAMGMT_SELF_TEST_STATE_START; -static NVDATAMGMT_EXEC_STATE_T NVDataMgmtExecState = NVDATAMGMT_EXEC_STATE_WAIT_FOR_POST; -static SELF_TEST_STATUS_T NVDataMgmtSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; -static U32 bootloaderFlag = 0; -static BOOL hasLogRecordCRCFailed = FALSE; -static BOOL hasCommandTimedout = FALSE; -static U32 currentTime = 0; +static MEMORY_OPS_T jobQueue [ QUEUE_MAX_SIZE ]; ///< Job queue buffer +static MEMORY_OPS_T currentJob; ///< Current job +static LOG_RECORD_T logRecord; ///< Log record variable +static TREATMENT_TIME_RECORD_T treatmentTimeRecord; ///< Treatment time record +static WATER_CONSUMPTION_RECORD_T waterConsumptionRecord; ///< Water consumption record +static LOG_DATA_T logData; ///< Log data record +static MFG_RECORD_T mfgRecord; ///< Manufacturing record +static CALIBRATION_RECORD_T calibrationRecord; ///< Calibration record +static SERVICE_RECORD_T serviceRecord; ///< Service record +static LAST_DISINFECTION_RECORD_T lastDisinfectionRecord; ///< Disinfection record +static U08 queueRearIndex = QUEUE_START_INDEX; ///< Queue rear index +static U08 queueFrontIndex = QUEUE_START_INDEX; ///< Queue front index +static U08 queueCount = 0; ///< Queue count +static NVDATAMGMT_SELF_TEST_STATE_T NVDataMgmtSelfTestState = NVDATAMGMT_SELF_TEST_STATE_START; ///< NVDataMgmt self test state variable +static NVDATAMGMT_EXEC_STATE_T NVDataMgmtExecState = NVDATAMGMT_EXEC_STATE_WAIT_FOR_POST; ///< NVDataMgmt exec state variable +static SELF_TEST_STATUS_T NVDataMgmtSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; ///< NVDataMgmt self test result +static U32 bootloaderFlag = 0; ///< Bootloader flag +static BOOL hasCommandTimedout = FALSE; ///< Boolean flag for timeout of the commands +static U32 currentTime = 0; ///< Current time // Private functions @@ -220,6 +243,7 @@ static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestReadMfgRecord ( void ); static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestReadCalibrationRecord ( void ); static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestReadServiceRecord ( void ); +static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestReadLastDisinfectionDate ( void ); static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestCheckCRC ( void ); static NVDATAMGMT_EXEC_STATE_T handleExecWaitForPostState ( void ); @@ -270,7 +294,6 @@ NVDataMgmtSelfTestState = NVDATAMGMT_SELF_TEST_STATE_START; NVDataMgmtExecState = NVDATAMGMT_EXEC_STATE_WAIT_FOR_POST; NVDataMgmtSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; - hasLogRecordCRCFailed = FALSE; queueRearIndex = QUEUE_START_INDEX; queueFrontIndex = QUEUE_START_INDEX; Fapi_initializeFlashBanks( ROUNDED_HCLK_FREQ ); @@ -405,7 +428,8 @@ { BOOL status = FALSE; - if ( !isQueueFull() ) + // If the header is corrupted, no more data is allowed to be written + if ( !isQueueFull() ) //&& logRecord.logHeader.isHdrCorrupted == FALSE ) { enqueue ( NVDATAMGMT_WRITE, NVDATAMGMT_EEPROM, 0, data, 0, length ); status = TRUE; @@ -505,6 +529,48 @@ } /************************************************************************* + * @brief setDisinfectionDate + * The setDisinfectionDate gets the last disinfection date, calculates the + * CRC for it and if the queue is not full, it schedules a write to RTC RAM + * to store the last date + * @details + * Inputs : U08* (buffer) + * Outputs : none + * @param none + * @return none + *************************************************************************/ +BOOL setDisinfectionDate ( char date [ MAX_DATE_CHARACTERS ] ) +{ + BOOL status = FALSE; + memcpy ( lastDisinfectionRecord.disinfectionDate, date, MAX_DATE_CHARACTERS ); + lastDisinfectionRecord.crc = crc16 ( (U08*)&lastDisinfectionRecord.disinfectionDate, sizeof(MAX_DATE_CHARACTERS) ); + + if ( !isQueueFull() ) + { + enqueue( NVDATAMGMT_WRITE, NVDATAMGMT_RTC, LAST_DISINFECTION_DATE_ADDRESS, + (U08*)&lastDisinfectionRecord, 0, sizeof(LAST_DISINFECTION_RECORD_T) ); + status = TRUE; + } + + return status; +} + +/************************************************************************* + * @brief getDisinfectionDate + * The getDisinfectionDate populates the provided buffer with the last + * disinfection date + * @details + * Inputs : U08* (buffer) + * Outputs : none + * @param none + * @return none + *************************************************************************/ +void getDisinfectionDate ( U08* buffer ) +{ + memcpy ( buffer, lastDisinfectionRecord.disinfectionDate, MAX_DATE_CHARACTERS ); +} + +/************************************************************************* * @brief execNVDataMgmtSelfTest * The execNVDataMgmtSelfTest runs the NVDataMgmt POST during the self test * @details @@ -562,19 +628,26 @@ NVDataMgmtSelfTestState = handleSelfTestReadServiceRecord(); break; + case NVDATAMGMT_SELF_TEST_STATE_READ_LAST_DISINFECTION_DATE: + + NVDataMgmtSelfTestState = handleSelfTestReadLastDisinfectionDate(); + break; + case NVDATAMGMT_SELF_TEST_STATE_CHECK_CRC: NVDataMgmtSelfTestState = handleSelfTestCheckCRC(); break; case NVDATAMGMT_SELF_TEST_STATE_COMPLETE: - // Done with the state - // TODO: If POST failed, set the proper alarm + // Done with POST. Do nothing break; default: - //TODO: Alarm + + SET_ALARM_WITH_2_U32_DATA ( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_NVDATAMGMT_INVALID_SELF_TEST_STATE, + NVDataMgmtSelfTestState ); + NVDataMgmtSelfTestState = NVDATAMGMT_SELF_TEST_STATE_COMPLETE; NVDataMgmtSelfTestResult = SELF_TEST_STATUS_FAILED; break; } @@ -669,12 +742,13 @@ case NVDATAMGMT_EXEC_STATE_FAULT: - // Something failed set the alarms - // TODO: set the alarms and stuff + // Something failed, we shouldn't be here break; default: + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_NVDATAMGMT_EXEC_INVALID_STATE, + NVDataMgmtExecState ); NVDataMgmtExecState = NVDATAMGMT_EXEC_STATE_FAULT; break; } @@ -940,10 +1014,40 @@ if ( getRTCRAMStatus() == RTC_RAM_STATUS_IDLE || timeoutStatus == TRUE ) { getDataFromRAM ( (U08*)&serviceRecord, sizeof(SERVICE_RECORD_T) ); + if ( getRTCRAMState() == RTC_RAM_STATE_READY ) + { + currentTime = getMSTimerCount(); + readFromRAM( LAST_DISINFECTION_DATE_ADDRESS, sizeof(LAST_DISINFECTION_RECORD_T) ); + } + state = NVDATAMGMT_SELF_TEST_STATE_READ_LAST_DISINFECTION_DATE; + } + + return state; +} + +/************************************************************************* + * @brief handleSelfTestReadLastDisinfectionDate + * The handleSelfTestReadLastDisinfectionDate reads the last disinfection date + * from RTC RAM + * @details + * Inputs : none + * Outputs : NVDATAMGMT_SELF_TEST_STATE_T + * @param none + * @return NVDATAMGMT_SELF_TEST_STATE_T + *************************************************************************/ +static NVDATAMGMT_SELF_TEST_STATE_T handleSelfTestReadLastDisinfectionDate ( void ) +{ + NVDATAMGMT_SELF_TEST_STATE_T state = NVDATAMGMT_SELF_TEST_STATE_READ_LAST_DISINFECTION_DATE; + BOOL timeoutStatus = didCommandTimeout ( ALARM_ID_RTC_RAM_OPS_ERROR, (U08*)&state ); + + if ( getRTCRAMStatus() == RTC_RAM_STATUS_IDLE || timeoutStatus == TRUE ) + { + getDataFromRAM ( (U08*)&lastDisinfectionRecord, sizeof(LAST_DISINFECTION_RECORD_T) ); state = NVDATAMGMT_SELF_TEST_STATE_CHECK_CRC; } return state; + } /************************************************************************* @@ -978,6 +1082,14 @@ hasCRCPassed = FALSE; SET_ALARM_WITH_2_U32_DATA( ALARM_ID_NVDATA_HW_USAGE_DATA_CRC_ERROR, recordCRC, calcCRC ); } + // Check the CRC for last disinfection date + calcCRC = crc16 ( (U08*)&lastDisinfectionRecord.disinfectionDate, sizeof(MAX_DATE_CHARACTERS) ); + recordCRC = lastDisinfectionRecord.crc; + if ( calcCRC != recordCRC ) + { + hasCRCPassed = FALSE; + SET_ALARM_WITH_2_U32_DATA( AlARM_ID_NVDATA_DISINFECTION_DATE_CRC_ERROR, recordCRC, calcCRC ); + } #endif // Check log header record calcCRC = crc16 ( (U08*)&logRecord.logHeader, sizeof(LOG_HEADER_T) ); @@ -989,10 +1101,10 @@ // The log header will be set to full by having the record count be at // maximum number of counts (1536 in this case) and the read index be a 0 // of the beginning of the log sectors - hasLogRecordCRCFailed = TRUE; - logRecord.logHeader.recordCount = MAX_NUM_OF_DATA_LOGS_IN_SECTOR3; - logRecord.logHeader.nextReadIndex = 0; - logRecord.logHeader.nextReadIndex = 0; + /*logRecord.logHeader.recordCount = MAX_NUM_OF_DATA_LOGS_IN_SECTOR3; + logRecord.logHeader.nextReadIndex = 0; + logRecord.logHeader.nextReadIndex = 0; + //logRecord.logHeader.isHdrCorrupted = TRUE; */ } // Check CRC for manufacturing record calcCRC = crc16 ( (U08*)&mfgRecord.mfgData, sizeof(MFG_DATA_T) ); @@ -1018,6 +1130,7 @@ hasCRCPassed = FALSE; SET_ALARM_WITH_2_U32_DATA( ALARM_ID_NVDATA_SRVC_RECORD_CRC_ERROR, recordCRC, calcCRC ); } + if ( hasCRCPassed || !hasCommandTimedout ) { NVDataMgmtSelfTestResult = SELF_TEST_STATUS_PASSED; @@ -1055,16 +1168,20 @@ logData.data4 = 80.125; logData.data5 = 68; - mytest.status = NVDATAMGMT_READ_IDLE; - mytest.externalBuffer = readBufferForTest; + //mytest.status = NVDATAMGMT_READ_IDLE; + //mytest.externalBuffer = readBufferForTest; + char a[10] = {'0','3','-', '0','3','-','2','0','2','0'}; + //setDisinfectionDate ( a); - //writeLogData ( (U08*)&logData, 32 ); + writeLogData ( (U08*)&logData, 32 ); //readLogData ( &mytest, sizeof(readBufferForTest) ); + //readLogData ( &mytest, sizeof(readBufferForTest) ); - //calTest.occSensorOffset = 3.4; - //calTest.tempSensorOffset = 13.2; + calTest.occSensorOffset = 3.4; + calTest.tempSensorOffset = 13.2; + memcpy(calTest.calibrationDate,a,10); //setCalibrationData(calTest); - char a[10] = {'0','3','-', '0','3','-','2','0','2','0'};; + memcpy(service.currentServiceDate, a, 10); memcpy(service.nextServiceDate, a, 10); //setServiceDate(service); @@ -1355,6 +1472,7 @@ logRecord.logHeader.nextWriteIndex = writeIndexChange; logRecord.logHeader.recordCount = logRecord.logHeader.recordCount + recordCountChange; logRecord.logHeader.nextReadIndex = logRecord.logHeader.nextReadIndex + readIndexChange; + logRecord.logHeader.isHdrCorrupted = FALSE; // Calculate the CRC for the new record logRecord.crc = crc16 ( (U08*)&logRecord.logHeader, sizeof(LOG_HEADER_T) ); @@ -1383,8 +1501,18 @@ U16 readIndexChange = INC_WRAP( logRecord.logHeader.nextReadIndex, LOG_DATA_START_INDEX, MAX_NUM_OF_DATA_LOGS_IN_SECTOR3 - 1 ); logRecord.logHeader.nextReadIndex = readIndexChange; - logRecord.crc = crc16 ( (U08*)&logRecord.logHeader, sizeof(LOG_RECORD_T) ); + // Check if the read index has been wrapped to 0 and the flag is for data corruption + // is true, the record count will be 0 and the data corruption flag will be false for + // normal operations + /*if ( logRecord.logHeader.nextReadIndex == 0 && + logRecord.logHeader.isHdrCorrupted == TRUE ) + { + logRecord.logHeader.recordCount = 0; + logRecord.logHeader.isHdrCorrupted = FALSE; + }*/ + logRecord.crc = crc16 ( (U08*)&logRecord.logHeader, sizeof(LOG_HEADER_T) ); + // Update the log record setMemoryOpsStruct ( NVDATAMGMT_WRITE, NVDATAMGMT_RTC, LOG_RECORD_START_ADDRESS, (U08*)&logRecord, 0, sizeof(LOG_RECORD_T) ); @@ -1545,7 +1673,7 @@ *************************************************************************/ static U32 getAvailableQueueCount ( void ) { - return QUEUE_MAX_SIZE - queueCount - 1; + return QUEUE_MAX_SIZE - queueCount; } /************************************************************************* Index: NVDataMgmt.h =================================================================== diff -u -r169b3efe1866e53f4d31db0cde00594a7c8ad210 -re1f9404958c9ddab9b004399fb0870e09e37512b --- NVDataMgmt.h (.../NVDataMgmt.h) (revision 169b3efe1866e53f4d31db0cde00594a7c8ad210) +++ NVDataMgmt.h (.../NVDataMgmt.h) (revision e1f9404958c9ddab9b004399fb0870e09e37512b) @@ -19,53 +19,59 @@ #include "Common.h" -#define MAX_SYS_SERIAL_NUMBER_CHARACTERS 7U -#define MAX_HW_SERIAL_NUMBER_CHARACTERS 5U -#define MAX_DATE_CHARACTERS 10U +#define MAX_SYS_SERIAL_NUMBER_CHARACTERS 7U ///< Max number of characters for SYS serial number +#define MAX_HW_SERIAL_NUMBER_CHARACTERS 5U ///< Max number of characters for HD serial number +#define MAX_DATE_CHARACTERS 10U ///< Max number of characters for date +/// Log event enum typedef enum LOG_EVENT { - NVDATAMGMT_MODE_CHANGE = 0, - NVDATAMGMT_ALARM, - NVDATAMGMT_DISINFECTION_STARTED, - NVDATAMGMT_DISINFECTION_ENDED, - NVDATAMGMT_DEVICE_TURNED_ON, - NVDATAMGMT_DEVICE_TURNED_OFF, - NVDATAMGMT_UI_CRASHED + NVDATAMGMT_MODE_CHANGE = 0, ///< Mode change + NVDATAMGMT_ALARM, ///< Alarm + NVDATAMGMT_DISINFECTION_STARTED, ///< Disinfection started + NVDATAMGMT_DISINFECTION_ENDED, ///< Disinfection ended + NVDATAMGMT_DEVICE_TURNED_ON, ///< Device turned on + NVDATAMGMT_DEVICE_TURNED_OFF, ///< Device turned off + NVDATAMGMT_UI_CRASHED ///< UI crashed } NVDATAMGMT_LOG_EVENT_T; +/// Read status enum typedef enum READ_STATUS { - NVDATAMGMT_READ_IDLE = 0, - NVDATAMGMT_READ_IN_PROGRESS, - NVDATAMGMT_READ_COMPLETE + NVDATAMGMT_READ_IDLE = 0, ///< Read status idle + NVDATAMGMT_READ_IN_PROGRESS, ///< Read status in progress + NVDATAMGMT_READ_COMPLETE ///< Read status complete } NVDATAMGMT_READ_STATUS_T; #pragma pack(push, 1) +/// Manufacturing data struct typedef struct mfg_Data { - char SYSSerialNumber [ MAX_SYS_SERIAL_NUMBER_CHARACTERS ]; - char HWSerialNumber [ MAX_HW_SERIAL_NUMBER_CHARACTERS ]; - char mfgDate [ MAX_DATE_CHARACTERS ]; + char SYSSerialNumber [ MAX_SYS_SERIAL_NUMBER_CHARACTERS ]; ///< SYS serial number + char HWSerialNumber [ MAX_HW_SERIAL_NUMBER_CHARACTERS ]; ///< HW serial number + char mfgDate [ MAX_DATE_CHARACTERS ]; ///< Manufacturing date } MFG_DATA_T; +/// Service dates struct typedef struct service_dates { - char currentServiceDate [ MAX_DATE_CHARACTERS ]; - char nextServiceDate [ MAX_DATE_CHARACTERS ]; + char currentServiceDate [ MAX_DATE_CHARACTERS ]; ///< Current service date + char nextServiceDate [ MAX_DATE_CHARACTERS ]; ///< Next service date } SERVICE_DATA_T; +/// Calibration data struct typedef struct calibration_Data { - F32 occSensorOffset; - F32 tempSensorOffset; - char calibrationDate [ MAX_DATE_CHARACTERS ]; + F32 occSensorOffset; ///< Item 1 + F32 tempSensorOffset; ///< Item 2 + char calibrationDate [ MAX_DATE_CHARACTERS ]; ///< Calibration date } CALIBRATION_DATA_T; +/// Read data status typedef struct get_data { - NVDATAMGMT_READ_STATUS_T status; - U08* externalBuffer; + NVDATAMGMT_READ_STATUS_T status; ///< Read data status + U08* externalBuffer; ///< External buffer address } READ_DATA_T; #pragma pack(pop) @@ -99,9 +105,9 @@ U32 getWaterConsumption ( void ); -BOOL setDisinfectionDate ( char date ); // TODO ADD TO AE +BOOL setDisinfectionDate ( char date [ MAX_DATE_CHARACTERS ] ); -void getDisinfectionDate ( void ); // TODO ADD TO AE +void getDisinfectionDate ( U08* buffer ); BOOL writeLogData ( U08* data, U32 length ); Index: RTC.c =================================================================== diff -u -r5d573b11d640b5b97c10a7d290c7c39cfa684ab6 -re1f9404958c9ddab9b004399fb0870e09e37512b --- RTC.c (.../RTC.c) (revision 5d573b11d640b5b97c10a7d290c7c39cfa684ab6) +++ RTC.c (.../RTC.c) (revision e1f9404958c9ddab9b004399fb0870e09e37512b) @@ -23,173 +23,177 @@ // ********** Definitions ********** -#define RTC_REG_1_12_HOUR_MODE_MASK 0x0004 // 12-hour mode mask -#define RTC_REG_1_PORO 0x0008 // Power On Reset Override -#define RTC_REG_1_CLK_STOPPED_MASK 0x0020 // RTC source clock mask -#define RTC_REG_1_UNUSED_MASK 0x0040 // Unused mask -#define RTC_REG_1_EXT_CLK_MODE_MASK 0x0080 // RTC external clock test mode mask +#define RTC_REG_1_12_HOUR_MODE_MASK 0x0004 ///< 12-hour mode mask (0x0004) +#define RTC_REG_1_PORO 0x0008 ///< Power On Reset Override (0x0008) +#define RTC_REG_1_CLK_STOPPED_MASK 0x0020 ///< RTC source clock mask (0x0020) +#define RTC_REG_1_UNUSED_MASK 0x0040 ///< Unused mask (0x0040) +#define RTC_REG_1_EXT_CLK_MODE_MASK 0x0080 ///< RTC external clock test mode mask (0x0080) -#define RTC_REG_2_MSF_MASK 0x0080 // Minute or second interrupt mask -#define RTC_REG_2_CDTF_MASK 0x0008 // Countdown timer interrupt mask -#define RTC_REG_2_AF_MASK 0x0010 // Alarm interrupt mask -#define RTC_REG_2_TSF2_MASK 0x0020 // Timestamp interrupt mask +#define RTC_REG_2_MSF_MASK 0x0080 ///< Minute or second interrupt mask (0x0080) +#define RTC_REG_2_CDTF_MASK 0x0008 ///< Countdown timer interrupt mask (0x0008) +#define RTC_REG_2_AF_MASK 0x0010 ///< Alarm interrupt mask (0x0010) +#define RTC_REG_2_TSF2_MASK 0x0020 ///< Timestamp interrupt mask (0x0020) -#define RTC_REG_3_BF_MASK 0x0008 // Battery status interrupt flag -#define RTC_REG_3_BLF_MASK 0x0004 // Battery status low flag +#define RTC_REG_3_BF_MASK 0x0008 ///< Battery status interrupt flag (0x0008) +#define RTC_REG_3_BLF_MASK 0x0004 ///< Battery status low flag (0x0004) // Indices used to check values read from RTC -#define RTC_REG_1_INDEX 1U -#define RTC_REG_2_INDEX 2U -#define RTC_REG_3_INDEX 3U -#define RTC_SECONDS_INDEX 4U -#define RTC_MINUTES_INDEX 5U -#define RTC_HOURS_INDEX 6U -#define RTC_DAYS_INDEX 7U -#define RTC_WEEKDAYS_INDEX 8U -#define RTC_MONTHS_INDEX 9U -#define RTC_YEARS_INDEX 10U +#define RTC_REG_1_INDEX 1U ///< RTC control register 1 index +#define RTC_REG_2_INDEX 2U ///< RTC control register 2 index +#define RTC_REG_3_INDEX 3U ///< RTC control register 3 index +#define RTC_SECONDS_INDEX 4U ///< RTC seconds index +#define RTC_MINUTES_INDEX 5U ///< RTC minutes index +#define RTC_HOURS_INDEX 6U ///< RTC hours index +#define RTC_DAYS_INDEX 7U ///< RTC days index +#define RTC_WEEKDAYS_INDEX 8U ///< RTC weekdays index +#define RTC_MONTHS_INDEX 9U ///< RTC months index +#define RTC_YEARS_INDEX 10U ///< RTC years index // Time and date acceptable ranges -#define MAX_ALLOWED_SECONDS 59U -#define MAX_ALLOWED_MINUTES 59U -#define MAX_ALLWOED_HOURS 23U -#define MAX_ALLOWED_DAYS 31U -#define MIN_ALLOWED_DAYS 1U -#define MAX_ALLOWED_MONTHS 12U -#define MIN_ALLOWED_MONTHS 1U -#define MAX_ALLOWED_YEARS 99U +#define MAX_ALLOWED_SECONDS 59U ///< Max allowed seconds (59) +#define MAX_ALLOWED_MINUTES 59U ///< Max allowed minutes (59) +#define MAX_ALLWOED_HOURS 23U ///< Max allowed hours (23) +#define MAX_ALLOWED_DAYS 31U ///< Max allowed days (31) +#define MIN_ALLOWED_DAYS 1U ///< Min allowed days (1) +#define MAX_ALLOWED_MONTHS 12U ///< Max allowed months (12) +#define MIN_ALLOWED_MONTHS 1U ///< Min allowed months (1) +#define MAX_ALLOWED_YEARS 99U ///< Max allowed years (99) -#define BUFFER_INDEX_0 0U -#define BUFFER_INDEX_1 1U -#define BUFFER_INDEX_2 2U -#define BUFFER_INDEX_3 3U -#define BUFFER_INDEX_4 4U +#define BUFFER_INDEX_0 0U ///< Buffer index 0 +#define BUFFER_INDEX_1 1U ///< Buffer index 1 +#define BUFFER_INDEX_2 2U ///< Buffer index 2 +#define BUFFER_INDEX_3 3U ///< Buffer index 3 +#define BUFFER_INDEX_4 4U ///< Buffer index 4 -#define MIBSPI_MAX_BUFFER_LENGTH 127U -#define MIBSPI_CONTINUOUS_MODE 4U -#define MIBSPI_CHIP_SELECT_ACTIVE 1U -#define MIBSPI_CHIP_SELECT_DEACTIVE 0U -#define MIBSPI_NO_WDELAY 0U -#define MIBSPI_LOCK_TG 0U -#define MIBSPI_DATA_FORMAT_ZERO 0U -#define MIBSPI_GROUP_ZERO 0U +#define MIBSPI_MAX_BUFFER_LENGTH 127U ///< MibSPI max buffer length (127) +#define MIBSPI_CONTINUOUS_MODE 4U ///< MibSPI continuous mode (4) +#define MIBSPI_CHIP_SELECT_ACTIVE 1U ///< MibSPI chip select active (1) +#define MIBSPI_CHIP_SELECT_DEACTIVE 0U ///< MibSPI chip select deactive (0) +#define MIBSPI_NO_WDELAY 0U ///< MibSPI no wdelay (0) +#define MIBSPI_LOCK_TG 0U ///< MibSPI lock TG (0) +#define MIBSPI_DATA_FORMAT_ZERO 0U ///< MibSPI data format zero (0) +#define MIBSPI_GROUP_ZERO 0U ///< MibSPI group zero (0) -#define MIBSPI_BUFFER_MODE_BIT_SHIFT_13 13U -#define MIBSPI_CHIP_SELECT_BIT_SHIFT_12 12U -#define MIBSPI_NO_WDELAY_BIT_SHIFT_10 10U -#define MIBSPI_LOCK_TRANS_BIT_SHIFT_11 11U -#define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 8U -#define MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 8U +#define MIBSPI_BUFFER_MODE_BIT_SHIFT_13 13U ///< MibSPI buffer mode bit shift by 13 (13) +#define MIBSPI_CHIP_SELECT_BIT_SHIFT_12 12U ///< MibSPI chip select big shift by 12 (12) +#define MIBSPI_NO_WDELAY_BIT_SHIFT_10 10U ///< MibSPI no wdelay bit shift by 10 (10) +#define MIBSPI_LOCK_TRANS_BIT_SHIFT_11 11U ///< MibSPI lock trans bit shift by 11 (11) +#define MIBSPI_DATA_FORMAT_ZERO_BIT_SHIFT_8 8U ///< MibSPI data format zero bit shift by 8 (8) +#define MIBSPI_BUFFER_TRANS_BIT_SHIFT_8 8U ///< MibSPI tran but shift by 8 (8) -#define RTC_RAM_PREP_BUFFER_LENGTH 3U -#define RTC_TIMESTAMP_BUFFER_LENGTH 8U -#define RTC_GENERAL_BUFFER_LENGTH 11U +#define RTC_RAM_PREP_BUFFER_LENGTH 3U ///< RTC RAM prep buffer length (3) +#define RTC_TIMESTAMP_BUFFER_LENGTH 8U ///< RTC RAM timestamp buffer length (8) +#define RTC_GENERAL_BUFFER_LENGTH 11U ///< RTC general buffer length (11) -#define RTC_PREP_RAM_INDEX 0U -#define RTC_RAM_HIGH_ADDRESS_INDEX 1U -#define RTC_RAM_LOW_ADDRESS_INDEX 2U -#define RTC_RAM_COMMAND_INDEX 3U +#define RTC_PREP_RAM_INDEX 0U ///< RTC prep RAM index (0) +#define RTC_RAM_HIGH_ADDRESS_INDEX 1U ///< RTC RAM high address index (1) +#define RTC_RAM_LOW_ADDRESS_INDEX 2U ///< RTC RAM low address index (2) +#define RTC_RAM_COMMAND_INDEX 3U ///< RTC RAM command index (3) -#define RTC_READ_FROM_REG0 0x00A0 // RTC read from address 0 -#define RTC_WRITE_TO_REG3 0x0023 // Seconds register -#define RTC_WRITE_TO_REG0 0x0020 -#define RTC_PREP_RAM_READ_WRITE 0x003A // RTC cmd prior to RAM ops -#define RTC_WRITE_TO_RAM 0x003C // RTC RAM write -#define RTC_READ_FROM_RAM 0x00BD // RTC RAM read +#define RTC_READ_FROM_REG0 0x00A0 ///< Read from RTC register0 (0x00A0) +#define RTC_WRITE_TO_REG3 0x0023 ///< Write to RTC from seconds register (0x0023) +#define RTC_WRITE_TO_REG0 0x0020 ///< Write to RTC from register0 (0x0020) +#define RTC_PREP_RAM_READ_WRITE 0x003A ///< RTC RAM command for read or write (0x003A) +#define RTC_WRITE_TO_RAM 0x003C ///< RTC write to RAM command (0x003C) +#define RTC_READ_FROM_RAM 0x00BD ///< RTC read from RAM command (0x00BD) -#define RTC_ACCURACY_TIMEOUT 1000U // ms -#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050U // ms -#define RTC_PUBLISH_INTERVAL 18U // Task general counts +#define RTC_ACCURACY_TIMEOUT 1000U ///< RTC accuracy timeout in ms (1000) +#define RTC_ACCURACY_TIMEOUT_TOLERANCE 1050U ///< RTC accuracy timeout tolerance in ms (1050) +#define RTC_PUBLISH_INTERVAL 18U ///< RTC publish interval in counts (18) -#define TIMER_COUNTER_TO_REQUEST_READ 18U -#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3U -#define MAX_ALLOWED_RTC_RAM_BYTES 100U -#define MAX_ALLOWED_RTC_RAM_ADDRESS 512U -#define TEN 10U -#define YEAR_2000 2000U -#define EPOCH_YEAR 1900U -#define YEAR_1900_TO_1970_SECONDS_DIFF 2208988800U +#define TIMER_COUNTER_TO_REQUEST_READ 18U ///< Timer counter for reading time from RTC (18) +#define MAX_ALLOWED_FAILED_RTC_TRANSFERS 3U ///< Max allowed failed RTC transfers (3) +#define MAX_ALLOWED_RTC_RAM_BYTES 100U ///< Max allowed RTC RAM bytes to be accepted from a caller (100) +#define MAX_ALLOWED_RTC_RAM_ADDRESS 512U ///< Max allowed RTC RAM legal address (512) +#define TEN 10U ///< Ten +#define YEAR_2000 2000U ///< Year 2000 +#define EPOCH_YEAR 1900U ///< Reference year to calculate epoch (1900) +#define YEAR_1900_TO_1970_SECONDS_DIFF 2208988800U ///< Difference in seconds from 1/1/1900 to 1/1/1970 (2208988800) #ifdef _VECTORCAST_ -#define LOCAL_TO_GTM_TIME_CONVERSION 8U +#define LOCAL_TO_GTM_TIME_CONVERSION 8U ///< Local time to GTM conversion for VectorCAST #endif +/// RTC self test state enums typedef enum RTC_Self_Test_States { - RTC_SELF_TEST_STATE_START = 0, - RTC_SELF_TEST_STATE_CHECK_CTRL_REGS, - RTC_SELF_TEST_STATE_WAIT_FOR_FIRST_SECOND, - RTC_SELF_TEST_STATE_WAIT_FOR_SECOND_SECOND, - RTC_SELF_TEST_STATE_CHECK_ACCURACY, - RTC_SELF_TEST_STATE_COMPLETE, - NUM_OF_RTC_SELF_TEST_STATES + RTC_SELF_TEST_STATE_START = 0, ///< Self test start + RTC_SELF_TEST_STATE_CHECK_CTRL_REGS, ///< Self test check control registers + RTC_SELF_TEST_STATE_WAIT_FOR_FIRST_SECOND, ///< Self test wait for first second + RTC_SELF_TEST_STATE_WAIT_FOR_SECOND_SECOND, ///< Self test wait for second second + RTC_SELF_TEST_STATE_CHECK_ACCURACY, ///< Self test check time accuracy + RTC_SELF_TEST_STATE_COMPLETE, ///< Self test complete + NUM_OF_RTC_SELF_TEST_STATES ///< Total number of self test states } RTC_SELF_TEST_STATE_T; +/// Read date states enums typedef enum RTC_Read_Data { - RTC_SEND_COMMAND = 0, - RTC_WAIT_FOR_TRANSFER_AND_READ, - RTC_SERVICE_COMPLETE, - NUM_OF_RTC_SERVICE_STATES + RTC_SEND_COMMAND = 0, ///< RTC send command + RTC_WAIT_FOR_TRANSFER_AND_READ, ///< RTC wait for transfer and read + RTC_SERVICE_COMPLETE, ///< RTC service complete + NUM_OF_RTC_SERVICE_STATES ///< Total number of RTC read date states } RTC_GET_DATA_STATE_T; +/// RTC exec state enums typedef enum RTC_Exec_State { - RTC_EXEC_STATE_WAIT_FOR_POST = 0, - RTC_EXEC_STATE_IDLE, - RTC_EXEC_STATE_PREP_RAM, - RTC_EXEC_STATE_WRITE_TO_RAM, - RTC_EXEC_STATE_READ_FROM_RAM, - RTC_EXEC_STATE_READ, - RTC_EXEC_STATE_WRITE, - RTC_EXEC_STATE_FAULT, - NUM_OF_RTC_EXEC_STATES + RTC_EXEC_STATE_WAIT_FOR_POST = 0, ///< Exec state wait for post + RTC_EXEC_STATE_IDLE, ///< Exec state idle + RTC_EXEC_STATE_PREP_RAM, ///< Exec state prep RAM + RTC_EXEC_STATE_WRITE_TO_RAM, ///< Exec state write to RAM + RTC_EXEC_STATE_READ_FROM_RAM, ///< Exec state read from RAM + RTC_EXEC_STATE_READ, ///< Exec state read + RTC_EXEC_STATE_WRITE, ///< Exec state write + RTC_EXEC_STATE_FAULT, ///< Exec state fault + NUM_OF_RTC_EXEC_STATES ///< Total number of exec states } RTC_EXEC_STATE_T; #pragma pack(push,4) +/// Timestamp struct typedef struct { - U16 seconds; - U16 minutes; - U16 hours; - U16 days; - U16 weekdays; - U16 months; - U16 years; + U16 seconds; ///< Seconds + U16 minutes; ///< Minutes + U16 hours; ///< Hours + U16 days; ///< Days + U16 weekdays; ///< Weekdays + U16 months; ///< Months + U16 years; ///< Years } RTC_TIMESTAMP_T; #pragma pack(pop) // ********** private data ********** -static RTC_SELF_TEST_STATE_T RTCSelfTestState = RTC_SELF_TEST_STATE_START; -static RTC_GET_DATA_STATE_T RTCServiceState = RTC_SEND_COMMAND; -static RTC_EXEC_STATE_T RTCExecState = RTC_EXEC_STATE_WAIT_FOR_POST; -static SELF_TEST_STATUS_T RTCSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; -static RTC_RAM_STATUS_T RTCRAMStatus = RTC_RAM_STATUS_IDLE; -static RTC_RAM_STATE_T RTCRAMState = RTC_RAM_STATE_READY; -static RTC_TIMESTAMP_T RTCTimestampStruct; -static RTC_TIMESTAMP_T RTCNewTimestampStruct; +static RTC_SELF_TEST_STATE_T RTCSelfTestState = RTC_SELF_TEST_STATE_START; ///< Self test variable +static RTC_GET_DATA_STATE_T RTCServiceState = RTC_SEND_COMMAND; ///< RTC get data variable +static RTC_EXEC_STATE_T RTCExecState = RTC_EXEC_STATE_WAIT_FOR_POST; ///< RTC exec state variable +static SELF_TEST_STATUS_T RTCSelfTestResult = SELF_TEST_STATUS_IN_PROGRESS; ///< RTC self test status variable +static RTC_RAM_STATUS_T RTCRAMStatus = RTC_RAM_STATUS_IDLE; ///< RTC RAM status variable +static RTC_RAM_STATE_T RTCRAMState = RTC_RAM_STATE_READY; ///< RTC RAM state +static RTC_TIMESTAMP_T RTCTimestampStruct; ///< Timestamp struct +static RTC_TIMESTAMP_T RTCNewTimestampStruct; ///< New timestamp struct -static U32 RTCSelfTestTimer = 0; -static U32 RTCPreviousSecond = 0; // Previous second is used to compare seconds in POST -static U32 RAMBufferLength = 0; -static U32 lastEpochTime = 0; // Last value that has been converted to epoch -static U32 previousTransferLength = 0; +static U32 RTCSelfTestTimer = 0; ///< Self test timer +static U32 RTCPreviousSecond = 0; ///< Previous second +static U32 RAMBufferLength = 0; ///< RAM buffer length +static U32 lastEpochTime = 0; ///< last epoch time +static U32 previousTransferLength = 0; ///< Previous transfer length -static U32 timeCounter = 1; -static U32 numberOfFailedRTCTransfers = 1; +static U32 timeCounter = 1; ///< Initial time counter (1) +static U32 numberOfFailedRTCTransfers = 1; ///< Initial number of failed RTC transactions (1) -static BOOL hasWriteToRTCRequested = FALSE; -static BOOL hasWriteToRAMRequested = FALSE; -static BOOL hasReadFromRAMRequested = FALSE; -static BOOL isRTCServiceOnEntry = FALSE; -static BOOL isTimestampBufferReady = FALSE; +static BOOL hasWriteToRTCRequested = FALSE; ///< Flag to request RTC write +static BOOL hasWriteToRAMRequested = FALSE; ///< Flag to write to RTC RAM +static BOOL hasReadFromRAMRequested = FALSE; ///< Flag to read from RTC RAM +static BOOL isRTCServiceOnEntry = FALSE; ///< Flag to check if service is on entry +static BOOL isTimestampBufferReady = FALSE; ///< Flag to check if the timestamp buffer is ready -static U16 rxBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; -static U16 txBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; +static U16 rxBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; ///< Buffer to receive data from RTC +static U16 txBuffer[ MIBSPI_MAX_BUFFER_LENGTH + 1 ]; ///< Buffer to transmit data to RTC -static U16 prepRAMBuffer[ RTC_RAM_PREP_BUFFER_LENGTH ]; -static U16 RAMBuffer[ MIBSPI_MAX_BUFFER_LENGTH ]; +static U16 prepRAMBuffer[ RTC_RAM_PREP_BUFFER_LENGTH ]; ///< Buffer to send prep commands to RTC RAM +static U16 RAMBuffer[ MIBSPI_MAX_BUFFER_LENGTH ]; ///< Buffer to read RTC RAM data // ********** Private function prototypes ********* @@ -325,14 +329,14 @@ case RTC_SELF_TEST_STATE_COMPLETE: - // Done with the state - // TODO: If POST failed, set the proper alarm + // Done with POST regardless of the results break; default: - // TODO: Add the alarms + SET_ALARM_WITH_2_U32_DATA ( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_RTC_SELF_TEST_INVALID_STATE, RTCSelfTestState ); RTCSelfTestResult = SELF_TEST_STATUS_FAILED; + RTCSelfTestState = RTC_SELF_TEST_STATE_COMPLETE; break; } @@ -389,10 +393,13 @@ case RTC_EXEC_STATE_FAULT: - // Something failed set the alarms + // Something failed, we shouldn't be here break; default: + + SET_ALARM_WITH_2_U32_DATA( ALARM_ID_SOFTWARE_FAULT, SW_FAULT_ID_RTC_EXEC_INVALID_STATE, RTCExecState ); + RTCExecState = RTC_EXEC_STATE_FAULT; break; } } Index: RTC.h =================================================================== diff -u -rc1cdf8965a4b1b913f939023b1b68fc48b0f06a5 -re1f9404958c9ddab9b004399fb0870e09e37512b --- RTC.h (.../RTC.h) (revision c1cdf8965a4b1b913f939023b1b68fc48b0f06a5) +++ RTC.h (.../RTC.h) (revision e1f9404958c9ddab9b004399fb0870e09e37512b) @@ -19,21 +19,23 @@ #include "Common.h" +/// RTC RAM status typedef enum RTC_RAM_STATUS { - RTC_RAM_STATUS_IDLE = 0, - RTC_RAM_STATUS_IN_PROGRESS, - RTC_RAM_STATUS_BYTES_EXCEEDED, - RTC_RAM_STATUS_ILLEGAL_ADDRESS, - RTC_RAM_STATUS_FAILED, - RTC_RAM_STATUS_COMPLETE + RTC_RAM_STATUS_IDLE = 0, ///< Status idle + RTC_RAM_STATUS_IN_PROGRESS, ///< Status in progress + RTC_RAM_STATUS_BYTES_EXCEEDED, ///< Status bytes exceeded + RTC_RAM_STATUS_ILLEGAL_ADDRESS, ///< Status illegal address + RTC_RAM_STATUS_FAILED, ///< Status failed + RTC_RAM_STATUS_COMPLETE ///< Status complete } RTC_RAM_STATUS_T; +/// RTC RAM states typedef enum RTC_RAM_STATE { - RTC_RAM_STATE_READY = 0, - RTC_RAM_STATE_BUSY + RTC_RAM_STATE_READY = 0, ///< RAM ready + RTC_RAM_STATE_BUSY ///< RAM busy } RTC_RAM_STATE_T;