Index: Integrity.c
===================================================================
diff -u -r2c4e882a6ebe84716461b171b77754e657530b9d -rfe57ea76fe86046ecef536ba0d144af8d3399e15
--- Integrity.c	(.../Integrity.c)	(revision 2c4e882a6ebe84716461b171b77754e657530b9d)
+++ Integrity.c	(.../Integrity.c)	(revision fe57ea76fe86046ecef536ba0d144af8d3399e15)
@@ -20,6 +20,9 @@
 #include "Integrity.h"
 #include "SafetyShutdown.h"
 #include "Utilities.h"
+#include "reg_tcram.h"      // DN-02SEPT2022
+#include "DGDefs.h"         // DN-02SEPT2022
+#include "TaskGeneral.h"    // DN-02SEPT2022
 
 /**
  *  @addtogroup Integrity
@@ -30,14 +33,27 @@
 
 #define CRC_TABLE_STARTING_ADDR             0x20                ///< The starting address of CRC table for firmware image.
 #define MAX_CRC_CALC_DATA_SIZE              0x8000              ///< The maximum size of data for each CRC calculation.
+#define SERR                    0x00000001          ///< Bit 0 - Single-bit error in TCRAM Module Error Status Register
+#define ADDR_DEC_FAIL           0x00000004          ///< Bit 2 - Address decode failed in TCRAM Module Error Status Register
+#define ADDR_COMP_LOGIC_FAIL    0x00000010          ///< Bit 4 - Address decode logic element failed in TCRAM Module Error Status Register
+#define DERR                    0x00000020          ///< Bit 5 - Multiple bit error in TCRAM Module Error Status Register
+#define RADDR_PAR_FAIL          0x00000100          ///< Bit 8 - Read Address Parity Failure in TCRAM Module Error Status Register
+#define WADDR_PAR_FAIL          0x00000200          ///< Bit 9 - Write Address Parity Failure in TCRAM Module Error Status Register
 
 // ********** private data **********
 
 static U32 currentRecord;                                       ///< Current CRC table record to check.
 static U32 currentProcessedSize;                                ///< Current data size processed for CRC calculation.
 static U32 crcCalculated;                                       ///< The calculated CRC value.
 static SELF_TEST_STATUS_T integrityTestStatus;                  ///< Current firmware integrity test status.
+static U32 processorRAMStatusCounter = 0;                       ///< Counter use to log system event if processor RAM error is detected.  DN-02SEPT2022
+static BOOL singleBitRAMErrorFlag = FALSE;                      ///< Flag to signal single bit RAM error.       - DN-02SEPT2022
 
+
+/// Time threshold to check RAM error is 1 second
+static const U32 RAM_ERROR_CHECK_TIME_THRESHOLD = ((1 * MS_PER_SECOND) / TASK_GENERAL_INTERVAL);    // DN-02SEPT2022
+
+
 /*********************************************************************//**
  * @brief
  * The initIntegrity function initializes the Integrity module.
@@ -53,6 +69,49 @@
     integrityTestStatus = SELF_TEST_STATUS_IN_PROGRESS;
 }
 
+/********************************************************************************//**
+ * @brief
+ * The execRAMMonitor function monitors the processor RAM status.
+ * @details Inputs: none
+ * @details Outputs: system event log or alarm  activated if RAM error is detected.
+ * @return none
+ ***********************************************************************************/
+void execRAMMonitor( void )     // DN-02SEPT2022
+{
+    U32 tcram1ErrStat, tcram2ErrStat = 0;
+    U32 err1, err2 = 0;
+
+    // Check for processor RAM error
+    if ( ++processorRAMStatusCounter > RAM_ERROR_CHECK_TIME_THRESHOLD )
+    {
+        tcram1ErrStat = tcram1REG->RAMERRSTATUS;    // Single-bit error, bit 0 in B0TCM in TCRAM Module Error Status Register
+        tcram2ErrStat = tcram2REG->RAMERRSTATUS;    // Single-bit error, bit 0 in B1TCM in TCRAM Module Error Status Register
+        err1 = tcram1ErrStat & SERR;
+        err2 = tcram2ErrStat & SERR;
+        if( ( err1 != 0 ) || ( err2 != 0 ) )
+        {
+            if ( FALSE == singleBitRAMErrorFlag )
+            {
+              // Log the single-bit RAM error event once only
+              SEND_EVENT_WITH_2_U32_DATA( DG_EVENT_CPU_RAM_ERROR_STATUS, 0, 0 );
+              singleBitRAMErrorFlag = TRUE;
+            }
+            tcram1ErrStat = tcram1ErrStat & 0xFFFFFFFE;     // Clear bit 0
+            tcram2ErrStat = tcram2ErrStat & 0xFFFFFFFE;     // Clear bit 0
+        }
+
+        err1 = tcram1ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
+        err2 = tcram2ErrStat & (ADDR_DEC_FAIL | ADDR_COMP_LOGIC_FAIL | DERR | RADDR_PAR_FAIL | WADDR_PAR_FAIL);
+
+        if ( ( err1 != 0 ) || ( err2 != 0 ) )
+        {
+            SET_ALARM_WITH_2_U32_DATA( ALARM_ID_DG_CPU_RAM_ERROR, tcram1ErrStat, tcram2ErrStat );
+        }
+
+        processorRAMStatusCounter = 0;
+    }
+}
+
 /*********************************************************************//**
  * @brief
  * The execIntegrityTest function executes the integrity check for firmware image.
Index: Integrity.h
===================================================================
diff -u -r54a9bd09d6714d7faaa186959988a75ef3b83557 -rfe57ea76fe86046ecef536ba0d144af8d3399e15
--- Integrity.h	(.../Integrity.h)	(revision 54a9bd09d6714d7faaa186959988a75ef3b83557)
+++ Integrity.h	(.../Integrity.h)	(revision fe57ea76fe86046ecef536ba0d144af8d3399e15)
@@ -34,6 +34,7 @@
 
 void initIntegrity( void );
 SELF_TEST_STATUS_T execIntegrityTest( void );
+void execRAMMonitor( void );     // DN-02SEPT2022
 
 /**@}*/