Index: App/Services/FPGA.c =================================================================== diff -u -r40a959e1341c8964f872df462ac3a2d874e3b0b3 -r81ca79980a75ab71985d3d610bcef45fd6730458 --- App/Services/FPGA.c (.../FPGA.c) (revision 40a959e1341c8964f872df462ac3a2d874e3b0b3) +++ App/Services/FPGA.c (.../FPGA.c) (revision 81ca79980a75ab71985d3d610bcef45fd6730458) @@ -54,7 +54,7 @@ #define FPGA_READ_CMD_NAK 0xAF #define FPGA_CRC_LEN 2 -#define FPGA_WRITE_CMD_HDR_LEN 5 +#define FPGA_WRITE_CMD_HDR_LEN 4 #define FPGA_READ_CMD_HDR_LEN 4 #define FPGA_WRITE_RSP_HDR_LEN 1 #define FPGA_READ_RSP_HDR_LEN 1 @@ -480,7 +480,7 @@ FPGA_STATE_T result = FPGA_STATE_READ_HEADER; // did we get an FPGA response? - if ( fpgaReceiptCounter > 0 ) + if ( ( TRUE == fpgaWriteCommandACKed ) && ( TRUE == fpgaReadCommandACKed ) ) { // did FPGA Ack the read command? if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK ) @@ -510,11 +510,38 @@ static FPGA_STATE_T handleFPGAWriteAllActuatorsState( void ) { FPGA_STATE_T result = FPGA_STATE_RCV_ALL_SENSORS; + U16 crc; + // construct bulk write command to write actuator data registers starting at address 3 (TODO - change address later) + fpgaWriteCmdBuffer[0] = FPGA_WRITE_CMD_CODE; + fpgaWriteCmdBuffer[1] = 0x02; // start at FPGA address 8 + fpgaWriteCmdBuffer[2] = 0x00; + fpgaWriteCmdBuffer[3] = 1; // TODO - replace 1 with sizeof(FPGA_ACTUATORS_T) +// memcpy( &(fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN]), &fpgaActuatorSetPoints, sizeof(FPGA_ACTUATORS_T) ); + fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN] = 99; // TODO - remove and replace with memcpy above + crc = crc16( fpgaWriteCmdBuffer, FPGA_WRITE_CMD_HDR_LEN+1 ); // TODO - replace +1 with +sizeof(FPGA_ACTUATORS_T) + fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN+1] = GET_LSB_OF_WORD( crc ); // TODO - replace +1 with +sizeof(FPGA_ACTUATORS_T) + fpgaWriteCmdBuffer[FPGA_WRITE_CMD_HDR_LEN+1+1] = GET_MSB_OF_WORD( crc ); // TODO - replace +1 with +sizeof(FPGA_ACTUATORS_T) + // construct bulk read command to read sensor data registers starting at address 8 + fpgaReadCmdBuffer[0] = FPGA_READ_CMD_CODE; + fpgaReadCmdBuffer[1] = 0x08; // start at FPGA address 8 + fpgaReadCmdBuffer[2] = 0x00; + fpgaReadCmdBuffer[3] = sizeof(FPGA_SENSORS_T); + crc = crc16( fpgaReadCmdBuffer, FPGA_READ_CMD_HDR_LEN ); + fpgaReadCmdBuffer[4] = GET_LSB_OF_WORD( crc ); + fpgaReadCmdBuffer[5] = GET_MSB_OF_WORD( crc ); + // prep DMA for sending the bulk write cmd and receiving its response + setupDMAForWriteCmd( FPGA_WRITE_CMD_HDR_LEN + 1 + FPGA_CRC_LEN ); // TODO s/b sizeof(FPGA_ACTUATORS_T) instead of 1 + setupDMAForWriteResp( FPGA_WRITE_RSP_HDR_LEN ); + // prep DMA for sending the bulk read cmd and receiving its response + setupDMAForReadCmd( FPGA_READ_CMD_HDR_LEN + FPGA_CRC_LEN ); + setupDMAForReadResp( FPGA_READ_RSP_HDR_LEN + sizeof(FPGA_SENSORS_T) + FPGA_CRC_LEN ); + // set fpga comm flags for bulk write cmd and follow-up bulk read command fpgaWriteCommandInProgress = TRUE; fpgaBulkWriteAndReadInProgress = TRUE; - // TODO - setup for bulk write and follow-up bulk read commands - // TODO - initiate bulk write command + // initiate bulk write command and it's receipt - read will follow + startDMAReceiptOfWriteResp(); + startDMAWriteCmd(); return result; } @@ -533,17 +560,35 @@ { FPGA_STATE_T result = FPGA_STATE_WRITE_ALL_ACTUATORS; - // check commands success + // check bulk write command success if ( FALSE == fpgaWriteCommandACKed ) { // TODO - ??? } - if ( FALSE == fpgaReadCommandACKed ) + + // if bulk read command is ACK'd, collect the readings + if ( TRUE == fpgaReadCommandACKed ) { + // did we get an FPGA response? + if ( ( TRUE == fpgaWriteCommandACKed ) && ( TRUE == fpgaReadCommandACKed ) ) + { + // did FPGA Ack the read command? + if ( fpgaReadResponseBuffer[0] == FPGA_READ_CMD_ACK ) + { + // does the FPGA response CRC check out? + if ( 1 ) // TODO - check response CRC + { // capture the read values + memcpy( &fpgaSensorReadings, fpgaReadResponseBuffer, sizeof(FPGA_SENSORS_T) ); + result = FPGA_STATE_WRITE_ALL_ACTUATORS; + } + } + } + } + else + { // TODO - ??? } - // TODO - collect sensor readings return result; } @@ -577,7 +622,7 @@ { dmaSetCtrlPacket( DMA_CH2, fpgaDMAWriteControlRecord ); dmaSetChEnable( DMA_CH2, DMA_HW ); - scilinREG->SETINT = SCI_DMA_TRANSMIT_INT; + setSCI2DMATransmitInterrupt(); } /************************************************************************* @@ -609,7 +654,7 @@ { dmaSetCtrlPacket( DMA_CH0, fpgaDMAWriteRespControlRecord ); dmaSetChEnable( DMA_CH0, DMA_HW ); - scilinREG->SETINT = SCI_DMA_RECEIVE_INT; + setSCI2DMAReceiveInterrupt(); } /************************************************************************* @@ -641,7 +686,7 @@ { dmaSetCtrlPacket( DMA_CH2, fpgaDMAReadControlRecord ); dmaSetChEnable( DMA_CH2, DMA_HW ); - scilinREG->SETINT = SCI_DMA_TRANSMIT_INT; + setSCI2DMATransmitInterrupt(); } /************************************************************************* @@ -673,7 +718,7 @@ { dmaSetCtrlPacket( DMA_CH0, fpgaDMAReadRespControlRecord ); dmaSetChEnable( DMA_CH0, DMA_HW ); - scilinREG->SETINT = SCI_DMA_RECEIVE_INT; + setSCI2DMAReceiveInterrupt(); } /*************************************************************************