Index: App/Services/SystemComm.c
===================================================================
diff -u -r40a959e1341c8964f872df462ac3a2d874e3b0b3 -r81ca79980a75ab71985d3d610bcef45fd6730458
--- App/Services/SystemComm.c	(.../SystemComm.c)	(revision 40a959e1341c8964f872df462ac3a2d874e3b0b3)
+++ App/Services/SystemComm.c	(.../SystemComm.c)	(revision 81ca79980a75ab71985d3d610bcef45fd6730458)
@@ -103,7 +103,7 @@
     // TODO - remove this test code that sends a packet
 //    dmaSetCtrlPacket( DMA_CH3, pcDMAXmitControlRecord );
 //    dmaSetChEnable( DMA_CH3, DMA_HW );
-//    sciREG->SETINT = SCI_DMA_TRANSMIT_INT;
+//    setSCI1DMATransmitInterrupt();
 }
 
 /*************************************************************************
@@ -143,7 +143,7 @@
     }
 
     // if UART transmitter is idle, start transmitting any pending packets
-    if ( FALSE == SCI1_TX_IN_PROGRESS() )
+    if ( FALSE == isSCI1DMATransmitInProgress() )
     {
         transmitNextUARTPacket();
     }
@@ -204,8 +204,7 @@
     // prepare to receive next packet
     dmaSetCtrlPacket( DMA_CH1, pcDMARecvControlRecord );
     dmaSetChEnable( DMA_CH1, DMA_HW );
-    sciREG->SETINT = (uint32)((uint32)1U << 18U);  /* Rx DMA All */
-    sciREG->SETINT = (uint32)((uint32)1U << 17U);  /* Rx DMA */
+    setSCI1DMAReceiveInterrupt();
 }
 
 /*************************************************************************
@@ -284,7 +283,7 @@
     // initiate UART packet receiving readiness via DMA
     dmaSetCtrlPacket( DMA_CH1, pcDMARecvControlRecord );
     dmaSetChEnable( DMA_CH1, DMA_HW );
-    sciREG->SETINT = SCI_DMA_RECEIVE_INT;
+    setSCI1DMAReceiveInterrupt();
 }
 
 /*************************************************************************
@@ -424,7 +423,7 @@
     {
         dmaSetCtrlPacket( DMA_CH3, pcDMAXmitControlRecord );
         dmaSetChEnable( DMA_CH3, DMA_HW );
-        sciREG->SETINT = (uint32)((uint32)1U << 16U);  /* Tx DMA */
+        setSCI1DMATransmitInterrupt();
     }
 }